40th week of 2012 patent applcation highlights part 37 |
Patent application number | Title | Published |
20120250392 | DATA HOLDING DEVICE AND LOGIC OPERATION CIRCUIT USING THE SAME - A data holding device includes a loop structure unit configured to hold data using a plurality of logic gates connected in a loop shape, a nonvolatile storage unit including a plurality of ferroelectric elements, the nonvolatile storage unit configured to store the data held in the loop structure unit in a nonvolatile manner using hysteresis characteristics of the ferroelectric elements, and a circuit separation unit configured to electrically separate the loop structure unit and the nonvolatile storage unit. The ferroelectric elements of the nonvolatile storage unit are surrounded by a dummy element smaller in width than the ferroelectric elements. | 2012-10-04 |
20120250393 | SEMICONDUCTOR MEMORY DEVICE AND CONTROLLING METHOD THEREOF - According to one embodiment, a semiconductor memory device includes a memory cell array in which memory cells each including at least a rectification element and a variable resistance element, which are connected in series, a peripheral circuit, a sense amplifier configured to sense the memory cells via the peripheral circuit, and a control circuit configured to control operations of the memory cell array and the sense amplifier. The control circuit is configured to boost a potential of a selected bit line, which is one of a first even bit line and a first odd bit line of a first side, by charge sharing of a second even bit line and a second odd bit line which are nonselected bit lines and physically neighbor the first even bit line or the first odd bit line of the first side, which is connected to a selected one of the memory cells. | 2012-10-04 |
20120250394 | RESISTANCE CHANGE MEMORY - According to one embodiment, a resistance change memory includes a memory cell including a resistance change element and a stacked layer structure which are connected in series, a control circuit configured to control a first operation of changing the resistance change element from a first resistance value to a second resistance value lower than the first resistance value, and a voltage pulse generating circuit configured to generate a first voltage pulse to be applied to the memory cell in the first operation. The stacked layer structure includes two conductive layers and an insulating layer formed between the two conductive layers. Amplitude of the first voltage pulse is in a first voltage area in which the stacked layer structure functions as a capacitor. The first voltage pulse satisfies Ron×C2012-10-04 | |
20120250395 | SELECTOR TYPE ELECTRONIC DEVICE - An electronic device includes a first electrode, a second electrode and a solid electrolyte having a base of an ion conducting material. The device remains in the highly resistive state for as long as a first threshold voltage between the first electrode and the second electrode is not reached. The device switches from the state of high resistance to the state of low resistance when the potential difference between the first electrode and the second electrode is equal to or greater than the first threshold voltage. The device switches from the state of low resistance to the state of high resistance when the potential difference between the first electrode and the second electrode equal to or greater than this first threshold voltage is removed and as it decreases it reaches a second positive voltage threshold strictly lower than the first threshold voltage. | 2012-10-04 |
20120250396 | VERTICALLY STACKED FIELD PROGRAMMABLE NONVOLATILE MEMORY AND METHOD OF FABRICATION - A memory cell is provided that includes a steering element, and a non-volatile state change element coupled in series with the steering element. The steering element and state change element are disposed in a vertically-oriented pillar. Other aspects are also provided. | 2012-10-04 |
20120250397 | SEMICONDUCTOR DEVICE AND DRIVING METHOD THEREOF - The storage device includes a volatile first memory circuit and a nonvolatile second memory circuit which includes a transistor whose channel is formed in an oxide semiconductor layer. In the case of high-frequency driving, during a period when source voltage is applied, a data signal is input to and output from the first memory circuit, and during a part of a period when source voltage is supplied, which is before the supply of the source voltage is stopped, a data signal is input to the second memory circuit. In the case of low-frequency driving, during a period when source voltage is applied, a data signal is input to the second memory circuit, the data signal input to the second memory circuit is input to the first memory circuit, and the data signal input to the first memory circuit is output. | 2012-10-04 |
20120250398 | MAGNETIC STORAGE ELEMENT, MAGNETIC STORAGE DEVICE, AND MAGNETIC MEMORY - A magnetic storage element according to an embodiment includes: a magnetic thin wire extending in a first direction and having a plurality of magnetic domains partitioned by domain walls; an electrode capable of applying a current flowing in the first direction and a current flowing in the opposite direction from the first direction, to the magnetic thin wire; and an assisting unit receiving an electrical input and assisting movement of the domain walls in an entire or part of the magnetic thin wire. | 2012-10-04 |
20120250399 | MEMORY CIRCUIT USING SPIN MOSFETS, PATH TRANSISTOR CIRCUIT WITH MEMORY FUNCTION, SWITCHING BOX CIRCUIT, SWITCHING BLOCK CIRCUIT, AND FIELD PROGRAMMABLE GATE ARRAY - A memory circuit according to an embodiment includes: a first transistor including a first source/drain electrode, a second source/drain electrode, and a first gate electrode; a second transistor including a third source/drain electrode connected to the second source/drain electrode, a fourth source/drain electrode, and a second gate electrode; a third transistor and a fourth transistor forming an inverter circuit, the third transistor including a fifth source/drain electrode, a sixth source/drain electrode, and a third gate electrode connected to the second source/drain electrode, the fourth transistor including a seventh source/drain electrode connected to the sixth source/drain electrode, an eighth source/drain electrode, and a fourth gate electrode connected to the second source/drain electrode; and an output terminal connected to the sixth source/drain electrode. At least one of the third transistor and the fourth transistor is a spin MOSFET, and an output of the inverter circuit is sent from the output terminal. | 2012-10-04 |
20120250400 | SEMICONDUCTOR MEMORY DEVICE - The control circuit selects, as the first reference cell, the first memory cell having a maximum reading current supplied by turning on the first select transistor in a state in which resistance values of the first memory cells are all increased. The control circuit selects, as the second reference cell, the second memory cell having a maximum reading current supplied by turning on the second select transistor in a state in which resistance values of the second memory cells are all increased. | 2012-10-04 |
20120250401 | PHASE CHANGE MEMORY (PCM) ARCHITECTURE AND A METHOD FOR WRITING INTO PCM ARCHITECTURE - A phase change memory (PCM) architecture and a method for writing a PCM architecture are described. In one embodiment, a PCM architecture includes a PCM array, word line driver circuits, bit line driver circuits, a source driver circuit and a voltage supply circuit. The bit line driver circuits are connected to the PCM array and the electrical ground. Other embodiments are also described. | 2012-10-04 |
20120250402 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus includes a resistive memory cell; a data sensing unit configured to sense an output voltage, formed by a sensing current supplied to the resistive memory cell, based on a reference voltage, and output data having a value corresponding to the sensing result; and a reference voltage generation unit comprising a dummy memory cell including first and second resistors having first and second resistance values, respectively, and configured to output a voltage formed by the sensing current supplied to the dummy memory cell as the reference voltage. | 2012-10-04 |
20120250403 | Method for Programming A Resistive Memory Cell, A Method And A Memory Apparatus For Programming One Or More Resistive Memory Cells In A Memory Array - A method for programming a resistive memory cell is provided. The method may include providing a programming signal to the resistive memory cell. The programming signal may include an electrical pulse and a bias pulse coupled with the electrical pulse. The electrical pulse includes an electrical pulse portion, and the bias pulse includes at least two bias pulse portions, wherein the electrical pulse portion is positioned between the at least two bias pulse portions. The bias pulse includes a voltage below a threshold switching voltage of the resistive memory cell. The programming signal includes a peak voltage above the threshold switching voltage of the resistive memory cell. | 2012-10-04 |
20120250404 | MAGNETIC TUNNEL JUNCTION WITH FREE LAYER HAVING EXCHANGE COUPLED MAGNETIC ELEMENTS - A magnetic tunnel junction device includes a reference magnetic layer and a magnetic free layer including first and second magnetic elements that are magnetically exchange coupled. The magnetic exchange coupling between the first and second magnetic elements is configured to achieve a switching current distribution less than about 200% and a long term thermal stability criterion of greater than about 60 k | 2012-10-04 |
20120250405 | MAGNETIC FIELD ASSISTED STRAM CELLS - Memory units that have a magnetic tunnel junction cell that utilizes spin torque and a current induced magnetic field to assist in the switching of the magnetization orientation of the free layer of the magnetic tunnel junction cell. The memory unit includes a spin torque current source for passing a current through the magnetic tunnel junction cell, the spin torque current source having a direction perpendicular to the magnetization orientations, and also includes a magnetic ampere field current source is oriented in a direction orthogonal or at some angles to the magnetization orientations. | 2012-10-04 |
20120250406 | MAGNETIC MEMORY DEVICE AND METHOD OF MAGNETIC DOMAIN WALL MOTION - A magnetic memory device comprises a first electrode, a second electrode, a laminated structure comprising plural first magnetic layers being provided between the first electrode and the second electrode, a second magnetic layer comprising different composition elements from that of the first magnetic layer and being provided between plural first magnetic layers, a piezoelectric body provided on a opposite side to a side where the first electrode is provided in the laminated structure, and a third electrode applying voltage to the piezoelectric body and provided on a different position from a position where the first electrode is provided in the piezoelectric body. | 2012-10-04 |
20120250407 | MEMORY CIRCUIT, MEMORY UNIT, AND SIGNAL PROCESSING CIRCUIT - A memory circuit includes a transistor having a channel in an oxide semiconductor layer, a capacitor, a first arithmetic circuit, a second arithmetic circuit, a third arithmetic circuit, and a switch. An output terminal of the first arithmetic circuit is electrically connected to an input terminal of the second arithmetic circuit. The input terminal of the second arithmetic circuit is electrically connected to an output terminal of the third arithmetic circuit via the switch. An output terminal of the second arithmetic circuit is electrically connected to an input terminal of the first arithmetic circuit. An input terminal of the first arithmetic circuit is electrically connected to one of a source and a drain of the transistor. The other of the source and the drain of the transistor is electrically connected to one of a pair of electrodes of the capacitor and to an input terminal of the third arithmetic circuit. | 2012-10-04 |
20120250408 | MEMORY SYSTEM, CONTROLLER, AND METHOD FOR CONTROLLING MEMORY SYSTEM - According to one embodiment, a memory system includes nonvolatile memory having a plurality of memory cells of storage capacity of a specified number of bits equal to or greater than two bits, and a number-of-rewrites management table managing numbers of rewrites of the memory cells. The memory system of the embodiment includes a controller writing to the memory cells in a number of bits in accordance with a write request of a host, dividing the memory cells into groups in dependence on storage capacity after the numbers of rewrites of the memory cells managed by the number-of-rewrites management table exceed a specified number, and writing to the memory cells of the group corresponding to storage capacity of the number of bits in accordance with the write request of the host. | 2012-10-04 |
20120250409 | SEMICONDUCTOR MEMORY AND CONTROL METHOD THEREOF - According to one embodiment, a semiconductor memory includes a memory cell array which includes memory cells, the memory cells being arranged along a row direction and a column direction and storing data respectively corresponding to thresholds, a row control circuit which controls a row of the memory cell array, and a column control circuit which includes a control unit, the control unit generating a signal to control elements corresponding to column of the memory cell array in accordance with a pointer corresponding to an external address signal. | 2012-10-04 |
20120250410 | SEMICONDUCTOR INTEGRATED CIRCUIT AND DATA READ METHOD - A semiconductor integrated circuit includes a memory cell area comprising a main cell and a spare cell, and a memory controller configured to set an offset value using a program verify level which is set during a program operation, and set a read level using the offset value during a read operation. | 2012-10-04 |
20120250411 | NONVOLATILE SEMICONDUCTOR MEMORY - According to one embodiment, a nonvolatile semiconductor memory includes a memory cell array including memory cells of a first unit in which read and write are parallelly performed, n (n is a natural number of not less than 2) sense amplifiers, n detection circuits corresponding to the n sense amplifiers, an accumulator configured to divide the first unit data read from the memory cell array into z (z is a natural number) second unit data and accumulate a fail bit for which the write is incomplete for the second unit data, and a control circuit configured to control an operation of detecting the fail bit after the write. | 2012-10-04 |
20120250412 | FLASH MEMORY APPARATUS AND METHOD FOR GENERATING READ VOLTAGE THEREOF - A flash memory apparatus includes: a cell array including a plurality of main blocks, a code addressable memory (CAM) block, and a security block; a control unit configured to detect a threshold voltage change data of a main block to which a program operation has been performed among the plurality of main blocks, and set a trimming value corresponding to the detected threshold voltage change data; and a read voltage generation unit configured to generate a read voltage according to the set trimming value. | 2012-10-04 |
20120250413 | Non-Volatile Semiconductor Memory with Page Erase - In a nonvolatile memory, less than a full block maybe erased as one or more pages. A select voltage is applied through pass transistors to each of plural selected wordlines and an unselect voltage is applied through pass transistor to each of plural unselected wordlines of a selected block. A substrate voltage is applied to the substrate of the selected block. A common select voltage may be applied to each selected wordline and the common unselect voltage may be applied to each unselected wordline. Select and unselect voltages may be applied to any of the wordlines of a select block. A page erase verify operation may be applied to a block having plural erased pages and plural nonerased pages. | 2012-10-04 |
20120250414 | REDUCING NEIGHBOR READ DISTURB - Methods and devices for sensing non-volatile storage devices in a way that reduces read disturb are disclosed. Techniques are used to reduce read disturb on memory cells that are neighbors to selected memory cells. For example, on a NAND string, the memory cells that are next to the selected memory cell presently being read may benefit. In one embodiment, when reading memory cells on a selected word line WLn, Vread+Delta is applied to WLn+2 and WLn−2. Applying Vread+Delta to the second neighbor word line may reduce read disturb to memory cells on the neighbor word line WLn+1. | 2012-10-04 |
20120250415 | SIMULTANEOUS MULTI-STATE READ OR VERIFY IN NON-VOLATILE STORAGE - Methods and devices for simultaneously verifying or reading multiple states in non-volatile storage are disclosed. Methods and devices for efficiently reducing or eliminating cross-coupling effects in non-volatile storage are disclosed. Methods and devices for efficiently performing reads at a number of voltages to search for the threshold voltage of a memory cell are disclosed. Memory cells on different NAND strings that are read at the same time may be tested for different threshold voltage levels. Memory cells may be tested for different threshold voltages by applying different gate-to-source voltages to memory cells being tested for different threshold voltages. Memory cells may be tested for different threshold voltages by applying different drain to source voltages to the memory cells. Different amounts of compensation for cross-coupling affects may be applied to memory cells on different NAND strings that are read or programmed at the same time. | 2012-10-04 |
20120250416 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes: a memory cell array including plural memory cells; a first word line connected to a control gate of a first memory cell; a second word line connected to a control gate of a second memory cell and neighboring the first word line on one side; a third word line connected to a control gate of a third memory cell and neighboring the first word line on the opposite side to the one side; and a control circuit configured to read data from the first word line under a condition in which the memory cell connected to the second word line holds data while the memory cell connected to the third word line does not hold data, and to set a first voltage applied to the third word line to be lower than a second voltage applied to the second word line. | 2012-10-04 |
20120250417 | HOT ELECTRON INJECTION NANOCRYSTALS MOS TRANSISTOR - The disclosure relates to a hot electron injection MOS transistor, comprising source and drain regions formed in a semiconductor substrate, a control gate, and a floating gate comprising electrically conductive nanoparticles. The control gate comprises a first portion arranged at a first distance from the substrate, a second portion arranged at a second distance less than the first distance from the substrate, and an intermediary portion linking the first and the second portions. | 2012-10-04 |
20120250418 | Natural Threshold Voltage Distribution Compaction In Non-Volatile Memory - In a non-volatile memory system, a multi-phase programming operation is performed in which a drain-side select gate voltage (Vsgd) can be adjusted in different programming phases to accommodate different bit line bias (Vbl) levels. A higher Vbl can be used when Vsgd is higher to avoid unnecessary stress on the SGD transistor and reduce power consumption. For example, Vsgd can be higher in an earlier program phase than in a later program phase. The higher Vbl, which is not based on programming speed, can be is applied when the Vth of a storage element is between lower and upper verify levels of target data states, or throughout a programming phase, or at other times. The higher Vbl is an additional slow down measure which can be implemented in addition to a programming speed-based slow down measure such as a further raised Vbl which is applied to faster-programming storage elements. | 2012-10-04 |
20120250419 | METHOD OF CONTROLLING NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - In one embodiment, method of controlling a semiconductor nonvolatile memory device includes determining data written to an adjacent memory cell which is adjacent to a selection memory cell in memory cells configured as a matrix, the selection memory being selected by a program operation for writing the data to the selection memory, and writing the data to the selection memory with controlling an amount of charges injected into the selection memory based on a result of determining the data. | 2012-10-04 |
20120250420 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A control circuit performs a read operation of reading data held in a memory-cell by supplying a selected word-line with a read voltage that is a voltage between the lower limit and the upper limit of a plurality of threshold-voltage distributions provided to the memory-cell. The control circuit also performs a verify operation of determining whether a write operation is completed by supplying a selected word-line with a verify voltage higher than the read voltage to read the memory cell. The control circuit then performs a data variation determination operation of determining whether the memory-cells connected to a selected word-line each have a threshold voltage equal to or less than a certain value to determine, from among the plurality of memory cells connected to the selected word-line, whether the number of memory cells where data variation has occurred is not less than a certain number. | 2012-10-04 |
20120250421 | CHARGE PUMP CIRCUIT USING LOW VOLTAGE TRANSISTORS - The charge pump circuit has a plurality of cascaded charge pump stages, each provided with a first pump capacitor connected to a first internal node and receiving a first high voltage phase signal, and a second pump capacitor connected to a second internal node and receiving a second high voltage phase signal, complementary with respect to the first. A first transfer transistor is coupled between the first internal node and an intermediate node, and a second transfer transistor is coupled between the second internal node and the intermediate node. The first and second high voltage phase signals have a voltage dynamics higher than a maximum voltage sustainable by the first and second transfer transistors. A protection stage is set between the first internal node and second internal node and respectively, the first transfer transistor and second transfer transistor, for protecting the same transfer transistors from overvoltages. | 2012-10-04 |
20120250422 | Interleaving Charge Pumps for Programmable Memories - Systems and methods, including computer software for performing operations enable interleaving of charging operations in a charging pump. A first charge pump is charged to a predetermined level, and a first operation is performed using a charge stored in the first charge pump after it reaches the predetermined level. A second charge pump is charged during a time that overlaps with performing the first operation. A second operation is performed using a charge stored in the second charge pump as a result of charging the second charge pump. | 2012-10-04 |
20120250423 | INPUT CIRCUIT - The first input circuit detects an input signal to output a first output signal having the same phase as the input signal. The second input circuit is configured to detect a first strobe signal to output a second output signal. The third input circuit is configured to detect a second strobe signal as a reversed signal of the first strobe signal to output a third output signal. A data latch circuit includes a first latch circuit and a second latch circuit. It is configured to latch the first output signal in either one of the first latch circuit or the second latch circuit according to the first output signal, the second output signal and the third output signal. It also allows the other one of the first latch circuit or the second latch circuit to input the first output signal thereto. | 2012-10-04 |
20120250424 | SEMICONDUCTOR MEMORY DEVICE - A sense amplifier circuit is connected to a bit-line and senses and amplifies a signal read from a memory cell. A first data latch is connected to a sense amplifier via a first bus. A second data latch is connected to a second bus. A plurality of circuit groups are repeatedly provided in a first direction, each circuit group comprising one sense amplifier circuit and one first data latch. The second data latch is provided between the circuit groups and an input/output buffer. | 2012-10-04 |
20120250425 | SEMICONDUCTOR MEMORY AND SEMICONDUCTOR MEMORY CONTROL METHOD - According to one embodiment, the semiconductor memory includes a memory cell array which includes memory cells to store data, a buffer circuit which includes latches, each of the latches including transistors as control elements and a flip-flop, and a control circuit which turns off the transistors to deactivate one or more of the latches. | 2012-10-04 |
20120250426 | Apparatus and Method to Adjust Clock Duty Cycle of Memory - An embodiment of the invention provides a memory controller for controlling a memory. The memory controller comprises a pulse width modulation module, a voltage comparator and a duty cycle calibration device. The pulse width modulation module is suitable for receiving a clock signal to generate a first voltage. The voltage comparator is suitable for receiving and comparing a reference voltage with the first voltage to output a comparison signal. The duty cycle calibration device is suitable for adjusting a duty cycle of the clock signal according to the comparison signal. | 2012-10-04 |
20120250427 | Multi-Mode Interface Circuit - An interface circuit having a first signal path and a second signal path is disclosed. The first and second signal paths are coupled between a first and second nodes, wherein the first node is coupled to receive signals from a source external to an integrated circuit upon which the interface circuit is implemented. Each of the first and second signal paths include circuitry implemented with transistors rated at higher voltages than internal circuitry coupled to receive signals therefrom. The first and second signal paths may utilize different circuit topologies. The interface may thus be used in environments where external circuitry coupled to the external input node conforms to one of a number of different standards (e.g., LPDDR1 and LPDDR2). | 2012-10-04 |
20120250428 | MEMORY DEVICE, RECORDING METHOD, AND RECORDING AND REPRODUCING METHOD - A memory device, includes a recording medium; a probe to write a plurality of the signals; a first driving portion to vibratory drive the recording medium; a detecting unit which, when the first driving portion changes a frequency to vibratory drive the recording medium, detects a change in an amplitude of the resonance drive, detects the frequency at which the amplitude becomes maximum as a resonance frequency; and a calculating unit which calculates a timing when the probe writes a plurality of the signals using the resonance frequency; wherein, the first driving portion vibratory drives the recording medium and the probe writes a plurality of the signals. | 2012-10-04 |
20120250429 | SECURITY-PROTECTION OF A WAFER OF ELECTRONIC CIRCUITS - A process is provided for fabricating a wafer including a plurality of chips separated by scribe lines. The method includes locking at least one chip on the wafer using a secret key, and writing the secret key into at least one memory present on the wafer. | 2012-10-04 |
20120250430 | CIRCUIT FOR PREVENTING A DUMMY READ IN A MEMORY - A memory includes a row decoder, column logic, and a memory array having a plurality of memory cells arranged in rows and columns. A plurality of write word lines are coupled to the row decoder. A plurality of complementary write word lines is coupled to the row decoder. A plurality of read bit lines is coupled to the column logic. A plurality of write bit lines is coupled to the column logic. A plurality of column decoded write enable lines is coupled to the column logic. Each memory cell of the plurality of memory cells is coupled to a corresponding write control circuit. Each write control circuit comprises a transmission gate coupled between a column decoded write enable line and an access transistor of a memory cell. The transmission gate is controlled by a write word line signal. | 2012-10-04 |
20120250431 | SEMICONDUCTOR MEMORY APPARATUS AND METHOD FOR DRIVING THE SAME - A semiconductor memory apparatus includes: a memory block including first and second planes; and a reset signal generator configured to generate a first reset signal by logically combining a first plane selection signal and a control pulse signal which pulses after a first programming setup pulse signal pulses during a first programming command cycle, and generate a second reset signal by logically combining a second plane selection signal and the control pulse signal which again pulses after a second programming setup pulse signal pulses during a second programming command cycle after the first programming command cycle. A plurality of first page buffers allocated to the first plane are reset in response to the first reset signal, and a plurality of second page buffers allocated to the second plane are reset in response to the second reset signal. | 2012-10-04 |
20120250432 | SEMICONDUCTOR DEVICE - To provide a semiconductor device which can perform initialization to a first state of two states of the first state and a second state, and which can generate a signal having a potential corresponding to the initialized first state. The present invention is the semiconductor device which can perform initialization to “0” (a first state) of two states of “0” and “1” (a second state), and which can generate a signal having a potential corresponding to initialized “0”. The semiconductor device | 2012-10-04 |
20120250433 | MEMORY DEVICES, SYSTEMS AND METHODS EMPLOYING COMMAND/ADDRESS CALIBRATION - During a command/address calibration mode, a memory controller may transmit multiple cycles of test patterns as signals to a memory device. Each cycle of test pattern signals may be transmitted at an adjusted relative phase with respect to a clock also transmitted to the memory device. The memory device may input the test pattern signals at a timing determined by the clock, such as rising and/or falling edges of the clock. The test pattern as input by the memory device may be sent to the memory controller to determine if the test pattern was successfully transmitted to the memory device during the cycle. Multiple cycles of test pattern transmissions are evaluated to determine a relative phase of command/address signals with respect to the clock for transmission during operation of the system. | 2012-10-04 |
20120250434 | METHOD OF ACCELERATING WRITE TIMING CALIBRATION AND WRITE TIMING CALIBRATION ACCELERATION CIRCUIT IN SEMICONDUCTOR MEMORY DEVICE - A method of accelerating write timing calibration and a write timing calibration acceleration circuit in a semiconductor memory device are disclosed. The write timing calibration acceleration circuit includes a phase difference detection unit and a detection data output unit. The phase difference detection unit detects a phase difference between a first signal and a second signal applied for a write timing calibration. The detection data output unit outputs detection data corresponding to the detected phase difference through a data output line. According to the write timing calibration acceleration circuit of the inventive concept, a time taken to perform a write timing calibration is reduced, thereby minimizing boot up time and power consumption. | 2012-10-04 |
20120250435 | SEMICONDUCTOR DEVICE AND METHOD OF COTNROLING THE SAME - A device includes a command decoder that is configured to output, in a normal operation mode, a precharge signal in response to a first type transition edge of a synchronous signal, and an active signal in response to a next first type transition edge that is next to the first type transition edge. The command decoder is configured to output, in a test mode, the precharge signal in response to a second type transition edge of the synchronous signal, and the active signal in response to a next first type transition edge that is next to the second type transition edge. | 2012-10-04 |
20120250436 | IMPEDANCE MATCHING BETWEEN FPGA AND MEMORY MODULES - Embodiments of the present invention provide impedance matching between a Field Programmable Gate Array (FPGA) and memory modules in a semiconductor storage device (SSD) system architecture. Specifically, a set (at least one) of memory modules is coupled to an FPGA. A damping resistor is placed at the impedance mismatching point to reduce signal noise. | 2012-10-04 |
20120250437 | SEMICONDUCTOR DEVICE, CONTROL METHOD THEREOF AND DATA PROCESSING SYSTEM - Disclosed herein is a semiconductor device comprising a global bit line, a first local bit line coupled to normal memory cells, a second local bit line coupled to redundant memory cells first and second hierarchical switches, a precharge circuit precharging the global bit line, a redundancy determination circuit determining whether or not an accessed address matches a defective address, and a control circuit. In a standby state, the global bit line and the second local bit line are precharged through the second hierarchical switch. In an active state, the first local bit line is precharged through the first hierarchical switch, subsequently when the redundancy determination circuit determines that the addresses do not match, the second hierarchical switch is inactivated to access the normal memory cells, and when the redundancy determination circuit determines that the addresses match each other, the first hierarchical switch is inactivated to access the redundant memory cells. | 2012-10-04 |
20120250438 | Dynamic random access memory address line test technique - Verification of the address connections of a memory ( | 2012-10-04 |
20120250439 | Degradation Equalization for a Memory - In an embodiment, an integrated circuit includes a memory and a control circuit configured to cause an inversion of at least a portion of the data stored in the memory to more evenly balance the amount of time that a given memory cell in the memory stores a binary one or a binary zero. In some implementations, the inversion may be controlled for the memory as a whole via a global indication. In other implementations, data may be inverted on a row-by-row or column-by-column basis. In other embodiments, the global indication may be changed at each boot of a device including the integrated circuit. | 2012-10-04 |
20120250440 | Differential read write back sense amplifier circuits and methods - A differential read write back sense amplifier circuit and corresponding methods. A memory array comprises a plurality of memory cells arranged in rows and columns; a plurality of read word lines coupled to the memory cells; a plurality of write word lines coupled to the memory cells arranged along rows of the memory array; a plurality of read bit line pairs coupled to the memory cells arranged in columns; a plurality of write bit line pairs coupled to the memory cells arranged in columns; and at least one differential read write back sense amplifier coupled to a read bit line pair and coupled to a write bit line pair corresponding to one of the columns of memory cells, configured to differentially sense small signal read data on the read bit line pair, and output the sensed data onto the write bit line pair. Corresponding methods are disclosed. | 2012-10-04 |
20120250441 | Separate Pass Gate Controlled Sense Amplifier - A memory system that includes a first bit line coupled to a first set of dynamic random access memory (DRAM) cells, a second (complementary) bit line coupled to a second set of DRAM cells, and a sense amplifier coupled to the first and second bit lines. The sense amplifier includes a pair of cross-coupled inverters (or a similar latching circuit) coupled between the first and second bit lines, as well as a first select transistor coupling the first bit line to a first global bit line, and a second select transistor coupling the second bit line to a second global bit line. The first and second select transistors are independently controlled, thereby enabling improved read and write access sequences to be implemented, whereby signal loss associated with bit line coupling is eliminated, ‘read bump’ conditions are eliminated, and late write conditions are eliminated. | 2012-10-04 |
20120250442 | Methods For Accessing DRAM Cells Using Separate Bit Line Control - A memory system that includes a first bit line coupled to a first set of dynamic random access memory (DRAM) cells, a second (complementary) bit line coupled to a second set of DRAM cells, and a sense amplifier coupled to the first and second bit lines. The sense amplifier includes a pair of cross-coupled inverters (or a similar latching circuit) coupled between the first and second bit lines, as well as a first select transistor coupling the first bit line to a first global bit line, and a second select transistor coupling the second bit line to a second global bit line. The first and second select transistors are independently controlled, thereby enabling improved read and write access sequences to be implemented, whereby signal loss associated with bit line coupling is eliminated, ‘read bump’ conditions are eliminated, and late write conditions are eliminated. | 2012-10-04 |
20120250443 | Energy Efficient Power Distribution for 3D INTEGRATED CIRCUIT Stack - Multiple dies can be stacked in what are commonly referred to as three-dimensional modules (or “stacks”) with interconnections between the dies, resulting in an IC module with increased circuit component capacity. Such structures can result in lower parasitics for charge transport to different components throughout the various different layers. | 2012-10-04 |
20120250444 | PSEUDO-INVERTER CIRCUIT ON SeOI - A circuit made on a semiconductor-on-insulator substrate. The circuit includes a first transistor having a first channel, a second transistor having a second channel, with the transistors provided in serial association between first and second terminals for applying a power supply potential, each of the transistors comprising a drain region and a source region in the thin layer, a channel extending between the source region and the drain region, and a front control gate located above the channel. Each transistor has a back control gate formed in the base substrate below the channel of the transistor and capable of being biased in order to modulate the threshold voltage of the transistor. At least one of the transistors is configured for operating in a depletion mode under the action of a back gate signal which will sufficiently modulate its threshold voltage. | 2012-10-04 |
20120250445 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes a programmable logic chip configured to output a control signal, and a memory chip coupled to the programmable logic chip. The memory chip includes a plurality of memory cores, a plurality of bus-interface circuits each configured to couple with the memory cores, and a selection circuit configured to couple the memory cores with one of the bus-interface circuits in response to a predetermined logic level of the control signal. | 2012-10-04 |
20120250446 | Fluid Dispensing System and Method for Concrete Mixer - System and method for dispensing liquids into concrete mixer drums, particularly suitable for use on concrete mix trucks, involve use of liquid admixtures nozzle that is separate from water conduit and water nozzle, the admixtures nozzle being aimed and focused to spray through drum opening with dispersion pattern substantially within air/concrete interface defined by minimal volume concrete contained within the drum; and the water conduit or nozzle having a dispersion pattern preferably whereby wash water hits a portion of the inner drum wall and a portion of the air/concrete interface defined by a maximum amount of concrete contained within the drum. In preferred embodiments, a check valve assembly is used to connect separate admixture and water lines, so that both admixture and water nozzles can be used simultaneously during purging operation. | 2012-10-04 |
20120250447 | CLAY MIXING APPARATUS - A clay mixing apparatus includes a mixing chamber, a rotor arranged within the mixing chamber, a drive unit arranged to rotate the rotor, an ejecting unit, a pressure reducing unit; and an exhaust flow path. The rotor includes a shaft rotated by the drive unit, an extruding member and a mixing member. The mixing member includes a plurality of arms and a plurality of blades arranged at tip ends of the arms. The exhaust opening is opposed, in a radial direction about the center axis, to a portion of the mixing member lying near the extruding member and/or a portion of the extruding member lying near the mixing member. | 2012-10-04 |
20120250448 | DEVICE FOR MAKING MIXED DRINK - Disclosed is a blended liquor maker, including: a cup having a receiving space defined therein, wherein the cup includes an opened top portion, a curved portion continuously bended along a side surface thereof, and at least one inclined-stepped annular portion formed on an inner peripheral surface thereof; and at least one separation plate having a circular flat plate shape, wherein, when received in the receiving space of the cup, the at least one separation plate is caught and fixed at an edge thereof on the stepped annular portion to divide the receiving space into upper and lower portions. In this case, the separation plate received inside the cup can be adjusted in height by pushing down the separation plate to bend the edge, thereby allowing users to suitably divide the receiving space of the cup. Accordingly, amounts of contents (e.g., spirits, beer, soju, beverages and the like) to be received in the cup can be properly adjusted to be suitable to the preference of users, thereby increasing the effectiveness of using thereof. | 2012-10-04 |
20120250449 | SYSTEM FOR MANUFACTURING EMULSIFIED/DISPERSED LIQUID - A system for manufacturing an emulsified/dispersed liquid has first and second emulsification/dispersion devices which produce the emulsified/dispersed liquid by emulsifying/dispersing emulsification/dispersion material in a liquid mixture into a medium liquid in the liquid mixture. A multistage pressure/temperature control device of a multistage type cools the emulsified/dispersed liquid discharged by the second emulsification/dispersion device while applying a backpressure which can prevent occurrence of bubbling to the first and second emulsification/dispersion devices. The multistage pressure/temperature control device reduces the pressure of the emulsified/dispersed liquid gradually or in stages, and finally lowers the pressure of the emulsified/dispersed liquid to a pressure that bubbling is not caused if the emulsification/dispersion liquid is released into an atmospheric condition. The system can apply sufficient shearing force to the liquid mixture so as to sufficiently atomize the emulsification/dispersion material. | 2012-10-04 |
20120250450 | EXTERNAL MIXING DEVICE - An external mixing device comprises: arranging an inlet and an outlet on the single-use container; a sterilizable or a single-use pump head connected to the inlet and outlet with a mixer installed inside. Driven by a driving device, the mixer makes the liquid circulate continuously between the pump head and the single-use container. The external mixing device further comprises a sensor chamber installed with a plurality of sensors and extra ports, which are used for introducing solution or gas inside or for sampling and detecting liquid properties. A single-use connector is used to connect the single-use container to the external mixing device, which can be operated aseptically under general environment. The external mixing device is small-sized with the advantage of simplified operation procedures. | 2012-10-04 |
20120250451 | Method of Homogenizing a Liquid - Method of homogenizing a liquid, in particular a colorant for paint, in a container, comprising the steps of withdrawing liquid from the container at a first flow speed (S | 2012-10-04 |
20120250452 | METHODS FOR MANIPULATING LIQUID SUBSTANCES IN MULTI-CHAMBERED RECEPTACLES - A receptacle having a plurality of interconnected chambers arranged to permit multiple process steps or processes to be performed independently or simultaneously. The receptacles are manufactured to separate liquid from dried reagents and to maintain the stability of the dried reagents. An immiscible liquid, such as an oil, is included to control loading of process materials, facilitate mixing and reconstitution of dried reagents, limit evaporation, control heating of reaction materials, concentrate solid support materials to prevent clogging of fluid connections, provide minimum volumes for fluid transfers, and to prevent process materials from sticking to chamber surfaces. The receptacles can be adapted for use in systems having a processing instrument that includes an actuator system for selectively moving fluid substances between chambers and a detector. The actuator system can be arranged to concentrate an analyte present in a sample. The detector can be used to detect an optical signal emitted by the contents of the receptacle. | 2012-10-04 |
20120250453 | Torque limiting disposable agitator for a food mixer - An agitator ( | 2012-10-04 |
20120250454 | METHOD AND SYSTEM FOR SHAPING A CMUT MEMBRANE - The present disclosure is directed at a method and system for shaping a membrane a capacitive micromachined ultrasonic transducer, or CMUT. A bias voltage is asymmetrically applied to a membrane of the CMUT such that the membrane is directed to send ultrasonic waves that propagate along a propagation axis that is not parallel with a propagation axis along which ultrasonic waves propagate when the bias voltage is symmetrically applied to the membrane. In this way, the ultrasonic waves that are generated using a CMUT array can be physically steered to or focused on a target. Steering and focusing ultrasonic waves by altering the shape of the membrane by asymmetrically biasing the membrane reduces grating lobes and can also be used as part of an adaptive control system that can improve ultrasound image quality. | 2012-10-04 |
20120250455 | SELECTING A SURVEY SETTING FOR CHARACTERIZING A TARGET STRUCTURE - Complex-valued sensitivity data structures corresponding to respective candidate survey settings are provided, where the sensitivity data structures relate measurement data associated with a target structure to at least one parameter of a model of the target structure. Based on the sensitivity data structures, a subset of the candidate survey settings is selected according to a criterion for enhancing resolution in characterizing the target structure. | 2012-10-04 |
20120250456 | SYSTEMS AND METHODS FOR ENERGY HARVESTING IN A GEOPHYSICAL SURVEY STREAMER - A disclosed geophysical survey system includes one or more streamers having sensors powered by at least one energy harvesting device that converts vibratory motion of the streamers into electrical power. The vibratory motion may originate from a number of sources including, e.g., vortex shedding, drag fluctuation, breathing waves, and various flow noise sources including turbulent boundary layers. To increase conversion efficiency, the device may be designed with an adjustable resonance frequency. The design of the streamer electronics may incorporate the energy harvesting power source in a variety of ways, so as to reduce the amount of wiring mass that would otherwise be required along the length of the streamer. | 2012-10-04 |
20120250457 | SYSTEMS AND METHODS FOR WIRELESS COMMUNICATION IN A GEOPHYSICAL SURVEY STREAMER - A disclosed survey method includes towing geophysical survey streamers in a body of water and using sensors within the streamer to collect measurements that are then conveyed along the streamer to a recording station using at least one wireless transmission link. In some implementations at least one sensor is coupled to a wireless transceiver in a streamer to transmit geophysical survey measurement data along the streamer to a wireless base station. The base station receives the wirelessly transmitted seismic data and communicates it to a central recording station. Each segment of the streamer may contain a base station to collect wireless data from the sensors in that segment, and each base station may be coupled to the central recording station by wiring (e.g., copper or fiber optic). Other implementations employ ranges of sensors wired to local transceivers that form a peer-to-peer wireless network for communicating data to the central recording station. | 2012-10-04 |
20120250458 | ANTI-BARNACLE NET AND METHOD - Method and an array of streamers that prevent/slow down marine animals to attach to the streamers. The array includes at least one streamer including plural sections; and a net provided over at least one section of the at least one streamer. | 2012-10-04 |
20120250459 | METHODS FOR SEISMIC FRACTURE PARAMETER ESTIMATION AND GAS FILLED FRACTURE IDENTIFICATION FROM VERTICAL WELL LOG DATA - Methods for fracture characterization of unconventional formations are provided. Synthetic seismic fracture responses can be generated based on the derived fracture parameters. The synthetic seismic fracture responses may then be used to derive optimum seismic data acquisition geometry for fracture characterization. These methods of determining the seismic data acquisition geometry are advantageous over conventional methods in that these methods are more reliable and cheaper than existing empirical methods, particularly as applied to fractured unconventional formations. Moreover, these methods allow fracture parameters to be derived from limited but common well log data. Certain embodiments additionally contemplate determining the presence of gas filled fractures. These characterizations and evaluations of unconventional formations are useful for, among other things, determining optimal producing intervals and optimal drilling locations. These methods can eliminate the use of costly image logs and core data. These methods ultimately translate to more efficient seismic imaging and more optimal hydrocarbon production. | 2012-10-04 |
20120250460 | NOISE ATTENUATION USING ROTATION DATA - Measured seismic data is received from a seismic sensor. Rotation data is also received, where the rotation data represents rotation with respect to at least one particular axis. The rotation data is combined, using adaptive filtering, with the measured seismic data to attenuate at least a portion of a noise component from the measured seismic data. | 2012-10-04 |
20120250461 | TRANSMITTER AND RECEIVER SYNCHRONIZATION FOR WIRELESS TELEMETRY SYSTEMS - An acoustic modem for communication in a network of acoustic modems via a communication channel. The acoustic modem comprises a transceiver assembly, transceiver electronics, and a power supply. The transceiver assembly is adapted to convert acoustic messages into electrical signals. The transceiver electronics is provided with transmitter electronics and receiver electronics. The transmitter electronics cause the transceiver assembly to send acoustic signals into the communication channel. The receiver electronics comprises at least one microcontroller adapted to execute instructions to (1) enable the receiver electronics to receive electrical signals indicative of the acoustic message from at least one other acoustic modem via the transceiver assembly, (2) estimate a carrier frequency of the electrical signals by analyzing an estimation frame of the electrical signals, (3) estimate a starting time of a data frame of the electrical signals by synchronizing with a synchronization frame of the acoustic message in parallel with at least two bit rates, and (4) decode the data frame. The power supply supplies power to the transceiver assembly and the transceiver electronics. | 2012-10-04 |
20120250462 | TRANSMIT/RECEIVE SYSTEMS FOR IMAGING DEVICES - A transceiver for an ultrasonic imaging device includes a transmit circuit and a receive circuit. The transmit circuit outputs test pulses to a probe including a transducer to generate an image of a test object. A composite signal including the test pulses and a reflected signal is output by the transducer. The receive circuit receives the composite signal including the test pulses and the reflected signal and includes a filter circuit. The filter circuit filters the test pulses from the composite signal and passes the reflected signal. An impedance of the filter circuit is equal to substantially zero when the reflected signal is within a predetermined frequency range. | 2012-10-04 |
20120250463 | GUIDING SOUND GENERATING APPARATUS AND NON-TRANSITORY COMPUTER READABLE MEDIUM - A guiding sound generating apparatus which generates a guiding sound for guidance from a present location to a destination, the apparatus having a sound source, a variable sound-source attribute unit that changes a sound source attribute depending on a position or a positional change of a present location with respect to a destination, and an attribute-application unit that applies the sound-source attribute generated from the variable sound-source attribute unit to the sound source and generates a guiding sound where a sound-source attribute is changed by the position or positional change of the present location with respect to the destination. | 2012-10-04 |
20120250464 | THERMOACOUSTIC DEVICE - A thermoacoustic device includes a sound wave generator and a signal input device. The sound wave generator includes a carbon film. The carbon film includes at least one carbon nanotube layer and at least one graphene layer stacked on each other. The signal input device inputs signals to the sound wave generator. | 2012-10-04 |
20120250465 | COUPLING ELEMENT FOR ACOUSTICALLY COUPLING A SOUND TRANSDUCER TO A BODY, AND SOUND TRANSDUCER COMPRISING SAID COUPLING ELEMENT - The invention relates to a coupling element for acoustically coupling a sound transducer to a body for transmitting high-frequency structure-borne noise from the sound transducer to the body and/or from the body to the sound transducer, wherein the coupling element includes a deformable contact region for positively contacting the body. | 2012-10-04 |
20120250466 | Universal Mounting Appliance for a Marine Transducer - The invention provides advances in the arts with useful and novel mounting devices for mounting a transducer or other device to a watercraft hull. Preferred embodiments include a forward plate to mount to the transom of the boat hull, a first housing to detachably connect to the forward plate, and a second housing to detachably connect to the first housing in an arrangement suitable for mounting a transducer or other device. | 2012-10-04 |
20120250467 | ESCAPEMENT MECHANISM IN PARTICULAR FOR A TIMEPIECE MOVEMENT - The constant force escapement mechanism in particular for a timepiece movement including a spring balance and an escapement gear connected to a barrel by a going train includes a constant force auxiliary spring ( | 2012-10-04 |
20120250468 | ESCAPEMENT MECHANISM IN PARTICULAR FOR A TIMEPIECE MOVEMENT - A timepiece movement includes an escapement mobile connected to a barrel by a going train and a spring balance as well as an escapement mechanism ( | 2012-10-04 |
20120250469 | Apparatus and Method of Keeping Time of Day Over an Industrial Temperature Range - Various embodiments of the invention relate generally to real-time clock circuit, and more particularly to systems, devices and methods of integrating two oscillators in one real-time clock circuit to generate accurate time of day over an industrial temperature range. A primary oscillator is employed to generate a first high precision clock while having a higher frequency and consuming more power; a secondary oscillator is employed to generate a second clock that has a low frequency and consumes less power, but may not meet the time accuracy requirement. When the real-time clock is provided with sufficient power (MSN mode), time of day is constantly tracked by the primary oscillator, but when the real-time clock is powered by a battery (SLEEP mode), time of day is tracked by the secondary oscillator while the primary oscillator is switched on at an update frequency to compensate errors in the time of day. | 2012-10-04 |
20120250470 | Electronic Device and Method Providing Improved Indication that an Alarm Clock is in an on Condition - An improved electronic device and method provide an improved clock feature having an alarm clock function that advantageously provides an indication to a user that the alarm is set, i.e., is in an ON condition, by outputting the alarm time itself. | 2012-10-04 |
20120250471 | BRACELET WITH COMFORT PAD - A bracelet strand ( | 2012-10-04 |
20120250472 | MAGNETIC HEAD FOR MICROWAVE ASSISTED MAGNETIC RECORDING - A magnetic head that writes information to a recording medium includes a magnetic pole layer that generates a writing magnetic field to the recording medium, a microstripline that is disposed in proximity to the magnetic pole layer and to which high frequency current is applied, and a ferromagnetic thin film that is disposed on a portion of the microstripline that faces the recording medium, and that generates a high frequency alternate-current (AC) magnetic field to be applied to the recording medium, using a current magnetic field generated on the microstripline due to the high frequency current. | 2012-10-04 |
20120250473 | METHOD AND DEVICES FOR COPY PROTECTION, COPY PROTECTED RECORD CARRIER - A method for copy protection includes providing audiovisual or audio data stored in sectors of a record carrier having a file system, and providing additional or modified data to be stored in further sectors. The method includes generating a first file of the file system referencing at least a part of the sectors and none of the further sectors, so when the first file is rendered by a playback device, the data is reproduced which is included in the part of the sectors. The method also includes generating a second file of the file system being another file than the first file and referencing at least a part of the sectors and further referencing at least one of the further sectors, such that when the second file is rendered by the playback device the part of the sectors and the at least one of the further sectors are reproduced. | 2012-10-04 |
20120250474 | OPTICAL DISK APPARATUS - An optical disk apparatus which conducts overwriting of data on a rewritable optical disk or conducts write-once recording of data on a write-once optical disk includes a control unit for receiving a recording command which specifies a recording area and orders recording and receiving transfer data, and a collation unit for collating existing data on the optical disk with the transfer data. Upon reception of the recording command and the transfer data by the control unit, the existing data is collated with the transfer data by the collation unit, and overwrite recording of data in places where the transfer data is different from the existing data is conducted on the rewritable optical disk, or data in places where the transfer data is different from the existing data is recorded in an unrecorded area of the write-once optical disk. | 2012-10-04 |
20120250475 | RECORDING AND/OR REPRODUCING APPARATUS - A recording and/or reproducing apparatus includes a recording medium accommodation table including recording medium accommodation portions each capable of accommodating a recording medium, a recording medium drive unit on which the recording medium is removably mounted and which is capable of performing recording and/or reproduction of an information signal onto and/or from it, a mechanical chassis that supports the recording medium accommodation table to freely rotate and also support the recording medium drive unit to be movable, a drive-moving unit that moves the recording medium drive unit closer to and away from the recording medium accommodation table, and a recording medium transport unit that transports the recording medium between a recording medium mounting and removing position of a recording medium-mounting portion and a recording medium accommodation position of the recording medium accommodation portions. | 2012-10-04 |
20120250476 | RECORDING/REPRODUCING DEVICE - The present invention relates to a recording/reproducing device that records data on a double-sided recordable optical disk for storage and management purposes. The device includes a unit which stores a plurality of optical disks, a unit which records data onto and reproduces data from an upper side of an optical disk, a unit which records data onto and reproduces data from a lower side of an optical disk, a unit which conveys an optical disk between the disk storage unit and each recording/reproducing unit. When a request for reading data recorded on the lower side of the disk is received while the upper side is being written onto, a control unit interrupts a data recording process on the upper side, reproduces data recorded on the lower side, and after completion of reproducing the recorded data, resumes the interrupted data recording process. | 2012-10-04 |
20120250477 | METHOD AND DEVICES FOR COPY PROTECTION, COPY PROTECTED RECORD CARRIER - A method for copy protection includes providing audiovisual or audio data stored in sectors of a record carrier having a file system, and providing additional data to be stored in further sectors. The method includes generating first and second files referencing respective first and second parts of the sectors and respective further first and second parts of the further sectors, so when the first and second files are completely rendered by a playback device, respective first and second parts of the data and respective further first and second parts of the additional data are reproduced. The method also includes determining program instructions, which when executed by the playback device, control switching between reading the first file and the second file, and when the record carrier is an original, switching is controlled so only the sectors and none of the further sectors are read such that no additional data is reproduced. | 2012-10-04 |
20120250478 | OPTICAL DISC APPARATUS - An optical disc apparatus, for recording or reproducing information by irradiating a laser beam on an optical disc. More particularly, the present application relates to an optical pickup of the optical disc apparatus that produces a tracking error signal, in general, and the optical disc apparatus executes a tracking servo with using the tracking error signal. | 2012-10-04 |
20120250479 | ELECTRON BEAM EXPOSURE SYSTEM AND ELECTRON BEAM EXPOSURE METHOD - When applying an electron beam to a master substrate of disk-shaped recording medium placed on a rotation stage, while rotating the master substrate by rotating the rotation stage, to write a master pattern of disk-shaped recording medium on the master substrate, causing the writing to be suspended based on abnormality information of environment and storing a rotation angle of the master substrate when the writing is suspended and causing, thereafter, the writing to be resumed from a suspended position of the writing on the master substrate based on the rotation angle. | 2012-10-04 |
20120250480 | METHOD FOR ADJUSTING RECORDING CONDITION, OPTICAL DISC DEVICE, AND INFORMATION RECORDING METHOD - Provided is a recording adjustment method capable of controlling an edge position of a mark with high accuracy. Based on the acquired read-out signal waveform, a starting position of a last pulse is adjusted such that a so-called L-SEAT shift value for an end edge of the mark becomes minimum. | 2012-10-04 |
20120250481 | DISC DEVICE - Provided is an optical disc drive device which stably controls an actuator of an optical pickup, by individually controlling an optical spot when following the guide track and an optical spot when recording/reproducing information on/from each recording layer. An optical spot when following the guide track and an optical spot when recording/reproducing information on/from each recording layer are individually controlled. At this time, the optical spot exclusive for the track and the optical spot exclusive for the recording/reproducing are formed on an optical disc. | 2012-10-04 |
20120250482 | OPTICAL DISC DEVICE AND RECORDING METHOD - An optical disc device and a recording method is provided in which information can be additionally recorded on an optical disc, which has a servo layer and recording layers separately formed, by accurately correcting a relative angle between a light beam and the optical disc used in the previous recording without providing an area where recording is not performed while maintaining the stability of tracking servo. The above subject can be solved by studying with high accuracy the relative angle between the optical disc and the optical axis used in the previous recording by applying a radial tilt servo according to a signal from the recording layers with the tracking servo applied by the servo layer. Further, the additional recording can be performed stably by fixing the radial tilt at the previously studied angle when the recording is performed. | 2012-10-04 |
20120250483 | WRITE POWER ADJUSTMENT METHOD AND INFORMATION RECORDING METHOD - In write power adjustment for an optical disc having a plurality of information storage layers, data of trial writing is varied by the influence of layers other than a target layer. It is difficult, therefore, to determine optimal write power. A modulation M[m] is obtained from a reproduction signal amplitude of a signal subjected to the trial writing performed with use of write powers Pw[m] (m being an integer) of a plurality of kinds. At least an optimum write power intercept Pint_opt is determined by fitting a relation between the Pw[m] and the M[m] by a modulation characteristic formula M=Masy×(1−(Pint−Pasy)/(Pw−Pasy)) having an asymptotic modulation Masy, a write power intercept Pint, and an asymptotic write power Pasy as parameters. Approximation accuracy by the fitting and/or quality of the trial writing signal are evaluated with use of at least the M[m], the modulation characteristic formula, and the Pint_opt. An optimum write power Pw_opt is calculated by performing a specified operation at least with use of the Pint_opt. | 2012-10-04 |
20120250484 | PROXIMITY SENSING SYSTEM - A data storage system for detecting a location of a head relative to a magnetic media is described. This system comprises arms, a preamplifier circuit coupled to the arms for controlling the arms, a proximity sensing system positioned within the preamplifier circuit, the proximity sensing system comprising: an input stage for transmitting an input sense signal; a programmable gain stage coupled to receive the input sense signal and operative for transmitting a gain signal in response to receiving the input sense signal; a multiplexer coupled to receive the gain signal and at least one control signal, the multiplexer operative for transmitting a multiplexed signal; a detector coupled to receive the multiplexed signal and a second control signal, the detector operative for transmitting an output signal; wherein an amplitude associated with the output signal enables detecting the location of the head. | 2012-10-04 |
20120250485 | RECORDING/REPRODUCING APPARATUS AND RECORDING/PRODUCING SYSTEM - A recording/reproducing apparatus includes an optical source and a near-field light generating unit. The near-field light generating unit includes two conductors facing to each other at a predetermined distance and generating near-field light between the two conductors by irradiation of light from the optical source. These two conductors are arranged so that a direction along which the two conductors face to each other is substantially in parallel with the longitudinal direction of a recording mark region. Here, the recording mark region is prepared from a predetermined recording material and having shape anisotropy when information is recorded on a recording medium on which the recording mark is independently formed. | 2012-10-04 |
20120250486 | METHOD AND APPARATUS FOR READING FROM AND/OR WRITING TO AN OPTICAL RECORDING MEDIUM - A method and an apparatus for reading data from or writing data to an optical recording medium is described, the data being stored as marks having different lengths. Marks having a length below the limit of diffraction at a first wavelength are read or written with the first wavelength, whereas marks having a length above the limit of diffraction at the first wavelength are read or written with a second wavelength larger than the first wavelength. | 2012-10-04 |
20120250487 | ELASTIC MEMBER, MOUNTING STRUCTURE OF OPTICAL ELEMENT, AND PICKUP APPARATUS HAVING THE SAME - A mounting structure of an optical element, includes: an optical element; an elastic member usable when the optical element is mounted; and a holding unit configured to be mounted with the optical element and the elastic member, the elastic member configured to be pressed into the holding unit, the holding unit configured to be mounted with the optical element by use of the elastic member. | 2012-10-04 |
20120250488 | ROTOR HUB, MOTOR, AND DISK DRIVING DEVICE - A rotor hub includes a shaft connecting portion arranged to be connected to a shaft serving as a central axis, a disk loading portion centered about the central axis and arranged to support a disk shaped storage medium mounted thereon, a yoke arranged below the disk loading portion and supporting a field magnet at one of an inner side surface thereof and an outer side surface thereof, and a flexible portion connecting the disk loading portion to the yoke and being flexible with respect to a force applied thereto from the yoke. | 2012-10-04 |
20120250489 | VIBRATION-REDUCED TURNTABLE - The present document describes a vibration-reduced turntable adapted to receive a disc, the vibration-reduced turntable comprising: a frame; a first platter mounted on the frame and for receiving the disc, the first platter for rotation in a first direction; a second platter mounted on one of: the frame and the first platter, the second platter for rotation in a second direction; and a suspension system supporting the frame for reducing vibrations on the disc received by the first platter and for reducing vibrations of the frame. | 2012-10-04 |
20120250490 | SYSTEMS AND METHODS FOR BYPASSING FAILED LINE CARDS IN MULTI-CARD VECTORING GROUPS - A communication system comprises a plurality of line cards having transceivers coupled to a plurality of subscriber lines. Each line card has at least one active transceiver within the same vectoring group, and each line card also has vector logic capable of cancelling crosstalk induced by an active transceiver that is a member of the vectoring group. Further, the line cards are coupled to one another via a ring connection across which vectoring information is passed from one line card to the next. In the event of a failure of one of the line cards, the failed card is bypassed by the vectoring stream so that the operational line cards can continue crosstalk vectoring operations despite such failure. | 2012-10-04 |
20120250491 | SYSTEMS AND METHODS FOR ADJUSTING TIME SLOTS OF VECTORING STREAMS BASED ON BIT LOADING - A communication system comprises a plurality of line cards having transceivers coupled to a plurality of subscriber lines. Each line card has at least one transceiver within the same vectoring group, and each line card also has vector logic capable of cancelling crosstalk induced by a tone communicated by any member of the vector group. Further, the line cards are coupled to one another via a data connection across which a vectoring stream carrying vectoring information from one line card to the next. The bandwidth of the vectoring stream is reduced by dynamically adjusting time slots of the vectoring stream based on bit loading for the communicated tones. | 2012-10-04 |