40th week of 2013 patent applcation highlights part 19 |
Patent application number | Title | Published |
20130256764 | GATE STACK OF FIN FIELD EFFECT TRANSISTOR - The description relates to a gate stack of a fin field effect transistor (FinFET). An exemplary structure for a FinFET includes a substrate including a first surface and an insulation region covering a portion of the first surface, where a top of the insulation region defines a second surface. The FinFET further includes a fin disposed through an opening in the insulation region to a first height above the second surface, where a base of an upper portion of the fin is broader than a top of the upper portion, wherein the upper portion has first tapered sidewalls and a third surface. The FinFET further includes a gate dielectric covering the first tapered sidewalls and the third surface and a conductive gate strip traversing over the gate dielectric, where the conductive gate strip has second tapered sidewalls along a longitudinal direction of the fin. | 2013-10-03 |
20130256765 | SEMICONDUCTOR DEVICE - A semiconductor device is disclosed. The semiconductor device includes: a substrate; a gate structure disposed on the substrate; a first spacer disposed on a sidewall of the gate structure; a second spacer disposed around the first spacer, wherein the second spacer comprises a L-shaped cap layer and a cap layer on the L-shaped cap layer; a source/drain disposed in the substrate adjacent to two sides of the second spacer; and a CESL disposed on the substrate to cover the gate structure, wherein at least part of the second spacer and the CESL comprise same chemical composition and/or physical property. | 2013-10-03 |
20130256766 | SPACER AND PROCESS TO ENHANCE THE STRAIN IN THE CHANNEL WITH STRESS LINER - Process for enhancing strain in a channel with a stress liner, spacer, process for forming integrated circuit and integrated circuit. A first spacer composed of a first oxide and first nitride layer is applied to a gate electrode on a substrate, and a second spacer composed of a second oxide and second nitride layer is applied. Deep implanting of source and drain in the substrate occurs, and removal of the second nitride, second oxide, and first nitride layers. | 2013-10-03 |
20130256767 | SOURCE/DRAIN CONTACTS FOR NON-PLANAR TRANSISTORS - The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of source/drain contacts within non-planar transistors, wherein a titanium-containing contact interface may be used in the formation of the source/drain contact with a discreet titanium silicide formed between the titanium-containing interface and a silicon-containing source/drain structure. | 2013-10-03 |
20130256768 | Floating diffusion pre-charge - An array comprises a plurality of pixels logically arranged in rows and columns. The pixels comprise a photoreceptor ( | 2013-10-03 |
20130256769 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Provided are a semiconductor device and a method of fabricating the same. The semiconductor device may include storage node pads disposed adjacent to each other between word lines but spaced apart from each other by an isolation pattern. Accordingly, it is possible to prevent a bridge problem from being caused by a mask misalignment. This enables to improve reliability of the semiconductor device. | 2013-10-03 |
20130256770 | TRANSISTOR, SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR MODULE INCLUDING THE SAME - A semiconductor device including a buried cell array transistor and an electronic device including the same are provided. The device includes a field region in a substrate and the filed region defines an active region. A first source/drain region and a second source/drain region are in the active region. A gate trench is between the first and second source/drain regions, and in the active region and the field region. A gate structure is within the gate trench. The gate structure includes a gate electrode, an insulating gate capping pattern on the gate electrode, a gate dielectric between the gate electrode and the active region, and an insulating metal-containing material layer between the insulating gate capping pattern and the active region. | 2013-10-03 |
20130256771 | SEMICONDUCTOR DEVICE - The semiconductor device includes a source line, a bit line, a signal line, a word line, memory cells connected in parallel between the source line and the bit line, a first driver circuit electrically connected to the source line and the bit line through switching elements, a second driver circuit electrically connected to the source line through a switching element, a third driver circuit electrically connected to the signal line, and a fourth driver circuit electrically connected to the word line. The memory cell includes a first transistor including a first gate electrode, a first source electrode, and a first drain electrode, a second transistor including a second gate electrode, a second source electrode, and a second drain electrode, and a capacitor. The second transistor includes an oxide semiconductor material. | 2013-10-03 |
20130256772 | Multiple-Time Programming Memory Cells and Methods for Forming the Same - A device includes an active region and a coupling capacitor. The capacitor includes a first floating gate as an upper capacitor plate of the coupling capacitor, and a doped semiconductor region as a lower capacitor plate of the coupling capacitor. The doped semiconductor region includes a surface portion at a surface of the active region, and a sidewall portion lower than a bottom surface of the surface portion. The sidewall portion is on a sidewall of the active region. A capacitor insulator is disposed between the upper capacitor plate and the lower capacitor plate. The capacitor insulator includes an upper portion, and a sidewall portion lower than a bottom surface of the upper portion. | 2013-10-03 |
20130256773 | ELECTRICALLY ERASABLE PROGRAMMABLE NON-VOLATILE MEMORY - In an embodiment of the invention, a method of fabricating a floating-gate PMOSFET (p-type metal-oxide semiconductor field-effect transistor) is disclosed. A silicide blocking layer (e.g. oxide, nitride) is used not only to block areas from being silicided but to also form an insulator on top of a poly-silicon gate. The insulator along with a top electrode (control gate) forms a capacitor on top of the poly-silicon gate. The poly-silicon gate also serves at the bottom electrode of the capacitor. The capacitor can then be used to capacitively couple charge to the poly-silicon gate. Because the poly-silicon gate is surrounded by insulating material, the charge coupled to the poly-silicon gate may be stored for a long period of time after a programming operation. | 2013-10-03 |
20130256774 | SEMICONDUCTOR MEMORY DEVICES - Semiconductor memory devices may include a write transistor including a first write gate controlling a first source/drain terminal and a second write gate controlling a channel region, and a read transistor including a memory node gate connected to the first source/drain terminal of the write transistor. The first write gate may have a first work function and the second write gate may have a second work function different from the first work function. The first source/drain terminal of the write transistor may not have a PN junction. | 2013-10-03 |
20130256775 | THREE-DIMENSIONAL MICROELECTRONIC DEVICES INCLUDING HORIZONTAL AND VERTICAL PATTERNS - A vertical NAND flash memory device includes a substrate having a face and a string of serially connected flash memory cells on the substrate. A first flash memory cell is adjacent the face, and a last flash memory cell is remote from the face. The flash memory cells include repeating layer patterns that are stacked on the face, and a pillar that extends through the series of repeating layer patterns. The pillar includes at least one oblique wall. At least two of the series of repeating layer patterns in the string are of different thicknesses. Other vertical microelectronic devices and related fabrication methods are also described. | 2013-10-03 |
20130256776 | DOUBLE-GATE ELECTRONIC MEMORY CELL AND METHOD OF MANUFACTURING SUCH A CELL - An electronic memory cell includes a first selection transistor gate surmounting a first part of the channel and a lateral spacer disposed against a lateral flank of the selection transistor gate, a part of the lateral spacer forming a memory transistor gate surmounting a second part of the channel. The memory transistor gate includes a stack of the ONO type and a conductive zone including a lateral face inclined at an angle α strictly between 0 and 90° with respect to the plane of the substrate. | 2013-10-03 |
20130256777 | THREE DIMENSIONAL FLOATING GATE NAND MEMORY - Memory arrays that include a first memory cell having a channel; a first insulator; a floating gate; a second insulator; and a control gate, wherein the first insulator is positioned between the channel and the floating gate, the second insulator is positioned between the floating gate and the control gate; and a second memory cell having a channel; a first insulator; a floating gate; a second insulator; and a control gate, wherein the first insulator is positioned between the channel and the floating gate, the second insulator is positioned between the floating gate and the control gate, wherein the first memory cell and the second memory cell are positioned parallel to each other. | 2013-10-03 |
20130256778 | SEMICONDUCTOR MEMORY DEVICES - A semiconductor memory device includes a substrate including a cell region and a peripheral region, word lines on the substrate of the cell region, each of the word lines including a charge storing part and a control gate electrode sequentially stacked, and a peripheral gate pattern on the substrate of the peripheral region. Each of the control gate electrode and the peripheral gate pattern includes a high-carbon semiconductor pattern and a low-carbon semiconductor pattern, the low-carbon semiconductor pattern being on the high-carbon semiconductor pattern. | 2013-10-03 |
20130256779 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device comprising: forming a first insulating film on a semiconductor substrate; forming an adsorption film on the first insulating film; forming a first film containing germanium on the adsorption film; forming a second insulating film on the first film; forming a floating electrode film on the second insulating film; forming a third insulating film on the floating electrode film; and forming a gate electrode on the third insulating film. | 2013-10-03 |
20130256780 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device comprising: a semiconductor substrate; a tunnel insulating film provided on the semiconductor substrate; a charge accumulation film having a rough interface in the charge accumulation film provided on the tunnel insulating film; a block insulating film provided on the charge accumulation film; and a gate electrode provided on the block insulating film. | 2013-10-03 |
20130256781 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - In a method of manufacturing a semiconductor device, a dielectric layer structure and a control gate layer can be formed sequentially on a substrate. The control gate layer can be partially etched to form a plurality of control gates. A gate spacer and a sacrificial spacer sequentially can be stacked on a sidewall of the control gate and on a portion of the dielectric layer structure. The dielectric layer structure can be partially etched using the sacrificial spacer and the gate spacer as an etching mask to form a plurality of dielectric layer structure patterns. The sacrificial spacer can be removed. An insulating interlayer can be formed on the substrate to form an air gap. The insulating interlayer can cover the dielectric layer structure pattern, the gate spacer and the control gate. The air gap can extend between the adjacent gate spacers and between the adjacent dielectric layer structure patterns. | 2013-10-03 |
20130256782 | FLASH MEMORY USING FRINGING EFFECTS AND ELECTROSTATIC SHIELDING - Disclosed is a flash memory using fringing effects and an electrostatic shielding function. A gap between adjacent gate stacks is controlled by fringing effects, and an operation of each of the gate stacks is electrostatically shielded by a gate electrode extending to a tunneling insulation layer. Thus, coupling between the adjacent gate stacks is minimized by electrostatic shielding. | 2013-10-03 |
20130256783 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A trench gate type MISFET and a diode are formed in a semiconductor substrate. First and second trenches are formed in the semiconductor substrate. A gate electrode is formed in the first trench through a gate insulating film. A dummy gate electrode is formed in the second trench through a dummy gate insulating film. A cathode n | 2013-10-03 |
20130256784 | MOSFETs with Channels on Nothing and Methods for Forming the Same - A device includes a semiconductor substrate, and a channel region of a transistor over the semiconductor substrate. The channel region includes a semiconductor material. An air gap is disposed under and aligned to the channel region, with a bottom surface of the channel region exposed to the air gap. Insulation regions are disposed on opposite sides of the air gap, wherein a bottom surface of the channel region is higher than top surfaces of the insulation regions. A gate dielectric of the transistor is disposed on a top surface and sidewalls of the channel region. A gate electrode of the transistor is over the gate dielectric. | 2013-10-03 |
20130256785 | SEMICONDUCTOR DEVICE, MODULE AND SYSTEM EACH INCLUDING THE SAME, AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE - A barrier for preventing a bridge between adjacent storage node contacts is formed below a bit line located between the bit line contacts, so that a contact region between each storage node contact and an active region is increased in size. The semiconductor device includes a device isolation film defining an active region, a bit line contact coupling the active region to a bit line, and a barrier formed below the bit line located between the bit line contacts. | 2013-10-03 |
20130256786 | TRENCH MOSFET WITH SHIELDED ELECTRODE AND AVALANCHE ENHANCEMENT REGION - A trench MOSFET with shielded electrode and improved avalanche enhancement region is disclosed. The inventive structure can achieve a better avalanche capability by applying an improved avalanche enhancement region having a same doping concentration as the epitaxial layer where said trench MOSFET is formed without increasing Rds. | 2013-10-03 |
20130256787 | MULTI-LANDING CONTACT ETCHING - A method for contacting MOS devices. First openings in a photosensitive material are formed over a substrate having a top dielectric in a first die area and a second opening over a gate stack in a second die area having the top dielectric, a hard mask, and a gate electrode. The top dielectric layer is etched to form a semiconductor contact while etching at least a portion the hard mask layer thickness over a gate contact area exposed by the second opening. An inter-layer dielectric (ILD) is deposited. A photosensitive material is patterned to generate a third opening in the photosensitive material over the semiconductor contact and a fourth opening inside the gate contact area. The ILD is etched through to reopen the semiconductor contact while etching through the ILD and residual hard mask if present to provide a gate contact to the gate electrode. | 2013-10-03 |
20130256788 | SEMICONDUCTOR DEVICE - A semiconductor device comprises an isolation region formed by filling a trench with an insulator, an active region surrounded with the sidewall of the trench, a combined pillar including a semiconductor pillar in the active region and an insulator pillar in the isolation region, a gate electrode covering a side surface surrounding the combined pillar; and a transistor including the combined pillar and the gate electrode. The trench has a sidewall in a semiconductor substrate. The insulator pillar contacts the semiconductor pillar with the sidewall of the trench interposed therebetween. | 2013-10-03 |
20130256789 | POWER SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A fabrication method of a power semiconductor device is provided. Firstly, a plurality of trenched gate structures is formed in the base. Then, a body mask is used for forming a pattern layer on the base. The pattern layer has at least a first open and a second open for forming at least a body region and a heavily doped region in the base respectively. Then, a shielding structure is formed on the base to fill the second open and line at least a sidewall of the first open. Next, a plurality of source doped regions is formed in the body region by using the pattern layer and the shielding structure as the mask. Then, an interlayer dielectric layer is formed on the base and a plurality of source contact windows is formed therein to expose the source doped regions. | 2013-10-03 |
20130256790 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes buried gates formed in a semiconductor substrate in which active regions and an isolation layer are defined. A bit line is coupled to an active region between the buried gates and disposed to cross the buried gates. In the 6F | 2013-10-03 |
20130256791 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - To satisfy both suppression of rise in contact resistance and improvement of breakdown voltage near the end part of a trench part. The trench part GT is provided between a source offset region and a drain offset region at least in plan view in a semiconductor layer, and is provided in a source-drain direction from the source offset region toward the drain offset region in plan view. A gate insulating film GI covers the side surface and the bottom surface of the trench part GT. A gate electrode is provided in the trench part at least in plan view, and contacts the gate insulating film GI. A contact GC contacts the gate electrode GE. The contact GC is disposed, shifted in a first direction perpendicular to the source-drain direction relative to the centerline in the trench part GT extending in the source-drain direction in plan view, and is provided in the trench part GT in plan view. | 2013-10-03 |
20130256792 | SEMICONDUCTOR DEVICE - The present invention provides a semiconductor device designed to prevent an electric field from being concentrated in the vicinity of a groove portion. The semiconductor includes a semiconductor layer, a source region, a drain region, a source offset region, a drain offset region, a groove portion, a gate insulating film, a gate electrode, and an embedded region. The groove portion is provided in at least a position between the source offset region and the drain offset region in the semiconductor layer in a plan view, in a direction from the source offset region to the drain offset region in a plan view. The gate insulating film covers a side and a bottom of the groove portion. The gate electrode is provided only within the groove portion in a plan view, and contacts the gate insulating film. | 2013-10-03 |
20130256793 | SEMICONDUCTOR DEVICES HAVING BIT LINE INSULATING CAPPING PATTERNS AND MULTIPLE CONDUCTIVE PATTERNS THEREON - A semiconductor device capable of reducing a thickness, an electronic product employing the same, and a method of fabricating the same are provided. The method of fabricating a semiconductor device includes preparing a semiconductor substrate having first and second active regions. A first transistor in the first active region includes a first gate pattern and first impurity regions. A second transistor the second active region includes a second gate pattern and second impurity regions. A first conductive pattern is on the first transistor, wherein at least a part of the first conductive pattern is disposed at a same distance from an upper surface of the semiconductor substrate as at least a part of the second gate pattern. The first conductive pattern may be formed on the first transistor while the second transistor is formed. | 2013-10-03 |
20130256794 | METAL OXIDE SEMICONDUCTOR DEVICES WITH MULTIPLE DRIFT REGIONS - A semiconductor device includes a semiconductor substrate of a first conductivity type, a buried layer a second conductivity type different from the first conductivity type on the substrate and an epitaxial layer of the second conductivity type on the buried layer. The device further includes a pocket well of the first conductivity type in the epitaxial layer, a first drift region in the epitaxial layer at least partially overlapping the pocket well, a second drift region in the epitaxial layer and spaced apart from the first drift region, and a body region of the first conductivity type in the pocket well. A gate electrode is disposed on the body region, the pocket well and the first drift region and has an edge overlying the epitaxial region between the first and second drift regions. | 2013-10-03 |
20130256795 | LDMOS WITH ACCUMULATION ENHANCEMENT IMPLANT - A lateral double-diffused metal-oxide-semiconductor (LDMOS) transistor device includes an enhancement implant region formed in a portion of an accumulation region proximate a P-N junction between body and drift drain regions. The enhancement implant region contains additional dopants of the same conductivity type as the drift drain region. There is a gap between the enhancement implant region and the P-N junction. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 2013-10-03 |
20130256796 | MOSFET WITH SLECTIVE DOPANT DEACTIVATION UNDERNEATH GATE - A method of fabricating a metal-oxide-semiconductor field-effect transistor (MOSFET) device on a substrate includes doping a channel region of the MOSFET device with dopants of a first type. A source and a drain are formed in the substrate with dopants of a second type. Selective dopant deactivation is performed in a region underneath a gate of the MOSFET device. | 2013-10-03 |
20130256797 | Asymmetric FET Formed Through Use of Variable Pitch Gate for Use as Logic Device and Test Structure - Asymmetric FET devices and methods for fabrication thereof that employ a variable pitch gate are provided. In one aspect, a FET device is provided. The FET device includes a wafer; a plurality of active areas formed in the wafer; a plurality of gate stacks on the wafer, wherein at least one of the gate stacks is present over each of the active areas, and wherein the gate stacks have an irregular gate-to-gate spacing such that for at least a given one of the active areas a gate-to-gate spacing on a source side of the given active area is greater than a gate-to-gate spacing on a drain side of the given active area; spacers on opposite sides of the gate stacks; and an angled implant in the source side of the given active area. | 2013-10-03 |
20130256798 | THIN FILM TRANSISTOR, METHOD OF MANUFACTURING THE SAME, DISPLAY UNIT, AND ELECTRONIC APPARATUS - A thin film transistor includes: a gate electrode and a pair of source-drain electrodes provided on a substrate; an oxide semiconductor layer provided between the gate electrode and the pair of source-drain electrodes, the oxide semiconductor layer forming a channel; a protection film provided over whole of a surface above the substrate; and a gate insulating film provided on a gate electrode side of the oxide semiconductor layer, the gate insulating film having end faces part or all of which are covered with the pair of source-drain electrodes or with the protection film. | 2013-10-03 |
20130256799 | CMOS FINFET DEVICE AND METHOD OF FORMING THE SAME - A CMOS FinFET device and method for fabricating a CMOS FinFET device is disclosed. An exemplary CMOS FinFET device includes a substrate including a first region and a second region. The CMOS FinFET further includes a fin structure disposed over the substrate including a first fin in the first region and a second fin in the second region. The CMOS FinFET further includes a first portion of the first fin comprising a material that is the same material as the substrate and a second portion of the first fin comprising a III-V semiconductor material deposited over the first portion of the first fin. The CMOS FinFET further includes a first portion of the second fin comprising a material that is the same material as the substrate and a second portion of the second fin comprising a germanium (Ge) material deposited over the first portion of the second fin. | 2013-10-03 |
20130256800 | SOI DEVICES FOR PLASMA DISPLAY PANEL DRIVER CHIP - SOI devices for plasma display panel driver chip, include a substrate, a buried oxide layer and an n-type SOI layer in a bottom-up order, where the SOI layer is integrated with an HV-NMOS device, an HV-PMOS device, a Field-PMOS device, an LIGBT device, a CMOS device, an NPN device, a PNP device and an HV-PNP device; the SOI layer includes an n+ doped region within the SOI layer at an interface between the n-type SOI layer and the buried oxide layer; and the n+ doped region has a higher doping concentration than the n-type SOI layer. | 2013-10-03 |
20130256801 | INTEGRATED CIRCUIT STRUCTURE TO RESOLVE DEEP-WELL PLASMA CHARGING PROBLEM AND METHOD OF FORMING THE SAME - During various processing operations, ions from process plasma may be transfer to a deep n-well (DNW) formed under devices structures. A reverse-biased diode may be connected to the signal line to protect a gate dielectric formed outside the DNW and is connected to the drain of the transistor formed inside the DNW. | 2013-10-03 |
20130256802 | Replacement Gate With Reduced Gate Leakage Current - Replacement gate work function material stacks are provided, which provides a work function about the energy level of the conduction band of silicon. After removal of a disposable gate stack, a gate dielectric layer is formed in a gate cavity. A metallic compound layer including a metal and a non-metal element is deposited directly on the gate dielectric layer. At least one barrier layer and a conductive material layer is deposited and planarized to fill the gate cavity. The metallic compound layer includes a material, which provides, in combination with other layer, a work function about 4.4 eV or less, and can include a material selected from tantalum carbide, metallic nitrides, and a hafnium-silicon alloy. Thus, the metallic compound layer can provide a work function that enhances the performance of an n-type field effect transistor employing a silicon channel. Optionally, carbon doping can be introduced in the channel. | 2013-10-03 |
20130256803 | METHOD OF INTEGRATING BURIED THRESHOLD VOLTAGE ADJUSTMENT LAYERS FOR CMOS PROCESSING - A semiconductor device and method of forming. According to one embodiment, the method includes providing a substrate with defined device regions and having an interface layer thereon, depositing a first high-k film on the interface layer, and performing a heat-treatment to form a modified interface layer. The method further includes depositing a first threshold voltage adjustment layer, removing the first threshold voltage adjustment layer from the second device region, depositing a second high-k film above the first high-k film, and depositing a gate electrode film on the second high-k film. A first gate stack is defined that contains the modified interface layer, the first high-k film, the first threshold voltage adjustment layer, the second high-k film, and the gate electrode film, and a second gate stack is defined that contains the modified interface layer, the first high-k film, the second high-k film, and the gate electrode film. | 2013-10-03 |
20130256804 | ROM Arrays Having Memory Cell Transistors Programmed Using Metal Gates - According to one exemplary implementation, an integrated circuit (IC) includes a first memory cell transistor of a read only memory (ROM) array, the first memory cell transistor including a first metal gate of a first work function and having a first threshold voltage. The IC also includes a second memory cell transistor of the ROM array, the second memory cell transistor including a second metal gate of a second work function and having a second threshold voltage. The first memory cell transistor and the second memory cell transistor can be of a first conductivity type. Furthermore, the first memory cell transistor can include a first high-k gate dielectric and the second memory cell transistor can include a second high-k gate dielectric. | 2013-10-03 |
20130256805 | METAL GATE SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THEREOF - A method of semiconductor fabrication including forming a first work function metal layer on a first region of the substrate and forming a metal layer on the first work function metal layer and on a second region of the substrate. A dummy layer is formed on the metal layer. The layers are then patterned to form a first gate structure in the first region and a second gate structure in the second region of the substrate. The dummy layer is then removed to expose the metal layer, which is treated. The treatment may be an oxygen treatment that allows the metal layer to function as a second work function layer. | 2013-10-03 |
20130256806 | SEMICONDUCTOR DEVICE INCLUDING CONTACT HOLES AND METHOD FOR FORMING THE SAME - A semiconductor device including contact holes and method for forming the same are provided. A dual-stress liner is formed on a substrate. A first, second and third dielectric layers are then formed over the dual-stress liner. The second dielectric layer has a top surface leveling with that of an overlapping portion of the dual-stress liner. The third dielectric layer is etched to form first openings to have the etching stop at the second dielectric layer and at the upper stress liner of the overlapping portion. The second dielectric layer, the first dielectric layer and the upper stress liner are etched along the first openings to form second openings having the etching stop at the lower stress liner of the overlapping portion and the dual-stress liner in other regions. The stress liners are etched to form contact holes. | 2013-10-03 |
20130256807 | Integrated Dual Power Converter Package Having Internal Driver IC - An integrated dual power converter package is disclosed. The package includes a leadframe having a first control FET paddle configured to support a drain of a first control FET, and a second control FET paddle configured to support a drain of a second control FET. The leadframe further includes a sync FET paddle configured to support a source of a first sync FET and a source of a second sync FET, and a driver integrated circuit (IC) paddle configured to support a driver IC for controlling each of the control FETs and each of the sync FETs. The leadframe may additionally include first and second switched nodes, configured for electrical connection to the first control FET and the first sync FET via a first clip, and to the second control FET and the second sync FET via a second clip, respectively. | 2013-10-03 |
20130256808 | Semiconductor Device and Method of Manufacturing the Same - The present invention discloses a semiconductor device, comprising a first MOSFET; a second MOSFET; a first stress liner covering the first MOSFET and having a first stress; a second stress liner covering the second MOSFET and having a second stress; wherein the second stress liner and/or the first stress liner comprise(s) a metal oxide. In accordance with the high-stress CMOS and method of manufacturing the same of the present invention, a stress layer comprising a metal oxide is formed selectively on PMOS and NMOS respectively by using a CMOS compatible process, whereby carrier mobility of the channel region is effectively enhanced and the performance of the device is improved. | 2013-10-03 |
20130256809 | ELECTRICAL-FREE DUMMY GATE - The present disclosure provides a semiconductor device. The semiconductor device includes an electrical-free dummy gate formed over a substrate. The dummy gate has an elongate shape and is oriented along a first direction. The semiconductor device includes a first functional gate formed over the substrate. The first functional gate has an elongate shape and is oriented along the first direction. The first functional gate is separated from the dummy gate in a second direction perpendicular to the first direction. A first conductive contact is formed on the first functional gate. The semiconductor device includes a second functional gate formed over the substrate. The second functional gate has an elongate shape and is oriented along the first direction. The second functional gate is aligned with and physically separated from the dummy gate in the first direction. A second conductive contact is formed on the second functional gate. | 2013-10-03 |
20130256810 | Semiconductor Device and Method for Manufacturing the Same - The present invention discloses a semiconductor device, which comprises: a first epitaxial layer on a substrate; a second epitaxial layer on the first epitaxial layer, wherein a MOSFET is formed in an active region of the second epitaxial layer; and an inverted-T shaped STI formed in the first epitaxial layer and the second epitaxial layer and surrounding the active region. In the semiconductor device and the method for manufacturing the same according to the present invention, the double epitaxial layers are selectively etched to form an inverted-T shaped STI, which effectively reduces the leakage current of the device without reducing the area of the active region, thereby improving the device reliability. | 2013-10-03 |
20130256811 | Electrically Conductive Lines And Integrated Circuitry Comprising A Line Of Recessed Access Devices - A method of forming an electrically conductive buried line and an electrical contact thereto includes forming of a longitudinally elongated conductive line within a trench in substrate material. A longitudinal end part thereof within the trench is of spoon-like shape having a receptacle. The receptacle is filled with conductive material. Insulative material is formed over the conductive material that is within the receptacle. A contact opening is formed over the conductive material that is within the receptacle. Conductor material is formed in the contact opening in electrical connection with the second conductive material that is within the receptacle. Other method and device implementations are disclosed. | 2013-10-03 |
20130256812 | METHOD FOR REDUCING INTERFACIAL LAYER THICKNESS FOR HIGH-K AND METAL GATE STACK - A method of performing an ultraviolet (UV) curing process on an interfacial layer over a semiconductor substrate, the method includes supplying a gas flow rate ranging from 10 standard cubic centimeters per minute (sccm) to 5 standard liters per minute (slm), wherein the gas comprises inert gas. The method further includes heating the interfacial layer at a temperature less than or equal to 700° C. Another method of performing an annealing process on an interfacial layer over a semiconductor substrate, the second method includes supplying a gas flow rate ranging from 10 sccm to 5 slm, wherein the gas comprises inert gas. The method further includes heating the interfacial layer at a temperature less than or equal to 600° C. | 2013-10-03 |
20130256813 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The semiconductor device has a sensor unit including a sensing part, and a semiconductor substrate. The semiconductor substrate is bonded to the sensor unit through an insulation film such that the sensing part is disposed in an air-tightly sealed chamber provided between a recessed portion of the semiconductor substrate and the sensor unit. A surface of the semiconductor substrate provided on a periphery of the recessed portion includes a boundary region at a perimeter of the recessed portion and a bonding region on a periphery of the boundary region. The bonding region has an area greater than an area of the boundary region. The bonding region of the semiconductor substrate is bonded to the sensor unit through the insulation film. | 2013-10-03 |
20130256814 | PHYSICAL QUANTITY SENSOR AND ELECTRONIC APPARATUS - A physical quantity sensor includes: a movable body displaceable in a direction of a first axis; a fixed electrode portion disposed to face a movable electrode portion; a spring portion as a connection member connecting a fixed portion with the movable body and including a first extending portion extending from the fixed portion along a second axis crossing the direction of the first axis, a turn-around portion connected to the first extending portion, and a second extending portion extending from the turn-around portion along the second axis; and a wall portion extending from the fixed portion and disposed, in plan view, outside the first extending portion and the turn-around portion of the spring portion. The spring portion and the wall portion are electrically connected. | 2013-10-03 |
20130256815 | CAVITY PACKAGE DESIGN - A semiconductor device. The device including a substrate having electrical traces, at least one of a MEMS die and a semiconductor chip mounted on the substrate, and a spacer. The spacer has a first end connected to the substrate and includes electrical interconnects coupled to the electrical traces. The at least one MEMS die and a semiconductor chip are contained within the spacer. The spacer and substrate form a cavity which contains the at least one MEMS die and a semiconductor chip. The cavity forms an acoustic volume when the semiconductor device is mounted to a circuit board via a second end of the spacer. | 2013-10-03 |
20130256816 | MEMS PROCESS AND DEVICE - A method of fabricating a micro-electrical-mechanical system (MEMS) transducer comprises the steps of forming a membrane on a substrate, and forming a back-volume in the substrate. The step of forming a back-volume in the substrate comprises the steps of forming a first back-volume portion and a second back-volume portion, the first back-volume portion being separated from the second back-volume portion by a step in a sidewall of the back-volume. The cross-sectional area of the second back-volume portion can be made greater than the cross-sectional area of the membrane, thereby enabling the back-volume to be increased without being constrained by the cross-sectional area of the membrane. The back-volume may comprise a third back-volume portion. The third back-volume portion enables the effective diameter of the membrane to be formed more accurately. | 2013-10-03 |
20130256817 | ELEMENT ARRAY, ELECTROMECHANICAL CONVERSION DEVICE, AND PROCESS FOR PRODUCING THE SAME - An element array comprises a plurality of elements having a first electrode and a second electrode with a gap therebetween; the first electrode is separated for each of the elements by grooves, an insulating connection substrate is bonded to the first electrode, and wirings are provided from the respective first electrodes through the connection substrate to the side opposite to the first electrodes. | 2013-10-03 |
20130256818 | METHODS OF FORMING SPIN TORQUE DEVICES AND STRUCTURES FORMED THEREBY - Methods of forming spin torque microelectronic devices are described. Those methods may include forming a free FM layer on a substrate, forming a non-magnetic layer on the free FM layer, forming at least three input pillars on the non-magnetic layer, and forming an output pillar on the non-magnetic layer to form a majority gate device. | 2013-10-03 |
20130256819 | SEMICONDUCTOR DEVICE - A yield of semiconductor devices having a magnetic shield is enhanced. A magnetic shield member SIE has a first shield member SIE | 2013-10-03 |
20130256820 | THIN FILM ALUMINUM-CONTAINING PHOTOVOLTAICS - This invention relates to thin film photovoltaic materials containing aluminum, as well as methods for making materials using polymeric precursor compounds. This invention provides a range of compounds, polymeric compounds, compositions, materials and methods directed ultimately toward photovoltaic applications, devices and systems for energy conversion, and solar cells. This invention further relates to methods for making CA(I,G,A)S, CAIGAS, A(I,G,A)S, AIGAS, C(I,G,A)S, and CIGAS thin film materials by providing one or more polymeric precursor compounds or inks thereof, providing a substrate, depositing the compounds or inks onto the substrate; and heating the substrate. | 2013-10-03 |
20130256821 | SOLID-STATE IMAGING ELEMENT, METHOD OF MANUFACTURING THE SAME, SOLID-STATE IMAGING APPARATUS, AND IMAGING APPARATUS - A solid-state imaging element including a semiconductor substrate that has a light reception portion performing a photoelectric conversion of an incident light; an oxide layer that is formed on a surface of the semiconductor substrate; a light shielding layer that is formed on an upper layer further than the oxide layer via an adhesion layer; and an oxygen supply layer that is disposed between the oxide layer and the adhesion layer and is formed of a material which shows an oxidation enthalpy smaller than that of a material forming the oxide layer. | 2013-10-03 |
20130256822 | METHOD AND DEVICE WITH ENHANCED ION DOPING - Techniques for providing a pixel cell which exhibits improved doping in a semiconductor substrate. In an embodiment, a first doping is performed through a backside of the semiconductor substrate. After the first doping, the semiconductor substrate is thinned to expose a front side which is opposite of the backside. In another embodiment, a second doping is performed through the exposed front side of the thinned semiconductor substrate to form at least part of a pixel cell structure. | 2013-10-03 |
20130256823 | METHOD FOR MANUFACTURING DETECTING ELEMENT, METHOD FOR MANUFACTURING IMAGING DEVICE, DETECTING ELEMENT, IMAGING DEVICE, AND ELECTRONIC DEVICE - A detecting element has an absorbing section where a temperature rises according to an amount of electromagnetic waves which are absorbed and a detecting section where characteristics change according to an amount of heat which is transmitted from the absorbing section. A method for manufacturing the detecting element includes: forming the detecting section on a substrate; forming a protective film which covers the detecting section; forming a hollow space portion in a region which overlaps with the detecting section of the substrate in a planar view after the forming of the protective film; and forming the absorbing section by applying a liquid body, which contains a material constituting the absorbing section, in a region on the protective film on an opposite side from the detection section, which overlaps with the detecting section in a planar view, and solidifying the liquid body after the forming of the hollow space portion. | 2013-10-03 |
20130256824 | SOLID-STATE IMAGING DEVICE, METHOD OF MANUFACTURING SOLID-STATE IMAGING DEVICE, APPARATUS FOR MANUFACTURING SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND ELECTRONIC DEVICE - There is provided a solid-state imaging device including a sensor substrate having a sensor-side semiconductor layer including a pixel region in which a photoelectric conversion section is provided and a sensor-side wiring layer provided on an opposite surface side from a light receiving surface of the sensor-side semiconductor layer, a circuit substrate having a circuit-side semiconductor layer and a circuit-side wiring layer and provided on a side of the sensor-side wiring layer of the sensor substrate, a connection unit region in which a connection section is provided, the connection section having a first through electrode, a second through electrode, and a connection electrode connecting the first through electrode and the second through electrode, and an insulating layer having a step portion which has the connection electrode embedded therein and has a film thickness that gradually decreases from the connection unit region to the pixel region. | 2013-10-03 |
20130256825 | INTEGRATED CIRCUIT COMPRISING A GAS SENSOR - An integrated circuit and a method of making the same. The integrated circuit includes a semiconductor substrate having a major surface. The integrated circuit also includes a thermal conductivity based gas sensor having an electrically resistive sensor element located on the major surface for exposure to a gas to be sensed. The integrated circuit further includes a barrier located on the major surface for inhibiting a flow of the gas across the sensor element. | 2013-10-03 |
20130256826 | DISCONTINUOUS GUARD RING - An integrated circuit chip comprising a guard ring formed on a semiconductor substrate that surrounds the active region of the integrated circuit chip and extends from the semiconductor substrate through one or more of a plurality of wiring levels. The guard ring comprises stacked metal lines with spaces breaking up each respective metal line. Each space may be formed such that it partially overlies the space in the metal line directly below but does not overlie any other space. Alternatively, each space may also be formed such that each space is at least completely overlying the space in the metal line below it. | 2013-10-03 |
20130256827 | EFFICIENT PITCH MULTIPLICATION PROCESS - Pitch multiplied and non-pitch multiplied features of an integrated circuit, e.g., features in the array, interface and periphery areas of the integrated circuit, are formed by processing a substrate through a mask. A photoresist layer is patterned to simultaneously define mask elements in the array, interface and periphery areas. The pattern is transferred to an amorphous carbon layer. Spacers are formed on the sidewalls of the patterned amorphous carbon layer. Protective material is deposited and patterned to expose mask elements in the array region and in parts of the interface or periphery areas. Exposed amorphous carbon is removed, leaving free-standing spacers in the array region. The protective material is removed, leaving a pattern of pitch multiplied spacers in the array region and non-pitch multiplied mask elements in the interface and periphery areas. The pattern is transferred to a hard mask layer, through which the substrate is etched. | 2013-10-03 |
20130256828 | SEMICONDUCTOR DEVICES HAVING INCREASED CONTACT AREAS BETWEEN CONTACTS AND ACTIVE REGIONS AND METHODS OF FABRICATING THE SAME - Provided are a semiconductor device and a method of fabricating the same. The semiconductor device may include a substrate including first and second junction regions, a word line buried in the substrate, a bit line provided over the word line to cross the word line, a first contact provided between the substrate and the bit line and electrically connected to the first junction region, and a second contact provided between the bit lines and electrically connected to the second junction region. An overlapping area of a lower portion of the second contact may be greater than an overlapping area of an upper portion of the second contact with respect to the second junction region. | 2013-10-03 |
20130256829 | COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - An AlGaN/GaN HEMT includes a compound semiconductor stack structure; an element isolation structure which demarcates an element region on the compound semiconductor stack structure; a first insulating film which is formed on the element region and is not formed on the element isolation structure; a second insulating film which is formed on at least the element isolation structure and is higher in hydrogen content than the first insulating film; and a gate electrode which is formed on the element region of the compound semiconductor stack structure via the second insulating film. | 2013-10-03 |
20130256830 | SEMICONDUCTOR-ON-OXIDE STRUCTURE AND METHOD OF FORMING - Semiconductor-on-oxide structures and related methods of forming such structures are disclosed. In one case, a method includes: forming a first dielectric layer over a substrate; forming a first conductive layer over the first dielectric layer, the first conductive layer including one of a metal or a silicide; forming a second dielectric layer over the first conductive layer; bonding a donor wafer to the second dielectric layer, the donor wafer including a donor dielectric and a semiconductor layer; cleaving the donor wafer to remove a portion of the donor semiconductor layer; forming at least one semiconductor isolation region from an unremoved portion of the donor semiconductor layer; and forming a contact to the first conductive layer through donor dielectric and the second dielectric layer. | 2013-10-03 |
20130256831 | N WELL IMPLANTS TO SEPARATE BLOCKS IN A FLASH MEMORY DEVICE - A semiconductor memory device that has an isolated area formed from one conductivity and formed in part by a buried layer of a second conductivity that is implanted in a substrate. The walls of the isolated area are formed by implants that are formed from the second conductivity and extend down to the buried layer. The isolated region has implanted source lines and is further subdivided by overlay strips of the second conductivity that extend substantially down to the buried layer. Each isolation region can contain one or more blocks of memory cells. | 2013-10-03 |
20130256832 | SEMICONDUCTOR DEVICES INCLUDING CELL-TYPE POWER DECOUPLING CAPACITORS - A semiconductor device includes an internal circuit and a cell-type power decoupling capacitor. The cell-type power decoupling capacitor is formed on a semiconductor substrate using a stack cell capacitor process. The cell-type power decoupling capacitor stabilizes a supply voltage to provide the stabilized supply voltage to the internal circuit. Accordingly, the semiconductor device including the cell-type power decoupling capacitor may be insensitive to power noise and may occupy a small area on a chip. | 2013-10-03 |
20130256833 | TRIPLE WELL ISOLATED DIODE AND METHOD OF MAKING - A triple well isolate diode including a substrate having a first conductivity type and a buried layer formed in the substrate, where the buried layer has a second conductivity type. The triple well isolated diode including an epi-layer formed over the substrate and the buried layer, where the epi-layer has the first conductivity type. The triple well isolated diode including a first well formed in the epi-layer, where the first well has the second conductivity type, a second well formed in the epi-layer, where the second well has the first conductivity type and surrounds the first well, a third well formed in the epi-layer, where the third well has the second conductivity type and surrounds the second well. The triple well isolated diode including a deep well formed in the epi-layer, where the deep well has the first conductivity type and extends beneath the first well. | 2013-10-03 |
20130256834 | BACK-SIDE MOM/MIM DEVICES - Back-side MOM/MIM structures are integrated on a device with front-side circuitry. Embodiments include forming a substrate having a front side and a back side that is opposite the front side, the substrate including circuitry on the front side of the substrate; and forming a metal-oxide-metal (MOM) capacitor, a metal-insulator-metal (MIM) capacitor, or a combination thereof on the back side of the substrate. Other embodiments include forming a through-silicon via (TSV), in the substrate, connecting the MOM capacitor, the MIM capacitor, or a combination thereof to the circuitry on the front side of the substrate. | 2013-10-03 |
20130256835 | NON-PLANAR CAPACITOR AND METHOD OF FORMING THE NON-PLANAR CAPACITOR - Disclosed herein are embodiments of non-planar capacitor. The non-planar capacitor can comprise a plurality of fins above a semiconductor substrate. Each fin can comprise at least an insulator section on the semiconductor substrate and a semiconductor section, which has essentially uniform conductivity, stacked above the insulator section. A gate structure can traverse the center portions of the fins. This gate structure can comprise a conformal dielectric layer and a conductor layer (e.g., a blanket or conformal conductor layer) on the dielectric layer. Such a non-planar capacitor can exhibit a first capacitance, which is optionally tunable, between the conductor layer and the fins and a second capacitance between the conductor layer and the semiconductor substrate. Also disclosed herein are method embodiments, which can be used to form such a non-planar capacitor and which are compatible with current state of the art multi-gate non-planar field effect transistor (MUGFET) processing. | 2013-10-03 |
20130256836 | Package-on-Package (PoP) Device with Integrated Passive Device - A package for a use in a package-on-package (PoP) device. The package includes a substrate, a polymer layer formed on the substrate, a first via formed in the polymer layer, and a material disposed in the first via to form a first passive device. The material may be a high dielectric constant dielectric material in order to form a capacitor or a resistive material to form a resistor. | 2013-10-03 |
20130256837 | CAPACITOR AND METHOD FOR FORMING THE SAME - A capacitor and a method of forming a capacitor including forming a first conductive layer, a dielectric film, a second conductive layer, and a hard mask on and/or over a substrate, forming a hard mask pattern and an upper electrode each having a sloped sidewall by etching the hard mask and the first conductive layer, forming a spacer on and/or over the sidewall of each of the hard mask pattern and the upper electrode, and forming a lower electrode by etching the dielectric film and the second conductive layer. | 2013-10-03 |
20130256838 | METHOD OF EPITAXIAL DOPED GERMANIUM TIN ALLOY FORMATION - A method for forming germanium tin layers and the resulting embodiments are described. A germanium precursor and a tin precursor are provided to a chamber, and an epitaxial layer of germanium tin is formed on the substrate. The germanium tin layer is selectively deposited on the semiconductor regions of the substrate and can include thickness regions of varying tin and dopant concentrations. The germanium tin layer can be selectively deposited by either alternating or concurrent flow of a halide gas to etch the surface of the substrate. | 2013-10-03 |
20130256839 | SEMICONDUCTOR WAFER AND SEMICONDUCTOR DEVICE - A semiconductor wafer may include: a disk-shaped wafer body made of silicon; and an identification trench section having at least one trench and provided at a periphery section of the wafer body, wherein the trench is opened in the periphery of the wafer body, and has a depth less than a thickness of the wafer body. | 2013-10-03 |
20130256840 | Semiconductor Device and Method of Forming Protective Coating Material Over Semiconductor Wafer to Reduce Lamination Tape Residue - A semiconductor device has a build-up interconnect structure formed over an active surface of a semiconductor wafer containing a plurality of semiconductor die separated by a saw street. An insulating layer is formed over the interconnect structure. Bumps are formed over the interconnect structure. A protective coating material is deposited over the insulating layer and saw street. A lamination tape is applied over the coating material. A portion of a back surface of the semiconductor wafer is removed. A mounting tape is applied over the back surface. The lamination tape is removed while leaving the coating material over the insulating layer and saw street. A first channel is formed through the saw street extending partially through the semiconductor wafer. The coating material is removed after forming the first channel. A second channel is formed through the saw street and the mounting tape is removed to singulate the semiconductor wafer. | 2013-10-03 |
20130256841 | VIA PLUGS - The present disclosure relates to providing via plugs in vias of a semiconductor material. The via plugs may be formed of a polymer, such as a polyimide, that can withstand subsequent soldering and operating temperatures. The via plugs effectively fill the vias to prevent the vias from being filled substantially with solder during a subsequent soldering processes. | 2013-10-03 |
20130256842 | SEMICONDUCTOR DEVICE PACKAGING STRUCTURE AND PACKAGING METHOD - Exemplary semiconductor device packaging structure and packaging method are provided. The packaging method uses an adhesive layer to bond multiple wafer pieces onto a first surface of a carrier substrate, each adjacent two of the wafer pieces having a gap formed therebetween for exposing a part of the adhesive layer. A packaging layer is filled in each of the gaps. At least one through silicon via is formed each of the wafer pieces to expose a bonding pad formed on an active surface of the wafer pieces. Redistribution circuit layers are formed on back surfaces of the respective wafer pieces and filled into the through silicon vias for electrical connection with the bonding pads. A sawing process is performed to saw starting from each of the packaging layers to a second surface of the carrier substrate, and thereby multiple semiconductor device packaging structures are obtained. | 2013-10-03 |
20130256843 | WAFER SAWING METHOD AND WAFER STRUCTURE BENEFICIAL FOR PERFORMING THE SAME - A wafer sawing method comprises steps as follows: A wafer having a first surface and a second surface is firstly provided. An integrated circuit fabricating process is performed on the first surface of the wafer to define a first integrated circuit region and a periphery region surrounding around the first integrated circuit region, wherein the integrated circuit fabricating process includes an etching process used to form a first deep trench having an aspect ratio larger than 10 as well as a depth substantially ranging from one-third to two-third thickness of the wafer on the periphery region. Subsequently, an adhesive tape is disposed on the first surface at least covering the first integrated circuit region and the periphery region. A tensile stress is then imposed on the adhesive tape in order to make the wafer broken off along the first deep trench. | 2013-10-03 |
20130256844 | Semiconductor Fabrication Utilizing Grating and Trim Masks - Disclosed are a method for fabricating a semiconductor device and the associated semiconductor structure. The method includes exposing a photoresist layer disposed on a semiconductor wafer utilizing a grating mask having a plurality of grating lines to produce exposed lines and unexposed lines in the photoresist layer. The method further includes exposing the photoresist layer utilizing a trim mask having a blocking portion situated over a selected one of the unexposed lines. The photoresist layer may be developed after exposing the photoresist layer utilizing the trim mask. A line may then be etched into the semiconductor wafer where the selected one of the unexposed lines was blocked by the blocking portion of the trim mask. The width of the unexposed lines may be controlled by adjusting an exposure time or an exposure power for the photoresist layer while utilizing the grating mask. | 2013-10-03 |
20130256845 | Semiconductor Device and Method for Manufacturing the Same - The present invention discloses a semiconductor device, which comprises: a substrate, and a shallow trench isolation in the substrate, characterized in that, the semiconductor device further comprises a stress release layer between the substrate and the shallow trench isolation. In the semiconductor device and the method for manufacturing the same according to the present invention, the stresses accumulated during the formation of the STI can be released by interposing the stress release layer made of a softer material between the substrate and the STI, thereby reducing the leakage current of the substrate of the device and improving the device reliability. | 2013-10-03 |
20130256846 | Semiconductor Overlapped PN Structure and Manufacturing Method Thereof - The present invention discloses a semiconductor overlapped PN structure and manufacturing method thereof. The method includes: providing a substrate; providing a first mask to define a P (or N) type well and at least one overlapped region in the substrate; implanting P (or N) type impurities into the P (or N) type well and the at least one overlapped region; providing a second mask having at least one opening to define an N (or P) type well in the substrate, and to define at least one dual-implanted region in the at least one overlapped region; implanting N (or P) type impurities into the N (or P) type well and the at least one dual-implanted region such that the at least one dual-implanted region has P type and N type impurities. | 2013-10-03 |
20130256847 | SEMICONDUCTOR DEVICES INCLUDING ELECTROMAGNETIC INTERFERENCE SHIELD - Provided are a semiconductor device including an EMI shield, a method of manufacturing the same, a semiconductor module including the semiconductor device, and an electronic system including the semiconductor device. The semiconductor device includes a lower semiconductor package, an upper semiconductor package, a package bump, and an EMI shield. The lower semiconductor package includes a lower substrate, a lower semiconductor chip mounted on the lower substrate, and a ground wire separated from the lower semiconductor chip. The upper semiconductor package includes an upper substrate stacked on the lower semiconductor package, and an upper semiconductor chip stacked on the upper substrate. The package bump electrically connects the upper semiconductor package and the lower semiconductor package. The EMI shield covers the upper and lower semiconductor packages and is electrically connected to the ground wire. | 2013-10-03 |
20130256848 | ELECTRONIC COMPONENT MODULE AND METHOD OF MANUFACTURING THE SAME - An electromagnetic component module includes: a molding resin provided so as to cover electronic components mounted on a substrate and a surface of the substrate; and a conductive shield formed so as to further cover the molding resin. The conductive shield includes a first filler and a second filler which are different from each other and the conductive shield is connected to ground wires exposed on lateral surfaces of the substrate. The average particle diameter of the first filler is ½ or less of the thickness of the ground wires and the second filler forms a metallic bond in the temperature range of 250 degrees Celsius or lower. | 2013-10-03 |
20130256849 | HIGH FREQUENCY TRANSITION MATCHING IN AN ELECTRONIC PACKAGE FOR MILLIMETER WAVE SEMICONDUCTOR DIES - A mmWave electronics package constructed from common Printed Circuit Board (PCB) technology and a metal cover. Assembly of the package uses standard pick and place technology and heat is dissipated directly to a pad on the package. Input/output of mmWave signal(s) is achieved through a rectangular waveguide. Mounting of the electronic package to an electrical printed circuit board (PCB) is performed using conventional reflow soldering processes and includes a waveguide I/O connected to an mmWave antenna. The electronic package provides for transmission of low frequency, dc and ground signals from the semiconductor chip inside the package to the PCB it is mounted on. An impedance matching scheme matches the chip to high frequency board transition by altering the ground plane within the chip. A ground plane on the high frequency board encircles the high frequency signal bump to confine the electromagnetic fields to the bump region reducing radiation loss. | 2013-10-03 |
20130256850 | ELECTRONIC PACKAGE FOR MILLIMETER WAVE SEMICONDUCTOR DIES - A mmWave electronics package constructed from common Printed Circuit Board (PCB) technology and a metal cover. Assembly of the package uses standard pick and place technology and heat is dissipated directly to a pad on the package. Input/output of mmWave signal(s) is achieved through a rectangular waveguide. Mounting of the electronic package to an electrical printed circuit board (PCB) is performed using conventional reflow soldering processes and includes a waveguide I/O connected to an mmWave antenna. The electronic package provides for transmission of low frequency, dc and ground signals from the semiconductor chip inside the package to the PCB it is mounted on. An impedance matching scheme matches the chip to high frequency board transition by altering the ground plane within the chip. A ground plane on the high frequency board encircles the high frequency signal bump to confine the electromagnetic fields to the bump region reducing radiation loss. | 2013-10-03 |
20130256851 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE USING MOLD HAVING RESIN DAM AND SEMICONDUCTOR DEVICE - The suppression of resin leakage is combined with the suppression of damage to the functional wiring area of a wiring board in forming an encapsulation resin. A method for manufacturing a semiconductor device includes the step of clamping a wiring board with a first mold and a second mold. The second mold includes: a flat portion contacting a wiring board; a recessed portion forming a cavity to form an encapsulation resin; and a projecting portion formed at a location spaced apart from the recessed portion on the flat portion, the projecting portion projecting on the first mold side, and extending along the first edge of the wiring board. | 2013-10-03 |
20130256852 | Stacked Semiconductor Package - A method of making a stacked semiconductor package having at least a leadframe, a first die mounted above and soldered to the lead frame and a first clip mounted above and soldered to the first die. The method includes positioning the leadframe, first die and first clip in a vertically stacked relationship and nonsolderingly locking the first clip in laterally nondisplaceble relationship with the leadframe. A stacked semiconductor package and an intermediate product produced in making a stacked semiconductor package are also disclosed. | 2013-10-03 |
20130256853 | STACKED PACKAGED INTEGRATED CIRCUIT DEVICES, AND METHODS OF MAKING SAME - A device is disclosed which includes a first packaged integrated circuit device, a second packaged integrated circuit device positioned above the first packaged integrated circuit device and a plurality of planar conductive members conductively coupling the first and second packaged integrated circuit devices to one another. A method is also disclosed which includes conductively coupling a plurality of extensions on a leadframe to each of a pair of stacked packaged integrated circuit devices and cutting the leadframe to singulate the extensions from one another. | 2013-10-03 |
20130256854 | LEAD FRAME, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING LEAD FRAME - A lead frame includes a plurality of leads defined by an opening extending in a thickness direction. An insulating resin layer fills the opening to entirely cover side surfaces of each lead and to support the leads. A first surface of each lead is exposed from a first surface of the insulating resin layer. | 2013-10-03 |
20130256855 | CHIP ARRANGEMENT, A METHOD FOR FORMING A CHIP ARRANGEMENT, A CHIP PACKAGE, A METHOD FOR FORMING A CHIP PACKAGE - A chip arrangement is provided, the chip arrangement including: a first chip carrier; a second chip carrier; a first chip electrically connected to the first chip carrier; a second chip disposed over the first chip carrier and electrically insulated from the first chip carrier; and a third chip electrically connected to the second chip carrier; wherein at least one of the first chip and the second chip is electrically connected to the third chip. | 2013-10-03 |
20130256856 | Multichip Power Semiconductor Device - An electronic device includes a first chip carrier and a second chip carrier isolated from the first chip carrier. A first power semiconductor chip is mounted on and electrically connected to the first chip carrier. A second power semiconductor chip is mounted on and electrically connected to the second chip carrier. An electrically insulating material is configured to at least partially surround the first power semiconductor chip and the second power semiconductor chip. An electrical interconnect is configured to electrically connect the first power semiconductor chip to the second power semiconductor chip, wherein the electrical interconnect has at least one of a contact clip and a galvanically deposited conductor. | 2013-10-03 |
20130256857 | Semiconductor Packages and Methods of Formation Thereof - In one embodiment, a method of forming a semiconductor package comprises providing a first die having contact regions on a top surface but not on an opposite bottom surface. A dielectric liner layer is deposited under the bottom surface of the first die. The first die is attached with the deposited dielectric liner layer to a die paddle of a substrate. | 2013-10-03 |
20130256858 | PCB Based RF-Power Package Window Frame - A semiconductor package includes a baseplate having a die attach region and a peripheral region, a transistor die having a first terminal attached to the die attach region, and a second terminal and a third terminal facing away from the baseplate, and a frame including an electrically insulative member having a first side attached to the peripheral region of the baseplate, a second side facing away from the baseplate, a first metallization at the first side of the insulative member and a second metallization at the second side of the insulative member. The insulative member extends outward beyond a lateral sidewall of the baseplate. The first metallization is attached to the part of the first side which extends outward beyond the lateral sidewall of the baseplate. The first and second metallizations are electrically connected at a region of the insulative member spaced apart from the lateral sidewall of the baseplate. | 2013-10-03 |
20130256859 | Dual Power Converter Package Using External Driver IC - A dual power converter package is disclosed. The package includes a leadframe having a first control FET paddle configured to support a drain of a first control FET, and a second control FET paddle configured to support a drain of a second control PET. The leadframe further includes a sync FET paddle configured to support a source of a first sync FET and a source of a second sync FET, and a first plurality of contacts configured to receive control signals for each of the control PETS and each of the sync FETs from a driver integrated circuit (IC) external to the leadframe. The leadframe may additionally include first and second switched nodes, configured for electrical connection to the first control FET and the first sync FET via a first clip, and to the second control PET and the second sync PET via a second clip, respectively. | 2013-10-03 |
20130256860 | SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD THEREOF - There is provided a technology enabling the improvement of the reliability of a semiconductor device manufactured by physically fixing separately formed chip mounting portion and lead frame. A feature of an embodiment resides in that, a second junction portion formed in a suspension lead is fitted into a first junction portion formed in a chip mounting portion, thereby to physically fix the chip mounting portion and the suspension lead. Specifically, the first junction portion is formed of a concave part disposed in the surface of the chip mounting portion. The second junction portion forms a part of the suspension lead. | 2013-10-03 |
20130256861 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ROUTABLE CIRCUITRY AND METHOD OF MANUFACTURE THEREOF - An integrated circuit packaging system, and a method of manufacture therefor, including: electrical terminals; circuitry protective material around the electrical terminals and formed to have recessed pad volumes; routable circuitry on the top surface of the circuitry protective material; and an integrated circuit die electrically connected to the electrical terminals. | 2013-10-03 |
20130256862 | Support Device for a Semiconductor Chip and Optoelectronic Component with a Carrier Device and Electronic Component with a Carrier Device - A carrier device for a semiconductor chip includes a bondable and/or solderable metallic carrier having a mounting region for the semiconductor chip and a soldering region. The carrier is at least partly covered with a covering material. A solder barrier is arranged between the soldering region and the mounting region at an interface between the carrier and the covering material. An electronic component and an optoelectronic component are furthermore specified. | 2013-10-03 |
20130256863 | EPOXY RESIN COMPOSITION FOR SEMICONDUCTOR ENCAPSULATION AND SEMICONDUCTOR DEVICE - A highly reliable semiconductor device with the improved humidity resistance reliability is disclosed. A disclosed epoxy resin composition for semiconductor encapsulation encapsulates, in the manufacture of the semiconductor device, a semiconductor element that is mounted on a lead frame having a die pad unit or a circuit substrate and a wire that connects an electrical junction disposed on the lead frame or circuit substrate and an electrode pad disposed on the semiconductor element. The epoxy resin composition includes an epoxy resin (A), a curing agent (B), and an inorganic filler (C). The epoxy resin (A) has a main peak area of 90% or more with respect to the total area of all peaks as measured by the gel permeation chromatography area method. | 2013-10-03 |