40th week of 2014 patent applcation highlights part 82 |
Patent application number | Title | Published |
20140298041 | PORTABLE COMPUTING DEVICE WITH METHODOLOGIES FOR CLIENT-SIDE ANALYTIC DATA COLLECTION - A portable computing device with methodologies for client-side analytic data collection are described. In one embodiment, for example, a method performed by a portable computing device having volatile and non-volatile memory includes obtaining a plurality of events to be logged; serializing the events to be logged; storing the serialized events in the volatile memory; encrypting the serialized events to produce serialized and encrypted events; storing the serialized and encrypted events in the non-volatile memory; decrypting the serialized and encrypted events to produce serialized and decrypted events; storing the serialized and decrypted events in the volatile memory; compressing the serialized and decrypted events to produce compressed, serialized, and decrypted events; encrypting the compressed, serialized, and decrypted events to produce encrypted, compressed, and serialized events and storing the encrypted, compressed, and serialized events in the non-volatile memory. | 2014-10-02 |
20140298042 | MEASURING DEVICE, INFORMATION PROCESSOR, KEY MANAGEMENT DEVICE, AND CONSUMPTION CALCULATING SYSTEM - A measuring device has a consumption measurer to measure a consumption of at least one target equipment at every unit time within a predetermined measurement area, a consumption storage to store the measured consumption, a secret key storage to store a secret key shared with a key management device, an encryption key updater to update an encryption key at every predetermined period based on the secret key and time information, an encryption key storage to store the encryption key, an encryptor to generate encrypted data by encrypting the consumption using the encryption key stored in the encryption key storage, an encrypted data storage to store the encrypted data, and a communication controller to control transmission of the encrypted data, which is stored in the encrypted data storage, to a total consumption detecting device. | 2014-10-02 |
20140298043 | MEMORY CHIP - According to one embodiment, a memory chip, which is connected to a controller that controls reading and writing of data in response to a request from an external device, includes: a memory including a special area that is a predetermined data storage area; a key storage unit that stores therein a second key that corresponds to a first key used by the external device to convert the data; a converting unit that receives, from the controller, data to be written into the special area and generates converted data by converting the data to be written using the second key; and a writing unit that writes the converted data into the special area. | 2014-10-02 |
20140298044 | METHOD AND APPARATUS FOR SECURE MEASUREMENT CERTIFICATION - The invention relates to methods and apparatuses for acquiring a physical measurement, and for creating a cryptographic certification of that measurement, such that its value and time can be verified by a party that was not necessarily present at the measurement. | 2014-10-02 |
20140298045 | Battery Management System - A method includes determining a need to perform a learn cycle on a battery in a processing module of an information handling system, detecting a learn cycle in progress on another battery in another processing module of the information handling system, and postponing the learn cycle on the battery in response to detecting the learn cycle on the other battery. | 2014-10-02 |
20140298046 | UNIVERSAL SERIAL BUS CHARGERS AND CHARGING MANAGEMENT METHODS - Universal serial bus chargers and charging management methods thereof are provided. The universal serial bus charger includes a control unit, a charger module, a universal serial bus interface device, and a switch device. The control unit receives a power management signal and provides a switching signal and a charging signal according to the power management signal. The charger module outputs power and a power suspending signal according to the charging signal and a communications protocol signal, respectively. The universal serial bus interface device operates according to the power, and outputs the communications protocol signal according to a universal serial bus peripheral device connected thereto. The switch device is coupled between the charger module and the universal serial bus interface device, and receives the power. Furthermore, the switch device provides the power to the universal serial bus interface device according to the switching signal. | 2014-10-02 |
20140298047 | POWER BUDGET ALLOCATION IN A CLUSTER INFRASTRUCTURE - A system and method for allocating power resources among host computers in a cluster uses lower and upper bounds with respect to a power budget to be distributed to each of the hosts. Each host is allocated a portion of the cluster power capacity. Any excess amount of the capacity is then allocated to the hosts based at least partly on the lower bound (reserve capacity) and the upper bound (host power limit) of each of the clients. | 2014-10-02 |
20140298048 | ELECTRONIC DEVICE AND METHOD OF CONTROLLING ELECTRONIC DEVICE - An electronic device includes a first supply target unit that accepts supply of power from an external power supply, a second supply target unit that accepts supply of power from a battery, a main body, and a controller, wherein the controller starts to accept supply of power from both the external power supply and the battery and starts to output, to the main body, a voltage of the power supplied from both the external power supply and the battery in a case where a predetermined time has elapsed since start of a predetermined operation of the main body while a voltage of power accepted from the external power supply has been output to the main body. | 2014-10-02 |
20140298049 | DIGITAL SIGNAL TRANSITION COUNTERS FOR DIGITAL INTEGRATED CIRCUITS - A digital integrated circuit may include a digital data processing circuit having multiple signal lines that each go through signal transitions during operation of the digital data processing circuit. A digital counter circuit may count the combined number of signal transitions that take place on at least two of the multiple signal lines during operation of the digital circuit. A digital counter circuit may count the number of times a particular pattern of signal transitions takes place on at least one signal line during operation of the circuit. A computer program may receive information indicative of a composition of a digital integrated circuit, input vectors to the digital integrated circuit, and how much power is being consumed by the digital integrated circuit under each of the input vectors. The program may output information indicative of an amount of power being consumed by each of multiple, different sub-sections of the digital integrated circuit while responding to the input vectors. | 2014-10-02 |
20140298050 | INFORMATION PROCESSING APPARATUS, CONTROL METHOD AND COMPUTER-READABLE RECORDING MEDIUM - An information processing apparatus includes a hardware button configured to enable a user to press; a control unit configured to define a predetermined press process executed in response to a press of the hardware button; a processing unit configured to execute a predetermined process; a press detection unit configured to detect the press of the hardware button; a press process rejection unit configured to instruct the control unit to reject the execution of the press process when the press of the hardware button is detected; and a process execution unit configured to instruct the processing unit to execute the predetermined process when the press of the hardware button is detected. | 2014-10-02 |
20140298051 | FEATURE MANAGEMENT SYSTEM AND METHOD OF MANAGING ACCESS TO APPLICATION PROGRAMMING INTERFACE FUNCTIONALITY - A feature management system and method of managing access to API functionality. One embodiment of the feature management system includes: (1) a driver configured to carry out functions, including a restricted function, in response to calls thereto, (2) a memory configured to store a management action associated with the restricted function and (3) a feature manager operable to recognize the call to the restricted function and to retrieve the management action from the memory and direct the driver to carry out the management action in addition to the restricted function. | 2014-10-02 |
20140298052 | ENERGY EFFICIENCY IN SOFTWARE DEFINED NETWORKS - Mechanism for implementing energy efficiency (EE) policies on flows in a software defined network are disclosed. A controller node receives from each of a plurality of datapath nodes, a corresponding set of EE actions that the respective datapath node is capable of implementing. A flow is identified, and a group of datapath nodes through which the flow is routed is identified. Based on an attribute of the flow, an EE policy is determined. Based on the EE policy, a datapath node in the group of datapath nodes is directed to perform an EE action on packets associated with the flow. | 2014-10-02 |
20140298053 | UNIVERSAL SERIAL BUS HUB AND CONTROL METHOD THEREOF - A universal serial bus and a control method thereof are provided. Different voltages are respectively provided to circuit groups when a universal serial bus hub is in a suspend state and a normal working state, so as to reduce leakage current. | 2014-10-02 |
20140298054 | INFORMATION PROCESSING APPARATUS CAPABLE OF CONNECTING TO NETWORK IN POWER SAVING STATE, METHOD OF CONTROLLING THE SAME, AND STORAGE MEDIUM - An information processing apparatus capable of changing packet patterns for determining, based on a condition of proxy ARP compatibility of a connected wireless LAN access point, communication requests to which the apparatus can respond in a power saving state, and thereby maintaining the power saving state for a longer time period. A RAM of an MFP operable in the normal state and the power saving state stores packet patterns which enable the MFP to respond to packets received in the power saving state while maintaining the power saving state. The MFP acquires proxy ARP support information from a wireless LAN access point that relays communication between the MFP and an external apparatus. The MFP determines whether or not the AP can respond to a received communication request on its behalf, and changes the packet patterns based on the determination result. | 2014-10-02 |
20140298055 | ENERGY SAVING CIRCUIT OF COMPUTER - An energy saving circuit of a computer is connected between a power supply and a motherboard. The energy saving circuit includes first to fifth electronic switches and a sensor. When the computer is in a stand-by state and the sensor senses a person nearby, the motherboard of the computer receives a standby voltage and the motherboard maintains the stand-by state. When the sensor senses no one nearby, the motherboard does not receive the standby voltage and the motherboard is placed in a power off state. | 2014-10-02 |
20140298056 | MEMORY CONTROL CIRCUIT - The memory power consumption is reduced more than in the past by performing a power control suitably for a nonvolatile memory. A memory control circuit is provided with a first register group for a CPU to perform separately initial setting of the operation mode (power OFF, standby, and power ON) of plural banks included in a nonvolatile memory, for every task of a program executed by the CPU, and an access determination unit which determines a bank to which an access from the CPU takes place, on the basis of the access address for instruction fetching and the kind of the fetched instruction. The memory control circuit switches the operation mode of each of the banks on the basis of the setting value of the first register group, and the determination result of the access determination unit. | 2014-10-02 |
20140298057 | METHOD AND APPARATUS FOR REDUCING CHIP POWER CONSUMPTION - The present invention discloses a method for reducing chip power consumption. The method includes: monitoring real-time load statuses of an input interface, an output interface, and an internal bus of a chip, and collecting load monitoring information; adjusting a working frequency of the chip according to the load monitoring information; and performing rate limiting for an information transmission rate of each channel of the chip according to the current working frequency of the chip. The method and apparatus for reducing chip power consumption according to the present invention solve a problem in the prior art that in a process of chip frequency modulation and power consumption reduction, it is difficult to implement constant rate limiting for a chip channel, thereby providing a feasible solution for reducing chip power consumption while maintaining constant rate limiting for the chip channel. | 2014-10-02 |
20140298058 | ADVANCED FINE-GRAINED CACHE POWER MANAGEMENT - Methods and apparatuses for reducing leakage power in a system cache within a memory controller. The system cache is divided into multiple sections, and each section is supplied with power from one of two supply voltages. When a section is not being accessed, the voltage supplied to the section is reduced to a voltage sufficient for retention of data but not for access. The cache utilizes a maximum allowed active section policy to limit the number of sections that are active at any given time to reduce leakage power. Each section includes a corresponding idle timer and break-even timer. The idle timer keeps track of how long the section has been idle and the break-even timer is used to periodically wake the section up from retention mode to check if there is a pending request that targets the section. | 2014-10-02 |
20140298059 | ELECTRONIC APPARATUS AND ASSOCIATED POWER MANAGEMENT METHOD - An electronic apparatus is provided. The electronic apparatus includes a dynamic random access memory (DRAM), a power integrated circuit (IC), and a central processing unit (CPU). When a standby mode of the electronic apparatus is set to a fast reboot mode, the CPU stops providing a clock signal to the DRAM and controls the power IC to continuously supplying power to the DRAM, so that the DRAM enters a self-refresh mode. | 2014-10-02 |
20140298060 | ASYMMETRIC MULTI-CORE PROCESSOR WITH NATIVE SWITCHING MECHANISM - A processor includes first and second processing cores configured to support first and second respective subsets of features of its instruction set architecture (ISA) feature set. The first subset is less than all the features of the ISA feature set. The first and second subsets are different but their union is all the features of the ISA feature set. The first core detects a thread, while being executed by the first core rather than by the second core, attempted to employ a feature not in the first subset and, in response, to indicate a switch from the first core to the second core to execute the thread. The unsupported feature may be an unsupported instruction or operating mode. A switch may also be made if the lower performance/power core is being over-utilized or the higher performance/power core is being under-utilized. | 2014-10-02 |
20140298061 | POWER CONTROL IN A DISPERSED STORAGE NETWORK - A method begins by a dispersed storage (DS) processing module of a dispersed storage network (DSN) receiving a plurality of data access requests regarding a plurality of data objects. As individual data access requests of the plurality of data access requests are received, the method continues with the DS processing module, for each of the individual data access requests identifying a corresponding one of a plurality of logical storage pools of the DSN and determining power based access status of the corresponding one of the plurality of logical storage pools. When the power based access status is power saving mode, the method continues with the DS processing module queuing the individual data access request. When the power based access status is not in the power saving mode, the method continues with the DS processing module executing the individual data access request. | 2014-10-02 |
20140298062 | ELECTRONIC DEVICE HAVING COVER - An electronic device having a cover includes a cover unit rotated about one side of the electronic device and having a magnet member; a magnetic body mounted within the electronic device and magnetized by the magnet member; a sensor unit provided close to the magnetic body to sense a magnetic flux generated by the magnetic body; and a controller which executes a user experience according to a signal output of the sensor unit. | 2014-10-02 |
20140298063 | BATTERY DEVICE AND ENERGY STORAGE SYSTEM INCLUDING THE SAME - Provided is an energy storage system including: a battery device that is configured from multiple battery unit modules; and a power converting system that is configured to be connected to the battery device and that converts electric power that is applied between an electric power system and the battery device, in which the battery device includes multiple switches, each of which establishes a connection between each of the battery unit modules and the power converting system. | 2014-10-02 |
20140298064 | ELECTRONIC SYSTEM WITH AUTO POWER-OFF FUNCTION AND OPERATING METHOD THEREOF - An electronic system with auto power-off function including a power source, an electronic device, a detection unit, and a processing unit is disclosed. The power source is used to provide the power need to operate the electronic system. The detection unit is used to detect a plurality of raw data on the electronic device. The processing unit is coupled to the detection unit and the power and used to determine whether a raw data changing region on the electronic device is larger than a threshold area according to the plurality of raw data and to selectively shut down the power source. | 2014-10-02 |
20140298065 | MOBILE TERMINAL AND DISPLAY PANEL DRIVER - A display device includes a boosting power supply circuit, a logic circuit and a charge transport path. The boosting power supply circuit generates a boosted power supply voltage by boosting an analog power supply voltage. The logic circuit is responsive to a decrease in a voltage level on at least one of power supply lines to which analog and logic power supply voltages are supplied for controlling a source line drive circuitry and a gate line drive circuitry to discharge charges accumulated in the display panel. The charge transport path is configured to transport charges from a power supply line on which the boosted power supply voltage is generated to a power supply line which supplies an internal logic power supply voltage to the logic circuit in response to the decrease in the voltage level on the at least one of the first and second power supply lines. | 2014-10-02 |
20140298066 | SYSTEM AND METHOD FOR SECURELY WAKING A COMPUTER SYSTEM OVER A NETWORK - System and method for securely waking a computer system over a network. A registration message may be received by a server from a network interface controller (NIC) in a first computer system over a network. The first computer system may be in a sleep mode. The first computer system may be registered by the server: identification information for the first computer system may be stored in a memory. A wakeup message may be received from a second computer system over the network. The wakeup message may include information identifying the first computer system and authentication information. The wakeup message may be sent to the first computer system over the network. The wakeup message may indicate to the NIC to wake up the first computer system. The authentication information may be authenticated by either or both of the server or the NIC prior to waking up the first computer system. | 2014-10-02 |
20140298067 | METHODS AND APPARATUS FOR REDUCING ENERGY CONSUMPTION OF NETWORK EQUIPMENT - In some embodiments, an equipment unit has a set of visual indicators, a power switch, and a set of compute components. The power switch receives a signal representing a status such that when the status is in a first mode, the power switch provides power to the set of visual indicators and when the status is in a second mode the power switch does not provide power to the set of visual indicators. The compute components are configured to receive power when the power switch does not provide power to the set of visual indicators. | 2014-10-02 |
20140298068 | DISTRIBUTION OF POWER GATING CONTROLS FOR HIERARCHICAL POWER DOMAINS - An integrated circuit device includes a first module disposed within a first power domain, a second module disposed in a second power domain that is a sub-domain of the first power domain, first power gating logic, and second power gating logic. The first power gating logic generates a first virtual power supply for the first module. The second power gating logic is powered by the first virtual power supply for generating a second virtual power supply for the second power domain. | 2014-10-02 |
20140298069 | KEY CIRCUIT AND ELECTRONIC DEVICE USING THE SAME - An electronic device includes a first voltage module, a second voltage module, a key circuit, and a processor. The key circuit controls the first voltage module to provide different voltages to the processor based on different operations of user. The processor determines whether the voltage provided by the first module is changed by one pressed key from the key circuit. When the voltage provided by the first module is changed by two pressed keys from the key circuit, the processor does not compares the voltage provided by the first module to standard voltages and does not execute any function. | 2014-10-02 |
20140298070 | PROCESSOR TIME SYNCHRONIZATION APPARATUS AND METHOD IN DATA COMMUNICATION SYSTEM WITH MULTIPLE PROCESSORS AND LINE INTERFACES - A processor time synchronization apparatus and method in a data communication system which includes a plurality of processors and line interfaces. The processor time synchronization apparatus includes a first local processor configured to recognize a time difference between an external device and the system based on a time message exchanged with the external device, and synchronize time between the external device and the system, and a second local processor configured to receive time information from the first local processor that has been time-synchronized with the external device, the time information containing the time difference between the external device and the system, and synchronize the first local processor with a system's internal time using the received time information. | 2014-10-02 |
20140298071 | SEMICONDUCTOR DEVICES AND SEMICONDUCTOR SYSTEMS INCLUDING THE SAME - A semiconductor device including an internal command generator and a bias generator is provided. The internal command generator generates first to fourth internal command signals sequentially enabled in synchronization with pulses of an external program signal. The first internal command signal controls a read operation for reading out data stored in memory cells, and the second and third internal command signals control a program operation for programming the memory cells. The bias generator generates a read bias signal for controlling a level of an output voltage signal, which is applied to an internal circuit, in response to the first and fourth internal command signals. | 2014-10-02 |
20140298072 | METHOD AND APPARATUS FOR SYNCHRONISING THE LOCAL TIME OF A PLURALITY OF INSTRUMENTS - A method of determining the downstream propagation time of signals from a USB Host Controller across one or more USB cables and one or more USB Hubs to a SuperSpeed USB device, including locking a clock of the SuperSpeed USB device to information that includes a first timestamp, transmitting a plurality of signals to the USB Host Controller, each of the signals containing a second timestamp indicative of a local time of the SuperSpeed USB device when the respective signal was generated by the SuperSpeed device; the USB Host Controller creating a third timestamp indicative of a time of reception from the SuperSpeed USB device; determining a time period from one or more respective time differences between corresponding second and third timestamps, the time period being indicative of a sum of a downstream propagation time and an upstream propagation time; and determining the downstream propagation time from the time period. | 2014-10-02 |
20140298073 | On-Demand Scalable Timer Wheel - Various embodiments enable on-demand scaling of a timer wheel. Some embodiments dynamically start and stop a timer wheel based, at least in part, on whether the timer wheel has any associated active timers. In some cases, the timer wheel is suspended when all associated active timers have been serviced. Alternately or additionally, the timer wheel is re-activated upon associating one or more active timers in need of service to the timer wheel. Various embodiments enable addition and removal of timer(s) to the timer wheel and/or various time slots associated with the timer wheel without using a global lock associated with the timer wheel. | 2014-10-02 |
20140298074 | METHOD OF CALCULATING CPU UTILIZATION - A method of determining processor utilization includes: counting, via a first counter on a processor, a number of elapsed clock cycles while code is being executed; counting, via a second counter on a processor, a total number of free-running clock cycles; and dividing the number of clock cycles where code is being executed by the total number of free-running clock cycles to determine a CPU utilization. | 2014-10-02 |
20140298075 | Serial-to-Parallel Converter - A method for converting serial data having a certain word size to parallel data, comprises the steps of: generating segments from the serial data using one or more serially-connected first stages, wherein the segments have a predetermined bit size; storing each of the segments into a selectively turned-on flip-flop of a final stage, wherein the final stage is serially connected to the first stages, wherein the final stage has a plurality of flip-flops and each of the flip-flops has a bit size equaling to the bit size of the segments; and outputting the stored segments in parallel from the final stage. | 2014-10-02 |
20140298076 | PROCESSING APPARATUS, RECORDING MEDIUM STORING PROCESSING PROGRAM, AND PROCESSING METHOD - A processing apparatus that constitutes an information processing system includes: a device that constitutes the processing apparatus; and a processing unit that detects an abnormality in the device, that counts the number of the abnormalities detected in the device, and that logically separates the device from the information processing system when the counted number of the abnormalities detected in the device is equal to or greater than a threshold. | 2014-10-02 |
20140298077 | Scalable Relational Database Replication - A relational database replication system includes a client, at least one primary database, a plurality of secondary databases and replication agents which coordinate database transactions. The system provides a high level of performance, reliability, and scalability with an end result of efficient and accurate duplication of transactions between the primary and secondary databases. In one implementation, the client transmits sets of database update statements to the primary database and primary agent in parallel; the primary agent replicates the statements to at least one secondary agent. A transaction prepare and commit process is coordinated between the primary database and the primary agent, which in turn coordinates with the at least one secondary agent. Databases can be partitioned into individual smaller databases, called shards, and the system can operate in a linearly scalable manner, adding clients, databases and replication agents without requiring central coordination or components that cause bottlenecks. | 2014-10-02 |
20140298078 | SYNCHRONOUS MIRRORING OF NVLog TO MULTIPLE DESTINATIONS (ARCHITECTURE LEVEL) - Systems and methods herein are operable to simultaneously mirror data to a plurality of mirror partner nodes. In embodiments, a mirror client may be unaware of the number of mirror partner nodes and/or the location of the plurality of mirror partner nodes, and issue a single mirror command requesting initiation of a mirror operation. An interconnect layer may receive the single mirror command and split the mirror command into a plurality of mirror instances, one for each mirror node partner, wherein the mirror instances may be simultaneously launched. After the plurality of mirror operations has begun, the interconnect layer may manage completion reports indicating the completion status of respective mirror operations, and send a single return to the mirror client indicating whether the mirror command succeeded. | 2014-10-02 |
20140298079 | Localized Fast Bulk Storage in a Multi-Node Computer System - A high performance computing (HPC) system includes computing blades having a first region that includes computing circuit boards having processors for performing a computation, and a second region that includes non-volatile memory for use in performing the computation. The regions are connected by a plurality of power connectors that convey power from the computing circuit boards to the memory, and a plurality of data connectors that convey data between the first and second regions. The power and data connectors are configured redundantly so that failure of a computing circuit board, a power connector, or a data connector does not interrupt the computation. A method of performing such a computation, and a computer program product implementing the method, are also disclosed. | 2014-10-02 |
20140298080 | INTRA-REALM AAA FALLBACK MECHANISM - There is provided an intra-realm AAA (authentication, authorization and accounting) fallback mechanism, wherein the single global realm may be divided in one or more sub-realms. The thus presented mechanism exemplarily comprises detecting a failure of an authentication server serving at least one authentication client within a first sub-realm of a single-realm authentication system, and routing authentication messages of the at least one authentication client to a fallback authentication server within a second sub-realm of the single-realm authentication system, wherein routing may exemplarily comprise sub-realm based source routing. | 2014-10-02 |
20140298081 | DISTRIBUTED SWITCHING SYSTEM FOR PROGRAMMABLE MULTIMEDIA CONTROLLER - In one embodiment, two or more programmable multimedia controllers are provided a multimedia system that includes a plurality of audio/video (A/V) devices that source or output digital media streams. Each of the programmable multimedia controllers has at least a processing subsystem and a switch capable of switching the digital media streams. Arbitration is conducted among the programmable multimedia controllers to select one of the programmable multimedia controllers as winning the arbitration. Master status is assigned to the one of the programmable multimedia controllers that won the artitration. Subordinate status is assigned to at least one other programmable multimedia controller that did not win the arbitration. It is periodically verified whether the programmable multimedia controller assigned master status is operating. In response to the programmable multimedia controller assigned master status having experienced a failure, master status is reassigned to a programmable multimedia controller that was originally is assigned subordinate status. | 2014-10-02 |
20140298082 | TESTING SERVER, INFORMATION PROCESSING SYSTEM, AND TESTING METHOD - A testing server performs a test to check whether servers properly execute failover. The testing server includes a generation unit, a transmitting unit, a testing unit, a restoring unit, a judgment unit, and a power control unit. The generation unit generates an image file of an OS. The transmitting unit transmits the image file to to-be-tested servers. The testing unit injects a simulated fault into a server among the servers to which the image file is transmitted and performs a test. The restoring unit, each time the testing unit performs a test, restores a status of the to-be-tested server to a pre-failover status. The judgment unit judges whether the restoring unit properly restores the status. The power control unit, when the judgment unit judges that the status of the to-be-tested server is not properly restored, turns off power of the to-be-tested server and turns on the power again. | 2014-10-02 |
20140298083 | METHOD FOR SIP PROXY FAILOVER - For SIP proxy failover in a SIP telecommunication network (SIPN) comprising a plurality of proxies (P | 2014-10-02 |
20140298084 | VIRTUAL TAPE DEVICE, TAPE CONTROL DEVICE, AND TAPE CONTROL METHOD - A virtual tape device connected to an upper device and a tape library device, and storing a tape volume includes: a storage unit to store the tape volume including a plurality of blocks; an identifier control unit to add to each block of the tape volume a first identification number which is incremented for each block, and a second identification number which is incremented only in a block subsequent to a leading block, a tape mark indicating a delimiter of a file, and a block subsequent to the tape mark; a first control unit to control a read and a write of the tape volume stored in the storage unit using the second identification number; and a second control unit to write the tape volume and the first identification number to the tape library device, and control the tape library device using the first identification number. | 2014-10-02 |
20140298085 | DETECTING DATA REQUIRING REBUILDING IN A DISPERSED STORAGE NETWORK - A method begins with a processing module within a dispersed storage network (DSN) determining to perform a rebuild scanning function for a virtual memory vault, where the virtual memory vault has a DSN address range that is divided into multiple DSN address sub-ranges. The method continues with a first rebuild scanning agent module initiating a rebuilding scanning function for a first group of DSN address sub-ranges and processing first rebuild responses to produce a first list of encoded data slices for rebuilding. The method continues with a second rebuild scanning agent module initiating the rebuilding scanning function for a second group of DSN address sub-ranges and processing second rebuild responses to produce a second list of encoded data slices for rebuilding. The method continues with the processing module queuing the first and second lists of encoded data slices for rebuilding. | 2014-10-02 |
20140298086 | STORAGE DEVICE, CONTROLLER DEVICE, AND MEMORY DEVICE - A storage device includes a controller device and a memory device. The controller device transmits communication information to which route information is added, the route information indicating a route to a destination of the communication information and including an address of a relay point that the communication information passes through before reaching the destination of the communication information. The memory device receives the communication information, and to transmit the communication information to a next relay point, when the destination of the communication information is not the local memory device, by using the address of the relay point included in the route information of the communication information. | 2014-10-02 |
20140298087 | HARD DISK DATA RECOVERY METHOD, APPARATUS, AND SYSTEM - This invention discloses a hard disk data recovery method, apparatus, and system. The method includes: recording a logical block address corresponding to erroneous data if an error is discovered when data is read from the hard disk; performing a recovery operation for data at a first physical block address corresponding to the logical block address according to a preset algorithm to obtain recovered data; and sending an instruction of writing the recovered data into the logical block address to the hard disk so that the hard disk writes the recovered data into the logical block address according to the instruction, where the logical block address corresponds to a remapped second physical block address. Therefore, the method repairs an erroneous sector or a bad block of the hard disk quickly and improves efficiency of repairing the erroneous sector of the hard disk or the bad block of the hard disk. | 2014-10-02 |
20140298088 | DATA CONDITIONING TO IMPROVE FLASH MEMORY RELIABILITY - Methods for managing data stored in a memory device facilitate managing utilization of memory of different densities. The methods include reading first data from a first number of pages or blocks of memory cells having a first density, performing a data handling operation on the read first data to generate second data, and writing the second data to a second number of pages or blocks of memory cells having a second density, wherein the second density is different than the first density, and wherein the second number is different than the first number. | 2014-10-02 |
20140298089 | STORAGE CONTROL DEVICE AND STORAGE CONTROL METHOD - A storage control device includes a processor. The processor is configured to request a plurality of disk devices storing data therein to notify the processor of degradation information on degradation of data stored in the respective disk devices. The processor is configured to instruct, based on first information among notified degradation information, the plurality of disk devices to rewrite data. The first information serves as a trigger of rewriting data. The first information is notified by at least one of the plurality of disk devices. | 2014-10-02 |
20140298090 | DATA RECOVERY IN A SOLID STATE STORAGE SYSTEM - Methods for data recovery and memory systems are provided. According to at least one such method, when defective data is read from a memory location, the data is recovered by an XOR operation on the remaining good data and associated RAID data to reconstruct the defective data. The defective data is excluded from the XOR operation. | 2014-10-02 |
20140298091 | Fault Tolerance for a Distributed Computing System - In one embodiment, a method detects a failure of a container in a controller node where the container includes a service being performed and isolated from other services being performed in other containers on the controller node. The controller node terminates the container including the service and determines a known state for the service. The known state is known to be operational without including a cause of the failure and the service operated from the known state saving changes to the known state during operation separately from the known state. The controller node restarts the service in a new container that replaces the terminated container where the restarted service starts from the known state without using the changes. | 2014-10-02 |
20140298092 | ADAPTIVE QUIESCE FOR EFFICIENT CROSS-HOST CONSISTENT CDP CHECKPOINTS - A disaster recovery system, including a target datastore for replicating data written to source datastores, and a checkpoint engine (i) for transmitting, at multiple times, quiesce commands to a plurality of host computers, each quiesce command including a timeout period that is adjusted at each of the multiple times, (ii) for determining, at each of the multiple times, whether acknowledgements indicating that a host has successfully stopped writing enterprise data to the source datastores, have been received from each of the host computers within the timeout period, (iii) for marking, at each of the multiple times, a cross-host checkpoint in the target datastore and reducing the timeout period for the quiesce commands at the next time, if the determining is affirmative, and (iv) for increasing, at each of the multiple times, the timeout period for the quiesce commands transmitted at the next time, if the determining is not affirmative. | 2014-10-02 |
20140298093 | USER OPERATION HISTORY FOR WEB APPLICATION DIAGNOSTICS - A system and method for diagnosing an error during a user operation in a web application. An example method is executed, at least in part, by a server system, wherein the server system also executes, at least in part, a web application. The example method includes recording user operations during a user's interaction with the web application; storing the user operations in a click history record in a primary memory device; determining that an error has occurred during the user's interaction with the web application; in response to the determining, transferring at least a portion of the click history record to a secondary memory device; including correlation information in association with the click history; identifying at least one other record by using the correlation information; and providing the click history record and the at least one other record to analysis software and accompanying user interface display screen so that the error can be diagnosed. | 2014-10-02 |
20140298094 | PROCESSOR POWER MEASUREMENT - A system can include a processing core to execute machine readable instructions. The system can also include a memory accessible by the processor core. The memory can include preprogrammed test data that characterizes one of an impedance of a processor and a current output to the processor during execution of a test routine. The processor can include the processing core and the one of the impedance of the processor and the current output to the processor is based on a power measurement taken during execution of a test routine. The power measurement can be taken with a current sensor that is at least one of lossy or at least about 98% accurate. | 2014-10-02 |
20140298095 | MEDICAL TEST SIGNAL GENERATOR AND INTERFACE - A cardiac signal generator includes a first circuit, a user input device, an output display, and a processing circuit. The first circuit provides, according to any of predetermined plurality of settings, cardiac signals comprising a repeating cardiac waveform, and respiratory signals comprising a repeated respiratory waveform. The output display includes a plurality of indicators, each indicator corresponding to one of the plurality of settings. Each setting includes a combination of a frequency of repetition of the cardiac waveform and a frequency of repetition of the respiratory waveform. The processing circuit causes the first circuit to provide cardiac and respiratory signals according to a selected one of the plurality of settings. The processing circuit is further configured to receive a signal from the user input device, and change the selected setting from a first setting of the plurality of settings to a second setting of the plurality of settings responsive thereto. | 2014-10-02 |
20140298096 | LOW POWER TEST SIGNAL GENERATOR FOR MEDICAL EQUIPMENT - A cardiac signal generator includes a portable housing, a memory, a processing device, a digital to analog converter, and at least one analog output. The memory stores programming instructions including instructions defining a plurality of mathematical relationships. The processing device is configured to execute said programming instructions to generate a sequence of output values using the plurality of mathematic relationships as a function of time, wherein said sequence of output values defines a sampled waveform output simulating an ECG signal and having linear portions and at least one curved portion. The processing device furthermore provides the sequence of output values at an output. The digital to analog converter is operably coupled to receive the sequence of output values from the output, and generates an electrical signal having a waveform corresponding to the sampled waveform output. The analog output is operably coupled to the digital to analog converter. | 2014-10-02 |
20140298097 | SYSTEM AND METHOD FOR CORRECTING OPERATIONAL DATA - A method implemented using a processor based device for generating a corrected data for deriving a decision related to a data source includes receiving measurement data representative of an operational parameter from the data source. The operational parameter includes a monotonous time series data. The method also includes identifying an event based on the measurement data and determining an event category based on the identified event. The method further includes processing the measurement data using a statistical data correction technique, based on the determined event category, to generate the corrected data for deriving the decision related to the data source. | 2014-10-02 |
20140298098 | DATA-AGNOSTIC ANOMALY DETECTION - This disclosure presents computational systems and methods for detecting anomalies in data output from any type of monitoring tool. The data is aggregated and sent to an alerting system for abnormality detection via comparison with normalcy bounds. The anomaly detection methods are performed by construction of normalcy bounds of the data based on the past behavior of the data output from the monitoring tool. The methods use data quality assurance and data categorization processes that allow choosing a correct procedure for determination of the normalcy bounds. The methods are completely data agnostic, and as a result, can also be used to detect abnormalities in time series data associated with any complex system. | 2014-10-02 |
20140298099 | INTELLIGENT DETECTION SYSTEM AND METHOD FOR DETECTING DEVICE FAULT - An intelligent detection system and detection method are presented. The system includes a central processing board (CPB), a data acquisition board (DAB), a synchronous communication board (SCB) and a plurality of connection plugs. For data transformation, the CPB, DAB and SCB are connected via the plurality of connection plugs. A plurality of sensors are connected to the intelligent detection system to collect the data reflecting the operation status of the device to be detected. The intelligent detection system and method achieve a real-time and accurate detection and diagnosis of the mechanical failure by detecting the temperature, the vibration and/or the noise signals of device. | 2014-10-02 |
20140298100 | METHOD FOR OPERATING A CONTAINER TREATMENT SYSTEM WITH FAULT DIAGNOSIS - Method for operating a container treatment system ( | 2014-10-02 |
20140298101 | DISTRIBUTED PRESSURE TESTING SYSTEM AND METHOD - A distributed pressure testing system and method are disclosed, in which a test server transmits different test commands to corresponding test terminals so that the test terminals performing a pressure test on a unit under test according to the test commands, and the unit under test transmits the test result to the test server after the test server transmits a back-transmit request, so that the test server adjusts a pressure until the performance index meets up with the predetermined threshold parameter according to the test result. By means of the technical means of the present invention, an efficacy of increased test accuracy may be achieved. | 2014-10-02 |
20140298102 | DIAGNOSTIC DATA SET COMPONENT - Various embodiments for retaining diagnostic information for data in a computing storage environment. In one such embodiment, a diagnostic component, apart from a volume table of contents (VTOC), associated with an integrated catalog facility (ICF) catalog and with a base data set from data sets via a catalog association record, is initialized. The diagnostic component is configured to retain base data set-specific diagnostic information retrievable by the computing storage environment to assist in error diagnosis and the ICF catalog is one of the data sets storing information about the data sets for facilitating a retrieval of a name of the base data set and assists with retaining and retrieval of the base data set-specific diagnostic information. The base data set-specific diagnostic information is stored pursuant to at least one event associated with the base data set. | 2014-10-02 |
20140298103 | METHOD OF FAILURE DETECTION IN AN OPERATING SYSTEM - Method of failure detection in an operating system, the method comprising sending a request from a client to a server through a router, storing a token at the router, carrying out the request at the server, and returning a reply from the server to the client through the router, wherein the method comprises the alternative steps of, in response to a failure in the server, generating at the router an error reply based on the token and returning the error reply from the router to the client. | 2014-10-02 |
20140298104 | Method for operating an IT system, and IT system - An IT system includes at least one first processing unit and one second processing unit The first and second processing units jointly execute an application program and are each associated with an installation routine designed to control updating of a first or second program part of the application program. A first actual state is associated with the first processing unit and a second actual state is associated with the second processing unit. After system reboot, or as soon as the first and second program part have been successfully stored, or an error is detected when storing the first and/or second program part, predefined processing steps are respectively carried out in a predefined order by the first processing unit aid the second processing unit depending on the actual state of the first processing unit and the actual state of the second processing unit. | 2014-10-02 |
20140298105 | IDENTIFYING AND TAGGING BREAKPOINT INSTRUCTIONS FOR FACILITATION OF SOFTWARE DEBUG - A processor stores an address of a first instruction of a first instruction set into a first register. The processor determines that a first instruction set location of the first instruction address matches a breakpoint instruction set location of a breakpoint instruction address stored in a second register, wherein the second register includes a state bit. The processor retrieves the first instruction. The processor determines that a breakpoint instruction offset of the breakpoint instruction address identifies the first instruction as the breakpoint. The processor sets the state bit of the second register. The processor removes the first instruction based on the state bit being set and then re-retrieves the first instruction. The processor tags the first instruction and generates an interrupt based on either the tagged first instruction being next to completion or the tagged first instruction being completed. | 2014-10-02 |
20140298106 | IDENTIFYING AND TAGGING BREAKPOINT INSTRUCTIONS FOR FACILITATION OF SOFTWARE DEBUG - A processor stores an address of a first instruction of a first instruction set into a first register. The processor determines that a first instruction set location of the first instruction address matches a breakpoint instruction set location of a breakpoint instruction address stored in a second register, wherein the second register includes a state bit. The processor retrieves the first instruction. The processor determines that a breakpoint instruction offset of the breakpoint instruction address identifies the first instruction as the breakpoint. The processor sets the state bit of the second register. The processor removes the first instruction based on the state bit being set and then re-retrieves the first instruction. The processor tags the first instruction and generates an interrupt based on either the tagged first instruction being next to completion or the tagged first instruction being completed. | 2014-10-02 |
20140298107 | Dynamic Near Real-Time Diagnostic Data Capture - To improve identifying and tracking errors on a computer, an operating system for a computer is programmed to have a framework allowing programmable monitors of events to be defined. These programmable monitors are programmed to detect one or more events or patterns of events, and have associated actions. When the pattern of events occurs, the monitor is triggered, and actions associated with the monitor can be performed. Various actions can be performed, including but not limited to data gathering about the events triggering the monitor, other events occurring during the same time period, and information about the configuration of the computer. Monitors can be dynamically updated remotely during operation of the computer. An operating system can be programmed to have any number of such monitors. Similarly, the actions that occur when a monitor is triggered also can be dynamically updated. | 2014-10-02 |
20140298108 | Desktop Management Method and Device - A desktop management method and device is disclosed in the present disclosure and the method comprising: acquiring a desktop icon of an operation object desktop to generate a mirror desktop; adjusting the desktop icon of the mirror desktop according to the desktop icon of the operation object desktop to make the desktop icon of the mirror desktop the same as the operation object desktop thereof; and displaying the desktop icon of the adjusted mirror desktop according to the stored mirror desktop arrangement manner. The present disclosure can avoid the loss and disorder of desktop contents. | 2014-10-02 |
20140298109 | INFORMATION PROCESSING DEVICE, COMPUTER-READABLE RECORDING MEDIUM, AND METHOD - An information processing device includes a plurality of memories, and a processor coupled to the plurality of memories and configured to carry out a first test to determine whether a first error is detected when first and second memories of the plurality of memories are concurrently operated, and when the first error is detected from the first test, carry out a second test to determine whether a second error is detected when the first and second memories are separately operated. | 2014-10-02 |
20140298110 | System and Method for Bit Error Rate Monitoring - In an embodiment, a method of determining whether to trigger an event based on data blocks having status data includes electronically receiving the data blocks over a channel, performing a data integrity check on the data blocks to determine whether a particular data block has a transmission fault, calculating a received error metric based on performing the data integrity check, and disabling an event trigger if the received error metric crosses a first error threshold. | 2014-10-02 |
20140298111 | CONTROLLER, SATA SYSTEM AND METHOD OF OPERATION THEREFOR - A controller for operably coupling a drive unit to a host unit in a serial advanced technology attachment (SATA) system is described. The controller comprises a hardware processor arranged to: receive a plurality of SATA data frames; identify a first primitive sequence in at least one of the plurality of SATA data frames that adversely affects a performance of the SATA system; and replace the identified first primitive sequence with a second primitive sequence in response thereto. | 2014-10-02 |
20140298112 | DETECTION METHOD, STORAGE MEDIUM, AND DETECTION DEVICE - A detection method includes: calculating a statistic for each of Q configuration items, where Q is at least one, among a plurality of configuration items, according to a first frequency and a second frequency, when an occurrence of a failure of a certain type is predicted according to a first pattern, which is a combination of P messages output from the Q configuration items within a period not longer than a predetermined length of time, where P is not less than Q; and generating result information according to the statistic, the result information indicating at least one configuration item in which the failure of a certain type is predicted to occur with a probability that is at least higher than a probability with which the failure of a certain type is predicted to occur in another of the plurality of configuration items. | 2014-10-02 |
20140298113 | STORAGE MEDIUM AND INFORMATION PROCESSING APPARATUS AND METHOD WITH FAILURE PREDICTION - A management computer performs a process comprising: a first step and a second step. The first step collects failure-predictive information including information on a plurality of kinds of phenomena related to occurrence of a failure from each of a plurality of computers including an active first computer in a redundant system that are managed by said management computer. The second step calculates, for each individual second computer of one or more second computers of a plurality of second computers associated with said first computer in said redundant system, an evaluation value that indicates the probability of occurrence of a future failure in the individual second computer using said failure-predictive information collected from the individual second computer and said failure-predictive information collected from one or more predetermined computers other than the individual second computer of said plurality of computers. | 2014-10-02 |
20140298114 | INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING SYSTEM, AND CONTROL METHOD THEREFOR - A first information processing apparatus executes an operation corresponding to a message entered thereto. Upon completion of the operation, the first information processing apparatus sends a notification to a second information processing apparatus. The second information processing apparatus stores such notifications in a memory. The second information processing apparatus also receives a message, and upon expiration of a predetermined time after receipt of the message, the second information processing apparatus determines whether the memory contains a notification relevant to the received message. When the memory contains such a notification, the second information processing apparatus avoids execution of an operation corresponding to the received message. | 2014-10-02 |
20140298115 | Program and Information Processing Apparatus - A non-transitory computer-readable medium has a program stored thereon and readable by a processor of an information processing apparatus configured to communicate with an image processing apparatus. The program, when executed by the processor, causes the information processing apparatus to perform: receiving a execution request to cause the image processing apparatus to perform the image processing, the execution request being corresponding to a job; acquiring status information indicating a status of the image processing apparatus; and notifying, during a notification time period, error information based on the status information when the status information is acquired during the notification time period, which starts at a time when the execution request is received. | 2014-10-02 |
20140298116 | METHOD AND APPARATUS FOR AN IMPROVED FILE REPOSITORY - A method and apparatus for of storing data comprising monitoring a plurality f storage units within a mass storage area and detecting when a storage unit within the mass storage area is overloaded, The method further comprising randomly distributing the data on the overloaded storage unit to the other storage units within the mass storage area. | 2014-10-02 |
20140298117 | DETECTION OF USER BEHAVIOR USING TIME SERIES MODELING - The embodiments provide a way to predict when a storage device will be accessed. In order to enhance performance, the storage device may proactively prepare for the access operation, and thus, minimize the access-time response of the storage device. The user behavior is recorded over time and collected into a dataset. In one embodiment, the intervals between the data points in the dataset are calculated and arranged into a matrix. Patterns in the matrix are recognized and used to recognize the next likely access by the user. The storage device may then take various actions, such as drive spin up, in anticipation of the next predicted access to minimize access-time response. | 2014-10-02 |
20140298118 | INFORMATION PROCESSING APPARATUS AND ERROR PROCESSING METHOD - An information processing apparatus according to one aspect of the present disclosure includes a communication control portion, an error code storage portion, an acquiring portion, and a determination portion. Communication control portion communicates with storage device based on interface communication standard, to perform data transfer therewith. Error code storage portion stores one or a plurality of selected error codes selected from a plurality of error codes defined by interface communication standard. Acquiring portion acquires error information outputted from storage device. Determination portion determines whether or not error code indicated by error information coincides with selected error code. When determination portion determines that error code coincides with selected error code, communication control portion communicates again with storage device to perform data transfer therewith. When determination portion determines that error code does not coincide with selected error code, communication control portion executes error processing corresponding to error code indicated by error information. | 2014-10-02 |
20140298119 | METHOD AND APPARATUS FOR REPAIRING HIGH CAPACITY/HIGH BANDWIDTH MEMORY DEVICES - Memory systems, systems and methods are disclosed that may include a plurality of stacked memory device dice and a logic die connected to each other by through silicon vias. One such logic die includes an error code generator that generates error checking codes corresponding to write data. The error checking codes are stored in the memory device dice and are subsequently compared to error checking codes generated from data subsequently read from the memory device dice. In the event the codes do not match, an error signal can be generated. The logic die may contain a controller that records the address from which the data was read. The controller or memory access device may redirect accesses to the memory device dice at the recorded addresses. The controller can also examine addresses or data resulting in the error signals being generated to identify faults in the through silicon vias. | 2014-10-02 |
20140298120 | Circuit and Method for Testing Memory Devices - The present application provides a circuit and method for testing a memory device. The memory device has multiple blocks addressable via a plurality of address lines and capable of inputting and/or outputting data via a plurality of data lines. The circuit comprises: a test pattern generator coupled to a first portion of the plurality of address lines to receive test data, and configured to store the test data and to generate a write test vector and a read test vector according to the test data, wherein the write test vector is associated with the read test vector; a multiplexer coupled to the test pattern generator, and configured to selectively transmit the write test vector to a subject block of the multiple memory blocks to enable the write test vector to be written into the subject block; and a comparator coupled to the test pattern generator and the subject block, and configured to compare the read test vector with a readout signal generated from the subject block and the write test vector, and to generate a flag indicative of the comparison result. | 2014-10-02 |
20140298121 | ANALYSIS SUPPORT APPARATUS, ANALYSIS SUPPORT METHOD, AND COMPUTER PRODUCT - An analysis support apparatus includes a processor that is configured to acquire circuit data that indicates plural elements within a circuit and a node to which at least two elements are connected among the elements, and determine, based on the acquired circuit data and by referring to a memory unit that correlates and stores for each of the elements, the type of the element and information that indicates whether the phase of a signal is reversed when the signal passes through the element, whether the phase of the signal is reversed when the signal that passed through a given node among a plurality of nodes within the circuit returns to the given node; and an output unit that outputs information that indicates the given node when the processor determines that the phase of the signal is not reversed. | 2014-10-02 |
20140298122 | DUAL MASTER JTAG METHOD, CIRCUIT, AND SYSTEM - A dual-master controller includes a plurality of JTAG data registers including a controller-mode register that stores information indicating a standard JTAG or a processor-controlled mode of operation. A JTAG TAP controller receives control signals over a standard test access port and a processor controller receives processor control signals over an external processor bus. A selection multiplexer outputs either signals on the standard JTAG access port or the external processor bus responsive to a JTAG mode selection signal. A logic circuit activates the JTAG mode selection signal responsive to the force JTAG signal being active or information in the controller-mode register indicating the standard JTAG mode, and deactivates the JTAG mode selection signal responsive to the force JTAG signal being deactivated or the information in the controller-mode register indicating the processor-controller mode. An instruction decoder and multiplexer circuit applies control signals from the selection multiplexer to control the JTAG data registers. | 2014-10-02 |
20140298123 | Scan Chain Reconfiguration and Repair - A system includes an integrated circuit. The integrated circuit includes at least one scan chain group. A particular scan chain group of the at least one scan chain group includes at least one scan chain and at least one spare scan chain. The at least one scan chain of the particular scan chain group includes a particular scan chain. The at least one spare scan chain of the particular scan chain group includes a particular spare scan chain. The particular spare scan chain is configured to bypass the particular scan chain. | 2014-10-02 |
20140298124 | SCAN CHAIN PROCESSING IN A PARTIALLY FUNCTIONAL CHIP - A method for scanning a partially functional chip. The method may include applying a failed core map to the partially functional chip, bypassing at least one failed core scan chain, based on contents of the failed core map. The method may also include performing comparisons of scan status information to the failed core map and inhibiting movement of scan data of at least one failed core, based on results of the comparisons. | 2014-10-02 |
20140298125 | System and method for optimized board test and configuration - The present invention, system and method for optimized board test and configuration, comprises a method for splitting test data into dynamic and static parts, a system for optimized test access using variable-length shift register (VLSR) that uses the latter method, a system for optimized test application using VLSR with accumulating buffer (VLSRB) and a method for switching between BS-based test and VLSR/VLSRB-based test. | 2014-10-02 |
20140298126 | LATCH CIRCUIT, SCAN TEST CIRCUIT AND LATCH CIRCUIT CONTROL METHOD - A latch circuit includes: a data latch that holds data that has been input according to a first control signal or a second control signal; and a latch controller that includes a first input terminal to which a first operation signal is input, the first operation signal operating the data latch in a first scan method, and a second input terminal to which a second operation signal is input, the second operation signal operating the data latch in a second scan method; wherein when a prescribed value is input to the first input terminal, the latch controller outputs the second control signal to control the data latch, and when a prescribed value is input to the second input terminal, the latch controller outputs the first control signal to control the data latch. | 2014-10-02 |
20140298127 | SEMICONDUCTOR DEVICE, PHYSICAL QUANTITY SENSOR, ELECTRONIC APPARATUS, AND MOVING OBJECT - A semiconductor device includes a digital circuit having a scan test mode. The digital circuit includes a first flip-flop forming a part of a scan chain when in the scan test mode, and a first selector provided on an input side of the first flip-flop. The first selector is capable of selecting a first signal when not in the scan test mode, and selecting a second signal that is different from the first signal when in the scan test mode. | 2014-10-02 |
20140298128 | SCAN CHAIN LATCH DESIGN THAT IMPROVES TESTABILITY OF INTEGRATED CIRCUITS - A scan chain latch circuit, a method of operating a latch circuit in a scan chain, and a computer-readable medium having stored thereon a data structure defining a scan chain latch circuit for instantiation on a semiconductor die are disclosed. In an embodiment, the scan chain latch circuit comprises a first latch for holding one data value, a second latch for holding another data value, and a multiplexor. The one data value is applied to a first data input of the multiplexor and the another data value is applied to a second data input of the multiplexor. An alternating clock signal is applied to a select input of the multiplexor to control the output of the multiplexor, wherein the output of the multiplexor toggles between the two data values held in the two latches at a defined frequency. | 2014-10-02 |
20140298129 | Generating Partially Sparse Generator Matrix for a Quasi-Cyclic Low-Density Parity-Check Encoder - A method and system for constructing a generator matrix is disclosed. The method includes: receiving a parity check matrix H, wherein the parity check matrix H includes multiple circulant sub-matrices; rearranging the parity check matrix H by column and row permutations to obtain a rearranged parity check matrix H′; and constructing the generator matrix G based on the rearranged parity check matrix H′. | 2014-10-02 |
20140298130 | LDPC MULTI-DECODER ARCHITECTURES - Systems, methods, and other embodiments associated with LDPC decoder architectures are described. According to one embodiment, an apparatus includes a super-parity-check matrix corresponding to at least a portion of a low density parity check (LDPC) code matrix. The super-parity-check-matrix is configured to operate with nx check node processing elements (NPEs) and ny bit NPEs. The super-parity-check matrix includes a plurality of parity check matrices. Each parity check matrix is configured to operate with x check NPEs and y bit NPEs. The numbers n, x, and y, are selected such that ny codeword bits are processed in the single time unit by a high throughput decoder and y codeword bits are processed in the single time unit by a low throughput decoder. | 2014-10-02 |
20140298131 | Priori Information Based Post-Processing in Low-Density Parity-Check Code Decoders - A low-density parity-check decoder utilizes information about hard errors in a storage medium to identify bit locations to flip log-likelihood ratios while attempting to decode codewords. The decoder iteratively flips and saturates log-likelihood ratios for bits at hard error locations and re-decodes until a valid codeword is produced. The decoder also identifies variable nodes associated with trapping sets for iterative log-likelihood ratio bit flipping. | 2014-10-02 |
20140298132 | DOUBLE QC-LDPC CODE - A double quasi-cyclic low density parity check (DQC-LDPC) code and a corresponding processor are disclosed herein. The parity-check matrix of DQC-LDPC codes has regularity with its corresponding processor including an input end, an output end and a processing module. The parity-check matrix includes a double quasi-cyclic matrix. The double quasi-cyclic matrix includes a plurality of sub-matrices. The sub-matrices are arranged in an array. Each sub-matrix includes a plurality of entries, and each sub-matrix is a circulant matrix having the entries circular shifted row-by-row. The double quasi-cyclic matrix is a circulant matrix having the sub-matrices circular shifted row-by-row. The processing module is configured to process an input signal and output an output signal correspond to the parity-check matrix of a low density parity check code (LDPC). | 2014-10-02 |
20140298133 | METHOD AND DEVICE FOR SERIALLY TRANSFERRING DATA, HAVING SWITCHABLE DATA ENCODING - A method and an apparatus for data transfer in a network having at least two data processing units that exchange messages via the network are described, the exchanged messages having a logical structure in accordance with the CAN specification ISO 11898-1, coding of the bits for at least one first predefinable region within the exchanged messages being accomplished according to the method in accordance with the CAN standard ISO-11898-1, and such that when a switchover condition exists, coding of the bits for at least one second predefinable region within the exchanged messages is accomplished according to a method departing from the CAN standard ISO 11898-1. | 2014-10-02 |
20140298134 | ENCODING DATA IN A DISPERSED STORAGE NETWORK - A method begins where a processing module segments data into data segments. On a data segment by data segment basis, the method continues with the processing module performing a decode threshold level of dispersed storage error encoding on a data segment to produce a set of decode threshold level encoded data slices and caching the set of decode threshold level encoded data slices. On a set by set basis, the method continues with the processing module performing a redundancy level of dispersed storage error encoding on the set of decode threshold level encoded data slices to produce a set of redundancy error coded data slices. The method continues with the processing module outputting at least one of at least some of a plurality of sets of decode threshold level encoded data slices and at least a corresponding some of a plurality of sets of redundancy error coded data slices. | 2014-10-02 |
20140298135 | REBUILDING DATA STORED IN A DISPERSED STORAGE NETWORK - A method begins where a processing module queues, in a rebuild queue, identifiers of encoded data slices for rebuilding, where an encoded data slice is of a set of encoded data slices. The method continues with the processing module accessing the rebuild queue to retrieve a valid rebuild request and querying a storage unit of the set of storage units regarding a most current revision value of another encoded data slice of a most current dispersed storage error encoded revision level of a data segment. When a revision value of the encoded data slice compares favorably with the most current revision level of the other encoded data slice, the method continues with the processing module retrieving a decode threshold number of encoded data slices, reconstructing the data segment from the decode threshold number of encoded data slices, and generating a rebuilt encoded data slice from the reconstructed data segment. | 2014-10-02 |
20140298136 | STORING DATA AND DIRECTORY INFORMATION IN A DISTRIBUTED STORAGE NETWORK - A method begins with a processing module issuing a set of write requests regarding storing a set of encoded data slices in dispersed storage network (DSN) memory and confirming that at least a write threshold number of encoded data slices have been temporarily stored in the DSN memory. When confirmed, the method continues with the processing module issuing a second set of write requests regarding storing a set of encoded directory slices in the DSN memory and confirming that at least a second write threshold number of encoded directory slices have been temporarily stored in the DSN memory. When confirmed, the method continues with the processing module issuing write commit requests regarding the at least a write threshold number of encoded data slices and the at least a second write threshold number of encoded directory slices. | 2014-10-02 |
20140298137 | VIRTUAL MEMORY MAPPING IN A DISPERSED STORAGE NETWORK - A method for evolving dispersed storage network (DSN) memory in a DSN begins by a processing module generating tracking information by tracking evolutionary change of storage units of the DSN memory, performance and reliability requirements of the DSN memory, and memory utilization of the DSN memory. The method continues with the processing module, for a given state of evolution of the DSN memory, interpreting the tracking information to produce given state DSN memory data and establishing virtual DSN address boundaries for a set of the storage units for storing data objects in a virtual memory vault of the DSN, where the virtual memory vault is mapped to the set of the storage units, where the data objects are dispersed storage error encoded into pluralities of sets of encoded data slices that are stored in the set of the storage units in accordance with the virtual DSN address boundaries. | 2014-10-02 |
20140298138 | PRIORITIZED DELETING OF SLICES STORED IN A DISPERSED STORAGE NETWORK - A method begins, as data objects are ingested, by determining, for each of some of the data objects, a priority indicator to produce a listing of priority indicators. The method continues for a data object by determining encoding parameters based on a corresponding priority indicator. The method continues by encoding the data object in accordance with the encoding parameters to produce a plurality of sets of encoded data slices and storing them. The method continues by identifying a first data object for analysis based on a corresponding priority indicator and an analysis priority. The method continues by decoding a plurality of sets of encoded data slices to recover the first data object and analyzing it in accordance with analysis criteria to determine its relevancy. The method continues by issuing a command to delete the plurality of sets of encoded data slices when the relevancy is below a threshold. | 2014-10-02 |
20140298139 | MEMORY DEVICE WITH INTERNAL SIGNAL PROCESSING UNIT - A method for operating a memory includes storing data in a plurality of analog memory cells that are fabricated on a first semiconductor die by writing input storage values to a group of the analog memory cells. After storing the data, multiple output storage values are read from each of the analog memory cells in the group using respective, different threshold sets of read thresholds, thus providing multiple output sets of the output storage values corresponding respectively to the threshold sets. The multiple output sets of the output storage values are preprocessed by circuitry that is fabricated on the first semiconductor die, to produce preprocessed data. The preprocessed data is provided to a memory controller, which is fabricated on a second semiconductor die that is different from the first semiconductor die. so as to enable the memory controller to reconstruct the data responsively to the preprocessed data. | 2014-10-02 |
20140298140 | APPARATUS AND METHOD FOR IMPLEMENT A MULTI-LEVEL MEMORY HIERARCHY - An apparatus and method are described for detecting and correcting instruction fetch errors within a processor core. For example, in one embodiment, an instruction processing apparatus for detecting and recovering from instruction fetch errors comprises, the instruction processing apparatus performing the operations of: detecting an error associated with an instruction in response to an instruction fetch operation; and determining if the instruction is from a speculative access, wherein if the instruction is not from a speculative access, then responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core. | 2014-10-02 |