40th week of 2014 patent applcation highlights part 19 |
Patent application number | Title | Published |
20140291727 | METHOD FOR FORMING SEMICONDUCTOR GATE STRUCTURE AND SEMICONDUCTOR GATE STRUCTURE - A method for forming a semiconductor gate structure and a semiconductor gate structure are provided. The method includes: providing a substrate with a Ge layer as a surface thereof; forming a Sn layer on the Ge layer, in which an interface between the Ge layer and the Sn layer is a GeSn layer; removing the Sn layer to expose the GeSn layer; forming a GeSnO | 2014-10-02 |
20140291728 | POWER DEVICE CHIP AND METHOD OF MANUFACTURING THE POWER DEVICE CHIP - According to example embodiments, a power device chip includes a plurality of unit power devices classified into a plurality of sectors, a first pad and a second pad. At least one of the first and second pads is divided into a number of pad parts equal to a number of the plurality of sectors. The first pad is connected to first electrodes of the plurality of unit power devices, and the second pad is connected to second electrodes of the plurality of unit power devices. The unit power devices may be diodes. The power device chip may further include third electrodes in the plurality of unit power devices, and a third pad may be connected to the third electrodes. In this case, the unit power devices may be high electron mobility transistors (HEMTs). Pad parts connected to defective sectors may be excluded from bonding. | 2014-10-02 |
20140291729 | MEMORY UNIT, MEMORY UNIT ARRAY AND METHOD OF MANUFACTURING THE SAME - A memory unit includes a substrate, at least one charge storage element, at least one first recessed access element, and an isolation portion. The substrate has a surface and the first recessed access element is disposed in an active area of the substrate and extending from the surface into the substrate. The first recessed access element is electrically connected to the charge storage element and induces in the substrate a first depletion region. The isolation portion is adjacent to the active area and extending from the surface into the substrate. The isolation portion includes a trenched isolating barrier and a second recessed access element. The second recessed access element is disposed in the trenched isolating barrier and induces in the substrate a second depletion region merging with the first depletion region. | 2014-10-02 |
20140291730 | Semiconductor Chip Including Digital Logic Circuit Including Linear-Shaped Conductive Structures Having Electrical Connection Areas Located Within Inner Region Between Transistors of Different Type and Associated Methods - A first linear-shaped conductive structure (LCS) forms a gate electrode (GE) of a first transistor of a first transistor type. A second LCS forms a GE of a first transistor of a second transistor type. A third LCS forms a GE of a fourth transistor of the first transistor type. A fourth LCS forms a GE of a fourth transistor of the second transistor type. Transistors of the first transistor type are collectively separated from transistors of the second transistor type by an inner region. Each of the first, second, third, and fourth LCS's has a respective electrical connection area. At least two of the electrical connection areas of the first, second, third, and fourth LCS's are located within the inner region. The first and fourth transistors of the first transistor type and the first and fourth transistors of the second transistor type form part of a cross-coupled transistor configuration. | 2014-10-02 |
20140291731 | Semiconductor Chip Including Region Including Linear-Shaped Conductive Structures Forming Gate Electrodes and Having Electrical Connection Areas Arranged Relative to Inner Region Between Transistors of Different Types and Associated Methods - A first linear-shaped conductive structure (LCS) forms gate electrodes (GE's) of a first transistor of a first transistor type and a first transistor of a second transistor type. A second LCS forms a GE of a second transistor of the first transistor type. A third LCS forms a GE of a second transistor of the second transistor type. A fourth LCS forms a GE of a third transistor of the first transistor type. A fifth LCS forms a GE of a third transistor of the second transistor type. A sixth LCS forms a GE of a fourth transistor of the first transistor type and a fourth transistor of the second transistor type. Transistors of the first transistor type are collectively separated from transistors of the second transistor type by an inner region. The second, third, fourth, and fifth LCS's have respective electrical connection areas arranged relative to the inner region. | 2014-10-02 |
20140291732 | PHOTOELECTRIC CONVERSION APPARATUS AND IMAGING SYSTEM USING THE PHOTOELECTRIC CONVERSION APPARATUS - In a photoelectric conversion apparatus including a charge holding portion, a part of an element isolation region contacting with a semiconductor region constituting the charge holding portion extends from a reference surface including the light receiving surface of a photoelectric conversion element into a semiconductor substrate at a level equal to or deeper than the depth of the semiconductor region in comparison with the semiconductor region. | 2014-10-02 |
20140291733 | STRAIN SENSING DEVICE USING REDUCED GRAPHENE OXIDE AND METHOD OF MANUFACTURING THE SAME - Provided is a strain sensing device using reduced graphene oxide (R-GO). The strain sensing device includes a flexible substrate, a gate electrode formed on the flexible substrate, a gate insulating layer configured to cover the gate electrode and include a part formed of a flexible material, an active layer formed of R-GO for sensing a strain, on the gate insulating layer, and a source and drain electrode formed on the active layer. | 2014-10-02 |
20140291734 | Thin Channel MOSFET with Silicide Local Interconnect - A semiconductor structure and method of manufacturing the same are provided. The semiconductor structure includes a semiconductor substrate having an isolated area comprising a first region and a second region. A first raised RSD region is formed in the first region and a second RSD region is formed in the second region. The first RSD region and second RSD region is separated laterally by a portion of the isolated area. A continuous silicide interconnect structure is formed overlying the first RSD region, the second RSD region and the portion of the isolated area situated between RSD regions. A contact may be formed on the surface of the silicide interconnect. | 2014-10-02 |
20140291735 | DOUBLE PATTERNING VIA TRIANGULAR SHAPED SIDEWALL SPACERS - An intermediate semiconductor structure in fabrication includes a silicon semiconductor substrate, a hard mask of silicon nitride (SiN) over the substrate and a sacrificial layer of polysilicon or amorphous silicon over the hard mask. The sacrificial layer is patterned into sidewall spacers for mandrels of a filler material substantially different in composition from the sidewall spacers, such as a flowable oxide. The mandrels are removed such that the sidewall spacers have vertically tapered inner and outer sidewalls providing a rough triangular shape. The rough triangular sidewall spacers are used as a hard mask to pattern the SiN hard mask below. | 2014-10-02 |
20140291736 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In one embodiment, a first main terminal region of a first conductivity type and a second main terminal region of a second conductivity type, which is an opposite conductivity type of the first conductivity type, formed in the semiconductor substrate so as to sandwich a gate electrode, a diffusion layer of the second conductivity type coming in contact with the first and second element isolation insulator films and having an upper surface in a position deeper than lower surfaces of the first and second main terminal regions, a first well region of the first conductivity type formed between the first main terminal region and the diffusion layer, and a second well region of the first conductivity type formed between the second main terminal region and the diffusion layer. The second well region has a impurity concentration higher than that of the first well region. | 2014-10-02 |
20140291737 | TRANSISTOR ARCHITECTURE HAVING EXTENDED RECESSED SPACER AND SOURCE/DRAIN REGIONS AND METHOD OF MAKING SAME - Techniques are disclosed for forming transistor architectures having extended recessed spacer and source/drain (S/D) regions. In some embodiments, a recess can be formed, for example, in the top of a fin of a fin-based field-effect transistor (finFET), such that the recess allows for forming extended recessed spacers and S/D regions in the finFET that are adjacent to the gate stack. In some instances, this configuration provides a higher resistance path in the top of the fin, which can reduce gate-induced drain leakage (GIDL) in the finFET. In some embodiments, precise tuning of the onset of GIDL can be provided. Some embodiments may provide a reduction in junction leakage (L | 2014-10-02 |
20140291738 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - A semiconductor electronic device structure includes an active area array disposed in a substrate, an isolation structure, a plurality of recessed gate structures, a plurality of word lines, and a plurality of bit lines. The active area array a plurality of active area columns and a plurality of active area rows, defining an array of active areas. The substrate has two recesses formed at the central region thereof. Each recessed gate structure is respectively disposed in the recess. A protruding structure is formed on the substrate in each recess. A STI structure of the isolation structure is arranged between each pair of adjacent active area rows. Word lines are disposed in the substrate, each electrically connecting the gate structures there-under. Bit lines are disposed above the active areas, forming a crossing pattern with the word lines. | 2014-10-02 |
20140291739 | JUNCTION-LESS TRANSISTOR HAVING REVERSE POLARITY STRUCTURE - A junction-less transistor having an reverse polarity structure includes a substrate, a semiconductor body, a gate and a gate insulation layer. The substrate has a first polarity. The semiconductor body is disposed on the substrate, and includes a drain, a source and a channel section connected between the drain and the source. The gate covers one side of the channel section away from the substrate. The semiconductor body has a second polarity opposite to the first polarity. With the semiconductor body and the substrate respectively having the opposite second polarity and first polarity, a leakage current can be reduced while also lowering element production costs. | 2014-10-02 |
20140291740 | Perforated Channel Field Effect Transistor - A device including a plurality of perforations to a semiconductor channel is provided. The device includes a semiconductor structure forming the semiconductor channel. Additionally, the device includes a source contact, a drain contact, and a gate contact to the semiconductor channel. The plurality of perforations can be located in the semiconductor structure below the gate contact. Furthermore, a perforation in the plurality of perforations can extend into the semiconductor structure beyond a location of the semiconductor channel. | 2014-10-02 |
20140291741 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A method of fabricating a semiconductor device includes forming a first metal gate electrode over a substrate, forming a second metal gate electrode over the substrate, removing at least a part of the first metal gate electrode to form a first opening, and filling the first opening with a non-conductive material. | 2014-10-02 |
20140291742 | PIXEL STRUCTURE AND FABRICATING METHOD THEREOF - A fabrication method of a pixel structure and a pixel structure are provided. A first patterned metal layer including scan lines and a gate is formed on a substrate. A first insulation layer, a semiconductor layer, an etching stop pattern and a metal layer are formed sequentially on the first patterned metal layer. The metal layer and the semiconductor layer are patterned to form a second patterned metal layer and a patterned semiconductor layer. The second patterned metal layer includes data lines, a source and a drain. The patterned semiconductor layer includes a first semiconductor pattern completely overlapping the second patterned metal layer and a second semiconductor pattern without overlapping the second patterned metal layer, wherein the second semiconductor pattern includes a channel pattern and a marginal pattern. The channel pattern is between the source and the drain and the marginal pattern surrounds the first semiconductor pattern. | 2014-10-02 |
20140291743 | PHOTOELECTRIC CONVERSION APPARATUS, IMAGING APPARATUS USING THE SAME, AND MANUFACTURING METHOD THEREOF - A photoelectric conversion apparatus includes: an active matrix-type TFT array substrate on which photoelectric conversion elements and thin film transistors are arranged in a matrix shape, wherein the photoelectric conversion element connects with a drain electrode via a contact hole opened through a first interlayer insulation film provided above the thin film transistor, wherein a data line and a bias line are connected with the source electrode and the photoelectric conversion element via respective contact holes opened through the second interlayer insulation, and wherein at least a part of the photoelectric conversion element is fixed to have a shape different from a normal pixel between pixels adjacent to each other in an extending direction of the gate line, and an electrical connection between the photoelectric conversion element and the data line is cut off in the transistor of the pixel having the different shape. | 2014-10-02 |
20140291744 | SPIN FET AND MAGNETORESISTIVE ELEMENT - A spin FET of an aspect of the present invention includes source/drain regions, a channel region between the source/drain regions, and a gate electrode above the channel region. Each of the source/drain regions includes a stack structure which is comprised of a low work function material and a ferromagnet. The low work function material is a non-oxide which is comprised of one of Mg, K, Ca and Sc, or an alloy which includes the non-oxide of 50 at % or more. | 2014-10-02 |
20140291745 | Deposited Material and Method of Formation - A system and method for manufacturing a semiconductor device is provided. An embodiment comprises forming a deposited layer using an atomic layer deposition (ALD) process. The ALD process may utilize a first precursor for a first time period, a first purge for a second time period longer than the first time period, a second precursor for a third time period longer than the first time period, and a second purge for a fourth time period longer than the third time period. | 2014-10-02 |
20140291746 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A non-volatile semiconductor memory device is proposed that has an unprecedented novel structure in which carriers can be injected into a floating gate by applying various voltages of the same polarity. According to the non-volatile semiconductor memory device of the present invention, in a memory transistor, a PN junction is formed at the boundary between a channel region and an opposite polarity type impurity diffusion layer, to allow a floating gate to be charged to have the same polarity as the polarity of the channel region, whereby a part of electrons accelerated in a depletion layer between the channel region and an opposite polarity type extension region, and secondary electrons generated by the accelerated electrons can be injected into the floating gate by being attracted to a gate electrode, as a result of which electrons can be injected into the floating gate even when, without simultaneously applying positive and negative voltages as in the conventional case, various voltages of the same polarity are applied to the floating gate, an impurity diffusion layer, and the opposite polarity type impurity diffusion layer. | 2014-10-02 |
20140291747 | Tungsten Salicide Gate Source For Vertical NAND String To Control On Current And Cell Pillar Fabrication - A non-volatile memory device and a method for forming the non-volatile memory device are disclosed. During fabrication of the memory device, a tungsten salicide is utilized as an etch-stop layer in place of a conventionally used aluminum oxide to form channel pillars having a high aspect ratio. Use of the tungsten salicide is useful for eliminating an undesired etch-stop recess and an undesired floating gate that is formed when an Al oxide etch-stop layer is conventionally used. | 2014-10-02 |
20140291748 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a bit line, an active region formed in a semiconductor substrate, a plug formed on the active region and connecting the bit line to the active region, a memory cell which includes a first gate insulating film on the active region, a charge storage layer on the first gate insulating film, a first insulating film on the charge storage layer, and a control gate electrode on the first insulating film, a select transistor formed between the plug and the memory cell on the active region and including a second gate insulating film on the active region, a first electrode layer on the second gate insulating film, a second insulating film on the first electrode layer, and a second electrode layer on the second insulating film, and a wiring formed above the active region between the plug and the second electrode layer of the select transistor. | 2014-10-02 |
20140291749 | MEMORY DEVICE HAVING MULTIPLE DIELECTRIC GATE STACKS AND RELATED METHODS - A memory device may include a semiconductor substrate, and a memory transistor in the semiconductor substrate. The memory transistor may include source and drain regions in the semiconductor substrate and a channel region therebetween, and a gate stack. The gate stack may include a first dielectric layer over the channel region, a first diffusion barrier layer over the first dielectric layer, a first electrically conductive layer over the first diffusion barrier layer, a second dielectric layer over the first electrically conductive layer, a second diffusion barrier layer over the second dielectric layer, and a second electrically conductive layer over the second diffusion barrier layer. The first and second dielectric layers may include different dielectric materials, and the first diffusion barrier layer may be thinner than the second diffusion barrier layer. | 2014-10-02 |
20140291750 | MEMORY DEVICE HAVING MULTIPLE DIELECTRIC GATE STACKS WITH FIRST AND SECOND DIELECTRIC LAYERS AND RELATED METHODS - A memory device may include a semiconductor substrate, and a memory transistor in the semiconductor substrate. The memory transistor may include source and drain regions in the semiconductor substrate and a channel region therebetween, and a gate stack having a first dielectric layer over the channel region, a second dielectric layer over the first dielectric layer, a first diffusion barrier layer over the second dielectric layer, a first electrically conductive layer over the first diffusion barrier layer, a second diffusion barrier layer over the first electrically conductive layer, and a second electrically conductive layer over the second diffusion barrier layer. The first and second dielectric layers may include different dielectric materials, and the first diffusion barrier layer may be thinner than the second diffusion barrier layer. | 2014-10-02 |
20140291751 | SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of conductive layers and a plurality of insulating layers formed alternately with each other, at least one channel layer passing through the plurality of conductive layers and the plurality of insulating layers, and at least one first charge blocking layer surrounding the at least one channel layer, wherein a plurality of first regions, interposed between the at least one channel layer and the plurality of conductive layers, and a plurality of second regions, interposed between the at least one channel layer and the plurality of insulating layers, are alternately defined on the at least one first charge blocking layer, and each of the plurality of first regions has a greater thickness than each of the plurality of second regions. | 2014-10-02 |
20140291752 | MEMORY STRUCTURE AND METHOD FOR FORMING SAME - A memory structure and a method for forming the same are provided. The memory structure comprises: a substrate; a plurality of channel structures formed on the substrate, in which the plurality of channel structures are parallel with each other, each channel structure comprises a plurality of single crystal semiconductor layers and a plurality of oxide layers alternately stacked in a direction perpendicular to the substrate, and at least one of the plurality of oxide layers is a single crystal oxide layer; and a plurality of gate structures matched with the plurality of channel structures, in which each gate structure comprises a gate dielectric layer immediately adjacent to the plurality of channel structures and a gate electrode layer immediately adjacent to the gate dielectric layer. | 2014-10-02 |
20140291753 | TRENCH MOSFET STRUCTURE HAVING SELF-ALIGNED FEATURES FOR MASK SAVING AND ON-RESISTANCE REDUCTION - A trench MOSFET structure having self-aligned features for mask saving and on-resistance reduction is disclosed, wherein the source region is formed by performing source Ion Implantation through contact opening of a contact interlayer, and further source diffusion. A dielectric sidewall spacer is formed on sidewalls of the contact interlayer in the contact open areas to define trenched source-body contacts for on-resistance reduction and avalanche capability improvement. | 2014-10-02 |
20140291754 | SEMICONDUCTOR STRUCTURE HAVING BURIED WORD LINE AND METHOD OF MANUFACTURING THE SAME - A semiconductor structure having buried word line formed in a trench in a semiconductor substrate includes a gate oxide layer, a gate conductor, a gate cap layer, a blocking layer, and an isolation structure. The gate oxide layer is formed on the inner surface of the trench, the gate conductor is formed in the trench, and the gate cap layer is formed on the gate conductor. The blocking layer surrounds a bottom portion of the gate conductor, and the bottom portion of the gate conductor is isolated from the gate oxide layer by the blocking layer. The isolation structure surrounds a top portion of the gate conductor and in contact with the top end of the blocking layer. The top portion of the gate conductor is isolated from the gate oxide layer and the from the gate cap layer by the isolation structure. | 2014-10-02 |
20140291755 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MODULE - A semiconductor device includes a first source/drain region and a second source/drain region disposed in an active region of a semiconductor substrate, and a gate structure crossing the active region and disposed between the first and second source/drain regions, the gate structure including a gate electrode having a first part and a second part on the first part, the gate electrode being at a lower level than an upper surface of the active region, an insulating capping pattern on the gate electrode, a gate dielectric between the gate electrode and the active region, and an empty space between the active region and the second part of the gate electrode. | 2014-10-02 |
20140291756 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a first n-type semiconductor layer, a p-type semiconductor layer, a second n-type semiconductor layer and a trench. The first n-type semiconductor layer includes a first interface and a second interface. The second interface forms an upper surface of a convex protruded from the first interface. The p-type semiconductor layer is stacked on the first n-type semiconductor layer and includes a first region stacked on the first interface and a second region stacked on the second interface. The first region is uniformly continuous with the second region. The second n-type semiconductor layer is stacked on the p-type semiconductor layer. The trench is depressed from the second n-type semiconductor layer through the p-type semiconductor layer into the convex of the first n-type semiconductor layer. | 2014-10-02 |
20140291757 | SEMICONDUCTOR DEVICE - A semiconductor device disclosed herein includes an insulated gate, a main and a sub trench conductors. The main and sub trench conductors are formed in the cell region, and have a conductor that is covered with an insulation film and fills a trench extending in a first direction. The sub trench is located, with respect to the main trench conductor, in a second direction perpendicularly crossing the first direction and extending from the cell region side to the non-cell region. Length of the sub trench conductor in the first direction is shorter than a length of the insulated gate in the first direction. Distance between the main and sub trench conductors is shorter than a distance between the main trench conductor and the insulated gate. At least a part of the sub trench conductor reaches a position deeper than a boundary between the first and second semiconductor regions. | 2014-10-02 |
20140291758 | SEMICONDUCTOR DEVICE HAVING PLANAR SOURCE ELECTRODE - A semiconductor device includes a channel layer on a substrate; cell trench patterns in the channel layer; and a source pattern on the cell trench patterns. The source pattern includes: grooves, each having inclined sidewalls and bottom that extends in a horizontal direction in a portion of the channel layer between the cell trench patterns, source regions at the inclined sidewalls of the grooves, source isolation regions at the bottoms of the grooves, and a source electrode at interior regions of the grooves and that has a planar upper surface. | 2014-10-02 |
20140291759 | MOS TRANSISTOR AND FABRICATION METHOD - MOS transistors and fabrication methods are provided. An exemplary MOS transistor includes a gate structure formed on a semiconductor substrate. A lightly doped region is formed by a light ion implantation in the semiconductor substrate on both sides of the gate structure. A first halo region is formed by a first halo implantation to substantially cover the lightly doped region in the semiconductor substrate. A groove is formed in the semiconductor substrate on the both sides of the gate structure. Prior to forming a source and a drain in the groove, a second halo region is formed in the semiconductor substrate by a second halo implantation performed into a groove sidewall that is adjacent to the gate structure. The second halo region substantially covers the lightly doped region in the semiconductor substrate and substantially covers the groove sidewall that is adjacent to the gate structure. | 2014-10-02 |
20140291760 | FET SEMICONDUCTOR DEVICE WITH LOW RESISTANCE AND ENHANCED METAL FILL - In a method of fabricating a FET semiconductor device, a FET structure with a gate channel and dummy gate is formed on a layer of substrate. The gate channel includes one or more FINs, and spacer layers that line the sides of the gate channel and abut the layer of substrate. The dummy gate is removed and the height of the gate channel is reduced to substantially near that of a top surface of one or more FINs. A layer of high-k material is deposited into the gate channel. A layer of first metal is then deposited that fills the gate channel and covers, at least in part, the layer of high-k material. Excess material is removed from the layers of high-k material and first metal to create a surface. A layer of second metal is selectively deposited onto the surface to form a continued gate conductor. | 2014-10-02 |
20140291761 | Asymmetric Spacers - A semiconductor device having asymmetric spacers and steps for forming the same are disclosed. The spacers have difference capacitances, with the spacer having a higher capacitance formed over a source region of the device and the spacer having a lower capacitance formed over a drain region of the device. Embodiments of the disclosed invention include spacers made from different materials, having different or substantially equal thicknesses. | 2014-10-02 |
20140291762 | POWER DEVICE INTEGRATION ON A COMMON SUBSTRATE - A semiconductor structure for facilitating an integration of power devices on a common substrate includes a first insulating layer formed on the substrate and an active region having a first conductivity type formed on at least a portion of the first insulating layer. A first terminal is formed on an upper surface of the structure and electrically connects with at least one other region having the first conductivity type formed in the active region. A buried well having a second conductivity type is formed in the active region and is coupled with a second terminal formed on the upper surface of the structure. The buried well and the active region form a clamping diode which positions a breakdown avalanche region between the buried well and the first terminal. A breakdown voltage of at least one of the power devices is a function of characteristics of the buried well. | 2014-10-02 |
20140291763 | TECHNIQUES FOR PROVIDING A SEMICONDUCTOR MEMORY DEVICE - Techniques for providing a semiconductor memory device are disclosed. In one embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell may include a first region connected to a source line extending in a first orientation, a second region connected to a bit line extending a second orientation, and a body region spaced apart from and capacitively coupled to a word line, wherein the body region is electrically floating and disposed between the first region and the second region. The semiconductor device may also include a first barrier wall extending in the first orientation of the array and a second barrier wall extending in the second orientation of the array and intersecting with the first barrier wall to form a trench region configured to accommodate each of the plurality of memory cells. | 2014-10-02 |
20140291764 | ESD PROTECTION STRUCTURE AND ESD PROTECTION CIRCUIT - An electrostatic discharge (ESD) protection structure and an ESD protection circuit are provided. A PMOS transistor is located in a first region of a first N-type well region of a semiconductor substrate. A first doped base region located in a second region of a first N-type well region is N-type doped and connected to an external trigger-voltage adjustment circuit. An NMOS transistor is located in a third region of a first P-type well region. Second doped base regions discretely located in a fourth region of a first P-type well region are P-type doped and connected to the external trigger-voltage adjustment circuit. A first N-region is located in the fourth region, surrounding the second doped base regions, and connected to the I/O interface terminal. A second N-region is located in the fourth region, surrounding the first N-region and the second doped base regions, and connected to the ground terminal. | 2014-10-02 |
20140291765 | ESD PROTECTION STRUCTURE AND ESD PROTECTION CIRCUIT - An electrostatic discharge (ESD) protection structure and an ESD protection circuit are provided. A PMOS transistor is located in a first region of a first N-type well region of a semiconductor substrate. A first doped base region located in a second region of a first N-type well region is N-type doped and connected to an external trigger-voltage adjustment circuit. An NMOS transistor is located in a third region of a first P-type well region. A second doped base region located in the fourth region of the first P-type well region is P-type doped and connected to the external trigger-voltage adjustment circuit. The external trigger-voltage adjustment circuit can be configured to pull up an electric potential of the second doped base region when the power supply terminal generates an instantaneous electric potential difference. | 2014-10-02 |
20140291766 | PLANAR DEVICE ON FIN-BASED TRANSISTOR ARCHITECTURE - Techniques are disclosed for forming a planar-like transistor device on a fin-based field-effect transistor (finFET) architecture during a finFET fabrication process flow. In some embodiments, the planar-like transistor can include, for example, a semiconductor layer which is grown to locally merge/bridge a plurality of adjacent fins of the finFET architecture and subsequently planarized to provide a high-quality planar surface on which the planar-like transistor can be formed. In some instances, the semiconductor merging layer can be a bridged-epi growth, for example, comprising epitaxial silicon. In some embodiments, such a planar-like device may assist, for example, with analog, high-voltage, wide-Z transistor fabrication. Also, provision of such a planar-like device during a finFET flow may allow for the formation of transistor devices, for example, exhibiting lower capacitance, wider Z, and/or fewer high electric field locations for improved high-voltage reliability, which may make such devices favorable for analog design, in some instances. | 2014-10-02 |
20140291767 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes: a deep trench in a substrate; a sidewall insulating film on a side surface of the deep trench; an interlayer insulating film on the sidewall insulating film; and an air gap in the interlayer insulating film. | 2014-10-02 |
20140291768 | SPACER ELEMENTS FOR SEMICONDUCTOR DEVICE - The present disclosure describes a semiconductor device including a semiconductor substrate and a gate stack disposed on the semiconductor substrate. A first spacer element is disposed on the substrate abutting the first gate stack. A second spacer element is adjacent the first spacer element. A source/raised drain is provided adjacent the gate stack. A conductive feature (e.g., silicide) is disposed on the source/drain and laterally contacts sidewalls of the second spacer element. In an embodiment, a contact directly interfaces with the second spacer element. | 2014-10-02 |
20140291769 | Cost-Effective Gate Replacement Process - The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a first gate structure and a second gate structure over a substrate. The first and second gate structures each include a high-k dielectric layer located over the substrate, a capping layer located over the high-k dielectric layer, an N-type work function metal layer located over the capping layer, and a polysilicon layer located over the N-type work function metal layer. The method includes forming an inter-layer dielectric (ILD) layer over the substrate, the first gate structure, and the second gate structure. The method includes polishing the ILD layer until a surface of the ILD layer is substantially co-planar with surfaces of the first gate structure and the second gate structure. The method includes replacing portions of the second gate structure with a metal gate. A silicidation process is then performed to the semiconductor device. | 2014-10-02 |
20140291770 | Method of Making a FinFET Device - The present disclosure provides many different embodiments of fabricating a FinFET device that provide one or more improvements over the prior art. In one embodiment, a method of fabricating a FinFET includes providing a semiconductor substrate and a plurality of dummy fins and active fins on the semiconductor substrate. A predetermined group of dummy fins is removed. | 2014-10-02 |
20140291771 | TID Hardened and Single Even Transient Single Event Latchup Resistant MOS Transistors and Fabrication Process - A radiation-hardened transistor is formed in a p-type body. An active region is disposed within the p-type body and has a perimeter defined by a shallow-trench isolation region filled with a dielectric material. Spaced-apart source and drain regions are disposed in the active region, forming a channel therebetween. A polysilicon gate is disposed above, aligned with, and insulated from the channel region. A p-type isolation ring is disposed in the p-type body separating outer edges of at least one of the source and drain regions from the perimeter of the active region. A body contact is disposed in the p-type isolation ring. | 2014-10-02 |
20140291772 | SEMICONDUCTOR DEVICES WITH GERMANIUM-RICH ACTIVE LAYERS AND DOPED TRANSITION LAYERS - Semiconductor device stacks and devices made there from having Ge-rich device layers. A Ge-rich device layer is disposed above a substrate, with a p-type doped Ge etch suppression layer (e.g., p-type SiGe) disposed there between to suppress etch of the Ge-rich device layer during removal of a sacrificial semiconductor layer richer in Si than the device layer. Rates of dissolution of Ge in wet etchants, such as aqueous hydroxide chemistries, may be dramatically decreased with the introduction of a buried p-type doped semiconductor layer into a semiconductor film stack, improving selectivity of etchant to the Ge-rich device layers. | 2014-10-02 |
20140291773 | POWER SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A power semiconductor device includes a cell region on a semiconductor substrate, at least a transistor device in the cell region, a peripheral termination region encompassing the cell region, a plurality of epitaxial islands arranged around the cell region, and a grid type epitaxial layer in the peripheral termination region. The grid type epitaxial layer separates the plurality of epitaxial islands from one another. | 2014-10-02 |
20140291774 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes: a nitride semiconductor layer; a first silicon nitride film that is formed on the nitride semiconductor layer, has a first opening whose inner wall is a forward tapered shape; a second silicon nitride film that is formed on the first silicon nitride film, and has a second opening whose inner wall is an inverse tapered shape; and a gate electrode formed so as to cover the whole surface of the nitride semiconductor layer exposed on the inside of the first opening; wherein a side wall of the gate electrode separates from the first silicon nitride film and the second silicon nitride film via a cavity. | 2014-10-02 |
20140291775 | SEMICONDUCTOR DEVICE - A semiconductor device comprises: a gate insulating film | 2014-10-02 |
20140291776 | Methods of atomic-layer deposition of hafnium oxide/erbium oxide bi-layer as advanced gate dielectrics - Provided is a two-step ALD deposition process for forming a gate dielectric involving an erbium oxide layer deposition followed by a hafnium oxide layer deposition. Hafnium oxide can provide a high dielectric constant, high density, large bandgap and good thermal stability. Erbium oxide can act as a barrier against oxygen diffusion, which can lead to increasing an effective oxide thickness of the gate dielectric and preventing hafnium-silicon reactions that may lead to higher leakage current. | 2014-10-02 |
20140291777 | BUFFER LAYER ON SEMICONDUCTOR DEVICES - A semiconductor device including a substrate having a source region, a drain region, and a channel region disposed between the source region and the drain region. Additionally, the semiconductor device includes a high-k dielectric layer formed over the channel region, an n-metal formed over the high-k dielectric layer and a barrier layer formed between the high-k dielectric layer and the n-metal, the barrier layer including a layer of annealed silicon. | 2014-10-02 |
20140291778 | INTEGRATED DEVICE OF A CAPACITIVE TYPE FOR DETECTING HUMIDITY, IN PARTICULAR MANUFACTURED USING A CMOS TECHNOLOGY - An integrated capacitive-type humidity sensor formed in a semiconductor chip integrating a sensing capacitor and a reference capacitor. Each of the sensing and reference capacitors have at least a first electrode and at least a second electrode, the first and second electrodes of each of the sensing and reference capacitors being arranged at distance and mutually insulated. A hygroscopic layer extends on the sensing and reference capacitors and a conductive shielding region extends on the reference capacitor but not on the sensing capacitor. | 2014-10-02 |
20140291779 | Semiconductor Devices and Methods for Manufacturing Semiconductor Devices - A method includes a step of performing a time multiplexed etching process, wherein the last etching step of the time multiplexed etching process is of a first time duration. After performing the time multiplexed etching process, an etching step having a second time duration is performed, wherein the second time duration is greater than the first time duration. | 2014-10-02 |
20140291780 | MEMS DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a MEMS device including a first electrode provided on a support substrate, a second electrode opposed to the first electrode, having at least one end part overlapping the first electrode, and able to move in a direction it is opposed to the first electrode, and beam parts provided on the support substrate and supporting the second electrode. The surface of that part of the first electrode, which opposes the end part of the second electrode, is set at a lower level than the surface of that part of the second electrode, which opposes a center part of the second electrode. | 2014-10-02 |
20140291781 | METHOD OF PACKAGING A MEMS TRANSDUCER DEVICE AND PACKAGED MEMS TRANSDUCER DEVICE - A packaged MEMS transducer device comprising: a die, including: a semiconductor body having a front side and a back side, opposite to one another in a first direction, at least one cavity extending through the semiconductor body between the front side and the back side, and at least one membrane extending on the front side at least partially suspended over the cavity; and a package designed to house the die on an inner surface thereof. The transducer device moreover includes a sealing layer extending on the back side of the semiconductor body for sealing the cavity, and includes a paste layer extending between the sealing layer and the inner surface of the package for firmly coupling the die to the package. | 2014-10-02 |
20140291782 | METHODS AND DEVICES FOR PACKAGING INTEGRATED CIRCUITS - Methods and devices for packaging integrated circuits. A packaged device may include an integrated circuit, a first packaging component including a patterned surface, and a second packaging component. The patterned surface of the first packaging component may be adhesively coupled to a surface of the second packaging component or a surface of the integrated circuit. The integrated circuit may be at least partially enclosed between the first and second packaging components. A packaging method may include patterning a surface of a packaging component of an integrated circuit package. The surface of the packaging component may be for adhesively coupling to a second component to at least partially enclose an integrated circuit in the integrated circuit package. | 2014-10-02 |
20140291783 | COVER FOR A MEMS MICROPHONE - A microphone assembly includes a base, a cover, and a microelectromechanical system (MEMS) die. The cover extends at least partially over and is coupled to the base. The cover and the base form a cavity. The MEMS die is coupled to the base and disposed within the cavity. At least a portion of the cover is constructed of a copper-nickel-zinc alloy that is effective in preventing solder from moving from a first portion of the cover to a second portion of the cover. | 2014-10-02 |
20140291784 | MEMS APPARATUS WITH INCREASED BACK VOLUME - A microelectromechanical system (MEMS) microphone assembly includes a base and a cover. The cover is coupled to the base and together with the base defines a cavity. The base forms a recess and the recess has dimensions and a shape so as to hold a MEMS die. The MEMS die includes a diaphragm and back plate. | 2014-10-02 |
20140291785 | MICROPHONE - A microphone has a base substrate having a main surface, an acoustic sensor mounted on the main surface, and a circuit element that processes a signal output from the acoustic sensor. The acoustic sensor has a sensor substrate having a first surface opposed to the base substrate, a second surface on a side opposite to the first surface, and a cavity formed while piercing the sensor substrate from the first surface to the second surface, and a movable electrode that covers the cavity from the second surface side. A through-hole is formed in the base substrate while piercing the base substrate in a thickness direction to communicate with the cavity. The through-hole overlaps the sensor substrate when viewed in the thickness direction of the base substrate. | 2014-10-02 |
20140291786 | component having a micromechanical microphone structure - Substrate-side overload protection for the diaphragm structure of a microphone component having a micromechanical microphone structure which impairs the damping properties of the microphone structure as little as possible, in which the microphone structure includes a diaphragm structure having at least one acoustically active diaphragm which is formed in a diaphragm layer above a semiconductor substrate. The diaphragm structure spans at least one sound opening in the rear side of the substrate. A stationary, acoustically permeable counter element is formed in the layer structure of the component above the diaphragm layer. According to the invention, at least projections are formed at the outer edge area of the diaphragm structure which protrude beyond the edge area of the sound opening, so that the edge area of the sound opening acts as a substrate-side stop for the diaphragm structure. | 2014-10-02 |
20140291787 | STRUCTURE OF MEMS ELECTROACOUSTIC TRANSDUCER - A structure of micro-electro-mechanical systems (MEMS) electroacoustic transducer is disclosed. The MEMS electroacoustic transducer includes a substrate having a MEMS device region, a diaphragm having openings and disposed in the MEMS device region, a silicon material layer disposed on the diaphragm and sealing the diaphragm, and a conductive pattern disposed beneath the diaphragm in the MEMS device region. Preferably, a first cavity is also formed between the diaphragm and the substrate. | 2014-10-02 |
20140291788 | Magnetoresistive Devices and Methods for Manufacturing Magnetoresistive Devices - A magnetoresistive device includes a substrate and an electrically insulating layer arranged over the substrate. The magnetoresistive device further includes a first free layer embedded in the electrically insulating layer and a second free layer embedded in the electrically insulating layer. The first free layer and the second free layer are separated by a portion of the electrically insulating layer. | 2014-10-02 |
20140291789 | SEMICONDUCTOR MAGNETORESISTIVE RANDOM-ACCESS MEMORY (MRAM) DEVICE AND MANUFACTURING METHOD THEREOF - The present disclosure describes a semiconductor MRAM device and a manufacturing method. The device reduces magnetic field induction “interference” (disturbance) phenomenon between adjacent magnetic tunnel junctions when data is written and read. This semiconductor MRAM device comprises a magnetic tunnel junction unit and a magnetic shielding material layer covering the sidewalls of the magnetic tunnel junction unit. The method for manufacturing a semiconductor device comprises: forming a magnetic tunnel junction unit, depositing an isolation dielectric layer to cover the top and the sidewall of the magnetic tunnel junction unit, and depositing a magnetic shielding material layer on the isolation dielectric layer. | 2014-10-02 |
20140291790 | ENCAPSULATION OF BACKSIDE ILLUMINATION PHOTOSENSITIVE DEVICE - An encapsulation of backside illumination photosensitive device including a circuit sub-mount, a backside illumination photosensitive device, a plurality of conductive terminals, and a heat dissipation structure is provided. The backside illumination photosensitive device includes an interconnection layer and a photosensitive device array, wherein the interconnection layer is located on the circuit sub-mount, and between the photosensitive device array and the circuit sub-mount. The conductive terminals are located between the interconnection layer and the circuit sub-mount to electrically connect the interconnection layer and the circuit sub-mount. The heat dissipation structure is located under the interconnection layer, and the heat dissipation structure and the photosensitive device array are respectively located at two opposite sides of the interconnection layer. | 2014-10-02 |
20140291791 | SOLID STATE IMAGING APPARATUS AND ELECTRONIC DEVICE - Provided is a solid state imaging apparatus including a transparent substrate formed of a birefringent material having a high refractive index in a direction vertical to a light receiving surface and a low refractive index in a direction parallel to the light receiving surface, the transparent substrate being disposed on the light receiving surface, and an electronic device including the solid state imaging apparatus. | 2014-10-02 |
20140291792 | TRANSPARENT ELECTRODE APPARATUS, METHOD, AND APPLICATIONS - A shaped electrode on a light transmitting substrate utilizes total internal reflection to provide improved transmission of electromagnetic radiation (‘light’) compared to standard electrode designs that involve flat electrode surfaces. Redirection of incident light by a tilted or otherwise shaped contact or material added on the contact provides otherwise reflected light to an open surface region. Optional plasmon mediated focusing of incident p-polarized light may be realized. | 2014-10-02 |
20140291793 | SOLID-STATE IMAGING APPARATUS, SOLID-STATE IMAGING APPARATUS MANUFACTURING METHOD, AND ELECTRONIC APPARATUS - There is provided a solid-state imaging apparatus including a plurality of photoelectric conversion regions which photoelectrically convert light incident from a rear surface side of a semiconductor substrate, element isolation regions formed between the plurality of photoelectric conversion regions arranged in a matrix shape, and shielding members formed on upper surfaces of the element isolation regions. The element isolation regions have high impurity concentration regions of a high impurity concentration connected to at least a part of the shielding members. | 2014-10-02 |
20140291794 | MICROCHANNEL AVALANCHE PHOTODIODE (VARIANTS) - The invention is directed to an avalanche photodiode containing a substrate and semiconductor layers with various electro-physical properties having common interfaces both between themselves and with the substrate. The avalanche photodiode may be characterized by the presence in the device of at least one matrix consisting of separate solid-state areas with enhanced conductivity surrounded by semiconductor material with the same type of conductivity. The solid-state areas are located between two additional semiconductor layers, which have higher conductivity in comparison to the semiconductor layers with which they have common interfaces. The solid-state areas are generally made of the same material as the semiconductor layers surrounding them but with conductivity type that is opposite with respect to them. The solid-state areas may be made of a semiconductor with a narrow forbidden zone with respect to the semiconductor layers with which they have common interfaces. | 2014-10-02 |
20140291795 | CABLE CONNECTING STRUCTURE AND CABLE CONNECTING METHOD - The embodiments provide a cable connecting structure and a cable connecting method that can downsize a head unit. | 2014-10-02 |
20140291796 | IMAGING DEVICE, IMAGING APPARATUS, PRODUCTION APPARATUS AND METHOD, AND SEMICONDUCTOR DEVICE - There is provided an imaging device including a semiconductor having a light-receiving portion that performs photoelectric conversion of incident light, electrically conductive wirings, and a contact group including contacts that have different sizes and connect the semiconductor and the electrically conductive wirings. | 2014-10-02 |
20140291797 | Semiconductor Device - A semiconductor device of this disclosure includes: a circuit element mounted on a main face of a lead frame; an inductor mounted on a back face of the lead frame; and a resin body sealing the circuit element and the inductor; wherein the circuit element includes a thermo-sensitive element and has an overheating protection function of the inductor. | 2014-10-02 |
20140291798 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises: a semiconductor substrate; a plurality of memory units provided on the semiconductor substrate and each including a plurality of memory cells that are stacked; and a plurality of bit lines formed above each of a plurality of the memory units aligned in a column direction, an alignment pitch in a row direction of the plurality of bit lines being less than an alignment pitch in the row direction of the memory units, and an end of each of the memory units aligned in the column direction being connected to one of the plurality of bit lines formed above the plurality of the memory units aligned in the column direction. | 2014-10-02 |
20140291799 | SEMICONDUCTOR DEVICE INCLUDING STI STRUCTURE AND FABRICATION METHOD - Semiconductor devices including STI structures and their fabrication methods are provided. A mask layer is provided on a semiconductor substrate and patterned to form an opening in the mask layer to expose a surface portion of the semiconductor substrate. A trench is then formed in the semiconductor substrate by etching along the opening. A first dielectric layer is formed in the trench and has a top surface lower than a top surface of the semiconductor substrate to provide an uncovered sidewall surface of the trench in the semiconductor substrate. An epitaxial layer is formed on the uncovered sidewall surface of the trench in the semiconductor substrate. The epitaxial layer includes a spacing to expose a surface portion of the first dielectric layer. A second dielectric layer is formed on the exposed surface portion of the first dielectric layer to fill the spacing formed in the epitaxial layer. | 2014-10-02 |
20140291800 | SEMICONDUCTOR DEVICE - When a conductive layer occupying a large area is provided in a coiled antenna portion, it has been difficult to supply power stably. A memory circuit portion and a coiled antenna portion are disposed by being stacked together; therefore, it is possible to prevent a current from flowing through a conductive layer occupying a large area included in the memory circuit portion, and thus, power saving can be achieved. In addition, the memory circuit portion and the coiled antenna portion are disposed by being stacked together, and thus, it is possible to use a space efficiently. Therefore, downsizing can be realized. | 2014-10-02 |
20140291801 | ANTI-FUSE STRUCTURE AND PROGRAMMING METHOD THEREOF - A method of programming an anti-fuse includes steps as follows. First, an insulating layer is provided. An anti-fuse region is defined on the insulating layer. An anti-fuse is embedded within the anti-fuse region of the insulating layer. The anti-fuse includes at least a first conductor and a second conductor. Then, part of the insulating layer is removed by a laser to form an anti-fuse opening in the insulating layer. Part of the first conductor and part of the second conductor are exposed through the anti-fuse opening. After that, a under bump metallurgy layer is formed in the anti-fuse opening to connect the first conductor and the second conductor electrically. | 2014-10-02 |
20140291802 | SEMICONDUCTOR STRUCTURES WITH METAL LINES - Disclosed are semiconductor structures with metal lines and methods of manufacture which reduce or eliminate extrusion formation. The method includes forming a metal wiring comprising a layered structure of metal materials with an upper constraining layer. The method further includes forming a film on the metal wiring which prevents metal extrusion during an annealing process. | 2014-10-02 |
20140291803 | CAPACITOR STRUCTURE OF GATE DRIVER IN PANEL - A capacitor structure of gate driver in panel (GIP) includes a first metal layer, a first dielectric layer, a second metal layer, a second dielectric layer, a first and second transparent capacitor electrode layers. The first dielectric layer covers the first metal layer. The second metal layer is disposed on the first dielectric layer and coupled to the first metal layer. The second dielectric layer covers the second metal layer. The first transparent capacitor electrode layer is disposed on the first dielectric layer and connected to the second metal layer. The second transparent capacitor electrode layer is disposed on the second dielectric layer and coupled to the first metal layer, in which the second and first transparent capacitor electrode layers are arranged to be stacked in a thickness direction and mutually opposed across the second dielectric layer therebetween. | 2014-10-02 |
20140291804 | SEMICONDUCTOR DEVICES HAVING BALANCING CAPACITOR AND METHODS OF FORMING THE SAME - A semiconductor memory device includes a substrate including cell block, a balancing block, and a sense block. A plurality of cell bit lines are formed in the cell block of. A plurality of cell plugs are formed adjacent to side surfaces of the bit lines. Cell inner spacers, air spacers, and cell outer spacers are formed between the cell bit lines and the cell plugs. A plurality of balancing bit lines are formed in the balancing block. A plurality of balancing plugs are formed adjacent to side surfaces of the balancing bit lines. Balancing inner spacers and balancing outer spacers are formed between the balancing bit lines and the balancing plugs. The balancing bit lines and at least some of the cell bit lines are connected to the sense block. | 2014-10-02 |
20140291805 | SEMICONDUCTOR DEVICE CONTAINING MIM CAPACITOR AND FABRICATION METHOD - A semiconductor device containing an MIM capacitor and its fabrication method are provided. A metal-insulator-metal (MIM) capacitor is formed on a first interlayer dielectric layer covering a substrate. The MIM capacitor includes a bottom electrode layer and a top electrode layer that are isolated from and laterally staggered with one another. A second interlayer dielectric layer is formed to cover both the MIM capacitor and the first interlayer dielectric layer. A first conductive plug and a second conductive plug are formed each passing through the second interlayer dielectric layer. The first conductive plug contacts a sidewall and a surface portion of the top electrode layer of the MIM capacitor and the second conductive plug contacts a sidewall and a surface portion of the bottom electrode layer of the MIM capacitor. | 2014-10-02 |
20140291806 | CAPACITOR ARRAYS FOR MINIMIZING GRADIENT EFFECTS AND METHODS OF FORMING THE SAME - Semiconductor devices having capacitor arrays. A semiconductor device is formed including a capacitor array formed in a plurality of cells in a two-dimensional grid. The capacitor array includes a plurality of operational capacitors formed in a first subset of the plurality of cells along a diagonal of the capacitor array. A first operational capacitor is formed in a cell at a first edge of the capacitor array and at a first edge of the diagonal of the capacitor array. The capacitor array also includes a plurality of dummy patterns formed about the plurality of operational capacitors in the capacitor array in a second subset of the plurality of cells to achieve symmetry in the grid about the diagonal. Each one of the plurality of operational capacitors is electrically coupled to another one of the plurality of operational capacitors. | 2014-10-02 |
20140291807 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate, a first well of a first conductivity type formed within the substrate, a second well of a second conductivity type formed underneath the first well within the substrate and a third well of the second conductivity type formed horizontally to the first well within the substrate, and including a first region formed to a first depth from a surface of the substrate, and a second region formed to a second depth greater than the first depth from the surface of the substrate and connected to the second well. | 2014-10-02 |
20140291808 | Avalanche Diode Having an Enhanced Defect Concentration Level and Method of Making the Same - The invention relates to an avalanche diode that can be employed as an ESD protection device. An avalanche ignition region is formed at the p-n junction of the diode and includes an enhanced defect concentration level to provide rapid onset of avalanche current. The avalanche ignition region is preferably formed wider than the diode depletion zone, and is preferably created by placement, preferably by ion implantation, of an atomic specie different from that of the principal device structure. The doping concentration of the placed atomic specie should be sufficiently high to ensure substantially immediate onset of avalanche current when the diode breakdown voltage is exceeded. The new atomic specie preferably comprises argon or nitrogen, but other atomic species can be employed. However, other means of increasing a defect concentration level in the diode depletion zone, such as an altered annealing program, are also contemplated. | 2014-10-02 |
20140291809 | Semiconductor Substrate and a Method of Manufacturing the Same - The semiconductor substrate includes a high-ohmic semiconductor material with a conduction band edge and a valence band edge, separated by a bandgap, wherein the semiconductor material includes acceptor or donor impurity atoms or crystal defects, whose energy levels are located at least 120 meV from the conduction band edge, as well as from the valence band edge in the bandgap; and wherein the concentration of the impurity atoms or crystal defects is larger than 1×10 | 2014-10-02 |
20140291810 | METHODS FOR GROWING III-V MATERIALS ON A NON III-V MATERIAL SUBSTRATE - The present invention relates to a method for manufacturing semiconductor materials comprising epitaxial growing of group III-V materials, for example gallium arsenide (GaAs), on for example a non III-V group material like silicon (Si) substrates (wafers), and especially to pre-processing steps providing a location stabilisation of dislocation faults in a surface layer of the non III-V material wafer in an orientation relative to an epitaxial material growing direction during growing of the III-V materials, wherein the location stabilised dislocation fault orientations provides a barrier against threading dislocations (stacking of faults) from being formed in the growing direction of the III-V materials during the epitaxial growth process. | 2014-10-02 |
20140291811 | GROUP III NITRIDE CRYSTAL SUBSTRATE, EPILAYER-CONTAINING GROUP III NITRIDE CRYSTAL SUBSTRATE, SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A group III nitride crystal substrate is provided in which a uniform distortion at a surface layer of the crystal substrate represented by a value of |d | 2014-10-02 |
20140291812 | SEMICONDUCTOR PACKAGES HAVING AN ELECTRIC DEVICE WITH A RECESS - Embodiments are directed to a package that includes an electric device having a recess. In one embodiment, the electric device is a sensor and the recess reduces signal drift of the sensor caused by thermal expansion of the package. In another embodiment, the recess is substantially filled with adhesive material, thus increasing adhesion between the electric device and a substrate of the package while at the same time allowing for lower adhesive fillets. | 2014-10-02 |
20140291813 | LASER MACHINING METHOD AND CHIP - While reliably cutting an object to be processed, the strength of the resulting chips is improved. An object to be processed | 2014-10-02 |
20140291814 | INSULATING SUBSTRATE, METHOD OF MANUFACTURING THE SAME, AND SEMICONDUCTOR DEVICE - An insulating substrate includes: a transparent insulating layer; a first metal layer that is provided on a first face of the transparent insulating layer; and a second metal layer that is provided on a second face of the transparent insulating layer that is opposite from the first face. The first face of the transparent insulating layer is formed with an exposed section that is an area not provided with the first metal layer. The second metal layer includes an area that is overlapped with the exposed section when seen in an orthogonal direction to the first face. | 2014-10-02 |
20140291815 | PROCESSING A WAFER FOR AN ELECTRONIC CIRCUIT - According to a disclosed embodiment, there is provided a method of processing a silicon wafer for use in a substrate for an electronic circuit, comprising: impregnating the silicon wafer with impurities that form one or more deep energy levels within the band gap of silicon, wherein at least one of said deep energy levels is positioned at least 0.3 eV away from the conduction band if the level is a donor level or at least 0.3 eV away from the valence band if the level is an acceptor level; and pre-processing the silicon wafer, prior to or after said impregnation step, so that precipitation of oxide during, after, or during and after, said impregnating step is suppressed. | 2014-10-02 |
20140291816 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE WITH A CONTINUOUS SILICATE GLASS STRUCTURE - A method of manufacturing a semiconductor device includes forming a continuous silicate glass structure over a first surface of a semiconductor body, including a first part of the continuous glass structure over an active area of the semiconductor body and a second part of the continuous glass structure over an area of the semiconductor body outside of the active area. A first composition of dopants included in the first part of continuous glass structure differs from a second composition of dopants of the second part of the continuous glass structure. | 2014-10-02 |
20140291817 | SEMICONDUCTOR DEVICE INCLUDING POROUS LOW-K DIELECTRIC LAYER AND FABRICATION METHOD - Semiconductor devices including porous low-k dielectric layers and fabrication methods are provided. A dielectric layer is formed on a substrate by introducing and polymerizing a main reaction gas on a surface of the substrate. The main reaction gas has a chemical structure including a ring-shaped group, silicon, carbon, and hydrogen, and the ring-shaped group includes at least carbon and hydrogen. A porous low-k dielectric layer is then formed from the dielectric layer by curing the dielectric layer with UV light. | 2014-10-02 |
20140291818 | Integrated Circuit Device Facilitating Package on Package Connections - In embodiments described herein, an integrated circuit (IC) package is provided. The IC package can include a substrate having opposing first and second surfaces, an IC die coupled to the first surface of the substrate, a first plurality of conductive elements coupled to conductive regions on the first surface of the substrate, an interposer having opposing first and second surfaces, and a second plurality of conductive elements coupled to conductive regions on the first surface of the interposer. The second surface of the substrate is configured be coupled to at least one device. Each of the first plurality of conductive elements is electrically coupled to a respective one of the second plurality of conductive elements. The interposer is configured to be attached to a printed circuit board (PCB). | 2014-10-02 |
20140291819 | HYBRID CARBON-METAL INTERCONNECT STRUCTURES - Embodiments of the present disclosure are directed towards techniques and configurations for hybrid carbon-metal interconnect structures in integrated circuit assemblies. In one embodiment, an apparatus includes a substrate, a metal interconnect layer disposed on the substrate and configured to serve as a growth initiation layer for a graphene layer and the graphene layer, wherein the graphene layer is formed directly on the metal interconnect layer, the metal interconnect layer and the graphene layer being configured to route electrical signals. Other embodiments may be described and/or claimed. | 2014-10-02 |
20140291820 | Semiconductor Device and Method of Forming Shielding Layer Over Active Surface of Semiconductor Die - A semiconductor wafer contains a plurality of semiconductor die separated by a non-active area of the semiconductor wafer. A plurality of contact pads is formed on an active surface of the semiconductor die. A first insulating layer is formed over the semiconductor wafer. A portion of the first insulating layer is removed to expose the contact pads on the semiconductor die. An opening is formed partially through the semiconductor wafer in the active surface of the semiconductor die or in the non-active area of the semiconductor wafer. A second insulating layer is formed in the opening in the semiconductor wafer. A shielding layer is formed over the active surface. The shielding layer extends into the opening of the semiconductor wafer to form a conductive via. A portion of a back surface of the semiconductor wafer is removed to singulate the semiconductor die. | 2014-10-02 |
20140291821 | SEMICONDUCTOR PACKAGE HAVING GROUNDING MEMBER AND METHOD OF MANUFACTURING THE SAME - A semiconductor package and method of manufacture are provided. The semiconductor package may include a package substrate, a semiconductor chip, a molding member and a grounding member. The package substrate may include a ground pad and a signal pad. The semiconductor chip may be arranged on an upper surface of the package substrate. The semiconductor chip may be electrically connected with the signal pad of the package substrate. The molding member may be formed on the upper surface of the package substrate to cover the semiconductor chip. The grounding member may be arranged on a surface of the molding member. The grounding member may be electrically connected with the ground pad. | 2014-10-02 |
20140291822 | INTEGRATED CIRCUIT PACKAGE - An integrated circuit (“IC”) package including an IC assembly mounted on a leadframe and an encapsulant block covering the IC assembly and portions of the leadframe. The encapsulant block has a molded chamfered outer surface portion and the leadframe has a saw cut outer periphery. | 2014-10-02 |
20140291823 | CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME - Embodiments provide provides a chip package. The chip package may include a leadframe having a die pad and a plurality of lead fingers; a first chip attached to the die pad, the first chip being bonded to one or more of the lead fingers via a first set of wire bonds; a second chip bonded to one or more of the lead fingers via flip chip; and a heat slug attached to the second chip. | 2014-10-02 |
20140291824 | Leadframe, Semiconductor Package Including a Leadframe and Method for Producing a Leadframe - A lead frame includes a die pad and a lead finger with an inner portion which is configured to be electrically connected to contact pads of a die and with an outer portion which has an attach portion. The attach portion is configured to be soldered to an external solder pad, wherein the attach portion has a width, a length and a thickness. An opening extends through the thickness of the attach portion. | 2014-10-02 |
20140291825 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MODULE - A semiconductor device in the preferred embodiment includes: a lead frame comprising a die pad and an electrode terminal; and at least one semiconductor chip bonded to a surface of the die pad, wherein the lead frame excluding a bottom surface thereof and the semiconductor chip are sealed by a sealing resin, and an unevenness is introduced on a bonding interface between the surface of the die pad and the semiconductor chip. | 2014-10-02 |
20140291826 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE - A semiconductor device and a manufacturing method for a semiconductor device in which during QFP (quad flat package assembly) a wire passing over a bus bar and coupled to an inner lead is set at a loop height different from a second wire at a low loop height, and a third wire at a high loop height, and also mounted nearer a standard suspension lead than the second wire and the third wire. The loop height of the wire becomes gradually higher than the direction of resin flow in the resin sealing process so that wire sweep can be reduced and the reliability of the QFP assembly can be improved. | 2014-10-02 |