40th week of 2015 patent applcation highlights part 88 |
Patent application number | Title | Published |
20150280692 | DATA OUTPUT CIRCUIT OF A SEMICONDUCTOR APPARATUS - A data output circuit of a semiconductor apparatus includes a pull-up driver including a plurality of leg units configured to be controlled in respective resistance values in response to code signals, be controlled in an entire resistance value as one or more of the plurality of leg units are selectively activated in response to selection signals, and configured to apply an output voltage with an output voltage level selected according to a control of the entire resistance value among a plurality of output voltage levels, to a data output pad; a control block configured to generate the selection signals in response to mode register signals; and a code generator configured to generate the code signals according to an external resistor. | 2015-10-01 |
20150280693 | DATA OUTPUT CIRCUIT OF A SEMICONDUCTOR APPARATUS - A data output circuit of a semiconductor apparatus includes a pull-up driver including a plurality of leg units configured to be controlled in respective resistance values in response to code signals, be controlled in an entire resistance value as one or more of the plurality of leg units are selectively activated in response to selection signals, and configured to apply an output voltage with an output voltage level selected according to a control of the entire resistance value among a plurality of output voltage levels, to a data output pad; a control block configured to generate the selection signals in response to mode register signals; and a code generator configured to generate the code signals according to an external resistor. | 2015-10-01 |
20150280694 | RAPID TRANSITION SCHMITT TRIGGER CIRCUIT - A small-sized rapid transition Schmitt trigger circuit for use with a silicon-on-insulator process includes: a first NMOS transistor, a first PMOS transistor, a second NMOS transistor, a second PMOS transistor, and a PMOS/NMOS body control circuit; wherein, the PMOS/NMOS body control circuit is configured to, through changing threshold voltages of the first NMOS transistor and the first PMOS transistor, enable different flip-flop threshold voltages for input transitions from high electrical levels to low electrical levels and from low electrical levels to high electrical levels. | 2015-10-01 |
20150280695 | SYSTEMS AND METHODS FOR COMMON MODE LEVEL SHIFTING - A common mode voltage level shifting circuit including: input nodes configured to receive a differential signal with a first common mode voltage, a pair of shunt capacitors coupled between the input nodes and a corresponding pair of output nodes, a threshold voltage circuit, including the output nodes, coupled to the differential signal though the shunt capacitors, the threshold voltage circuit configured to provide a second common mode voltage for the differential signal at the output nodes, and current sources that are controlled according to a level of the first common mode voltage, the current sources coupled to the output nodes to effect the second common mode voltage. | 2015-10-01 |
20150280696 | CIRCUIT FOR COMMON MODE REMOVAL FOR DC-COUPLED FRONT-END CIRCUITS - In one example, a method includes receiving a first differential signal including a first voltage signal and a second voltage signal, wherein the first differential signal includes a first common mode voltage; receiving a second common mode voltage. The method further includes determining, by a circuit, a second differential signal including a third voltage signal and a fourth voltage signal, wherein a difference between the third voltage signal and the fourth voltage signal is based on a difference between the first voltage signal and the second voltage signal, wherein the second differential signal includes the second common mode voltage. The method further includes outputting, substantially continuously, the second differential signal. | 2015-10-01 |
20150280697 | HIGH FREQUENCY SEMICONDUCTOR DEVICE - Certain embodiments provide a high frequency semiconductor device including a plurality of unit FETs, an input dividing/matching circuit, an output combining/matching circuit, and a low-frequency-oscillation-suppressing-circuit. The input dividing/matching circuit has an input end and a plurality of divided output ends connected to the unit FETs, and is symmetrical about a center axis of the input end. The output combining/matching circuit has an output end and a plurality of divided input ends connected to the unit FETs, and is symmetrical about a center axis of the output end. The low-frequency-oscillation-suppressing-circuit is connected to at least one of the input end of the input dividing/matching circuit and the output end of the output combining/matching circuit. | 2015-10-01 |
20150280698 | DATA SIGNAL RECEIVER, TRANSCEIVER SYSTEM AND METHOD OF RECEIVING DATA SIGNAL - A data signal receiver includes a clock signal filter, a falling pulse signal generator, a mixing block, and a sampler. The clock signal filter generates a first filtered clock signal and a second filtered clock signal by filtering a clock signal. The falling pulse signal generator generates a falling pulse signal based on the first filtered clock signal. The mixing block generates a mixed data signal by mixing a data signal and the falling pulse signal. The sampler generates a recovered data signal by sampling the mixed data signal in response to the second filtered clock signal. | 2015-10-01 |
20150280699 | LINEARIZATION CIRCUIT FOR HIGH FREQUENCY SIGNAL PHASE ADJUSTMENT - A circuit includes a phase adjustment capacitor (PAC) coupled to a signal path and configured to adjust a phase of a signal on the signal path. A transistor switch device is coupled in series with the PAC to provide a circuit branch parallel with the signal path. The transistor switch device is configured to selectively open or close the circuit branch of the signal path to enable or disable, respectively, the adjustment of the phase of the signal on the signal path via the PAC. A nonlinear capacitance is coupled to a node interconnecting the PAC and the transistor switch device. The nonlinear capacitance is configured to vary inversely proportional with a capacitance of the transistor switch device with respect to the signal on the signal path and to linearize a total capacitance provided by the circuit branch when the circuit branch is open. | 2015-10-01 |
20150280700 | APPARATUS FOR SUPPLYING GATE DRIVING VOLTAGES, METHOD THEREFOR AND DISPLAY APPARATUS - There are provided an apparatus for supplying gate driving voltages, a method for supplying gate driving voltages and a display apparatus to which the apparatus for supplying gate driving voltages is applied to. In the apparatus for supplying gate driving voltages, there is disposed a starting voltage boost module connected with a starting voltage output module. The starting voltage boost module is configured to boost a second preset voltage to a third preset voltage higher than a first preset voltage in advance within a predetermined period of time when the second preset voltage is restored to the first preset voltage. By means of the third preset voltage with a higher voltage, the time taken by a gate ON voltage to be restored to the first preset voltage from the second preset voltage is shortened, a response speed is quicken and a problem of too slow restoration due to a large load is settled, so that a charging time of a liquid crystal display panel is increased and the display quality of the picture is enhanced. | 2015-10-01 |
20150280701 | SYSTEM AND METHOD FOR BREAKDOWN PROTECTION FOR SWITCHING OUTPUT DRIVER - An integrated circuit device includes a driver circuit ( | 2015-10-01 |
20150280702 | SEMICONDUCTOR DEVICE HAVING SUBTHRESHOLD OPERATING CIRCUITS INCLUDING A BACK BODY BIAS POTENTIAL BASED ON TEMPERATURE RANGE - A semiconductor device that may include at least one temperature sensing circuit is disclosed. The temperature sensing circuits may be used to control various operating parameters to improve the operation of the semiconductor device over a wide temperature range. In this way, operating specifications of a semiconductor device at worst case temperatures may be met without compromising performance at other operating temperatures. The temperature sensing circuit may provide a plurality of temperature ranges for setting the operational parameters. Each temperature range can include a temperature range upper limit value and a temperature range lower limit value and adjacent temperature ranges may overlap. The temperature ranges may be set in accordance with a count value that can incrementally change in response to the at least one temperature sensing circuit. | 2015-10-01 |
20150280703 | POWER GATING CIRCUIT AND INTEGRATED CIRCUIT - A power gating circuit in an integrated circuit, including a circuit block coupled to a virtual power supply line, includes a first transistor and a buffer. The first transistor is coupled between a first power supply line and the virtual power supply line, and has a body coupled to the first power supply line. The buffer buffers a control signal to apply the buffered control signal to the first transistor, and includes a second transistor having a source coupled to a second power supply line and a body coupled to the first power supply line. | 2015-10-01 |
20150280704 | SHIFT REGISTER, DISPLAY APPARATUS, GATE DRIVING CIRCUIT, AND DRIVING METHOD - A shift register, a display apparatus, a gate driving circuit and a driving method, the shift register comprises a plurality of stages of shift register circuits (SR | 2015-10-01 |
20150280705 | START-UP TECHNIQUE AND SYSTEM FOR A SELF-POWERED GATE DRIVE CIRCUIT - A start-up method for a self-powered gate drive circuit driving a power transistor gate. The method comprises charging, with a single-supply voltage, a first supply capacitor of a first gate drive circuit; switching on a first power transistor by applying a current supplied by a discharge of the first supply capacitor of the first gate drive circuit to the gate of the first power transistor; charging a second supply capacitor of the first gate drive circuit using an output signal from the first power transistor; and re-charging the first supply capacitor by applying a current supplied by a discharge of the second supply capacitor to the first capacitor. | 2015-10-01 |
20150280706 | SELF-POWERED GATE DRIVE CIRCUIT APPARATUS AND METHOD - A self-powered gate drive circuit comprising a first capacitor electrically coupled to a power semiconductor collector node of the circuit; a first switch arranged between the first capacitor and a second capacitor, the first switch electrically coupling the first and second capacitors when switched on; the second capacitor; a first diode, the first diode anode electrically coupled to the first capacitor and the first diode cathode electrically coupled to the first switch; a second diode, the second diode cathode electrically coupled to the first capacitor and the second diode anode electrically coupled with a ground node of the circuit; and a second switch, wherein the second switch electrically couples the second capacitor with a power semiconductor gate node when switched on. | 2015-10-01 |
20150280707 | DYNAMICALLY RECONFIGURABLE CAPACITIVE SENSOR ARRAY - In a keyboard of the type including a key cap and a capacitive sensor disposed underneath the key cap, a method including operating the capacitive sensor in a first mode configured for near field detection and generating a first variable capacitance, and operating the capacitive sensor in a second mode configured for far field detection and generating a second variable capacitance. The method further includes determining key motion based on the first variable capacitance and determining finger presence based on the second variable capacitance. | 2015-10-01 |
20150280708 | INFORMATION PROCESSING DEVICE, INPUT DEVICE, INFORMATION PROCESSING METHOD, AND PROGRAM - There is provided an information processing device including a temperature compensation unit configured to correct an operation input value indicating an operation input to each of a plurality of key regions provided on a sheet-like operation member based on ambient temperature of an input device in which the operation input to each of the key regions is detected as a capacitance variation amount of a capacitive element depending on a change in a distance between the key region and the capacitive element, the capacitive element being provided in a manner that the capacitive element corresponds to each of the key regions. | 2015-10-01 |
20150280709 | SEMICONDUCTOR DEVICE - The semiconductor device includes: a first die configured to include a first input pad and a first output pad; and a second die configured to include a second input pad and a second output pad. The second die corrects a level of an output voltage in response to a feedback reference voltage applied from the first output pad to the second input pad. | 2015-10-01 |
20150280710 | CLOCK TREE UNIT CELL CIRCUIT, CLOCK TREE, AND APPARATUS - A clock tree unit cell circuit includes a first input terminal configured to receive a clock signal from an upstream side of a clock tree; a first output terminal configured to output a clock signal to a downstream side of the clock tree; a second input terminal configured to receive a standby signal from the upstream side of the clock tree; a third input terminal configured to receive a standby signal from the downstream side of the clock tree; a logic circuit configured to perform a predetermined logical operation on the clock signal inputted to the first input terminal and output the clock signal to the first output terminal; and a control circuit that is connected to the second input terminal, the third input terminal, and an output control terminal of the logic circuit. | 2015-10-01 |
20150280711 | SEMICONDUCTOR CIRCUIT, SEMICONDUCTOR DEVICE AND POTENTIAL SUPPLY CIRCUIT - The present invention provides a semiconductor circuit including: a level shifter circuit that, in accordance with supply of a power supply voltage, converts a potential of an input signal from a first potential to a second potential that is higher than the first potential and outputs the second potential through an output node; a potential supply circuit, to which a reset signal at a level in accordance with the power supply voltage is supplied, that supplies a predetermined potential in accordance with the level of the reset signal; and a control circuit that controls the potential of the output node of the level shifter circuit in accordance with the level of the predetermined potential supplied from the potential supply circuit. | 2015-10-01 |
20150280712 | DATA OUTPUT CIRCUIT OF SEMICONDUCTOR APPARATUS - A data output circuit of a semiconductor apparatus includes a pull-up driver electrically coupled between a power supply terminal and an output terminal, and configured to drive the output terminal in response to pull-up control signals. The data output circuit may also include a pull-down driver electrically coupled between the output terminal and a ground terminal, and configured to drive the output terminal in response to pull-down control signals. Further, the data output circuit may include a compensation unit configured to open a current path between the output terminal and the ground terminal during an operation period of the pull-up driver, and allow leakage current of the pull-up driver to flow through the current path. | 2015-10-01 |
20150280713 | DATA OUTPUT CIRCUIT OF SEMICONDUCTOR APPARATUS - A data output circuit of a semiconductor apparatus includes a pull-up driver electrically coupled between a power supply terminal and an output terminal, and configured to drive the output terminal in response to pull-up control signals. The data output circuit may also include a pull-down driver electrically coupled between the output terminal and a ground terminal, and configured to drive the output terminal in response to pull-down control signals. Further, the data output circuit may include a compensation unit configured to open a current path between the output terminal and the ground terminal during an operation period of the pull-up driver, and allow leakage current of the pull-up driver to flow through the current path. | 2015-10-01 |
20150280714 | VOLTAGE LEVEL SHIFTER CIRCUIT, SYSTEM, AND METHOD FOR WIDE SUPPLY VOLTAGE APPLICATIONS - A level shifter circuit is configured to receive first and second complementary input signals. Each of the first and second complementary input signals have a value of either a first supply voltage or a first reference voltage. The level shifter further includes a strong latch circuit operable in response to the first and second complementary input signals to drive one of first and second output signals to a second supply voltage and includes a weak latch circuit operable to drive the other of the first and second output signals to a second reference voltage. | 2015-10-01 |
20150280715 | SEMICONDUCTOR DEVICE - [Object] A novel programmable logic device is provided. | 2015-10-01 |
20150280716 | BUFFER CIRCUIT WITH REDUCED STATIC LEAKAGE THROUGH CONTROLLED BODY BIASING IN FDSOI TECHNOLOGY - A buffer includes an input configured to receive a first digital signal having first and second logic states referenced, respectively, to a first high voltage and a first low voltage of a first supply domain. A first inverter circuit includes a pMOS transistor and nMOS transistor having gate terminals connected to the input. A second inverter is connected in series with the output of the first inverter. The second inverter has an output configured to generate a second digital signal having first and second logic states referenced, respectively, to a second high voltage and a second low voltage of a second, different, supply domain, wherein at least the second high voltage is greater than the first high voltage. A feedback circuit is configured to apply the second digital signal as a bias to a transistor body of the p-MOS transistor of the first inverter circuit. | 2015-10-01 |
20150280717 | RECONFIGURABLE SEMICONDUCTOR DEVICE - A reconfigurable semiconductor device includes a plurality of logic units connected to each other via address lines or data lines, each of the logic units including: a plurality of address lines; a plurality of data lines; a first address decoder that decodes addresses inputted from some of the address lines; a second address decoder that decodes addresses inputted from the other of the address lines; a first memory cell unit having a plurality of memory cells and selecting, among said plurality of memory cells, a predetermined number of memory cells in accordance with the address decoded by the first address decoder; and a second memory cell unit having a plurality of memory cells and selecting, among said plurality of memory cells, a predetermined number of memory cells in accordance with the address decoded by the second address decoder. | 2015-10-01 |
20150280718 | FREQUENCY COMPENSATION - A first oscillator generates a first frequency. A second oscillator generates a second frequency. A controller determines a difference between the first frequency and the second frequency and determines a non-ideal component of the first frequency in dependence on a temperature response of the first and second oscillators. | 2015-10-01 |
20150280719 | METHOD OF ADJUSTING FREQUENCY OF RESONATION DEVICE AND METHOD OF MANUFACTURING RESONATION DEVICE - A method of adjusting a frequency of a resonation device including a resonator element and a heating element includes performing the frequency adjustment of the resonator element while heating the resonator element by the heating element. | 2015-10-01 |
20150280720 | OUTPUT CONTROL CIRCUIT FOR SEMICONDUCTOR APPARATUS AND OUTPUT DRIVING CIRCUIT INCLUDING THE SAME - An output control circuit may include a period setting signal generation unit configured to output a setup signal enabled during a designated period, in response to a delayed locked loop (DLL) locking signal and an output enable reset signal. The output control circuit may also include a clock division unit configured to divide an internal clock at a preset division ratio in response to the setup signal, and output a divided clock. In addition, the output control circuit may include a shift unit configured to shift the setup signal by a preset first time in response to the divided clock, and output a first delayed setup signal. Further, the output control circuit may include an output unit configured to receive and process the first delayed setup signal in response to the divided clock, and output the output enable reset signal. | 2015-10-01 |
20150280721 | CLOCK DELAY DETECTING CIRCUIT AND SEMICONDUCTOR APPARATUS USING THE SAME - Provided is a clock delay detecting circuit and semiconductor apparatus using the same that is capable of generating a period signal whose period is a delay time of a clock, dividing the period signal, and counting the divided period signal. The clock delay detection circuit comprises a period signal generating unit configured to generate a counting control signal, a period signal dividing unit configured to generate a counting enable signal by dividing the counting control signal, and a counting unit configured to generate a delay information signal by counting the counting enable signal with a clock, wherein the counting control signal has a period with a predetermined time. | 2015-10-01 |
20150280722 | DISTRIBUTED PHASE DETECTION FOR CLOCK SYNCHRONIZATION IN MULTI-LAYER 3D STACKS - There is provided a clock distribution network for synchronizing global clock signals within a 3D chip stack having two or more strata. The clock distribution circuit includes, on each of the two or more strata, phase detectors, a logic circuit, and a phase de-skewing element. Each phase detector has a respective output for providing phase information relating to a phase difference between two of the global clocks signals on respective different ones of the two or more strata. The logic circuit is connected to the respective outputs of the phase detectors for determining a phase adjustment plan for a given one of the two or more strata upon which the logic circuit is located responsive to the phase information. The phase de-skewing element is for adjusting a clock skew of a same stratum located one of the two of the global clock signals responsive to the phase adjustment plan. | 2015-10-01 |
20150280723 | OSCILLATING SIGNAL GENERATOR, PHASE-LOCK LOOP CIRCUIT USING THE OSCILLATING SIGNAL GENERATOR AND CONTROL METHOD OF THE OSCILLATING SIGNAL GENERATOR - An oscillating signal generator includes: a controllable oscillator arranged to output an oscillating signal according to a control signal and a band adjusting signal; a control circuit arranged to generate a continuous signal having a specific slew-rate when the control signal reaches a boundary of a control signal interval; and a current mirror arranged to generate the band adjusting signal according to at least the continuous signal. | 2015-10-01 |
20150280724 | Quantization Circuit and Method for Quantizing an Input Quantity - A quantization circuit includes a quantizer configured to provide a quantized sample using an input quantity and an error estimator configured to determine a quantization error of the quantized sample. An error corrector is configured to correct the quantized sample by a correction value depending on the quantization error. | 2015-10-01 |
20150280725 | METHOD AND APPARATUS FOR CALIBRATION OF A TIME INTERLEAVED ADC - Systems and methods for converting analog signals to digital signals. A reference slice is associated with each of a plurality of active slices to balance the loading on an active sampling track and hold amplifier within each active slice. Alternatively, the reference slice is split into a portion having a reference ADC that is shared by a plurality of partial reference slices, each partial reference slice having a partial reference input module. | 2015-10-01 |
20150280726 | ANALOGUE TO DIGITAL CONVERSION DEVICE - An A/D conversion device has an A/D conversion section including A/D conversion units. Each A/D conversion unit has a pulse delay circuit including delay units connected in daisy chain to form a ring delay line. Each delay unit delays a pulse signal by a delay time corresponding to an input voltage. The A/D conversion section counts the number of pulse signals that passed through the delay units during a period counted from a timing when a start signal is switched to an activation level from a non-activation level at a timing when a sampling signal is received. When each two successive timing signals CKi (i=1, 2, . . . and m) have a same specific period. The each two successive timing signals have a different phase shifted by 1/m of the specific period. Each A/D conversion unit receives the timing signal CK | 2015-10-01 |
20150280727 | MULTIPLYING DIGITAL-TO-ANALOG CONVERTER AND PIPELINE ANALOG-TO-DIGITAL CONVERTER USING THE SAME - A multiplying digital-to-analog converter (MDAC) with capacitive load reset on an operational amplifier and a pipeline analog-to-digital converter using the MDAC are disclosed. The MDAC includes an operational amplifier and first and second switched-capacitor networks sharing the operational amplifier. The operational amplifier is further coupled with first capacitive load cells when the first switched-capacitor network is coupled to the operational amplifier, and the first capacitive load cells are reset when the first switched-capacitor network is disconnected from the operational amplifier. The operational amplifier is further coupled with second capacitive load cells when the second switched-capacitor network is coupled to the operational amplifier, and the second capacitive load cells are reset when the second switched-capacitor network is disconnected from the operational amplifier. | 2015-10-01 |
20150280728 | ADAPTIVE DELAY BASED ASYNCHRONOUS SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER - An asynchronous SAR ADC to convert an analog signal into a series of digital pulses in an efficient, low power manner. In synchronous SAR ADC circuits, a separate and cumbersome clock signal is used to trigger the internal circuitry of the SAR ADC. Instead of triggering the components of the SAR DAC synchronously with a clock signal, the asynchronous solution uses its own internal signals to trigger its components in an asynchronous cyclic manner. Further, in order to increase efficiency and guard against circuit failures due to difficulties arising from transient signals, the asynchronous SAR ADC may also include a delay circuit for introducing a variable delay to the SAR ADC cycle. | 2015-10-01 |
20150280729 | SYSTEMS AND METHODS FOR CAPACITIVE DIGITAL TO ANALOG CONVERTERS - A capacitive digital to analog converter (DAC) includes a first switching device that receives first, second, third, and fourth reference potentials at respective inputs and that selectively connects one of the first, second, third, and fourth reference potentials to a first output. The first and second reference potentials are approximately equal. The third and fourth reference potentials are approximately equal. A first capacitor is connected between the first output and a common node. A second switching device receives the first, second, third, and fourth reference potentials at respective inputs and selectively connects one of the first, second, third, and fourth reference potentials to a second output. A second capacitor is connected between the second output and the common node. | 2015-10-01 |
20150280730 | SUCCESSIVE COMPARISON TYPE ANALOG/DIGITAL CONVERTER, PHYSICAL QUANTITY SENSOR, ELECTRONIC DEVICE, MOVING OBJECT, AND SUCCESSIVE COMPARISON TYPE ANALOG/DIGITAL CONVERSION METHOD - A successive approximation type AD converter includes a charge redistribution type DA conversion circuit, a comparator, and a control circuit. The charge redistribution type DA conversion circuit is configured such that each of k unit elements connects a switch and a unit capacitance in series and includes a unit capacitor array that is connected to a common output line in parallel and a selector that selects one voltage supplied to one input terminal, through m voltage supply lines, among at least three input terminals of switches included in j unit elements which are the targets for dynamic element matching (DEM) in k unit elements based on the DEM. | 2015-10-01 |
20150280731 | SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER - Aspects of a method and apparatus for converting an analog input value to a digital output code are provided. One embodiment of the apparatus includes a digital-to-analog converter, a comparator, and control logic circuitry. The digital-to-analog converter is configured to generate an analog reference value based on a received digital reference value. The comparator is configured to compare an analog input value to the analog reference value after expiration of an allotted settling time for the digital-to-analog converter and generate a comparison result indicative a relationship between the analog input value and the analog reference value. The control logic circuitry is configured to select the allotted settling time for the digital-to-analog converter based on a bit position of a digital output code to be determined, and update the bit position of the digital output code based on the comparison result. | 2015-10-01 |
20150280732 | COMMUNICATION UNIT, DIGITAL BAND-PASS SIGMA-DELTA MODULATOR AND METHOD THEREFOR - A communication unit comprises a power DAC. The DAC comprises: a switched mode power amplifier (SMPA); and a digital band-pass sigma-delta modulator operably coupled to the SMPA. The sigma-delta modulator comprises an input to receive an input baseband signal; a delay; an adder module arranged to add a feedback signal with an output from the delay; and at least two feedback branches. The sigma-delta modulator is arranged to digitally oversample the input baseband signal such that a ratio of a sampling frequency employed by the sigma-delta modulator to a radio frequency (RF) output from the DAC is fixed and the sampling frequency tuned or wherein the sampling frequency is fixed and the ratio is adjusted, such that a first feedback branch in the sigma-delta modulator is formed using at least one from a group of: a zero gain, an additive inverse of a second feedback branch. | 2015-10-01 |
20150280733 | SIGMA DELTA RF MODULATOR HAVING CAPACITIVE COUPLING, ANALOG/DIGITAL CONVERTER AND APPARATUS INCLUDING SUCH A MODULATOR - A continuous-time sigma delta radio frequency modulator is provided, including at least two LC resonators coupled in parallel by a coupling capacitive element, producing an at least 4 | 2015-10-01 |
20150280734 | Sigma-Delta Analog-to-Digital Converter - The application disclose a sigma-delta analog-to-digital converter. The converter comprises: a summing stage, configured to receive an input signal and subtract a first feedback signal and a second feedback signal from the input signal to generate a difference signal; a loop filter coupled to an output node of the summing stage, and configured to filter the difference signal; a quantizer coupled to an output node of the loop filter, and configured to quantize the filtered difference signal to generate a quantized signal, and to generate an overload signal according to the filtered difference signal, wherein the overload signal indicates whether the filtered difference signal is overloaded and/or an overload amount of the filtered difference signal; a first digital-to-analog converter coupled to the quantizer to receive the quantized signal, and configured to generate the first feedback signal according to the quantized signal; and a second D/A converter coupled to the quantizer to receive the overload signal, and configured to generate the second feedback signal according to the overload signal. | 2015-10-01 |
20150280735 | DELTASIGMA D/A CONVERTER, SIGNAL PROCESSING CIRCUIT INCLUDING THE SAME, AND ELECTRONIC APPARATUS - A ΔΣ D/A converter for converting a digital input data to an analog output signal, includes: a ΔΣ modulator configured to generate a first data by ΔΣ-modulating the digital input data; a digital filter configured to generate a second data by smoothing the first data; and a D/A converter configured to convert the second data to the analog output signal. | 2015-10-01 |
20150280736 | INCREASING SPEED OF DATA COMPRESSION - A computer implemented method of performing data compression includes applying, with a computing device, a hash function to a selected part of a character string to calculate a hash value; searching, using the hash value, through entries in a bucket chain having the hash value previously registered in a hash table, and finding a longest matching character string; acquiring, an index indicating that a longest matching character string cannot be found in the search through the entries and thus the search operation is wasted; and switching the hash function to a different hash function for expanding the selected part of the character string, without reconstructing the hash table, when the index exceeds a predetermined threshold. | 2015-10-01 |
20150280737 | COMPRESSION RATIO FOR A COMPRESSION ENGINE - An output sequence of data elements is processed. The output sequence of data elements represents a sequence of input data elements in a compressed format. An output data element comprises a backward reference for each string in the input data elements that occurs again in an input data element that is used to produce the output data element. A backward reference identified in a selected output data element is used for selecting the string to which it refers in the stored input data elements. The selected string is combined with strings of one or more subsequent output data elements. A matching sequence in the stored input data elements matching at least part of one or more combined strings is found. A combined string of the one or more combined strings having the longest matching sequence is selected. The backward reference is redefined to indicate the longest matching sequence. | 2015-10-01 |
20150280738 | HARDWARE COMPRESSION TO FIND BACKWARD REFERENCES WITH MULTI-LEVEL HASHES - Concurrently writing an uncompressed data element, if the uncompressed data element comprises an indication that it is valid, in a main hash table using a first address generated by a first hash function, and reading a first data element from the main hash table using the first address. Introducing a first pipeline delay for maintaining the uncompressed data element in a first data path until the first data element is read. Concurrently writing the first data element to a victim hash table, if the first data element comprises an indication that it is valid, using a second address generated by a second hash function, and reading a second data element from the victim hash table using a third address generated by the second hash function. Introducing a second pipeline delay for maintaining the uncompressed data element in the first data path until the second data element is read. | 2015-10-01 |
20150280739 | Variable Bit-Length Reiterative Lossless Compression System and Method - A computer-implemented method of performing lossless compression of a digital data set uses an iterative compression process in which the number of symbols N and bit length per symbol n may vary on successive iterations. The process includes analyzing at least a part of the data set to establish a partition thereof into N symbols of symbol length n, and to determine whether the N symbols can be further compressed, and, if so, a model to be used in encoding the N symbols. | 2015-10-01 |
20150280740 | METHOD OF COMPRESSING AND RESTORING CONFIGURATION DATA - A method of compressing configuration data used in a reconfigurable processor including generating one piece of combined data by combining configuration data used at two or more cycles and generating a bit table indicating valid operations at each of the two or more cycles among operations included in the combined data | 2015-10-01 |
20150280741 | CALCULATING CYCLIC REDUNDANCY CHECKS OVER OVERLAPPING WINDOWS OF STREAMING DATA - To calculate sequential CRCs, a CRC pipeline may be used to calculate the sequential CRCs for a block of data The CRC pipeline includes a plurality of stages, where, in each subsequent stage a CRC calculated from a previous stage is used to calculate an offset CRC. For example, using at least one CRC calculator and CRC shifter, a stage in the pipeline removes an effect of first portion of the data represented by a previously calculated CRC from the CRC and then adds an effect of a second portion of data neighboring the first portion in a received data block to yield an offset CRC. For example, a stage may change CRC(0:63) to CRC(32:95) by removing the effect of bytes 0:31 and adding the effect of bytes 64:95. At each stage, the byte offset may get smaller until all the sequential CRCs have been calculated. | 2015-10-01 |
20150280742 | CACHING METHOD AND DATA STORAGE SYSTEM CAPABLE OF PROLONGING SERVICE LIFETIME OF A CACHE MEMORY - In a caching method implemented by a data storage system, a data word as user data is encoded into a codeword that is then written into an area of a cache memory. The codeword includes a data portion, a checksum parity portion and an error correction code (ECC) parity portion. In response to a read request for the user data, the codeword read from the cache memory is decoded based on the ECC parity portion to correct one or more bit errors within the data portion so as to generate a read data portion and a read checksum parity portion. Upon identifying that a validating checksum portion generated based on the read data portion matches the read checksum parity portion, the read data portion serving as the user data is outputted. Otherwise, a data storage unit outputs the user data previously stored therein. | 2015-10-01 |
20150280743 | APPARATUS AND METHOD FOR TRANSMITTING AND RECEIVING A QUASI-CYCLIC LOW DENSITY PARITY CHECK CODE IN A MULTIMEDIA COMMUNICATION SYSTEM - A method and apparatus are provided for transmitting an LDPC code in a multimedia system. The method includes generating an LDPC code based on a resulting parity check matrix which is generated by performing a row splitting operation on a base parity check matrix; and transmitting the LDPC code. The row splitting operation includes splitting each row block included in the base parity check matrix into row blocks, a number of the row blocks is determined based on a splitting factor, and the splitting factor is determined based on a number of repair symbols included in a repair symbol block of the base parity check matrix, a number of rows included in the base parity check matrix, and a scaling factor for determining a size of each permutation matrix in the resulting parity check matrix and a size of each zero matrix included in the resulting parity check matrix. | 2015-10-01 |
20150280744 | DECODING APPARATUS AND METHOD IN MOBILE COMMUNICATION SYSTEM USING NON-BINARY LOW-DENSITY PARITY-CHECK CODE - A decoding method in a mobile communication system using a non-binary LDPC code according to various embodiments of the present disclosure includes: selecting a message value having the highest reliability from each column and each row of an input vector message; generating a configuration set using the message value selected for each column and a GL element corresponding to the message value; and generating a check node output message using the generated configuration set and an extra output message value. According to various embodiments of the present disclosure, a decoding time period is reduced. | 2015-10-01 |
20150280745 | DATA PROCESSING BLOCK AND DATA STORAGE DEVICE INCLUDING THE SAME - A data processing block that includes a syndrome computation unit suitable for generating odd syndrome values in response to a received codeword, an ELP solver suitable for generating even syndrome values, based on the odd syndrome values in a first mode, and generating an error location polynomial, based on the odd syndrome values and the even syndrome values in a second mode, and a Chien search unit suitable for generating solutions of the error location polynomial. | 2015-10-01 |
20150280746 | Low Latency Serial Data Encoding Scheme For Enhanced Burst Error Immunity and Long Term Reliability - A high performance computing system and method communicate data packets between computing nodes on a multi-lane communications link using a modified header bit encoding. Each data packet is provided with flow control information and error detection information, then divided into per-lane payloads. Sync header bits for each payload are added to the payloads in non-adjacent locations, thereby decreasing the probability that a single correlated burst error will invert both header bits. The encoded blocks that include the payload and the interspersed header bits are then simultaneously transmitted on the multiple lanes for reception, error detection, and reassembly by a receiving computing node. | 2015-10-01 |
20150280747 | BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 64800 AND CODE RATE OF 5/15 AND 4096-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME - A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 5/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 4096-symbol mapping. | 2015-10-01 |
20150280748 | DOUBLE CONSECUTIVE ERROR CORRECTION - Double consecutive error correction is described. An integrated circuit with double consecutive error correction logic includes a data storage structure operative to store a set of data and a first error correction code that corresponds to the set of data. The set of data includes multiple data bits. The first error correction code was generated using a generator matrix having multiple bit groups, each bit group including a unique set of bit positions. The integrated circuit also includes an error correction code generator operative to generate, using the generator matrix, a second error correction code that corresponds to the set of data. The integrated circuit further includes a comparator operative to generate a comparison result of the first error correction code and the second error correction code. The integrated circuit includes a data corrector operative to correct two consecutive data bits of the set of data. | 2015-10-01 |
20150280749 | BOOT MANAGEMENT IN A NON-VOLATILE MEMORY SYSTEM - According to one configuration, computer processor hardware retrieves boot data stored in the non-volatile memory system. The boot data includes executable boot code and corresponding error correction information. The computer processor hardware applies first error correction decoding to the retrieved boot data. In response to detecting an inability to decode the retrieved boot data via application of the first error correction decoding, the computer processor hardware applies second error correction decoding to the retrieved boot data to configure the computer processor hardware. | 2015-10-01 |
20150280750 | DEVICE FOR ENCODING AND DECODING USING SMALLER BLOCK OF SYMBOLS - A method of encoding user data into codevectors of an error correcting code, includes generating a first block of data symbols including user data symbols and dummy data symbols; encoding the first block using an ECC encoder to obtain a codeword comprising the first block of data symbols and a second block of parity symbols; and generating a codevector by selecting a user data portion of the user data symbols from the first block and a parity portion of the parity symbols from the second block. The sum of a number of the user data portion and a number of the parity portion is smaller than the sum of a number of the user data symbols and a number of the parity symbols of the second block. | 2015-10-01 |
20150280751 | JOINT SOURCE-CHANNEL ENCODING AND DECODING FOR COMPRESSED AND UNCOMPRESSED DATA - A memory controller includes a joint source-channel encoder circuit and a joint source-channel decoder circuit. The joint source-channel encoder circuit source encodes received data independent of whether the received data is compressible data, performs error correction coding on the source encoded data, and stores the source encoded data in a memory device. The joint source-channel decoder circuit performs source decoding of the data read from the memory device between iterations of error correction coding of the read data, and outputs the read data to at least one of a buffer memory and a storage device interface. The joint source-channel decoder circuit performs the source decoding of the read data independent of whether the read data is compressed data. | 2015-10-01 |
20150280752 | PSEUDO TRUE TIME DELAY FOR MULTI-ANTENNA SYSTEMS - A linear transform can be performed using a passive analog multi-stage charge re-use linear transform circuit. The passive analog multi-stage charge re-use linear transform circuit transforms an input analog circuit to generate a transformed analog output signal. The passive analog multi-stage charge re-use linear transform circuit may be included in a software defined radio (SDR), where the transformed analog output signal may be output to an analog-to-digital converter (ADC) of the SDR device so as to enable the ADC to perform wideband spectrum sensing. The passive analog multi-stage charge re-use linear transform circuit may also be included in a beamforming device so as to enable the device to perform spectral shifting and spatial shifting of signals. This passive analog multi-stage charge re-use linear transform circuit may promote reduced power consumption in comparison to other circuits while also supporting wideband applications at high sampling rates. | 2015-10-01 |
20150280753 | SWITCHED MULTIPLEXER - This invention is about the switched multiplexers used for adaptive filtering in systems operating in signal dense environments such as electronic warfare systems. The aim of this invention is to design a switched multiplexer with lower input/output return losses and having lower level of destructive interaction between channels compared to the known examples. | 2015-10-01 |
20150280754 | PROCESS VARIABLE TRANSMITTER WITH REMOVABLE TERMINAL BLOCK - A process variable transmitter includes a sensor terminal block having a plurality of sensor line connectors to connect to sensor lines from at least one process variable sensor. The sensor terminal block defines a reception area that in a first instance accepts a removable standard power terminal block and in a second instance accepts a removable transient power terminal block. One of the removable standard power terminal block and the removable transient power terminal block is inserted in the reception area of the sensor terminal block. | 2015-10-01 |
20150280755 | Systems and Methods for Reducing Signal Distortion in Wireless Communication - System and methods are provided for reducing signal distortion in wireless communication. An example system includes: an up-converter configured to generate a radio frequency signal based at least in part on a baseband signal for wireless communication and an oscillation signal; an amplifier configured to amplify the radio frequency signal and generate a transmission signal, the transmission signal including a first counter-intermodulation component associated with the up-converter and a second counter-intermodulation associated with the amplifier; and a signal generator configured to output a distortion-cancellation signal to the up-converter to reduce signal distortion associated with the first counter-intermodulation component and the second counter-intermodulation component. | 2015-10-01 |
20150280756 | WIRELESS DEVICE AND WIRELESS ACCESS SYSTEM - A wireless device includes a digital-to-analog converter that converts a digital transmission signal within a digital signal processing band to an analog transmission signal, a modulator that performs quadrature modulation of an analog transmission signal obtained by the digital-to-analog converter using a first local signal having a first frequency outside a frequency range, the frequency range centered around a center frequency of a transmission signal and having a bandwidth of the digital signal processing band, and outputs a modulated signal, a frequency converter that performs a frequency shift of a modulated signal output from the modulator using a second local signal having a second frequency within the frequency range, and an inhibitor that performs carrier leakage inhibition processing on the digital transmission signal, based on a signal obtained by the frequency converter. | 2015-10-01 |
20150280757 | MULTICARRIER DYNAMIC PREDISTORTION FOR DIGITAL TRANSMISSION - An approach for predistorting signals to be transmitted via a multicarrier satellite transponder to account for inter-symbol interference. Multiple source signals are received. A transmit filter model is applied to each source signal to generate a respective filtered signal. Each filtered signal is translated to a carrier frequency, and the translated signals are summed to generate a composite signal. A common non-linearity model is applied to the composite signal to generate a model transmit signal. The transmit signal is translated to generate a receive signal estimate for each of the filtered signals. A receive filter model is applied to each receive estimate to generate a filtered estimate. Each filtered estimate is subtracted from the respective source signal to generate an error sequence. A fraction of the error sequence is added to the respective source signal to generate a predistorted signal for transmission via a multicarrier satellite transponder. | 2015-10-01 |
20150280758 | RECONFIGURABLE MULTI-CHANNEL UWB RECEIVER - A pulsed multi-channel UWB receiver. The receiver includes a first stage translating a received signal into baseband or at an intermediate frequency, a second stage carrying out quadrature mixing on the in-phase and quadrature channels of the first stage, a third stage carrying out an integration on a time window of the signals from the second stage, and a fourth stage carrying out a combination of the integration results from the third stage to provide the real part and the imaginary part of the modulation symbol. The receiver is configurable according to the receiving channel and processing type selected. | 2015-10-01 |
20150280759 | ENHANCED RECEIVE SENSITIVITY FOR CONCURRENT COMMUNICATIONS - A system using multiple communication technologies for concurrent communication is disclosed. The system includes a loopback receiver, a receiver, and a noise remover component. The loopback receiver is configured to obtain a coupled signal and generate a noise signal from the coupled signal. The noise signal includes direct transmission noise. The receiver is configured to receive a chain receive signal and to provide a receive signal therefrom. The noise remover component is configured to generate a wanted receive signal from the noise signal and the receive signal. | 2015-10-01 |
20150280760 | METHOD AND DEVICE FOR CANCELLING A NARROW BAND INTERFERENCE IN A SINGLE CARRIER SIGNAL AND COMPUTER PROGRAM - The present invention concerns a method for cancelling a narrow band interference in a single carrier signal, characterized in that the method comprises the steps executed by a receiver of:
| 2015-10-01 |
20150280761 | MULTI-LANE SERIAL LINK SIGNAL RECEIVING SYSTEM - A multi-lane serial link signal receiving system includes a clock generating circuit and a plurality of data receiving channels. The clock generating circuit provides a fundamental clock signal. Each of the data receiving channels receives an input signal and the fundamental clock signal, and includes a phase detecting circuit, a multi-order digital clock data recovery circuit and a phase adjusting circuit. The phase detecting circuit samples the input signal according to a sampling clock signal to generate a sampled signal. The multi-order digital clock data recovery circuit performs a digital clock data recovery process on the sampled signal to generate phase adjusting information. The phase adjusting circuit adjusts the phase of the fundamental clock signal according to the phase adjusting information to generate the sampling clock signal. | 2015-10-01 |
20150280762 | Phase Correction Apparatus and Method - A method for differential buffer phase correction comprises generating a pair of differential signals from a local oscillator, applying one of the signals to a first inverter and the other signal to a second inverter of a buffer through a differential pair of lines, applying a first positive feedback signal to the first inverter through a first feedback capacitor, wherein the first positive feedback signal is generated from an output of the second inverter and applying a second positive feedback signal to the second inverter through a second feedback capacitor, wherein the second positive feedback signal is generated from an output of the first inverter. | 2015-10-01 |
20150280763 | MOBILE TERMINAL - Disclosed is a mobile terminal having a differentiated structure from the conventional one. The mobile terminal includes a neck band unit configured to be wearable on a user's neck, and having a main power supply unit; and a glass unit having a frame configured to be wearable on a user's head, having an input/output module installed at the frame, and electrically-connectable to the neck band unit so as to be provided with power from the main power supply unit, wherein the neck band unit is provided with accommodation recesses formed such that at least part thereof corresponds to the frame, and wherein the glass unit is coupled to the neck band unit when two ends thereof are inserted into the accommodation recesses, respectively, and wherein the glass unit is separated from the neck band unit when the two ends thereof are withdrawn from the accommodation recesses, respectively. | 2015-10-01 |
20150280764 | Lanyard - Various embodiments relate generally to a mobile device (e.g., cellular phone) case and neck lanyard (with integrated headphones and microphone) allowing hands-free use of the mobile device. An embodiment magnetically couples the case to the lanyard. Other embodiments are described herein. | 2015-10-01 |
20150280765 | COMMUNICATION DEVICE MANAGEMENT - The present invention relates to a mobile communications network node comprising package switched communication ability, the network comprising: one or several mobile stations or devices, one or several service providers providing communication with said mobile stations, wherein the mobile communication netwok node comprises means arranged to provide a mobile station with instructions, which is arranged to communicate with an agent comprising a programmable control unit in the mobile station to provide instructions for the configuratin and management of the mobile station. | 2015-10-01 |
20150280766 | SIM CARD CONNECTOR AND MOBILE TERMINAL - An SIM card connector and a mobile terminal are disclosed. The SIM card connector comprises a card holder as well as a power supply terminal, a first terminal and a second terminal disposed within the card holder. When the SIM card is plugged, the power supply terminal connects with a power supply contact of the SIM card earlier than the first terminal, and the first terminal connects with the power supply contact earlier than the second terminal. The mobile terminal comprises an interruption detection module, a power supply management module and an SIM card connector. The power supply management module is configured to stop supplying power to the power supply terminal when it is determined that a signal, received by the power supply management module changes from a second control signal into a first control signal. | 2015-10-01 |
20150280767 | LASER WELDING OF TRANSPARENT AND OPAQUE MATERIALS - Welding of transparent material in electronic devices. An electronic device may include an enclosure having at least one aperture formed through a portion of the enclosure. The electronic device may also include a component positioned within the aperture formed through the portion of the enclosure. The component may be laser welded to the aperture formed through the enclosure. Additionally, the component may include transparent material. A method for securing a component within an electronic device may include providing an electronic device enclosure including at least one aperture, and positioning a component within the aperture formed through the enclosure. The component positioned within the aperture may include a transparent material. The method may also include welding the component to the electronic device enclosure. | 2015-10-01 |
20150280768 | PROTECTIVE COVER FOR A TABLET - A protective cover for a tablet includes a foldable board, a base board, a wireless communication module, and a first input device. A foldable board comprising a first segment, and a second segment connected to the one side of the first segment and foldable with respect to the first segment, and the foldable board defining limiting members on edges of the interior surface of the foldable board; a base board connected to an opposite side of the first segment and foldable with respect to the first segment; a first input device mounted on the base board to be connected to the tablet by means of the wireless communication module; wherein the first segment and the second segment are foldable with respective to each other to form a triangular support structure supported by the holder lobe. | 2015-10-01 |
20150280769 | CASE FOR A MOBILE COMMUNICATIONS DEVICE - The present invention relates to a case for releasably securing a mobile communications device in a sealed environment. The case is adapted to enable the device to operate with mobile, wireless, cellular and satellite communications. | 2015-10-01 |
20150280770 | ELECTRONIC DEVICE AND METHOD OF TRANSMITTING DATA BETWEEN ELECTRONIC DEVICE AND FLIP COVER THEREOF - An electronic device includes a flip cover connected thereto. The electronic device includes a first display. The flip cover includes: a first surface that includes a second display; a second surface that is opposite to the first display and includes at least one light receiving unit; and a second control unit that controls the flip cover to receive light emitted from the first display through the light receiving unit, to covert the received light to an electrical signal, and to display information on the second display on the basis of the converted electrical signal. | 2015-10-01 |
20150280771 | TUNABLE ANTENNA SYSTEMS - An electronic device has wireless communications circuitry including an adjustable antenna system coupled to a radio-frequency transceiver. The adjustable antenna system may include one or more adjustable electrical components that are controlled by storage and processing circuitry in the electronic device. The adjustable electrical components may include switches and components that can be adjusted between numerous different states. The adjustable electrical components may be coupled between antenna system components such as transmission line elements, matching network elements, antenna elements and antenna feeds. By adjusting the adjustable electrical components, the storage and processing circuitry can tune the adjustable antenna system to ensure that the adjustable antenna system covers communications bands of interest. | 2015-10-01 |
20150280772 | TRANSCEIVER WITH ASYMMETRIC MATCHING NETWORK - A system on a chip (SoC) includes a transceiver comprising a transmitter and a receiver, wherein at least one of the transmitter and receiver has a configurable portion that can be configured to operate in a single ended mode and in a differential mode. Two interface pins are provided for coupling the transceiver to an antenna via a matching network, wherein the two interface pins are shareably coupled to the transmitter and to the receiver. A tunable capacitor is coupled to differential signal lines of the configurable portion, wherein the tunable capacitor is configured to be tuned to optimize impedance matching of the configurable portion for each mode of operation. | 2015-10-01 |
20150280773 | ANTENNA DISTRIBUTION CONTROLLER - An antenna distribution controller including a plurality of antenna connectors, at least one device connector, an antenna switching circuit and a controller is provided. The antenna connector is configured to connect an external antenna. The device connector is configured to connect an external wireless communication device. The antenna switching circuit has a plurality of antenna ports and at least one device port. These antenna ports are coupled to one of the antenna connectors, respectively. The device port is coupled to the device connector. The controller is coupled to a control terminal of the antenna switching circuit for controlling an electrical connection relationship between the antenna ports and the device port. | 2015-10-01 |
20150280774 | SWITCHING MODULE AND WIRELESS COMMUNICATION EQUIPMENT - A switching module includes a common terminal, individual terminals connected to respective corresponding signal paths, and a switch portion that selectively switches and connects the common terminal to one of the individual terminals. The switch portion includes first switches and at least one second switch, each first switch being connected to the common terminal at one end portion within the switch, the at least one second switch being connected to the common terminal at one end portion via a connection wiring electrode provided on a wiring board. This does not allow directional connection between the one end portion of the second switch and the common terminal within the switch. Thus, mutual interference between a communication signal transmitted through the first switch and a communication signal transmitted through the second switch is prevented. | 2015-10-01 |
20150280775 | METHOD AND SYSTEM FOR BLIND INTERFERENCE CANCELLATION IN A WIRELESS COMMUNICATION SYSTEMS - Aspects of the present invention include methods, systems, and computer-readable medium for canceling interference in wireless communication. The method includes receiving wireless CDMA communication signals using one or more antennas at least from a first entity via a first communication channel and a second entity via a second communication channel, determining a set of known characteristics associated with the first entity, the first set of characteristics comprising a first signal strength, a first synchronization information, and an first channel identification information, and determining an aggregate signal matrix based on signals received from at least the first entity and the second entity. The method further includes determining a covariance matrix associated with the aggregate signal value, determining a reference signal matrix based on the set of known characteristics, calculating an interference matrix by subtracting the reference signal matrix from the covariance matrix, and removing the interference estimation from the communication signals. | 2015-10-01 |
20150280776 | METHOD FOR ESTABLISHING RADIOFREQUENCY LINKS - A method for establishing radiofrequency links by satellite also making it possible to assure the return link transmission of hyperfrequency radioelectrical signals in an efficient manner in terms of performances, easily adaptable to a pre-existing broadcasting system, using the same forward link and return link frequency band, enabling the use of two independent terrestrial stations for the two channels, and enabling operation of the amplification chain of the transponder of the satellite at saturation or close to saturation. | 2015-10-01 |
20150280777 | METHODS AND ARRANGEMENTS FOR VERY LARGE BANDWIDTH OPERATIONS - Logic may determine a first frame comprising a hopping pattern value and a target hopping time (THT). The hopping pattern may indicate a pattern of channels to which to hop. Logic may determine a clear-to-send (CTS) frame comprising a duration value indicative of a duration of a data transmission. Logic may transmit the first frame on at least a primary channel of the channels. Logic may transmit the CTS frame prior to transmitting the data transmission on the one or more channels in accordance with the hopping pattern, each channel having a bandwidth of at least 450 megahertz and being within in a 6 gigahertz to 10 gigahertz frequency band. Logic may receive a frame on at least a primary channel of the channels. Logic may receive CTS frames at the THT in accordance with the hopping pattern. | 2015-10-01 |
20150280778 | DIFFERENTIAL INTERCONNECT WITH STUB TRACES - This disclosure relates generally to an electronic assembly and method having a first electrical connection point and a second electrical connection point and a differential interconnect coupling the first electrical connection point to the second electrical connection point, the differential interconnect including first and second transmission traces including a interior edges and a exterior edges opposite the interior edges, the second interior edge facing the first interior edge, and stub traces, each stub trace coupled to one of the first and second transmission traces and projecting from one of the first interior edge, the first exterior edge, the second interior edge, and the second exterior edge. A substantially equal number of stub traces project from the first exterior edge and the second exterior edge. At least twice as many stub traces project from the first and second exterior edges as project from the first and second interior edges. | 2015-10-01 |
20150280779 | METHOD AND APPARATUS TO IMPROVE THE LINEARITY OF THE TIME DOMAIN TRACE DERIVED FROM A SINGLE ENDED LINE TEST - The present invention is related to improvements to SELT testing, and more particularly to methods and apparatuses for reducing the effects of distortions of the reflected signal without sacrificing the integrity of the original signal. In embodiments, a method according to the invention consists of first modifying the transmit sequence to utilize and better “excite” the low frequency tones. In embodiments, the method includes compensating for transformer roll-off at low frequencies. In other embodiments, the method includes filling gaps in the received frequency domain S11 sequence with a predicted, or estimated, version of the S11 signal. | 2015-10-01 |
20150280780 | Analysis of Captured Random Data Signals to Measure Linear and Nonlinear Distortions - A method to capture random data signals at an end point in a broadband network and process them via digital signal processing (DSP) techniques to determine both linear distortions and nonlinear distortions. In a distribution network, such as a tree and branch cable network, the location of the impairment addition can be identified by determining location of terminals have a distortion and locations of terminals that do not have a distortion. Linear distortions may be determined by an autocorrelation of the captured signal with itself. Nonlinear distortions may be determined by processing measured energy in a vacant band with manufactured energy in the vacant band. If a vacant band is not available, one can be created by demodulating a signal occupying the band, and subtracting the demodulated signal from the measured signal plus interference in a band, leaving only the interference. | 2015-10-01 |
20150280781 | INTERFERENCE TESTING - In one example a controller comprises logic, at least partially including hardware logic, configured to implement a first iteration of an interference test on a communication interconnect comprising a victim lane and a first aggressor lane by generating a first set of pseudo-random patterns on the victim lane and the aggressor lane using a first seed and implement a second iteration of an interference test by advancing the seed on the first aggressor lane. Other examples may be described. | 2015-10-01 |
20150280782 | METHOD AND DEVICE FOR TRANSMITTING DATA VIA A LOAD LINE AND LIGHTING SYSTEM - A data transmission from a control device ( | 2015-10-01 |
20150280783 | BUS COMMUNICATION DEVICE - A bus communication device ( | 2015-10-01 |
20150280784 | METHOD AND APPARATUS FOR THREE-PHASE POWER LINE COMMUNICATIONS - Method and apparatus for generating a balanced three-phase power line communication signal. In one embodiment, the method comprises generating a plurality of modulation signals based on at least one data stream; modulating a plurality of carrier signals by the plurality of modulation signals to generate a balanced three-phase PLC signal comprising a first phase signal, a second phase signal, and a third phase signal; and coupling the balanced three-phase PLC signal to a three-phase power line. | 2015-10-01 |
20150280785 | SYSTEMS AND DEVICES WITH COMMON MODE NOISE SUPPRESSION STRUCTURES AND METHODS - An embodiment of a transformer-based system or galvanic isolation device includes a first coil, a second coil aligned with the first coil across a gap, and a first capacitor coupled between the first coil and a first voltage reference. A first electrode of the first capacitor may be formed from a conductive electrode structure that is electrically isolated from the first coil, and a second electrode of the first capacitor may be formed from at least a portion of the first coil. The system or device also may include a second capacitor coupled between the second coil and a second voltage reference. The first and second coils may form portions of first and second IC die, respectively, and the system or device may also include one or more dielectric components within the gap between the IC die, where the dielectric component(s) are positioned directly between the first and second coils. | 2015-10-01 |
20150280786 | NEAR FIELD COMMUNICATION BASED DATA TRANSFER - A near field communication (NFC) tag is programmed to execute a NFC tag based data transfer. The NFC tag may receive a device-tap from an NFC enabled device. Upon receiving the device-tap, the NFC tag initiates a communication with an associated server. The NFC tag authenticates the NFC enabled device with the associated server, and determines notifications available at the server. The NFC tag fetches a plurality of notifications corresponding to the authenticated NFC enabled device from the server and forwards the notifications to the NFC enabled device. | 2015-10-01 |
20150280787 | NFC DEVICE COMPRISING CONFIGURABLE NOTIFICATION MEANS - The present invention relates to a near field communication device configured to establish a near field communication channel with an external device, and provide a first host processor with application data sent by the external device. The device is configured to provide a second host processor with notifications relating to the nature or content of application data provided to the first host processor, and configure the notifications according to a characteristic parameter of an application in the framework of which the external device sends data to the first host processor. | 2015-10-01 |
20150280788 | ELECTRONIC NOTIFICATION DISPLAY APPARATUS AND METHOD - A notification display apparatus and method is provided, which may display a notification indicating a person's absence, location, or contact information. The notification display apparatus includes a near field communicator; an electronic paper display; and a controller that controls authentication of a mobile terminal of a user through the near field communicator, and receiving of a notification from the authenticated mobile terminal to display the received notification on the electronic paper display. A user may easily change a notification displayed on the notification display apparatus, and may display unique and various types of information. | 2015-10-01 |
20150280789 | TECHNIQUES FOR COMMUNICATION WITH TAG DEVICES - Various embodiments are generally directed to techniques for resolving interference in near field communications (NFC) among multiple NFC tag devices communicating with a reading device in which one of the tag devices employs a Tag-Talks-First (TTF) protocol while the others use a Request-Response (RR) protocol. An apparatus to communicate with tag devices via near NFC includes a timing component to determine an amount of time remaining in a current sleep pause between two consecutive transmissions of a TTF tag device; and a communications component to determine whether the amount of time remaining in the current sleep pause is sufficient to transmit a request for response to a RR tag device and receive a response to the request from the RR tag device, and to transmit the request based on the amount of time remaining in the current sleep pause. Other embodiments are described and claimed. | 2015-10-01 |
20150280790 | CONTROL APPARATUS, POWER TRANSMISSION APPARATUS, POWER RECEPTION APPARATUS, AND CONTROL METHOD - According to an embodiment, a control apparatus includes a controller and an estimator. The controller commands a frequency-variable signal source to perform a first frequency sweep on an input signal to a second resonator coupling with the first resonator under the first impedance condition. The frequency-variable signal source generates the input signal. The controller commands the frequency-variable signal source to perform a second frequency sweep on the input signal under the second impedance condition. The estimator detects at least one first specific frequency that provides the input signal with a maximal value or a minimal value during a period when the first frequency sweep is performed. The estimator detects at least one second specific frequency that provides the input signal with a maximal value or a minimal value during a period when the second frequency sweep is performed. The estimator estimates, based on the first specific frequency and the second specific frequency, at least one of a coupling coefficient for coupling between the first resonator and the second resonator, a first resonant frequency of the first resonator, and a second resonant frequency of the second resonator. | 2015-10-01 |
20150280791 | POWER RECEIVING DEVICE, AND INFORMATION PROCESSING METHOD - A power receiving device that receives power from a power supply device, according to a predetermined wireless power supply scheme for transmitting a control signal through wireless communication, includes a communication circuitry for a terminal, configured to perform communication with a terminal including a power supply to which power received by the power receiving device is supplied, a reception circuitry configured to receive a predetermined control signal from the power supply device, a memory, and a processor coupled to the memory, configured to perform power control and a setting of an operation mode of the terminal, based on the predetermined control signal, through the communication circuitry for a terminal. | 2015-10-01 |