40th week of 2009 patent applcation highlights part 38 |
Patent application number | Title | Published |
20090244937 | DC BUS VOLTAGE HARMONICS REDUCTION - In one aspect, in general, the invention features a control system configured for use with a three-phase PWM converter. The control system receives an input signal from a three-phase power supply and provides an output signal at a DC link. A voltage-separating module generates on the basis of the input signal a positive sequence voltage component and a negative sequence voltage component in a rotating reference frame. A reference current computation module uses at least the positive sequence voltage component and the negative sequence voltage component to compute a first reference current and a second reference current. A current regulating module uses at least the first reference current and the second reference current to generate a command signal. The command signal is provided to a driving circuit of the three-phase PWM converter for generating a regulated DC bus voltage at the DC link. | 2009-10-01 |
20090244938 | Switching apparatus for grounding an inverter - A switching apparatus for grounding an inverter ( | 2009-10-01 |
20090244939 | Method and apparatus for resetting silicon controlled rectifiers in a hybrid bridge - A method and apparatus for resetting Silicon Controlled Rectifiers (SCRs) in an H-bridge. The apparatus comprises a hybrid bridge, comprising at least one SCR and at least one switch, and an abnormal current detector, coupled to the hybrid bridge. The abnormal current detector detects an abnormal current in the hybrid bridge and drives the at least one switch to control current flow through the hybrid bridge. | 2009-10-01 |
20090244940 | VOLTAGE GENERATING CIRCUIT - A voltage generating circuit is provided, including a voltage output terminal, a ground terminal, a capacitor, a selector, a first switch, and a second switch. The capacitor is connected between a pump signal and the output of the selector. The selector is controlled by a first control signal and used to select the voltage source or the voltage output terminal to connect the capacitor. The first switch is controlled by a second control signal, and the second switch is controlled by a third control signal. When the first switch is turn-on, the voltage output terminal is connected to the ground terminal. When the second switch is turn-on, the voltage output terminal is connected to the voltage source. | 2009-10-01 |
20090244941 | POWER SOURCE APPARATUS AND IMAGE FORMING APPARATUS - A transformer accepts an AC voltage from an AC power source, transforms the AC voltage, and supplies the transformed AC voltage to first rectifying circuits. Similarly, another transformer accepts an AC voltage from an AC power source, transforms the AC voltage, and supplies the transformed AC voltage to second rectifying circuits. The first rectifying circuits convert the accepted AC voltage into a positive DC voltage, and the second rectifying circuits convert the accepted AC voltage to a negative DC voltage. The positive DC voltage and the negative DC voltage then are superimposed and outputted to a secondary side of a transformer in the AC circuits. The AC voltage outputted from the transformers in the AC circuits and the DC voltage formed by superimposing the positive and negative DC voltages outputted from the first and second rectifying circuits are further superimposed, and supplied to each developing section. | 2009-10-01 |
20090244942 | Synchronous rectification control circuit - A synchronous rectification control circuit is connected with a secondary-side rectification circuit and includes a driving circuit, a dead-time acquisition circuit, and a zero-voltage detection circuit. The driving circuit includes a differentiating circuit, a first comparator, and a capacitor, wherein the differentiating circuit generates a signal to the first comparator and the capacitor functions to charge and discharge to form a cycle. The dead-time acquisition circuit includes a second comparator and a third comparator, wherein the second comparator has a positive input connected to an output of the first comparator of the driving circuit, the second comparator has an output connected to a positive input of the third comparator, and the third comparator has a negative input connected to the output of the first comparator to acquire a dead-time signal. The zero-voltage detection circuit includes a fourth comparator and a totem pole circuit, wherein the fourth comparator has a negative input connected to an input terminal of the driving circuit for detecting a potential present in the input terminal of the driving circuit and the fourth comparator has an output that is connected to the totem pole circuit to supply an output of a signal. With such an arrangement, shorting is prevented from occurring in the secondary-side rectification circuit. | 2009-10-01 |
20090244943 | Power Converter - A power converter includes a small-sized inductor connected to an AC voltage input line for power factor correction and a filter for suppressing conduction noise. The inductor is connected to a rectifier and comprises first and second windings and that are wound on a common magnetic core and loosely coupled with each other. A leakage inductance component of the inductor functions as an energy storage element in a main conversion operation and an excitation inductance component of the inductor functions as a noise reduction element for suppressing an conduction noise caused by on-off operation of a switching element. | 2009-10-01 |
20090244944 | POWER CONVERTER SYSTEM THAT OPERATES EFFICIENTLY OVER A RANGE OF LOAD CONDITIONS - A power converter system supplies power to one or more loads. The power converter system comprises at least one power converter operating at a desired efficiency; and a power storage system coupled to the at least one power converter for receiving power supplied from the at least one power converter and storing power therein when the at least one power converter operates at an efficiency that is below the desired efficiency. | 2009-10-01 |
20090244945 | POWER CONVERTING APPARATUS - In a power converting apparatus in which two three-phase converters ( | 2009-10-01 |
20090244946 | DC-AC CONVERTER - A DC-AC converter includes a signal generating module, a first switch, a first capacitor, a transformer, and a trigger signal generating module. The signal generating module generates a pulse width modulation (PWM) signal according to a trigger signal. The first switch has a control terminal receiving the PWM signal, and a first terminal and a second terminal coupled to a first terminal and a second terminal of the first capacitor respectively. The transformer has a primary winding coupled to the second terminal of the first switch, and a secondary winding coupled to a load. The transformer generates a driving signal to the load according to a signal variation of the primary winding. The trigger signal generating module compares a first signal outputted from the second terminal of the first switch with a phase delay signal thereof and thereby generates the trigger signal for controlling the frequency of the PWM signal. | 2009-10-01 |
20090244947 | Method and apparatus for resetting a silicon controlled rectifier bridge - A method and an apparatus for resetting at least one Silicon Controlled Rectifier (SCR) in an H-bridge. The apparatus comprises a current interruption device for controlling current flow through the H-bridge, and a negative voltage detector for detecting a negative voltage at the H-bridge and driving the current interruption device to control the current flow through the H-bridge. | 2009-10-01 |
20090244948 | EMBEDDED MEMORY APPARATUS WITH REDUCED POWER RING AREA - An embedded memory apparatus with reduced power ring area is disclosed. In order to save the area consumption of a chip, a scheme for removing the power rings originally disposed in a memory core, or another scheme for sharing the power rings with other adjacent memory cores is provided. According to the preferred embodiment of the routing, the power strips originally bridging the inner elements and the outer power serve as the power source (VDD) and ground (VSS) respectively since the peripheral power ring surrounded the core is removed. Thus the area consumption is reduced as if the surrounded power ring shrinks inwardly. The shared power ring for the adjacent memory cores can also be another aspect for reducing the area. | 2009-10-01 |
20090244949 | Memory Device and Method Providing Logic Connections for Data Transfer - In an embodiment, a method for transferring data in a memory device is provided. The method may include transferring data from a first memory cell arrangement including a plurality of memory cells to a second memory cell arrangement including a plurality of memory cells via a connecting circuit arrangement coupled to the plurality of memory cell arrangements and providing a plurality of controllable connections via a plurality of connecting circuit terminals, the memory cell arrangements being connected with at least one connecting circuit terminal of the plurality of connecting circuit terminals, wherein the connecting circuit is configured to provide arbitrarily controllable signal flow connections between the plurality of connecting circuit terminals. The data are transferred via a logic connection using the controllable connections. Simultaneously, a further logic connection may be provided to a memory cell arrangement of the memory cell arrangements using the controllable connections. | 2009-10-01 |
20090244950 | SEMICONDUCTOR MEMORY DEVICE HIGHLY INTEGRATED IN DIRECTION OF COLUMNS - First and second read word lines are provided in each set made of two adjacent rows. First, second, third, and fourth read bit lines are provided in each column. Each of the first and second read word lines is connected to memory cells in a corresponding one of the sets. Each of the first and third read bit lines is connected to a memory cell in one row in each of the sets, out of memory cells in a corresponding one of the columns. Each of the second and fourth read bit lines is connected to a memory cell in the other row in each of the sets, out of the memory cells in the corresponding one of the columns. | 2009-10-01 |
20090244951 | SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY SYSTEM - A semiconductor memory device includes a plurality of memory cell arrays each including a plurality of memory cells arranged in a matrix pattern, and a plurality of cell plate lines each being shared by the memory cell arrays, each of the cell plate lines corresponding to each of rows of the memory cells and each of the cell plate lines being connected to the memory cells of a corresponding one of the rows. Each of the memory cell arrays includes a plurality of word lines each of which corresponds to each of the rows of the memory cells in the memory cell array. The number of the memory cells connected to each of the cell plate lines is larger than the number of the memory cells connected to one of the word lines corresponding to the each of the cell plate lines. | 2009-10-01 |
20090244952 | ELECTRODE MASTER FOR FERROELECTRIC RECORDING AND METHOD FOR RECORDING ON FERROELECTRIC RECORDING MEDIUM - The present invention provides an electrode master for ferroelectric recording that records information on a ferroelectric recording medium in which the direction of polarization of a ferroelectric material has been unified in one direction by applying a voltage thereto, based on the direction of polarization of the ferroelectric material by applying voltage pulses to the ferroelectric recording medium, the electrode master including: an electroconductive base material; a plurality of electrode convexes provided on a surface of the electroconductive base material so as to correspond to information to be recorded on the ferroelectric recording medium; and an electrode terminal conducted to each of the electrode convexes and provided on the electroconductive base material. | 2009-10-01 |
20090244953 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device comprises a memory cell array including first and second mutually crossing lines and electrically erasable programmable memory cells arranged at intersections of the first and second lines, each memory cell containing a variable resistive element; a data write circuit operative to apply a voltage required for data write to the memory cell via the first and second lines; and a current limit circuit operative to limit the value of current flowing in the memory cell on the data write at a certain current limit value. | 2009-10-01 |
20090244954 | STRUCTURE AND METHOD FOR IMPROVING STORAGE LATCH SUSCEPTIBILITY TO SINGLE EVENT UPSETS - A digital logic storage structure includes cross coupled first and second complementary metal oxide semiconductor (CMOS) inverters formed on a semiconductor substrate, the CMOS inverters including a first storage node and a second storage node that is the logical complement of the first storage node; both of the first and second storage nodes each selectively coupled to a deep trench capacitor through a switching transistor, with the switching transistors controlled by a common capacitance switch line coupled to gate conductors thereof; wherein, in a first mode of operation, the switching transistors are rendered nonconductive so as to isolate the deep trench capacitors from the inverter storage nodes and, in a second mode of operation, the switching transistors are rendered conductive so as to couple the deep trench capacitors to their respective storage nodes, thereby providing increased resistance of the storage nodes to single event upsets (SEUs). | 2009-10-01 |
20090244955 | SEMICONDUCTOR STORAGE DEVICE - This invention provides static random access memory (SRAM). The SRAM has a plurality of memory cells arranged in row and column directions. The plurality of memory cells each have a latch circuit in which input and output terminals of a pair of inverters are cross-connected and which maintains complementary levels at a pair of storage nodes, and a pair of write transistors provided between the pair of storage nodes and a prescribed power supply voltage. Further, the gate potentials of the pair of write transistors are respectively controlled according to a row address, a column address, and write data. | 2009-10-01 |
20090244956 | Semiconductor memory device - In a memory cell, a margin for data preservation is provided while suppressing a current consumption associated with a low-power consumption mode. A MOS transistor has the same structure as NMOS transistors included in each of memory cells. When a low-power consumption mode is designated, a voltage developed at a node is stabilized by subtracting a margin voltage for data preservation across a first resistor from a voltage applied to a first node and by subtracting a threshold voltage of the MOS transistor from the resultant voltage is applied to a second node. | 2009-10-01 |
20090244957 | MULTILEVEL MAGNETIC STORAGE DEVICE - The present invention includes a memory configured to store data having a pinned layer and a plurality of stacked memory locations. Each memory location includes a nonmagnetic layer and a switchable magnetic layer. The plurality of stacked memory locations are capable of storing a plurality of data bits. | 2009-10-01 |
20090244958 | HYBRID SUPERCONDUCTING-MAGNETIC MEMORY CELL AND ARRAY - In one embodiment, the invention is a hybrid superconducting-magnetic memory cell and array. One embodiment of a memory cell includes a magnetoresistive element and at least one superconducting element wired in parallel with the magnetoresistive element. In a further embodiment, memory cells of the disclosed configuration are arranged to form a memory array. | 2009-10-01 |
20090244959 | THIN FILM MAGNETIC MEMORY DEVICE WRITING DATA WITH BIDIRECTIONAL CURRENT - An end of a selected bit line in a selected column is electrically coupled to an end of a corresponding current return line by one of first and second write column select gates, which are selectively turned on in response to results of column selection. A data write circuit sets the other end of the selected bit line and the other end of the current return line to one and the other of a power supply voltage and a ground voltage in accordance with a level of write data via one of first and second data buses and an inverted data bus, respectively. | 2009-10-01 |
20090244960 | MAGNETORESISTIVE EFFECT ELEMENT AND MAGNETIC MEMORY - It is made possible to provide a highly reliable magnetoresistive effect element and a magnetic memory that operate with low power consumption and current writing and without element destruction. The magnetoresistive effect element includes a first magnetization pinned layer comprising at least one magnetic layer and in which a magnetization direction is pinned, a magnetization free layer in which a magnetization direction is changeable, a tunnel barrier layer provided between the first magnetization pinned layer and the magnetization free layer, a non-magnetic metal layer provided on a first region in an opposite surface of the magnetization free layer from the tunnel barrier layer, a dielectric layer provided on a second region other than the first region in the opposite surface of the magnetization free layer from the tunnel barrier layer; and a second magnetization pinned layer provided to cover opposite surfaces of the non-magnetic metal layer and the dielectric layer from the magnetization free layer. | 2009-10-01 |
20090244961 | PHASE CHANGE MEMORY - The present disclosure includes devices and methods for operating phase change memory cells. One or more embodiments include applying a programming signal to a phase change material of a memory cell, and decreasing a magnitude of a trailing portion of the applied programming signal successively according to a number of particular decrements. The magnitude and the duration of the number of particular decrements correspond to particular programmed values. | 2009-10-01 |
20090244962 | Immunity of phase change material to disturb in the amorphous phase - Disturb from the reset to the set state may be reduced by creating an amorphous phase that is substantially free of crystal nuclei when programming the reset state in a phase change memory. In some embodiments, this can be achieved by using a current or a voltage to program that exceeds the threshold voltage of the phase change memory element, but does not exceed a safe current voltage which would cause a disturb. | 2009-10-01 |
20090244963 | Programming multilevel cell phase change memories - A multilevel phase change memory cell may have a plurality of intermediate levels between a set and a reset or a crystalline and amorphous states. These intermediate levels between set and reset may be differentiated not only by programming current, but also by different programming pulse widths. As a result, the intermediate states may be positioned, on the programming current versus programming pulse width curve, in regions of common resistance with a relatively large range of programming current. | 2009-10-01 |
20090244964 | Reducing temporal changes in phase change memories - A phase change memory in the reset state may be heated to reduce or eliminate electrical drift. | 2009-10-01 |
20090244965 | MULTI-LAYER MAGNETIC RANDOM ACCESS MEMORY USING SPIN-TORQUE MAGNETIC TUNNEL JUNCTIONS AND METHOD FOR WRITE STATE OF THE MULTI-LAYER MAGNETIC RANDOM ACCESS MEMORY - A stacked magnetic tunnel junction (MTJ) structure of a multi-layer magnetic random access memory (MRAM) which includes a plurality of stacked MTJ devices serially connected to each other and an access transistor shared between the stacked MTJ devices. The stacked MTJ structure further includes a write word line through which a write current flows. The write current generates a hard axis magnetic field used to selectively write an MTJ device of the stacked MTJ devices. | 2009-10-01 |
20090244966 | Threshold Evaluation Of EPROM Cells - Evaluating an embedded EPROM in a host IC device involves using program circuitry to program/unprogram all of the floating-gate cells of the embedded EPROM, then simultaneously transmitting a predetermined test bias voltage to all of the programmed/unprogrammed floating-gate cells, and then evaluating the output terminals of all of the floating-gate cells using a logic (e.g., wired NOR or NAND) circuit, whereby successful operation of all of the embedded EPROM cells causes the wired logic circuit to generate a single positive test result signal, and the failure of one or more of the embedded EPROM cells causes the wired logic circuit to generate a single negative test signal. A reference cell is also evaluated using a bias testing circuit to determine that the reference voltage supplied during normal operation is at an acceptable voltage level. | 2009-10-01 |
20090244967 | FLASH MEMORY DEVICE HAVING DUMMY CELLS AND METHOD OF OPERATING THE SAME - Disclosed is a flash memory device having multiple strings, where each string includes first memory cells and second memory cells. One second memory cell of the second memory cells in each string is set to a programmed state, and remaining second memory cells are set to an erased state. | 2009-10-01 |
20090244968 | SEMICONDUCTOR MEMORY DEVICE INCLUDING MEMORY CELL HAVING CHARGE ACCUMULATION LAYER AND CONTROL GATE - A semiconductor memory device includes a select transistor, a memory cell transistor, a select gate line, a word line, and a row decoder. The memory cell transistor includes a charge accumulation layer and a control gate, and a current path one end of which is connected to a current path in the select transistor. The select gate line and word line are connected to a gate and the control gate of the select transistor and memory cell transistor. The row decoder includes a transfer circuit which transfers a voltage to the select gate line and includes a first switch including a first MOS transistor of a depression type. The first MOS transistor includes a current path one end of which is connected to the select gate line, and transfers a first voltage provided to the other end of the current path to the select gate line. | 2009-10-01 |
20090244969 | SEMICONDUCTOR MEMORY DEVICE COMPRISING MEMORY CELL HAVING CHARGE ACCUMULATION LAYER AND CONTROL GATE AND METHOD OF ERASING DATA THEREOF - A semiconductor memory device includes a memory cell, a bit line, a source line, and a sense amplifier. The memory cell has a stacked gate including a charge accumulation layer and a control gate. The bit line is electrically connected to a drain of the memory cell. The source line is electrically connected to a source of the memory cell. The sense amplifier, during erase verification to determine whether or not a threshold voltage of the memory cell in an erased state is at a threshold level, reads the data from the memory cell and senses the data with a first voltage applied to the control gate of the memory cell, with a positive second voltage higher than the first voltage applied to the semiconductor substrate and the source line, and with a third voltage higher than the second voltage applied to the bit line. | 2009-10-01 |
20090244970 | RANDOM ACCESS MEMORY WITH CMOS-COMPATIBLE NONVOLATILE STORAGE ELEMENT AND PARALLEL STORAGE CAPACITOR - Systems, methods, and memory device with row lines and column lines arranged in a matrix configuration with a memory cell coupled to one of the column lines and one of the row lines. The memory cell includes a storage capacitor with a first plate coupled to a storage node, a CMOS-compatible non-volatile storage element having a node coupled to the storage node and configured to hold a charge corresponding to a binary value, and an access transistor coupled to the storage node. The access transistor includes a word line gate, a first node, and a second node, the word line gate being coupled to the one of the plurality of row lines, the first node being coupled to the one of the plurality of column lines, the second node being coupled to the storage node and to said node of the CMOS-compatible non-volatile storage element. | 2009-10-01 |
20090244971 | Memory cell structure, a memory device employing such a memory cell structure, and an integrated circuit having such a memory device - A memory cell structure for a memory device is provided, the memory cell structure comprising a read transistor having a floating gate node, a tunnelling capacitor, and a coupling capacitor stack. The tunnelling capacitor is connected to the floating gate node and has a first programming terminal, whilst the coupling capacitor stack is connected to the floating gate node and has a second programming terminal. The coupling capacitor stack comprises at least two coupling capacitors arranged in series between the floating gate node and the second programming terminal, with the coupling capacitor stack having a larger capacitance than the tunnelling capacitor. During a programming operation, a voltage difference is established between the first programming terminal and the second programming terminal to cause charge tunnelling to occur through the tunnelling capacitor, such that after the programming operation a charge is stored in the floating gate node. During a read operation, the read transistor is activated to produce an output signal indicative of the charge stored in the floating gate node. Such a memory cell structure is efficient in terms of area, and can be manufactured using standard CMOS logic manufacturing processes, thereby avoiding some of the complexities involved in the production of more conventional EEPROM and Flash memory devices. | 2009-10-01 |
20090244972 | Nonvolatile Semiconductor Memory Device and Usage Method Thereof - A nonvolatile semiconductor memory device comprises a first PMOS transistor and a second PMOS transistor having a gate, the first and the second PMOS transistors being connected in series; and a first NMOS transistor and a second NMOS transistor having a gate, the first and the second NMOS transistors being connected in series; wherein the gate of the second PMOS transistor and the gate of the second NMOS transistor are commonly connected and floated. | 2009-10-01 |
20090244973 | Memory Read-Out - A memory system having a plurality of memory cells for storing payload data and redundancy data. The memory system having a read-out circuit configured to read-out a status of the plurality of memory cells, the read-out status having payload data, redundancy data and associated reliability information. Moreover, the memory system has a data processor configured to derive the payload data from the read-out status using the reliability information. | 2009-10-01 |
20090244974 | MEMORY SYSTEM AND DATA WRITING METHOD - A data writing method is disclosed. In a memory system comprising a NAND flash memory and a controller which controls the memory, the memory system storing data provided from a host to the NAND flash memory, the data writing method comprises a steps of specifying a column address in which a column failure which has occurred in the NAND flash memory by the controller, and a step of, during writing into the NAND flash memory, writing data of a first logic level into a memory cell which corresponds to the specified column address regardless of write data provided from the controller. | 2009-10-01 |
20090244975 | FLASH MEMORY DEVICE AND BLOCK SELECTION CIRCUIT THEREOF - The present invention relates to a block selection circuit of a flash memory device. The block selection circuit includes a control signal output unit, switching means, and an operation controller. The control signal output unit outputs a control signal for enabling or disabling memory blocks connected thereto by employing block address signals. The block address signals are decoded according to an input address and provided. The switching means switches the control signal so that the control signal is input as a block selection control signal. The operation controller turns off drain and source select transistors of a memory block connected thereto according to a logic level of a first control signal. | 2009-10-01 |
20090244976 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - The present invention provides a non-volatile memory capable of realizing erase/write operations in sufficiently small division units while suppressing an increase in chip area to the minimum, and shortening an erase time. Two of a physical erase state and a logical erase state are provided as threshold voltage distribution states of each memory cell. In the logical erase state, a threshold voltage criterion of the memory cell is shifted to a state higher than the physical erase state. When data rewriting of the memory cell placed in the physical erase state is performed, a logical erase is performed and the threshold voltage criterion is shifted to a high voltage level. The logical erase simply shifts the voltage level of the threshold voltage criterion. Since an electrical charge accumulated in the memory cell is not moved, erasing can be done at high speed and in a short period of time. | 2009-10-01 |
20090244977 | VARIABLE INITIAL PROGRAM VOLTAGE MAGNITUDE FOR NON-VOLATILE STORAGE - Multiple programming processes are performed for a plurality of non-volatile storage elements. Each of the programming process operates to program at least a subset of said non-volatile storage elements to a set of target conditions using program pulses. In one embodiment, a first programming pass includes soft programming and additional programming passes include the programming of data. In another embodiment, all of the programming process includes programming data. For at least a subset of said programming processes, a program pulse associated with achieving a particular result for a respective programming process is identified. The identified program pulse is used to adjust programming for a subsequent programming process. | 2009-10-01 |
20090244978 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises a plurality of memory cells connected to a bit line; and a sense amplifier operative to sense the magnitude of cell current flowing via the bit line in a selected memory cell connected to the bit line to determine the value of data stored in the memory cell. The sense amplifier includes a first transistor for precharge operative to supply current in the bit line via a first and a second sense node, a second transistor for charge transfer interposed between the first and second sense nodes, and a third transistor for continuous current supply operative to supply current in the bit line not via the first and second sense nodes. | 2009-10-01 |
20090244979 | ERASE DEGRADATION REDUCTION IN NON-VOLATILE MEMORY - Methods for erasing a memory device and memory systems are provided, such as those including a non-volatile memory device is erased by using an intermediate erase step prior to a normal erase step. The intermediate erase step is comprised of an erase pulse voltage, applied to the semiconductor well of the selected memory block of memory cells, while edge rows of memory cells are biased at a low positive voltage (e.g., 0.8-2V). An erase verify operation is then performed. If the selected memory block is not erased, a normal memory erase step is then performed in which the same erase pulse voltage is used but all of the rows are biased at ground potential as in a normal erase step. If the memory block is still fails the erase verify operation, the erase pulse voltage is increased and the process repeated. | 2009-10-01 |
20090244980 | Method for reducing lateral movement of charges and memory device thereof - Provided is a method and device for reducing lateral movement of charges. The method may include pre-programming at least one memory cell that is in an erased state by applying a pre-programming voltage to the at least one memory cell to have a narrower distribution of threshold voltages than the at least one erased state memory cell and verifying that the pre-programmed memory cell is in the pre-programmed state using a negative effective verifying voltage. | 2009-10-01 |
20090244981 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND ITS WRITING METHOD - It is made possible to provide a non-volatile semiconductor memory device capable of improving the writing efficiency and its writing method. Predetermined voltages are respectively applied to a drain region and a control gate, and then the voltage applied to the control gate is opened. | 2009-10-01 |
20090244982 | MEMORY BLOCK REALLOCATION IN A FLASH MEMORY DEVICE - A non-volatile memory device has the pages of a certain memory block reallocated to other blocks in order to increase decrease disturb and increase reliability. Each of the reallocation blocks that contain the reallocated pages from the desired memory block are coupled to a wordline driver. These wordline drivers have a subset of the global wordlines as inputs. The desired wordline driver is selected by an appropriate select signal from a block decoder and an indication on an appropriate global wordline. This causes the wordline driver to generate a local wordline to the desired block with the reallocated page to be accessed. | 2009-10-01 |
20090244983 | FLASH MEMORY DEVICE AND PROGRAM METHOD THEREOF - A nonvolatile memory device that includes first and second storage areas, and a control logic configured to control the first and second storage areas, wherein when a program operation of the first storage area is passed before a program operation of the second storage area is passed, the control logic completes the program operation of the first storage area and continues the program operation of the second storage area is provided. | 2009-10-01 |
20090244984 | METHOD FOR DRIVING A NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A method for driving a nonvolatile semiconductor memory device is provided. The nonvolatile semiconductor memory device includes a semiconductor layer having a channel, a first insulating film provided on the channel, a floating electrode provided on the first insulating film, a second insulating film provided on the floating electrode, and a gate electrode provided on the second insulating film, and changes its data memory state by injection of charges into the floating electrode. The method includes to achieve a state in which charges having a first polarity are injected into the floating electrode: providing a first potential difference between the semiconductor layer and the gate electrode to inject charges having the first polarity into the second insulating film; subsequently providing a second potential difference between the semiconductor layer and the gate electrode to inject charges having a second polarity opposite to the first polarity into the second insulating film; and subsequently providing a third potential difference between the semiconductor layer and the gate electrode to inject charges having the first polarity into the floating electrode. | 2009-10-01 |
20090244985 | METHOD FOR ERASING A P-CHANNEL NON-VOLATILE MEMORY - A present invention relates to a method of erasing a P-channel non-volatile memory is provided. This P-channel non-volatile memory includes a select transistor and a memory cell connected in series and disposed on a substrate. In the method of erasing the P-channel non-volatile memory, holes are injected into a charge storage structure by substrate hole injection effect. Hence, the applied operational voltage is low, so the power consumption is lowered, and the efficiency of erasing is enhanced. As a result, an operational speed of the memory is accelerated, and the reliability of the memory is improved. | 2009-10-01 |
20090244986 | Semiconductor memory device and methods thereof - A semiconductor memory device and methods thereof are provided. The example semiconductor memory device may include a memory cell configured to store data, a storage unit configured to store at least one data pattern, a data output circuit configured to output the stored data during a first type of read operation and configured to output the at least one data pattern during a second type of read operation and an output control circuit for controlling the data output circuit such that the memory cell is not accessed during read operations of the second type. A first example method may include storing at least one data pattern in a storage unit, outputting the stored data within the memory cell in response to a first type of read operation and outputting the at least one data pattern in the storage unit in response to a second type of read operation and blocking access to the memory cell during read operations of the second type. A second example method may include storing at least one fixed data pattern within a storage unit, the at least one fixed data pattern only accessible during read operations of a first type, storing normal data within at least one memory cell, the normal data only accessible during read operations of a second type and blocking access to the at least one memory cell during an execution of read operations of the second type. | 2009-10-01 |
20090244987 | Dynamic Column Block Selection - Selecting circuits for columns of an array of memory cells are used to hold read data or write data of the memory cells. The memory cells may be multistate memory cells. There is a shift register chain, having a stage for columns of the array. A strobe pulse is shifted through this shift register. The strobe points, with each clock, at and enables a different selecting circuit in sequence. That particular selecting circuit that has been enabled by the strobe will then perform a certain function. In a read mode, the selected selecting circuit will send the stored information through to the output buffer for output from the integrated circuit. And while in a programming mode, the selected selecting circuit will receive data from an input buffer. This data will be written into a memory cell. | 2009-10-01 |
20090244988 | COMPILED MEMORY, ASIC CHIP, AND LAYOUT METHOD FOR COMPILED MEMORY - Each of memory blocks includes word line groups each having at least one of word lines, memory cells and bit lines. A decoder unit selects couple control units corresponding to the memory blocks to be accessed, and decodes an address signal to select any of the word line groups. A logic of the decoder unit is formed by assigning a bit of the address signal to identify the memory blocks and the couple control units lower than a bit of the address signal to identify the word line groups. Accordingly, the numbers of word lines disposed at the memory blocks can be equalized with each other, and lengths of the bit lines can be shortened. As a result, a wiring delay of each of the bit lines can be minimized, and an access time of a compiled memory can be shortened. | 2009-10-01 |
20090244989 | BITLINE VOLTAGE DRIVER - A method and structure for passing a bitline voltage regardless of its voltage level via a bitline in a memory device is disclosed. In one embodiment, the method includes detecting the bitline voltage of the bitline, feeding a control signal at an activation voltage level to the bitline pass device to maintain a pass voltage differential of the bitline pass device when the bitline is selected and passing the bitline voltage via the bitline pass device in response to the control signal, where the pass voltage differential is greater than a threshold voltage of the bitline pass device regardless of a level of the bitline voltage. | 2009-10-01 |
20090244990 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises a comparing unit that comprises a potential of a memory cell with a reference potential supplied by a reference cell to read data of the memory cell; first and second bit lines connected to inputs of the comparing unit; a first memory cell connected to the first bit line; a second memory cell connected to the second bit line; a first reference cell acting as the reference cell; a second reference cell acting as another reference cell; a potential line that supplies the reference potential to the first and second reference cells; and a dummy cell comprising a coupling capacitor that stabilizes potential of the potential line. | 2009-10-01 |
20090244991 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises a first exclusive-OR circuit which compares mth N-bit first data with (m+1)th N-bit second data, a majority circuit which generates flag data to invert the second data if a comparison result of the first exclusive-OR circuit indicates that the number of mismatch bits between the first data and the second data is not less than N/2, and generates flag data to noninvert the second data if the number of mismatch bits between the first data and the second data is less than N/2, a second exclusive-OR circuit which inverts or noninverts the second data based on the flag data, a shift register which stores the flag data generated by the majority circuit, and a pad to serially output both the inverted or noninverted second data and the flag data. | 2009-10-01 |
20090244992 | INTEGRATED CIRCUIT AND METHOD FOR READING THE CONTENT OF A MEMORY CELL - In an embodiment, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include at least one memory cell, a read circuit configured to read the memory cell, wherein the read circuit includes an output holding circuit configured to hold a memory cell content signal read from the memory cell, and an enable circuit configured to provide the memory cell content signal at an output of the read circuit only in case the memory cell fulfills a predefined criterion. | 2009-10-01 |
20090244993 | MAINTAINING DYNAMIC COUNT OF FIFO CONTENTS IN MULTIPLE CLOCK DOMAINS - Disclosed is a system that generates a write count value for indicating whether data can be read from a FIFO and a system that generates a read count value for indicating whether data can be written to a FIFO. Each of these systems operates in two separate clock domains. In the system that generates a write count value, write strobes are stored in parallel in a register in a first clock domain. The plurality of synchronizers trigger on a rising edge of the write strobe that is stored in the parallel register and generate an increment pulse in a second clock domain. An up/down counter reads the increment pulse in parallel and increments the up/down counter in parallel. A decrement signal from a read strobe decrements the up/down counter. The output of the counter is fed to a register that provides a write counter value to handshake logic that indicates whether data can be read from a FIFO without underflowing the FIFO. | 2009-10-01 |
20090244994 | Data strobe signal generating circuit capable of easily obtaining valid data window - A data strobe signal generating circuit includes a pre-driver control unit for selectively transferring a ground voltage and a supply voltage, as a first control signal and a second control signal, in response to first and second clock pulse signals, wherein the second control signal is driven in response to a preamble signal, a pre-driver for generating a driving signal in response to the first and second control signals and the preamble signal, and an output buffer for driving an output pad in response to the driving signal. | 2009-10-01 |
20090244995 | Circuit for Locking a Delay Locked Loop (DLL) and Method Therefor - A receive circuit ( | 2009-10-01 |
20090244996 | Circuit Using a Shared Delay Locked Loop (DLL) and Method Therefor - A transceiver ( | 2009-10-01 |
20090244997 | Method for Training Dynamic Random Access Memory (DRAM) Controller Timing Delays - Timing delays in a double data rate (DDR) dynamic random access memory (DRAM) controller ( | 2009-10-01 |
20090244998 | SYNCHRONOUS MEMORY DEVICE - A synchronous memory device, which includes a read command buffer, a replica circuit, and a latency circuit. The read command buffer provides a read signal in response to a read command. The replica circuit provides a transfer signal whose time difference with respect to the feedback clock signal is substantially identical to a period that it takes a read command buffer to provide the read signal. The latency circuit receives the read signal, and provides a latency signal having a difference of a predetermined time corresponding to CAS latency with respect to the read signal in response to the transfer signal. | 2009-10-01 |
20090244999 | Clock control during self-test of multi port memory - A multiport memory | 2009-10-01 |
20090245000 | SEMICONDUCTOR INTEGRATED CIRCUIT - A one-hot data generating unit generates one-hot data for the maximum data bit width in which a state of one bit is exclusively inverted with respect to states of other bits while sequentially shifting a bit position to be inverted, and writes the one-hot data in an area of a memory designated by an address. A short defect between wirings connected to the memory is detected by comparing the one-hot data written in the memory with the one-hot data before being written. | 2009-10-01 |
20090245001 | INTEGRATED CIRCUIT AND METHOD FOR TESTING THE CIRCUIT - An integrated circuit includes a memory; a memory test circuit that tests the memory; and an input/output port, wherein the memory test circuit includes a latch circuit that outputs output of the memory, an address of the memory to be accessed is changed in accordance with a first clock signal, and output of the memory corresponding to the changed address is latched in accordance with a latch signal having a cycle of an integral multiple of the first clock signal, data of the latch circuit is output via the input/output port in a cycle of the latch signal, an address of a memory cell corresponding to the output of the memory to be latched by the latch circuit is changed, and the latch and the output is repeated. | 2009-10-01 |
20090245002 | SEMICONDUCTOR MEMORY DEVICE HAVING HIGH STABILITY AND QUALITY OF READOUT OPERATION - A semiconductor memory cell device includes a first multiplexer selecting a sub-block including a memory cell storing data to be read out in a row, a drain selector selecting a first column line connected to one terminal of the memory cell to be read, a precharge selector selecting a second column line connected to the other terminal of the memory cells adjacent to the one terminal of the memory cell storing the data to be readout, a second multiplexer selecting the sub-block including the second column line, a source selector selecting a third column line connected to the other terminal of the memory cell storing the data to be read out. The second multiplexer and precharge selector, when selecting, apply a first voltage to the second column line, and the source selector, when selecting, applies a second voltage to the third column line. | 2009-10-01 |
20090245003 | SEMICONDUCTOR MEMORY DEVICE, METHOD OF OPERATING SEMICONDUCTOR MEMORY DEVICE, AND MEMORY SYSTEM - A semiconductor memory device is provided which comprises: a sense amplifier; and a bit line, wherein the disconnection of the sense amplifier from the bit line is performed in a data read operation when temperature in the semiconductor memory device is at a first temperature, and wherein the disconnection of the sense amplifier from the bit line is not performed in the data read operation when the temperature in the semiconductor memory device is at a second temperature. | 2009-10-01 |
20090245004 | SEMICONDUCTOR DEVICE INCLUDING MULTI-CHIP - In order to implement a memory having a large storage capacity and a reduced data retention current, a non-volatile memory, an SRAM, a DRAM, and a control circuit are modularized into one package. The control circuit conducts assignment of addresses to the SRAM and DRAM, and stores data that must be retained over a long period of time in the SRAM. In the DRAM, a plurality of banks are divided into two sets, and mapped to the same address space, and sets are refreshed alternately. A plurality of chips of them are stacked and disposed, and wired by using the BGA and chip-to-chip bonding. | 2009-10-01 |
20090245005 | RECOVERY OF EXISTING SRAM CAPACITY FROM FUSED-OUT BLOCKS - A system, device, and method are disclosed. In one embodiment the system includes an interconnect within an integrated circuit. The system also includes a first fuse-disabled design block within the integrated circuit that has an internal static random access memory (SRAM). The first fuse-disabled design block is coupled to the interconnect. The system also includes a memory controller that is coupled to the interconnect. The memory controller is capable of selecting the internal SRAM and allocating the internal SRAM for storage accessible by one or more devices external to the first fuse-disabled integrated peripheral. | 2009-10-01 |
20090245006 | Semiconductor memory device - The present invention provides a semiconductor memory device that includes: a fuse circuit having multiple fuse elements; and a fuse selection circuit connected to an internal address signal line that receives an address signal externally inputted. The fuse circuit is connected to the fuse selection circuit to receive an output from the fuse selection circuit, is supplied with an externally inputted trigger signal that permits nonvolatile recording of the fuse elements, and, in response to the output and the trigger signal, records the fuse element corresponding to the internal address signal line among the plurality of fuse elements while recording at least one of the plurality of fuse elements other than the fuse element thus recorded. | 2009-10-01 |
20090245007 | SELECTIVELY CONTROLLED MEMORY - Embodiments of methods, apparatuses, and systems that enable power conservation in data buffering components are disclosed. Other embodiments may also be disclosed. | 2009-10-01 |
20090245008 | SYSTEM AND METHOD FOR PROVIDING VOLTAGE POWER GATING - A system and method for providing voltage power gating. The system includes a device for providing voltage power gating. The device includes logic circuitry, a mechanism for receiving a control signal associated with the logic circuitry and a selector. The control signal indicates an active state or an idle state of the logic circuitry. The selector enables a power source to the logic circuitry in response to the control signal indicating the active state. The selector also disables the power source to the logic circuitry in response to the control signal indicating the idle state. Thus, the power source is dynamically eliminated from the logic circuitry on the device when it is in the idle state. | 2009-10-01 |
20090245009 | 256 Meg dynamic random access memory - A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to datalines. A data path is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks. A plurality of voltage supplies provide the voltages needed in the array and in the peripheral circuits. The power supplies are organized to match their power output to the power demand and to maintain a desired ratio of power production capability and decoupling capacitance. A powerup sequence circuit is provided to control the powerup of the chip. Redundant rows and columns are provided as is the circuitry necessary to logically replace defective rows and columns with operational rows and columns. Circuitry is also provided on chip to support various types of test modes. | 2009-10-01 |
20090245010 | Data Driver Circuit for a Dynamic Random Access Memory (DRAM) Controller or the Like and Method Therefor - A data driver includes a first latch ( | 2009-10-01 |
20090245011 | WORDLINE DRIVER FOR DRAM AND DRIVING METHOD THEREOF - A wordline driver for DRAM comprises a multiplexer, an inverter and a transistor switch. One end of the multiplexer is connected to a wordline charging voltage, and the other end is connected to an external voltage, wherein the external voltage is less than the wordline charging voltage, and initially the external voltage is outputted. The output end of the inverter is connected to the select line of the multiplexer, and the input end thereof is electrically connected to the output end of the multiplexer. One end of the transistor switch is connected to the input end of the inverter, and the other end thereof is connected to the word line. | 2009-10-01 |
20090245012 | SEMICONDUCTOR STORAGE DEVICE AND MEMORY SYSTEM - A semiconductor storage device includes an external terminal to which a first signal is supplied, a core circuit, and an access operation control circuit that generates a signal indicating an access operation mode to the core circuit for subsequent cycles based on a pulse width of the first signal. | 2009-10-01 |
20090245013 | Sequential storage circuitry for an integrated circuit - Sequential storage circuitry is provided for an integrated circuit, comprising input circuitry, a storage structure, and output circuitry. The input circuitry receives an input data value to the sequential storage circuitry, and generates an internal data value. The input circuitry receives a first control signal which when asserted causes it to generate as the internal data value an inverted version of the input data value, and which when not asserted causes the input circuitry to generate as the internal data value the input data value. The storage structure then stores an indication of the internal data value. The output circuitry generates, from the indication of the internal data value stored in the storage structure, an output data value for outputting from the sequential storage circuitry. More particularly, the output circuitry receives a second control signal derived from the first control signal, which causes the output circuitry to generate as said output data value an inverted version of the internal data value in the event that the input circuitry generated as the internal data value an inverted version of the input data value, and otherwise generates as the output data value the internal data value. Such a mechanism provides a simple and effective technique for annealing stress build-up within the storage structure, as for example may arise as a result of the NBTI phenomenon. The technique of the present invention can be also be used for other purposes, for example to improve security of the data held within such a sequential storage circuitry. | 2009-10-01 |
20090245014 | CLAY KNEADER - A clay kneader has a drum having a pressure raising section on a supply opening side, an extrusion section having an inner diameter smaller than that of the pressure raising section on side of an extrusion opening for extruding clay as a columnar article, and a flow controlling section located between the pressure raising section and the extrusion section and being equipped with a supply opening for clay, a screw having a rotary shaft having a diameter which gradually decreases toward the extrusion opening in the flow controlling section and being ended around a boundary between the flow controlling section and the extrusion section, and a helical rotating blade provided along the rotary shaft for kneading the clay a rotary shaft. | 2009-10-01 |
20090245015 | APPARATUS AND METHOD FOR APPLYING OSCILLATORY MOTION - Method and apparatus for applying oscillatory motion to a substance in a vessel to provide improved mixing, in particular to enable different mixing patterns to be applied to a substance in a vessel without “stop, change and start” protocol, has a member and a control means operatively linked such that the movement of the member is determined by a control signal generated by the control means. | 2009-10-01 |
20090245016 | HORIZONTAL MIXER - An easily cleanable horizontal mixer. This horizontal mixer ( | 2009-10-01 |
20090245017 | MICROMIXERS FOR NANOMATERIAL PRODUCTION - A micromixer device has at least one fluid inlet channel and at least one fluid outlet channel. A plurality of pathways extend between the fluid inlet channel and the fluid outlet channel. The width of at least some of the plurality of pathways varies in a substantially parabolic manner along at least one dimension of the micromixer device. | 2009-10-01 |
20090245018 | COMBINED PROBE AND CORRESPONDING SEISMIC MODULE FOR THE MEASUREMENT OF STATIC AND DYNAMIC PROPERTIES OF THE SOIL - A combined probe includes a dilatometer probe, a gas conduit coupled to the dilatometer probe for providing a gas connection between the dilatometer probe and an external gas source, a wire located in the gas conduit for providing an electrical connection between the dilatometer probe and an external circuit, and a seismic module coupled to the wire located in the gas conduit to provide an electrical connection between the seismic module and the external circuit. | 2009-10-01 |
20090245019 | Method and system for determining geodetic positions of towed marine sensor array components - A method for determining positions of geophysical sensor streamers includes towing laterally spaced apart streamers maintained in relative relationship therebetween by paravanes proximate their forward ends. The streamers include spaced apart acoustic transmitters and acoustic receivers. The paravanes each include an acoustic transmitter or receiver. Signals are sent from the acoustic transmitters and are received at the acoustic receivers. Geodetic position signals are detected at each paravane. The identities of the transmitters of the received acoustic signals are determined to determine travel times of the received acoustic signals. The travel times are converted to distances between the identified transmitters and the receivers. Relative positions of the streamers are determined from the distances. The relative positions of the streamers are combined with the detected geodetic position signals to determine geodetic positions of the streamers. | 2009-10-01 |
20090245020 | METHOD FOR DETERMINATION OF DIFFERENTIAL TRANSFER FUNCTION BETWEEN TWO CLOSELY SPACED HYDROPHONES - Methods and apparatus for determining an accurate differential transfer function (DTF) between two closely spaced hydrophones in a dual-hydrophone configuration such that the wavefield may be properly separated into up- and down-going components are provided. The methods disclosed herein are based on the premise that the cross-correlation at a lag of zero between up- and down-going wavefields should be at a minimum for perfectly matched hydrophones. Thus, any suitable global optimization technique may be utilized to determine an accurate DTF where the zero-lag cross-correlation between up- and down-going energy is at a minimum after multiplying a particular hydrophone spectrum of the pair (depending on how the DTF was defined) with a possible DTF suggested by the global optimization technique. | 2009-10-01 |
20090245021 | RECONSTRUCTING LOW FREQUENCY DATA RECORDINGS USING A SPREAD OF SHALLOW AND DEEP STREAMERS - A technique includes obtaining first data indicative of seismic measurements acquired by seismic sensors of a first set of towed streamers and obtaining second data indicative of seismic measurements acquired by seismic sensors of a second set of towed streamers. The second set of towed streamers is towed at a deeper depth than the first set of towed streamers. The technique includes interpolating seismic measurements based on the first and second data. The interpolation includes assigning more weight to the second data than to the first data for lower frequencies of the interpolated seismic measurements. | 2009-10-01 |
20090245022 | DUAL-WAVEFIELD MULTIPLE ATTENUATION - Method for attenuating surface multiple reflections in dual-wavefield seismic data. In one implementation, the method may include: (a) performing wavefield separation on dual-wavefield seismic data to separate events in the seismic data into data sets according to ghost characteristics; (b) applying a multidimensional Surface-Related Multiple Elimination (SRME) to two or more of the data sets to yield an SRME result in a manner that retains surface reflection information affecting surface multiple reflections; and (c) repeating step (b) one or more times. | 2009-10-01 |
20090245023 | A METHOD FOR REFLECTION TIME SHIFT MATCHING A FIRST AND A SECOND SET OF SEISMIC REFLECTION DATA - A method is disclosed for reflection time shift matching a first and a second set of seismic reflection data ( | 2009-10-01 |
20090245024 | THERMAL EXPANSION MATCHING FOR ACOUSTIC TELEMETRY SYSTEM - Thermal expansion matching for an acoustic telemetry system. An acoustic telemetry system includes at least one electromagnetically active element and a biasing device which reduces a compressive force in the element in response to increased temperature. A method of utilizing an acoustic telemetry system in an elevated temperature environment includes the steps of: applying a compressive force to at least one electromagnetically active element of the telemetry system; and reducing the compressive force as the temperature of the environment increases. | 2009-10-01 |
20090245025 | Underwater communications - An environmental monitoring system including at least one underwater measurement device and a transmitter for transmitting data from the measurement device to an above water station using a magnetically coupled antenna. | 2009-10-01 |
20090245026 | SYSTEM AND METHOD FOR GENERATING A THREAT ALERT - A system for generating a threat alert in an infrastructure component is provided. The system includes multiple acoustic sensors disposed in a protected zone around the infrastructure component, wherein each of the sensors is configured to detect a signal corresponding to an outcome that causes damage to the infrastructure component. The system also includes a processing circuitry coupled to each of the multiple acoustic sensors. The processing circuitry includes at least one analog-to-digital converter configured to digitize the signal. The processing circuitry also includes a digital signal processor configured to process the acoustic signal in a sequential routine. The sequential routine includes a noise filtering routine configured to filter background noise from the acoustic signal and generate a filtered signal. The sequential routine also includes a source identification routine configured to identify a source generating the acoustic signal based upon the filtered signal. The sequential routine further includes a threat analysis routine configured to detect a threat based upon the source identified and generate a threat level signal. The system also includes a remote monitoring center that receives the threat level signals from the processing circuitry and transmit an alert message to a concerned authority. | 2009-10-01 |
20090245027 | SLOTTED CYLINDER ACOUSTIC TRANSDUCER - A slotted cylinder acoustic transducer has a crescent-shaped insert disposed between a ceramic stack assembly and s cylindrical housing shell. In some embodiments, all of the ceramic elements in the ceramic stack assembly can have the same shape. | 2009-10-01 |
20090245028 | ULTRA LOW FREQUENCY ACOUSTIC VECTOR SENSOR - An acoustic vector sensor mounted in a housing is provided for measuring ultra low frequency acoustic wave particle velocities in a liquid, comprising a horn for amplifying the acoustic wave particle velocities, and a neutrally buoyant object supported in a liquid contained in the horn. The neutrally buoyant object, in reacting to the amplified acoustic wave particle velocities, produces displacements that are sensitively measured. | 2009-10-01 |
20090245029 | ACTIVITY REMINDER SMART CARD - A method and apparatus for reminding a user when an activity is to be performed is disclosed. The apparatus includes a smartcard ( | 2009-10-01 |
20090245030 | ONE-PIECE HAIRSPRING AND METHOD OF MANUFACTURING THE SAME - The invention relates to a one-piece hairspring ( | 2009-10-01 |
20090245031 | LIQUID CRYSTAL DISPLAY DEVICE DISPLAYING COLOURED SEGMENTS AND TIMEPIECE FITTED WITH THE SAME - The invention proposes a liquid crystal ( | 2009-10-01 |
20090245032 | WATCH CASE WITH A COMPOSITE MIDDLE PART - The middle part includes an inner metallic middle part ( | 2009-10-01 |
20090245033 | Adaptive High Fidelity Reproduction System - Audio is adaptively associated with speakers, depending on the speaker configuration that is present. Each speaker it receives an audio assignment based on its individual spectral characteristics. As more speakers are added, content is adaptively associated with that you speaker, and taken away from the previous. | 2009-10-01 |
20090245034 | OPTICAL DEVICE, OPTICALLY ASSISTED MAGNETIC RECORDING HEAD AND OPTICALLY ASSISTED MAGNETIC RECORDING APPARATUS - Provided are an optical device, optically assisted magnetic recording head and optically assisted magnetic recording apparatus that effectively emit the introduced light, from the apex portion of a waveguide. The optical device includes: an optical element having a substantially parabolic outline which contains a side surface and the apex portion with a light-emitting surface; a light guiding unit for forming a light spot on the core layer; and a light introducing section provided on the core layer at the position at which the light spot is formed. The light introduced into the core layer travels substantially parallel to the axis of the parabola, and is reflected by the side surface so as to be converged at the focal point of the parabola and is then emitted from the apex portion. The position of the point where the light intensity is greatest in the light spot is deviated from the axis. | 2009-10-01 |
20090245035 | Disc storage apparatus and disc storage method - A disc storage apparatus includes a disc changer mechanism including a disc slot through which a disc is insertable, a storage section having storage locations that are capable of storing discs inserted through the disc slot, and a transport mechanism that transports the disc, inserted through the disc slot, to any of the storage locations in the storage section. The apparatus further includes an operation section having operations keys; a display section; and a controller that associates, when the disc is inserted and any of the operations keys is operated, the operated operation key with the storage location in which the disc is stored. In accordance with a predetermined operation on the operation section, the controller extracts all discs stored in the storage locations associated with the operated operation key and causes information regarding all the extracted discs to be displayed on the display section. | 2009-10-01 |
20090245036 | SERVO CONTROL DEVICE, SERVO CONTROL METHOD, AND SERVO CONTROL PROGRAM - A servo control device that is capable of optimizing gain that is used in servo control and stabilizing the servo control even when the gain changes due to change in the status of overrecording over the same radial position on an optical disc. When drawing a visible image on the label surface of an optical disc DK by an overrecording operation over the same radial position of that label surface, the servo control device comprises a CPU | 2009-10-01 |