40th week of 2009 patent applcation highlights part 18 |
Patent application number | Title | Published |
20090242935 | MONOLITHICALLY INTEGRATED PHOTODETECTORS - Methods and structures for monolithically integrating monocrystalline silicon and monocrystalline non-silicon materials and devices are provided. In one structure, a monolithically integrated semiconductor device structure comprises a silicon substrate and a first monocrystalline semiconductor layer disposed over the silicon substrate, wherein the first monocrystalline semiconductor layer has a lattice constant different from a lattice constant of relaxed silicon. The structure further includes an insulating layer disposed over the first monocrystalline semiconductor layer in a first region and a monocrystalline silicon layer disposed over the insulating layer in the first region. The structure includes at least one silicon-based photodetector comprising an active region including at least a portion of the monocrystalline silicon layer. The structure also includes a second monocrystalline semiconductor layer disposed over at least a portion of the first monocrystalline semiconductor layer in a second region and absent from the first region, wherein the second monocrystalline semiconductor layer has a lattice constant different from the lattice constant of relaxed silicon. The structure includes at least one non-silicon photodetector comprising an active region including at least a portion of the second monocrystalline semiconductor layer. | 2009-10-01 |
20090242936 | STRAINED ULTRA-THIN SOI TRANSISTOR FORMED BY REPLACEMENT GATE - A semiconductor structure is described. The structure includes a transistor formed in a semiconductor substrate, the semiconductor substrate having a semiconductor-on-insulator (SOI) layer; a channel associated with the transistor and formed on a first portion of the SOI layer; and a source/drain region associated with the transistor and formed in a second portion of the SOI layer and in a recess at each end of the channel, where the second portion of the SOI layer is substantially thicker than the first portion of the SOI layer. A method of fabricating the semiconductor structure is also described. The method includes forming a dummy gate in a semiconductor substrate; performing a SIMOX process to form a SOI layer such that a first portion of the SOI layer under the dummy gate is substantially thinner than a second portion of the SOI layer; forming a source/drain extension in the SOI layer; and recessing the source/drain extension for forming a source/drain region; epitaxially growing the second portion of the SOI layer; forming an insulating layer over the epitaxial growth; removing the dummy gate for forming a gate opening; and filling the gate opening with a gate dielectric material and a gate conductor material. | 2009-10-01 |
20090242937 | Semiconductor device and manufacturing method - A semiconductor device has source and drain electrodes formed on a substrate, a gate insulation film formed on the substrate between the source and drain electrodes, and a gate electrode formed on the gate insulation film. These elements are all covered by a dielectric sub-insulation film. An opening is formed in the sub-insulation film, partially exposing the gate electrode. A field plate extends from the top of the gate electrode down one side of the gate electrode as far as the sub-insulation film covering the gate insulation film, filling the opening. The thickness of the sub-insulation film can be selected to optimize the separation between the field plate and the substrate for the purpose of reducing current collapse by reducing electric field concentration at the edge of the gate electrode. | 2009-10-01 |
20090242938 | Field effect transistor - A field effect transistor formed of a semiconductor of a III group nitride compound, includes an electron running layer formed on a substrate and formed of GaN; an electron supplying layer formed on the electron running layer and formed of Al | 2009-10-01 |
20090242939 | WAFER FOR BACKSIDE ILLUMINATION TYPE SOLID IMAGING DEVICE, PRODUCTION METHOD THEREOF AND BACKSIDE ILLUMINATION SOLID IMAGING DEVICE - A wafer for backside illumination type solid imaging device has a plurality of pixels inclusive of a photoelectric conversion device and a charge transfer transistor at its front surface side and a light receiving surface at its back surface side, wherein said wafer is a SOI wafer obtained by forming a given active layer on a support substrate made of C-containing n-type or p-type semiconductor material through an insulating layer. | 2009-10-01 |
20090242940 | SENSOR DEVICE AND FABRICATION METHOD FOR THE SAME - The sensor device includes: a converter body made of silicon in the shape of a rhombus in plan, the converter body having an opening in the shape of a hexagon in plan; a substrate for holding the converter body; a movable film formed on the opening; a converter electrode formed on the converter body; and a substrate electrode formed on the substrate, the substrate electrode being electrically connected with the converter electrode. The opening is placed so that four of the six sides of the hexagon extend along the four sides of the rhombus of the converter body. | 2009-10-01 |
20090242941 | STRUCTURE AND METHOD FOR MANUFACTURING DEVICE WITH A V-SHAPE CHANNEL NMOSFET - A CMOS structure includes a v-shape surface in an nMOSFET region. The v-shape surface has an orientation in a (100) plane and extends into a Si layer in the nMOSFET region. The nMOSFET gate dielectric layer is a high-k material, such as Hf02. The nMOSFET has a metal gate layer, such as Ta. Poly-Si is deposited on top of the metal gate layer. | 2009-10-01 |
20090242942 | ASYMMETRIC SOURCE AND DRAIN FIELD EFFECT STRUCTURE AND METHOD - A semiconductor structure, such as a CMOS semiconductor structure, includes a field effect device that includes a plurality of source and drain regions that are asymmetric. Such a source region and drain region asymmetry is induced by fabricating the semiconductor structure using a semiconductor substrate that includes a horizontal plateau region contiguous with and adjoining a sloped incline region. Within the context of a CMOS semiconductor structure, such a semiconductor substrate allows for fabrication of a pFET and an nFET upon different crystallographic orientation semiconductor regions, while one of the pFET and the nFET (i.e., typically the pFET) has asymmetric source and drain regions. | 2009-10-01 |
20090242943 | SEMICONDUCTOR DEVICE - A semiconductor device which can prevent peeling off of a gate electrode is provided. The semiconductor device has GaN buffer layer formed on substrate | 2009-10-01 |
20090242944 | METHOD OF FORMING A SEMICONDUCTOR DEVICE USING STRESS MEMORIZATION - A stress memorization technique (SMT) film is deposited over a semiconductor device. The SMT film is annealed with a low thermal budget anneal that is sufficient to create and transfer the stress of the SMT film to the semiconductor device. The SMT film is then removed. After the SMT film is removed, a second anneal is applied to the semiconductor device sufficiently long and at a sufficiently high temperature to activate dopants implanted for forming device source/drains. The result of this approach is that there is minimal gate dielectric growth in the channel along the border of the channel. | 2009-10-01 |
20090242945 | Semiconductor device and method of fabricating the same - In a method of fabricating a semiconductor device on a substrate having a pillar pattern, a gate electrode is formed on the pillar pattern without etching the latter. A conductive pattern is filled between adjacent pillar patterns, a spacer is formed above the conductive pattern and surrounding sidewalls of each pillar pattern, and the gate electrode is formed by etching the conductive pattern using the spacer as an etch barrier. | 2009-10-01 |
20090242946 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD FOR THE SEMICONDUCTOR DEVICE - A semiconductor device which could strengthen the mechanical strength of the protective film and with which packaging of the wafer level with electric high reliability is performed and a fabrication method for the semiconductor device are provided. The semiconductor device includes a semiconductor substrate; a field effect transistor including a gate electrode, a drain electrode, and a source electrode which are formed on the semiconductor substrate; a hollow protective film provided on the semiconductor substrate so that an inner surface bonds to the upper surface of the one or both of the drain electrode and the source electrode of the field effect transistor, wherein the hollow protective film includes a first cap layer contacting the upper surface of the one or both of the drain electrode and the source electrode, and a second cap layer placed on the first cap layer. | 2009-10-01 |
20090242947 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD FOR THE SEMICONDUCTOR DEVICE - A semiconductor device and a fabrication method for the semiconductor device which can remove the sacrifice layer deposited on the semiconductor device surface in a short time and whose manufacturing yield can be improved are provided. The semiconductor device and the fabrication method for the semiconductor device includes a field effect transistor | 2009-10-01 |
20090242948 | METHOD OF FORMING AN INVERTED LENS IN A SEMICONDUCTOR STRUCTURE - A flat-top convex-bottom lower lens is formed by first applying a positive tone photoresist over a silicon oxide layer and an optional metallic barrier layer thereupon in a back-end-of-line (BEOL) metallization structure. The positive tone photoresist is exposed under defocused illumination conditions and/or employing a half-tone mask so that a cross-sectional profile of the positive tone photoresist after exposure contains a continuous and smooth concave profile, which is transferred into the underlying silicon oxide layer to form a concave cavity therein. After removing the photoresist, the cavity is filled with a high refractive index material such as silicon nitride, and planarized to form a flat-top convex-bottom lower lens. Various aluminum metal structures, a color filter, and a convex-top flat-bottom upper lens are thereafter formed so that the upper lens and the lower lens constitute a composite lens system. | 2009-10-01 |
20090242949 | CMOS IMAGE SENSOR WITH REDUCED DARK CURRENT - A carbon-containing semiconductor layer is formed on exposed surfaces of a p-doped semiconductor layer abutting sidewalls of a shallow trench. Following formation of a dielectric layer on the carbon-containing semiconductor layer, a surface pinning layer having a p-type doping is formed underneath the carbon-containing semiconductor layer. A shallow trench isolation structure and a photodiode are subsequently formed. Diffusion of defects directly beneath the shallow trench isolation structure, now contained in the carbon-containing semiconductor layer, is suppressed. Further, boron diffusion into the shallow trench isolation structure and into the photodiode is also suppressed by the carbon-containing semiconductor layer, providing reduction in dark current and enhancement of performance of the photodiode. | 2009-10-01 |
20090242950 | ACTIVE PIXEL SENSOR HAVING TWO WAFERS - A vertically-integrated image sensor includes a sensor wafer connected to a support circuit wafer. Each pixel region on the sensor wafer includes a photodetector, a charge-to-voltage conversion mechanism, a transfer mechanism for transferring charge from the photodetector to the charge-to-voltage conversion mechanism, and a reset mechanism for discharging the charge-to-voltage conversion mechanism. The support circuit wafer includes an amplifier and other support circuitry for each pixel region on the sensor wafer. An inter-wafer connector directly connects each charge-to-voltage mechanism on the sensor wafer to a respective gate to an amplifier on the support circuit wafer. | 2009-10-01 |
20090242951 | SOLID-STATE IMAGE PICKUP DEVICE - A solid-state image pickup device has a photoelectric conversion element that converts light incident from a first surface of a substrate into a signal charge and accumulates the signal charge, a transistor that is formed on a second surface side opposite to the first surface of the substrate and reads out the signal charge accumulated by the photoelectric conversion element, a supporting substrate stuck to the second surface of the substrate, and an antireflection coating formed on the first surface of the substrate, wherein the first surface of the substrate includes a curved surface or an inclined surface forming a prescribed angle to the second surface. | 2009-10-01 |
20090242952 | INTEGRATED CIRCUIT INCLUDING A CAPACITOR AND METHOD - An integrated circuit including a capacitor and a method of fabricating an integrated circuit. The capacitor has a first electrode. A plurality of conductive lines is separated from each other and is configured to be held at a potential being the same for all conductive lines. A second electrode encloses individual ones of the conductive lines at a top side and at least one lateral side and is separated from the first electrode by a dielectric layer. The second electrode includes a polycrystalline semiconductor material, a metal or a metal-semiconductor compound. | 2009-10-01 |
20090242953 | SHALLOW TRENCH CAPACITOR COMPATIBLE WITH HIGH-K / METAL GATE - Forming a shallow trench capacitor in conjunction with an FET by forming a plurality of STI trenches; for the FET, implanting a first cell well having a first polarity between a first and a second of the STI trenches; for the capacitor, implanting a second cell well having a second polarity in an area of a third of the STI trenches; removing dielectric material from the third STI trench; forming a gate stack having a first portion located between the first and the second of the STI trenches and a second portion located over and extending into the third trench; and performing a source/drain implant of the same polarity as the second cell well, thereby forming a FET in the first cell well, and a capacitor in the second cell well. The second polarity may be opposite from the first polarity. An additional implant may reduce ESR in the second cell well. | 2009-10-01 |
20090242954 | MEMORY DEVICE AND FABRICATION THEREOF - The invention is related to a memory device, including a substrate, a capacitor which is substantially C-shaped in a cross section parallel to the substrate surface and a word line coupling the capacitor. In an embodiment, the C-shaped capacitor is a deep trench capacitor, and in alternative embodiment, the C-shaped capacitor is a stack capacitor. Both inner edge and outer edge of the C-shaped capacitor can be used for providing capacitance. | 2009-10-01 |
20090242955 | Integrated Circuit, Memory Device and Methods of Manufacturing the Same - An integrated circuit includes: a contact structure with a first stack of at least two conductive layers, and a gate electrode with a second stack of conductive layers, the second stack of layers having the same sequence of conductive layers as the first stack. | 2009-10-01 |
20090242956 | TUNNEL DIELECTRICS FOR SEMICONDUCTOR DEVICES - Tunnel dielectrics for semiconductor devices are generally described. In one example, an apparatus includes a semiconductor substrate, a first tunnel dielectric having a first bandgap coupled to the semiconductor substrate, a second tunnel dielectric having a second bandgap coupled to the first tunnel dielectric, and a third tunnel dielectric having a third bandgap coupled to the second tunnel dielectric wherein the second bandgap is relatively smaller than the first bandgap and the third bandgap. | 2009-10-01 |
20090242957 | ATOMIC LAYER DEPOSITION PROCESSES FOR NON-VOLATILE MEMORY DEVICES - Embodiments of the invention provide memory devices and methods for forming memory devices. In one embodiment, a memory device is provided which includes a floating gate polysilicon layer disposed over source/drain regions of a substrate, a silicon oxynitride layer disposed over the floating gate polysilicon layer, a first aluminum oxide layer disposed over the silicon oxynitride layer, a hafnium silicon oxynitride layer disposed over the first aluminum oxide layer, a second aluminum oxide layer disposed over the hafnium silicon oxynitride layer, and a control gate polysilicon layer disposed over the second aluminum oxide layer. In another embodiment, a memory device is provided which includes a control gate polysilicon layer disposed over an inter-poly dielectric stack disposed over a silicon oxide layer disposed over the floating gate polysilicon layer. The inter-poly dielectric stack contains two silicon oxynitride layers separated by a silicon nitride layer. | 2009-10-01 |
20090242958 | NAND-TYPE NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - The present invention provides a high-performance MONOS-type NAND-type nonvolatile semiconductor memory device using an aluminum oxide film as a part of gate insulating film in a select transistor and as a block insulating film in a memory transistor. The NAND-type nonvolatile semiconductor memory device has, on a semiconductor substrate, a plurality of memory cell transistors connected to each other in series and a select transistor. The memory cell transistor includes a first insulating film on the semiconductor substrate, a charge trapping layer, a second insulating film made of aluminum oxide, | 2009-10-01 |
20090242959 | Flash Memory Cell - A flash memory cell is disclosed in the specification and drawing. The flash memory cell is described and shown with at least one floating gate heavily doped with P-type ions. | 2009-10-01 |
20090242960 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor memory device includes a semiconductor substrate, a memory cell provided on the semiconductor substrate and having a stacked gate structure formed by sequentially stacking a tunnel insulation film, a charge storage layer, a block insulation film, and a control gate electrode, a first transistor having a first gate electrode provided on the semiconductor substrate via a gate insulation film, and a resistor element provided on the semiconductor substrate and formed of polysilicon. The control gate electrode is entirely formed of a silicide layer. An upper portion of the first gate electrode partially includes a silicide layer. | 2009-10-01 |
20090242961 | RECESSED CHANNEL SELECT GATE FOR A MEMORY DEVICE - A memory device comprising one or more recessed channel select gates and at least one charge trapping layer. | 2009-10-01 |
20090242962 | Plasma oxidation of a memory layer to form a blocking layer in non-volatile charge trap memory devices - A blocking layer of a non-volatile charge trap memory device is formed by oxidizing a portion of a charge trapping layer of the memory device. In one embodiment, the blocking layer is grown by a radical oxidation process at temperature below 500° C. In accordance with one implementation, the radical oxidation process involves flowing hydrogen (H | 2009-10-01 |
20090242963 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - In a semiconductor device, the side walls are made of SiO | 2009-10-01 |
20090242964 | NON-VOLATILE MEMORY DEVICE - A finFET-based non-volatile memory device on a semiconductor substrate includes source and drain regions, a fin body, a charge trapping stack and a gate. The fin body extends between the source and the drain region as a connection. The charge trapping stack covers a portion of the fin body and the gate covers the charge trapping stack at the location of the fin body. The fin body has a corner-free shape for at least ¾ of the circumference of the fin body which lacks distinct crystal faces and transition zones in between the crystal faces. | 2009-10-01 |
20090242965 | MEMORY CELL DEVICE HAVING VERTICAL CHANNEL AND DOUBLE GATE STRUCTURE - A memory cell device having a vertical channel and a double gate structure is provided. More specifically, a memory cell device having a vertical channel and a double gate structure is characterized by having a pillar active region with a predetermined height, which is including a first semiconductor layer forming a first source/drain region, a second semiconductor layer being placed under the first semiconductor layer with a predetermined distance and forming a second source/drain region, and a third semiconductor layer forming a body region and a channel region between the first semiconductor layer and the second semiconductor layer, and therefore, there is no need for unnecessary contacts when it is used as a unit cell for any type of memory array, not to speak of NOR type flash memory array. And the present invention makes to program/erase more effectively and increase the read speed and the amount of sensing current. | 2009-10-01 |
20090242966 | Vertical-type semiconductor devices - In a vertical-type memory device and a method of manufacturing the vertical-type memory device, the vertical memory device includes an insulation layer pattern of a linear shape provided on a substrate, pillar-shaped single-crystalline semiconductor patterns provided on both sidewalls of the insulation layer pattern and transistors provided on a sidewall of each of the single-crystalline semiconductor patterns. The transistors are arranged in a vertical direction of the single-crystalline semiconductor pattern, and thus the memory device may be highly integrated. | 2009-10-01 |
20090242967 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A non-volatile semiconductor storage device has a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series. Each of the memory strings comprises: a first columnar semiconductor layer extending in a vertical direction to a substrate; a charge accumulation layer formed around the first columnar semiconductor layer via a first insulation layer; and a first conductive layer formed around the charge accumulation layer via a second insulation layer. Each of the first conductive layers is formed to expand in a two-dimensional manner, and air gaps are formed between the first conductive layers located there above and there below. | 2009-10-01 |
20090242968 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - In a nonvolatile semiconductor memory device, a stacked body is formed by alternately stacking dielectric films and conductive films on a silicon substrate and a plurality of through holes extending in the stacking direction are formed in a matrix configuration. A shunt interconnect and a bit interconnect are provided above the stacked body. Conductor pillars are buried inside the through holes arranged in a line immediately below the shunt interconnect out of the plurality of through holes, and semiconductor pillars are buried inside the remaining through holes. The conductive pillars are formed from a metal, or low resistance silicon. Its upper end portion is connected to the shunt interconnect and its lower end portion is connected to a cell source formed in an upper layer portion of the silicon substrate. | 2009-10-01 |
20090242969 | SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor storage device including a semiconductor substrate including an upper surface having a plurality of trenches formed into the upper surface; a plurality of element isolation insulating films filled in each of the trenches so as to protrude upward from the upper surface of the semiconductor substrate, the element isolation insulating films containing an oxide material; a tunnel insulating film formed on the semiconductor substrate situated between the element isolation insulating films; a charge storing layer comprising a first nitride film and being formed on the tunnel insulating film; a block film formed across an upper surface of the charge storing layer and an upper surface of the element isolation insulating film to prevent charge transfer; a gate electrode formed on the block film; and a barrier layer containing a second nitride film formed between the element isolation insulating film and the block film. | 2009-10-01 |
20090242970 | SEMICONDUCTOR DEVICE, CAPACITOR, AND FIELD EFFECT TRANSISTOR - It is made possible to provide a semiconductor device that has the effective work function of the connected metal optimized at the interface between a semiconductor and the metal. A semiconductor device includes: a semiconductor film; an oxide film formed on the semiconductor film, the oxide film including at least one of Hf and Zr, and at least one element selected from the group consisting of V, Cr, Mn, Nb, Mo, Tc, W, and Re being added to the oxide film; and a metal film formed on the oxide film. | 2009-10-01 |
20090242971 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - In a method of fabricating a semiconductor device on a substrate which includes a plurality of pillar patterns, an impurity region between adjacent pillar patterns, a gate electrode on each pillar pattern, a first capping layer covering the gate electrode, and a separation layer covering the first capping layer between the gate electrodes of adjacent pillar patterns, the first capping layer is removed except for a portion contacting the separation layer, a sacrificial layer is formed to cover the gate electrode, a second capping layer is formed on sidewalls of each pillar pattern, the sacrificial layer is removed and a word line connecting the gate electrodes of the adjacent pillar patterns is formed. In the manufactured device, the first capping layer isolates the impurity region from the word line and the second capping region prevents the sidewalls of the respective pillar pattern from being exposed. | 2009-10-01 |
20090242972 | VERTICAL CHANNEL TRANSISTOR IN SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A method of fabricating a vertical channel transistor for a semiconductor device includes forming, on a substrate, a plurality of active pillars each having a gate electrode formed on and surrounding a lower portion thereof; forming a first insulation layer over the active pillars to fill a gap region between the active pillars; partially removing the first insulation layer to exposes a circumferential surface of the gate electrode in all directions, without exposing the substrate in the gap region between the active pillars; forming a conductive layer on the remaining first insulation layer to fill the gap region between the active pillars; and patterning the conductive layer to form a word line that surrounds and contacts the circumferential surface of the gate electrode in all directions. | 2009-10-01 |
20090242973 | SOURCE AND BODY CONTACT STRUCTURE FOR TRENCH-DMOS DEVICES USING POLYSILICON - A semiconductor device includes a gate electrode, a top source region disposed next to the gate electrode, a drain region disposed below the bottom of the gate electrode, a oxide disposed on top of the source region and the gate electrode, and a doped polysilicon spacer disposed along a sidewall of the source region and a sidewall of the oxide. Methods for manufacturing such device are also disclosed. | 2009-10-01 |
20090242974 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a plurality of trench patterns formed over a substrate; gate insulation layers formed over sidewalls of the trench patterns; gate electrodes formed over the trench patterns; line patterns coupling the gate electrodes; and source and drain regions formed in upper and lower portions of the substrate adjacent to the sidewalls of the trench patterns. | 2009-10-01 |
20090242975 | Vertical pillar transistor - A vertical pillar transistor may include a plurality of lower pillars, a plurality of upper pillars, a first insulation part, a second insulation part and a word line. The plurality of lower pillars protrudes substantially perpendicular to a substrate and is defined by a plurality of trenches. The plurality of lower pillars extends along a second direction and may be separated from each other along a first direction substantially perpendicular to the second direction. The plurality of upper pillars may be formed on the plurality of lower pillars. The plurality of upper pillars has a width substantially smaller than that of the plurality of lower pillars. The first insulation part has a substantially uniform thickness on a sidewall of each of the plurality of lower pillars. The second insulation part may be formed on the first insulation part to fill a gap between the adjacent upper pillars. The word line may be formed on the second insulation part and may extend between facing sidewalls of the adjacent pair of upper pillars along the first direction. | 2009-10-01 |
20090242976 | Semiconductor device - The semiconductor device of the present invention includes a first conductive type semiconductor layer; a second conductive type source region formed in a surface layer portion of the semiconductor layer; a groove formed by digging in the source region from a surface thereof; an insulating film laminated on the semiconductor layer to cover a surface of the semiconductor layer; a contact hole penetrating through the insulating film in a layer thickness direction at least at a position facing the groove; a wiring formed on the insulating film; and a contact plug embedded in the contact hole so that a bottom portion thereof enters the groove to electrically connect the wiring and the source. | 2009-10-01 |
20090242977 | SEMICONDUCTOR DEVICE AND DC-DC CONVERTER - A semiconductor device includes: a semiconductor substrate of a first conductivity type; a semiconductor region provided in the semiconductor substrate; a first trench formed in the semiconductor region; a second trench formed in the semiconductor substrate; a trench gate electrode provided in the first trench; and a trench source electrode provided in the second trench. The trench source electrode is shaped like a stripe and connected to the source electrode through its longitudinal portion. | 2009-10-01 |
20090242978 | Termination Structure for Power Devices - A semiconductor power device includes an active region configured to conduct current when the semiconductor device is biased in a conducting state, and a termination region along a periphery of the active region. The termination region includes a first silicon region of a first conductivity type extending to a first depth within a second silicon region of a second conductivity type, the first and second silicon regions forming a PN junction therebetween. The second silicon region has a recessed portion extending below the first depth and out to an edge of a die housing the semiconductor power device. The recessed portion forms a vertical wall at which the first silicon region terminates. A first conductive electrode extends into the recessed portion and is insulated from the second silicon region. | 2009-10-01 |
20090242979 | Vertical Transistor of Semiconductor Device and Method of Forming the Same - A vertical transistor of a semiconductor device has a channel area formed in a vertical direction to a semiconductor substrate. After semiconductor poles corresponding to the length of semiconductor channels and gate electrodes surrounding sidewalls of the semiconductor poles are formed, subsequent processes of forming silicon patterns corresponding to junction areas, etc. are performed. The gate electrodes support the semiconductor poles during these subsequent processes. The height of the semiconductor poles corresponding to the length of the channel is increased, yet the semiconductor poles do not collapse or incline since the gate electrodes support the semiconductor poles. | 2009-10-01 |
20090242980 | Semiconductor device including capacitor element and method of manufacturing the same - In a semiconductor device, a memory region and a logic region are provided on one silicon substrate. A trench is provided in the silicon substrate in the memory region, a memory cell transistor is provided in the memory region and a logic transistor is provided in the logic region. The memory cell transistor includes a first gate electrode constituted by a metal material. The first gate electrode is provided to be buried in the trench and to protrude outside of the trench. The logic transistor includes a second gate electrode constituted by same material as the metal material constituting the first gate electrode. | 2009-10-01 |
20090242981 | SEMICONDUCTOR DEVICE - A semiconductor device includes: an epitaxial layer; a body layer, formed in the epitaxial layer, which includes a channel region; a source layer disposed in superposition on the body layer; a gate insulator, formed on the epitaxial layer, which is in a ring shape surrounding the source layer; a gate electrode formed through the gate insulator; a drift layer, formed in the epitaxial layer, which is in a ring shape surrounding the body layer; and a drain layer formed in the surface of the epitaxial layer and disposed opposite to the source layer. The body layer is disposed such that the boundary surface at an end in the gate-width direction is in contact with the undersurface of the gate insulator. The gate insulator has a thick film portion thicker than a part above the channel region in the gate-length direction at least in a part where the gate insulator is in contact with the boundary surface of the body layer at the end in the gate-width direction. | 2009-10-01 |
20090242982 | SELF-ALIGNED COMPLEMENTARY LDMOS - The invention includes a laterally double-diffused metal-oxide semiconductor (LDMOS) having a reduced size, a high breakdown voltage, and a low on-state resistance. This is achieved by providing a thick gate oxide on the drain side of the device, which reduces electric field crowding in the off-state to reduce the breakdown voltage and forms an accumulation layer in the drift region to reduce the device resistance in the on-state. A version of the device includes a low voltage version with a thin gate oxide on the source side of the device and a high voltage version of the device includes a thick gate oxide on the source side. The LDMOS may be configured in an LNDMOS having an N type source or an LPDMOS having a P type source. The source of the device is fully aligned under the oxide spacer adjacent the gate to provide a large SOA and to reduce the device leakage. | 2009-10-01 |
20090242983 | SEMICONDUCTOR DEVICE HAVING A FIELD EFFECT TRANSISTOR USING A HIGH DIELECTRIC CONSTANT GATE INSULATING FILM AND MANUFACTURING METHOD OF THE SAME - In a method for manufacturing a semiconductor device having an N-channel field effect transistor, the N-channel field effect transistor is formed by a process including the steps of forming a high dielectric constant gate insulating film on a substrate, forming a gate electrode on the high dielectric constant gate insulating film, forming an extension region by introducing N-type impurities into the substrate by using at least the gate electrode as a mask, and forming a pocket region by introducing P-type impurities under the extension region in the substrate by using at least the gate electrode as a mask. An amount of arsenic (As) that is introduced as the N-type impurities is in a range that is equal to or lower than a prescribed value that is determined based on a thickness of the high dielectric constant gate insulating film. | 2009-10-01 |
20090242984 | Semiconductor device and method of manufacturing the same - Aimed at providing a semiconductor device capable preventing transistor characteristics from departing from design characteristics, the semiconductor device of the present invention has a gate insulating film and a gate electrode positioned over a channel forming region; two second-conductivity-type, high-concentration impurity diffused layers which function as the source and drain of a transistor; two second-conductivity-type, low-concentration impurity diffused layers having a concentration lower than that of the second-conductivity-type, high-concentration impurity diffused layers, provided respectively around the second-conductivity-type, high-concentration impurity diffused layers, so as to expand the second-conductivity-type, high-concentration impurity diffused layers in the depth-wise direction and the channel-length-wise direction; and a first-conductivity-type buried layer having a concentration higher than that of the semiconductor layer, positioned below the second-conductivity-type, low-concentration impurity diffused layers, and extended from an area below the channel forming region via an area below the device isolation film towards the outer periphery of the device isolation film. | 2009-10-01 |
20090242985 | METHOD, STRUCTURE AND DESIGN STRUCTURE FOR CUSTOMIZING HISTORY EFFECTS OF SOI CIRCUITS - A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a high-leakage dielectric formed between a gate electrode and an outer portion of an active region of a FET. Also provided is a structure having a high-leakage dielectric formed between the gate electrode and the active region of the FET and a method of manufacturing such structure. | 2009-10-01 |
20090242986 | MULTI-GATE FIELD EFFECT TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME - A multi-gate field effect transistor includes: a plurality of semiconductor layers arranged in parallel on a substrate; source and drain regions formed in each of the semiconductor layers; channel regions each provided between the source region and the drain region in each of the semiconductor layers; protection films each provided on an upper face of each of the channel regions; gate insulating films each provided on both side faces of each of the channel regions; a plurality of gate electrodes provided on both side faces of each of the channel regions so as to interpose the gate insulating film, provided above the upper face of each of the channel region so as to interpose the protection film, and containing a metal element; a connecting portion connecting upper faces of the gate electrodes; and a gate wire connected to the connecting portion. | 2009-10-01 |
20090242987 | DOUBLE-GATE SEMICONDUCTOR DEVICES HAVING GATES WITH DIFFERENT WORK FUNCTIONS AND METHODS OF MANUFACTURE THEREOF - A double-gate FinFET and methods for its manufacture are provided. The FinFET includes first and second gates ( | 2009-10-01 |
20090242988 | HIGH FREQUENCY SEMICONDUCTOR CIRCUIT DEVICE - A high frequency semiconductor circuit device in which a microwave circuit can be miniaturized is provided, which includes a GaAs substrate; a plurality of FETs formed on the GaAs substrate; and a microstrip line formed on the GaAs substrate and electrically connecting FETs each other, wherein a thickness of a region of the GaAs substrate on which the microstrip line is formed is different from a thickness of a region of the GaAs substrate on which FETs are formed. | 2009-10-01 |
20090242989 | COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR DEVICE WITH EMBEDDED STRESSOR - In one embodiment, the invention is a complementary metal-oxide-semiconductor device with an embedded stressor. One embodiment of a field effect transistor includes a silicon on insulator channel, a gate electrode coupled to the silicon on insulator channel, and a stressor embedded in the silicon on insulator channel and spaced laterally from the gate electrode, where the stressor is formed of a silicon germanide alloy whose germanium content gradually increases in one direction. | 2009-10-01 |
20090242990 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SAME - A FinFET and nanowire transistor with strain direction optimized in accordance with the sideface orientation and carrier polarity and an SMT-introduced manufacturing method for achieving the same are provided. A semiconductor device includes a pMISFET having a semiconductor substrate, a rectangular solid-shaped semiconductor layer formed at upper part of the substrate to have a top surface parallel to a principal plane of the substrate and a sideface with a (100) plane perpendicular to the substrate's principal plane, a channel region formed in the rectangular semiconductor layer, a gate insulating film formed at least on the sideface of the rectangular layer, a gate electrode on the gate insulator film, and source/drain regions formed in the rectangular semiconductor layer to interpose the channel region therebetween. The channel region is applied a compressive strain in the perpendicular direction to the substrate principal plane. A manufacturing method of the device is also disclosed. | 2009-10-01 |
20090242991 | Semiconductor device - Aimed at reducing the area of a protective circuit in a semiconductor device provided therewith, a semiconductor device of the present invention has a first-conductivity-type well, a plurality of first diffusion layers formed in the well, a plurality of second diffusion layers formed in the well, and a diffusion resistance layer formed in the well, wherein the first diffusion layers have a second conductivity type, and are connected in parallel with each other to an input/output terminal of the semiconductor device; the second diffusion layers are arranged alternately with a plurality of first diffusion layers, and are connected to a power source or to the ground; the diffusion resistance layer has a second conductivity type, and is located in adjacent to any of the plurality of second diffusion layers; the diffusion resistance layer is connected to the input/output terminal of the semiconductor device, while being arranged in parallel with the first diffusion layers, and connects the internal circuit and the input/output terminal of the semiconductor device. | 2009-10-01 |
20090242992 | Inverter, logic circuit including an inverter and methods of fabricating the same - An inverter, a logic circuit including the inverter and method of fabricating the same are provided. The inverter includes a load transistor of a depletion mode, and a driving transistor of an enhancement mode, which is connected to the load transistor. The load transistor may have a first oxide layer as a first channel layer. The driving transistor may have a second oxide layer as a second channel layer. | 2009-10-01 |
20090242993 | ESD protection device and manufacturing method thereof - A junction forming region is formed between a drain region of a MOS structure and a device isolation region which surrounds the MOS structure and is in contact with the drain region, to form a PN junction together with the drain region. As a consequence, it is possible to adjust a breakdown voltage of an ESD protection device which is fabricated in the same process as that for an internal device without varying basic performance of the internal device even at a final stage of an LSI manufacturing process. | 2009-10-01 |
20090242994 | HYBRID TRANSISTOR BASED POWER GATING SWITCH CIRCUIT AND METHOD - A method includes forming a first transistor having a first gate dielectric thickness and a first source/drain extension depth, a second transistor having a second gate dielectric thickness and the first source/drain extension depth, and a third transistor having the second gate dielectric thickness and a second source/drain extension depth. The second source/drain extension depth is greater than the first source/drain extension depth. The second gate dielectric thickness is greater than the first gate dielectric thickness. The first transistor is used in a logic circuit. The third transistor is used in an I/O circuit. The second transistor is made without extra processing steps and is better than either the first or third transistor for coupling a power supply terminal to the logic circuit in a power-up mode and decoupling the power supply terminal from the logic circuit in a power-down mode. | 2009-10-01 |
20090242995 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes an isolation region ( | 2009-10-01 |
20090242996 | SOI TRANSISTOR WITH FLOATING BODY FOR INFORMATION STORAGE HAVING ASYMMETRIC DRAIN/SOURCE REGIONS - By laterally asymmetrically defining the well dopant concentration in a floating body storage transistor, an increased well dopant concentration may be provided at the drain side, while a moderately low concentration may remain in the rest of the floating body region. Consequently, compared to conventional symmetric designs, a reduction in the read/write voltages for switching on the parasitic bipolar transistor may be accomplished, while the increased punch-through immunity may allow further scaling of the gate length of the floating body storage transistor. | 2009-10-01 |
20090242997 | METHOD FOR FABRICATING SEMICONDUCTOR STRUCTURE AND STRUCTURE OF STATIC RANDOM ACCESS MEMORY - A method for fabricating a semiconductor structure is disclosed. A substrate with a first transistor having a first dummy gate and a second transistor having a second dummy gate is provided. The conductive types of the first transistor and the second transistor are different. The first and second dummy gates are simultaneously removed to form respective first and second openings. A high-k dielectric layer, a second type conductive layer and a first low resistance conductive layer are formed on the substrate and fill in the first and second openings, with the first low resistance conductive layer filling up the second opening. The first low resistance conductive layer and the second type conductive layer in the first opening are removed. A first type conductive layer and a second low resistance conductive layer are then formed in the first opening, with the second low resistance conductive layer filling up the first opening. | 2009-10-01 |
20090242998 | PENETRATING IMPLANT FOR FORMING A SEMICONDUCTOR DEVICE - A semiconductor device and method to form a semiconductor device is described. The semiconductor includes a gate stack disposed on a substrate. Tip regions are disposed in the substrate on either side of the gate stack. Halo regions are disposed in the substrate adjacent the tip regions. A threshold voltage implant region is disposed in the substrate directly below the gate stack. The concentration of dopant impurity atoms of a particular conductivity type is approximately the same in both the threshold voltage implant region as in the halo regions. The method includes a dopant impurity implant technique having sufficient strength to penetrate a gate stack. | 2009-10-01 |
20090242999 | METHOD FOR ENCAPSULATING A HIGH-K GATE STACK BY FORMING A LINER AT TWO DIFFERENT PROCESS TEMPERATURES - Encapsulation of a gate stack comprising a high-k dielectric material may be accomplished on the basis of a silicon nitride material that is deposited in a sequence of two deposition processes, in which the first process may be performed on the basis of a moderately low process temperature, thereby passivating sensitive surfaces without unduly contaminating the same, while, in a second deposition process, a moderately high process temperature may be used to provide enhanced material characteristics and a reduced overall cycle time compared to conventional ALD or multi-layer deposition techniques. | 2009-10-01 |
20090243000 | METHOD, STRUCTURE AND DESIGN STRUCTURE FOR CUSTOMIZING HISTORY EFFECTS OF SOI CIRCUITS - A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a high-leakage dielectric formed over an active region of a FET and a low-leakage dielectric formed on the active region and adjacent the high-leakage dielectric. The low-leakage dielectric has a lower leakage than the high-leakage dielectric. Also provided is a structure and method of fabricating the structure. | 2009-10-01 |
20090243001 | Sequential deposition and anneal of a dielectic layer in a charge trapping memory device - Deposition and anneal operations are iterated to break a deposition into a number of sequential deposition-anneal operations to reach a desired annealed dielectric layer thickness. In one particular embodiment, a two step anneal is performed including an NH | 2009-10-01 |
20090243002 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device according to one embodiment includes: a semiconductor substrate; a gate electrode formed on the semiconductor substrate via a gate insulating film; a first silicide layer formed on the gate electrode; a channel region formed in the semiconductor substrate below the gate electrode; source/drain regions formed in regions in the semiconductor substrate, the regions sandwiching the channel region; and second silicide layers formed on the source/drain regions and having an average grain size smaller than that of the first silicide layer or an average number of compositional boundaries in a crystal grain larger than that of the first silicide layer. | 2009-10-01 |
20090243003 | MANUFACTURING METHOD OF A GAS SENSOR INTEGRATED ON A SEMICONDUCTOR SUBSTRATE - A method manufactures a gas sensor integrated on a semiconductor substrate. The method includes: realizing a first plurality of openings in the semiconductor substrate; realizing a crystalline silicon membrane suspended on the semiconductor substrate, forming an insulating cavity buried in the substrate; realizing a second plurality of openings in the semiconductor substrate, so as to totally suspend on the semiconductor substrate the crystalline silicon membrane; realizing, through a thermal oxidation process of the totally suspended crystalline silicon membrane, a suspended dielectric membrane; realizing, through selective photolithography, a heating element; realizing, through selective photolithography, electrodes and a pair of electric contacts; and selectively realizing, above the electrodes, a sensitive element by compacting layers of metallic oxide through a sintering process generated in the gas sensor by connecting the electrodes to a voltage generator. | 2009-10-01 |
20090243004 | Integrated structure for MEMS device and semiconductor device and method of fabricating the same - The present invention relates to an integrated structure for a MEMS device and a semiconductor device and a method of fabricating the same, in which an etch stopping device is included on a substrate between the MEMS device and the semiconductor device for protecting the semiconductor device from lateral damage when an oxide releasing process is performed to fabricate the MEMS device. The etch stopping device has various profiles and is selectively formed by an individual fabricating process or is simultaneously formed with the semiconductor device in the same fabricating process. It is a singular structure or a combined stacked multilayered structure, for example, a plurality of rows of pillared etch-resistant material plugs, one or a plurality of wall-shaped etch-resistant material plugs, or a multilayered structure of a stack of which and an etch-resistant material layer. | 2009-10-01 |
20090243005 | Semiconductor physical quantity sensor and method for manufacturing the same - A method for manufacturing a semiconductor physical quantity sensor having a fixed portion, a movable portion and an output terminal includes: forming a metal layer on a semiconductor layer; forming a resist on the metal layer; forming an opening and a side etching hole in the resist; anisotropically etching the metal layer via the opening and the hole; anisotropically etching the semiconductor layer via the opening so that the fixed portion is formed in the semiconductor layer; and side etching the metal layer from the opening and the hole so that the output terminal is formed on a part of the fixed portion, and a metal member is formed on another part of the fixed portion in such a manner that the metal member is electrically separated from the output terminal. | 2009-10-01 |
20090243006 | ELECTRONIC PART WITH AFFIXED MEMS - According to an aspect of the invention, an electronic part includes a substrate having a first planar surface, a first bump affixed to the first planar surface of the substrate, a second bump affixed to the first planar surface of the substrate a predetermined distance from the first bump, a MEMS chip including a element, the MEMS chip coupled to the first bump and the second bump, the MEMS chip distanced from the first planar surface, an adhesive region bonding with the first bump, the substrate and the MEMS chip. | 2009-10-01 |
20090243007 | SPIN-DEPENDENT TUNNELLING CELL AND METHOD OF FORMATION THEREOF - A Spin-Dependent Tunnelling cell comprises a first barrier layer of a first material and a second barrier layer of a second material sandwiched between a first ferromagnetic layer and a second ferromagnetic layer. The first and second barrier layers are formed to a combined thicknesses so that a Tunnelling Magnetoresistance versus voltage characteristic of the cell has a maximum at a non-zero bias voltage. | 2009-10-01 |
20090243008 | MAGNETORESISTIVE ELEMENT AND MAGNETIC MEMORY - A magnetoresistive element includes an underlying layer having a cubic or tetragonal crystal structure oriented in a (001) plane, a first magnetic layer provided on the underlying layer, having perpendicular magnetic anisotropy, and having an fct structure oriented in a (001) plane, a non-magnetic layer provided on the first magnetic layer, and a second magnetic layer provided on the non-magnetic layer, and having perpendicular magnetic anisotropy. An in-plane lattice constant a | 2009-10-01 |
20090243009 | Magnetic Tunnel Junction Cell Including Multiple Vertical Magnetic Domains - Magnetic tunnel junction cell including multiple vertical domains. In an embodiment, a magnetic tunnel junction (MTJ) structure is disclosed. The MTJ structure includes an MTJ cell. The MTJ cell includes multiple vertical side walls. Each of the multiple vertical side walls defines a unique vertical magnetic domain. Each of the unique vertical magnetic domains is adapted to store a digital value. | 2009-10-01 |
20090243010 | THINFILM DEPOSITION METHOD, THINFILM DEPOSITION APPARATUS, AND THINFILM SEMICONDUCTOR DEVICE - A substrate holding unit, a plasma treatment chamber, and a nanoparticle supplying chamber are housed in a single chamber. The substrate holding unit holds a substrate. The plasma treatment chamber includes a gas passage for introducing a source gas to a vicinity of the substrate and a plasma generating unit that generates a plasma from the source gas. The nanoparticle supplying chamber includes a spraying member for spraying a nanoparticle-containing medium onto a surface of the substrate. | 2009-10-01 |
20090243011 | Manufacturing Optical MEMS with Thin-Film Anti-Reflective Layers - In accordance with the teachings of one embodiment of the present disclosure, a method for manufacturing a semiconductor device includes forming a support structure outwardly from a substrate. The support structure has a first thickness and a first outer sidewall surface that is not parallel with the substrate. The first outer sidewall surface has a first minimum refractive index. A first anti-reflective layer is formed outwardly from the support structure and outwardly from the substrate. A second anti-reflective layer is formed outwardly from the first anti-reflective layer. The first and second anti-reflective layers each includes respective compounds of at least two elements selected from the group consisting of: silicon; nitrogen; and oxygen. | 2009-10-01 |
20090243012 | ELECTROMAGNETIC INTERFERENCE SHIELD STRUCTURES FOR SEMICONDUCTOR COMPONENTS - A microelectronic device assembly with an integrated conductive shield is disclosed herein. The microelectronic device assembly includes a semiconductor substrate, an integrated circuit carried by the semiconductor substrate, a dielectric encapsulant encasing at least a portion of the semiconductor substrate. The microelectronic device assembly also includes a conductive shield in direct contact with at least a portion of the dielectric encapsulant and an interconnect extending through the semiconductor substrate and in direct contact with the conductive shield. | 2009-10-01 |
20090243013 | SEMICONDUCTOR PHOTORECEPTOR DEVICE - A semiconductor light detecting device includes an n-contact layer selectively disposed on an Fe—InP substrate. An optical waveguide layer is disposed on the n-contact layer and includes an n-cladding layer, a light absorption layer, and a p-cladding layer, laminated on one another over the n-contact layer, in that order. An Fe—InP current blocking layer is disposed on the n-cladding layer such that sides of the optical waveguide layer are buried in the Fe—InP current blocking layer. A p-electrode includes a contact electrode electrically connected to the p-cladding layer of the optical waveguide layer, a lead-out electrode portion extending on a side wall of the current blocking layer from the contact electrode and extending on the Fe—InP substrate, and an electrode pad disposed on a surface of the Fe—InP substrates with an SiN film between the electrode pad and the surface of the Fe—InP substrate and connected to the lead-out electrode portion. | 2009-10-01 |
20090243014 | Image Sensor - Disclosed is an image sensor. The image sensor includes a substrate having photodiodes therein; a dielectric layer on the substrate; a passivation layer on the dielectric layer exposing the dielectric layer in a region corresponding to a first color filter; and a color filter layer on the exposed dielectric layer and the passivation layer. | 2009-10-01 |
20090243015 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor device, includes the steps of: forming a resin layer on an upper surface of a substrate including a photodiode such that the resin layer does not cover a light receiving region of the photodiode; forming at least one groove in the resin layer so as to surround the light receiving region; and subsequently mold-sealing the photodiode by loading the substrate into a mold and filling the mold with a molding resin. | 2009-10-01 |
20090243016 | SEMICONDUCTOR DEVICE - An apparatus is provided. The apparatus generally comprises a photoreceptive region and a circuit region formed in a substrate. A multilayer wiring region is then formed on the substrate over at least a portion of the circuit region. The multilayer wiring region includes a wiring layer and a light-blocking layer. The wiring layer is coupled to the circuit region, and the light-blocking wall has a metal layer that is arranged along at least a portion of the perimeter of the photoreceptive region and that is formed in the same process step as the wiring layer. | 2009-10-01 |
20090243017 | METHOD OF MANUFACTURING SOLID STATE IMAGING DEVICE, SOLID STATE IMAGING DEVICE, AND CAMERA USING SOLID STATE IMAGING DEVICE - A method of manufacturing a solid state imaging device having a photo-electric conversion portion array and a transfer electrode array, these arrays being provided in parallel to each other, upper surfaces and side wall surfaces of the transfer electrode array being covered with a light-shielding layer, and a transparent layer showing an oxidizing property at the time of film formation, the transparent layer being formed on the photo-electric conversion parts and the light-shielding layer. | 2009-10-01 |
20090243018 | HYBRID INORGANIC-ORGANIC POLYMER COMPOSITIONS FOR ANTI-REFLECTIVE COATINGS - An organic-inorganic composition, which has a backbone containing —Si—O— units with chromophore groups attached directly to at least a part of the silicon atoms. The film forming composition and resulting coating properties can be tailored to suit the specific exposure wavelength and device fabrication and design requirements. By using two different chromophores the refractive index and the absorption co-efficient can be efficiently tuned and a desired Si-content of the anti-reflective coating composition can be obtained—a high Si-content will give good mechanical and thermal properties and also the required wet etch and dry etch properties. | 2009-10-01 |
20090243019 | OPTICAL SENSING DEVICE INCLUDING VISIBLE AND UV SENSORS - An optical sensing device includes a silicon-on-insulator (SOI) substrate a semiconductor support substrate, an insulating layer located on the semiconductor support substrate, and a semiconductor layer located on the insulating layer. The optical sensing device further includes a visible light sensor located in the semiconductor support substrate, and an ultraviolet ray sensor located in the semiconductor layer. | 2009-10-01 |
20090243020 | Producing Layered Structures With Layers That Transport Charge Carriers - Layered structures such as photosensing arrays include layers in which charge carriers can be transported. For example, a carrier-transporting substructure that includes a solution processing artifact can transport charge carriers that flow to or from it through charge-flow surface parts that are on electrically conductive regions of a circuitry substructure; the circuitry substructure can also have channel surface parts that are on semiconductive channel regions, with a set of the channel regions operating as acceptable switches in an application. Or a first substructure's surface can have carrier-active surface parts on electrode regions and line surface parts on line regions; a second substructure can include a transport layer on carrier-active surface parts and, over it, an electrically conductive layer; to prevent leakage, an open region can be defined in the electrically conductive layer over the line surface part and/or an electrically insulating layer portion can cover the line surface part. | 2009-10-01 |
20090243021 | ISOLATION STRUCTURES FOR PREVENTING PHOTONS AND CARRIERS FROM REACHING ACTIVE AREAS AND METHODS OF FORMATION - Regions of an integrated circuit are isolated by a structure that includes at least one isolating trench on the periphery of an active area. The trench is deep, extending at least about 0.5 μm into the substrate. The isolating structure prevents photons and electrons originating in peripheral circuitry from reaching the active area. Where the substrate has a heavily-doped lower layer and an upper layer on it, the trench can extend through the upper layer to the lower layer. A thermal oxide can be grown on the trench walls. A liner can also be deposited on the sidewalls of each trench. A fill material having a high-extinction coefficient is then deposited over the liner. The liner can also be light absorbent so that both the liner and fill material block photons. | 2009-10-01 |
20090243022 | METHOD OF FORMING MASK FOR LITHOGRAPHY, METHOD OF FORMING MASK DATA FOR LITHOGRAPHY, METHOD OF MANUFACTURING BACK-ILLUMINATED SOLID-STATE IMAGING DEVICE, BACK-ILLUMINATED SOLID-STATE IMAGING DEVICE AND ELECTRONIC DEVICE - A method of forming a mask for lithography includes the step of forming the mask by using reverse data in which positions of at least part of output terminals are reversed, when forming the mask for lithography used for manufacturing a back-illuminated solid-state imaging device which takes incident light from the side of a surface opposite to the side of a surface on which wiring of a device region in which photoelectric conversion elements are formed is formed. | 2009-10-01 |
20090243023 | DUAL SEED SEMICONDUCTOR PHOTODETECTORS - Dual seed semiconductor photodetectors and methods to fabricate thereof are described. A dual seed semiconductor photodetector is formed directly on an insulating layer on a substrate. The dual seed semiconductor photodetector includes an optical layer formed on a dual seed semiconductor layer. The dual seed semiconductor layer includes a seed layer and a buffer layer. The seed layer of a first material is formed on an insulating layer over a substrate. The buffer layer is formed on the seed layer. Next, an optical layer of a second material is formed on the buffer layer. The buffer layer includes the first material and the second material. In one embodiment, the first material is silicon. In one embodiment, the second material is germanium. | 2009-10-01 |
20090243024 | WIRING BOARD AND SOLID-STATE IMAGING DEVICE - Provided are a wiring board capable of mounting either a frontside incident type solid-state imaging element and a backside incident type solid-state imaging element and a solid-state imaging device. The wiring board | 2009-10-01 |
20090243025 | PIXEL STRUCTURE WITH A PHOTODETECTOR HAVING AN EXTENDED DEPLETION DEPTH - An image sensor includes an imaging area that includes a plurality of pixels that are formed in a substrate layer of a first conductivity type. Each pixel includes a collection region that is formed in a portion of the substrate layer and doped with a dopant of a first conductivity type. A plurality of wells are disposed in portions of the substrate layer and doped with another dopant of the second conductivity type. Each well is positioned laterally adjacent to each collection region. A buried layer spans the imaging area and is disposed in a portion of the substrate layer that is beneath the photodetectors and the wells. The buried layer is doped with a dopant of a second conductivity type. Each collection region, each well, and the buried layer are formed such that a region of the substrate layer having substantially the same doping as the substrate layer resides between each collection region and the buried layer. | 2009-10-01 |
20090243026 | Schottky Barrier Diode and Method for Using the Same - An intermediate metal film is formed between a Schottky electrode and a pad electrode. A Schottky barrier height between the intermediate metal film and a silicon carbide epitaxial film is equivalent to or higher than a Schottky barrier height between the Schottky electrode and the silicon carbide epitaxial film. By this configuration, an excess current and a leak current through a pin-hole can be suppressed even in the case in which a Schottky barrier height between the pad electrode and the silicon carbide epitaxial film is less than the Schottky barrier height between the Schottky electrode and the silicon carbide epitaxial film. | 2009-10-01 |
20090243027 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND A METHOD OF MANUFACTURING THE SAME - To achieve a further reduction in the size of a finished product by reducing the number of externally embedded parts, the embedding of a Schottky barrier diode which is relatively large in the amount of current in a semiconductor integrated circuit device has been pursued. In such a case, it is general practice to densely arrange a large number of contact electrodes in a matrix over a Schottky junction region. It has been widely performed to perform a sputter etching process with respect to the surface of a silicide layer at the bottom of each contact hole before a barrier metal layer is deposited. However, in a structure in which electrodes are thus arranged over a Schottky junction region, a reverse leakage current in a Schottky barrier diode is varied by variations in the amount of sputter etching. The present invention is a semiconductor integrated circuit device having a Schottky barrier diode in which contact electrodes are arranged over a guard ring in contact with a peripheral isolation region. | 2009-10-01 |
20090243028 | CAPACITIVE ISOLATION CIRCUITRY WITH IMPROVED COMMON MODE DETECTOR - An integrated circuit having voltage isolation capabilities comprising a first galvanically isolated area of the integrated circuit containing a first group of functional circuitry for processing a data stream. The first group of functional circuitry located in a substrate of the integrated circuit. Capacitive isolation circuitry located in conductive layers of the integrated circuit provides a high voltage isolation link between the first group of functional circuitry and a second group of functional circuitry connected to the integrated circuit through the capacitive isolation circuitry. The capacitive isolation circuitry includes a differential transmitter for transmitting data in a differential signal to the second group of functional circuitry via the capacitive isolation circuitry. A differential receiver receives data within the differential signal from the second group of functional circuitry via the capacitive isolation circuitry. A detector circuit within the differential receiver detects the received data. The detector circuit monitors the differential signal and generates a first logical output when a voltage generated responsive to the differential signal exceeds a programmable voltage threshold level and generates a second logical output when the voltage generated responsive to the differential signal falls below the programmable voltage threshold level. | 2009-10-01 |
20090243029 | METHOD, STRUCTURE AND DESIGN STRUCTURE FOR CUSTOMIZING HISTORY EFFECTS OF SOI CIRCUITS - A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a structure which comprises a high-leakage dielectric formed in a divot on each side of a segmented FET comprised of active silicon islands and gate electrodes thereon, and a low-leakage dielectric on the surface of the active silicon islands, adjacent the high-leakage dielectric, wherein the low-leakage dielectric has a lower leakage than the high-leakage dielectric. Also provided is a structure and method of fabricating the structure. | 2009-10-01 |
20090243030 | METHOD OF FORMING SHALLOW TRENCH ISOLATION STRUCTURE - A method of fabricating an isolation structure and the structure thereof is provided. The method is compatible with the embedded memory process and provides the isolation structure with a poly cap thereon to protect the top corners of the isolation structure, without using an extra photomask. | 2009-10-01 |
20090243031 | STRUCTURE AND METHOD TO CONTROL OXIDATION IN HIGH-K GATE STRUCTURES - In one embodiment, the present invention provides a method of fabricating a semiconducting device that includes providing a substrate including at least one semiconducting region and at least one oxygen source region; forming an oxygen barrier material atop portions of an upper surface of the at least one oxygen region; forming a high-k gate dielectric on the substrate including the at least one semiconducting region, wherein oxygen barrier material separates the high-k gate dielectric from the at least one oxygen source material; and forming a gate conductor atop the high-k gate dielectric. | 2009-10-01 |
20090243032 | ELECTRICAL FUSE STRUCTURE - An e-fuse structure includes a cathode block; a plurality of cathode contact plugs on the cathode block; an anode block; a plurality of anode contact plugs on the cathode block; and a fuse link connecting the cathode block with the anode block, wherein a front row of the cathode contact plugs is disposed in close proximity to the fuse link thereby inducing a high thermal gradient at an interface between the cathode block and the fuse link. | 2009-10-01 |
20090243033 | FUSE PART IN SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A fuse part in a semiconductor device has a plurality of fuse lines extended along a first direction with a given width along a second direction. The fuse part includes a first conductive pattern having a space part formed in a fuse line region over a substrate, wherein portions of the first conductive pattern are spaced apart by the space part along the first direction. The fuse part includes a first insulation pattern formed over the space part, the first insulation pattern having a width smaller than a width of the first conductive pattern along the second direction and a thickness greater than a thickness of the first conductive pattern, and a second conductive pattern formed over the first insulation pattern, the second conductive pattern having a width greater than the width of the first insulation pattern along the second direction. | 2009-10-01 |
20090243034 | SEMICONDUCTOR DEVICE - A semiconductor device including a doped substrate of a first doping polarity and a doped semiconductor material of a second doping polarity. The semiconductor material is on, or in, the substrate, and the second doping polarity is opposite the first doping polarity such that the semiconductor material and the substrate form a diode. The semiconductor device further includes an inductor on or above the semiconductor material, and a pattern in the semiconductor material for reducing eddy currents. The pattern includes a doped semiconductor material of the first doping polarity and a least one trench within the doped semiconductor material of the first doping polarity, wherein, at least at a depth at which the trench is closest to the inductor, the doped semiconductor material of the first doping polarity fully surrounds the trench so that, at least at the depth, the trench does not touch the doped semiconductor material of the second doping polarity. | 2009-10-01 |