39th week of 2021 patent applcation highlights part 70 |
Patent application number | Title | Published |
20210305123 | Package and Method for Manufacturing the Same - A package includes a die having a first side and a second side opposite to each other. The package also includes an encapsulating material surrounding the die. The package further includes a redistribution layer (RDL) structure disposed over the first side of the die and the encapsulating material. The package yet includes a heat dissipating feature disposed over the second side of the die and the encapsulating material. In addition, the package includes a first screw assembly penetrating through the die, the RDL structure and the heat dissipating feature. | 2021-09-30 |
20210305124 | Control of Thermal Interface Material in Multi-Chip Package - An electronic system includes a plurality of heat sources. At least two of the plurality of heat sources vary in height and each of the plurality of heat sources includes a first side and a second side. The electronic system also includes a substrate having a first side and a second side. The second side of each of the plurality of heat sources is positioned adjacent to the first side of the substrate. The electronic system further includes a cover member provided above the plurality of heat sources and a sintering thermal interface material provided between the cover member and the first side of one of the at least two heat sources that vary in height. | 2021-09-30 |
20210305125 | APPARATUS AND METHOD FOR HOLDING A HEAT GENERATING DEVICE - Systems, apparatuses, and methods are described for clamping a heat generating device such as a thyristor in place. The use of spring washers in various configurations is described. A spring washing washer may be used to apply force to a pad which in turn applies the force to a plate above a heat generating device. The plate above the heat generating device may apply downward pressure, which may force the heat generating device against a lower surface. Related systems, apparatuses, and methods are also described. | 2021-09-30 |
20210305126 | PACKAGE WITH CLIP AND CONNECTOR ABOVE ELECTRONIC COMPONENTS - A package which comprises a carrier, electronic components mounted on the carrier, an encapsulant at least partially encapsulating the carrier and the electronic components, a clip connected to upper main surfaces of the electronic components, and an electrically conductive bulk connector which is electrically connected with and mounted above the electronic components. | 2021-09-30 |
20210305127 | HETEROGENEOUS INTEGRATION MODULE COMPRISING THERMAL MANAGEMENT APPARATUS - Some examples described herein provide for a heterogeneous integration module (HIM) that includes a thermal management apparatus. In an example, an apparatus (e.g., a HIM) includes a wiring substrate, a first component, a second component, and a thermal management apparatus. The first component and the second component are communicatively coupled together via the wiring substrate. The thermal management apparatus is in thermal communication with the first component and the second component. The thermal management apparatus has a first thermal energy flow path for dissipating thermal energy generated by the first component and has a second thermal energy flow path for dissipating thermal energy generated by the second component. The first thermal energy flow path has a lower thermal resistivity than the second thermal energy flow path. | 2021-09-30 |
20210305128 | THERMAL PACKAGING WITH FAN OUT WAFER LEVEL PROCESSING - An opto-electronic package is described. The opto-electronic package is manufactured using a fan out wafer level packaging to produce dies/frames which include connection features. Additional structures such as heat exchanged structures are joined to a connection component and affixed to packages, using the connection features, to provide structural support and heat exchange to heat generating components in the package, among other functions. | 2021-09-30 |
20210305129 | LIQUID-COOLING RADIATOR MODULE - A liquid-cooling radiator module includes a first reservoir, a second reservoir, a heat dissipation stacked structure, a radiator inlet and a radiator outlet. The first reservoir includes a first chamber and a second chamber. The second reservoir includes a third chamber and a fourth chamber. A fin tube layer of the heat dissipation stacked structure is sandwiched between the first reservoir and the second reservoir. The radiator inlet is connected to the first reservoir and the first chamber. The radiator outlet is connected to the second reservoir and the fourth chamber. A part of fin tubes of the fin tube layer communicates with the first chamber and the third chamber, another part of the fin tubes communicates with the third chamber and the second chamber, and one another part of the fin tubes communicates with the second chamber and the fourth chamber. | 2021-09-30 |
20210305130 | INTEGRATED CIRCUIT SEMICONDUCTOR DEVICE INCLUDING THROUGH SILICON VIA - An integrated circuit semiconductor device includes a substrate including a first surface and a second surface opposite the first surface, a trench in the substrate, the trench extending from the first surface of the substrate toward the second surface of the substrate, a through silicon via (TSV) landing part in the trench, the TSV landing part having a first portion spaced apart from the first surface of the substrate, and a second portion between the first portion and the first surface of the substrate, the first portion being wider than the second portion, a TSV hole in the substrate, the TSV hole extending from the second surface of the substrate and aligned with a bottom surface of the TSV landing part, and a TSV in the TSV hole and in contact with the bottom surface of the TSV landing part. | 2021-09-30 |
20210305131 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - The present disclosure provides a semiconductor structure, including: a semiconductor device layer including a first surface and a second surface, wherein the first surface is at a front side of the semiconductor device layer, and the second surface is at a backside of the semiconductor device layer; an insulating layer above the second surface of the semiconductor device; and a through-silicon via (TSV) traversing the insulating layer. Associated manufacturing methods of the same are also provided. | 2021-09-30 |
20210305132 | OPEN CAVITY BRIDGE CO-PLANAR PLACEMENT ARCHITECTURES AND PROCESSES - Embodiments disclosed herein include multi-die packages with open cavity bridges. In an example, an electronic apparatus includes a package substrate having alternating metallization layers and dielectric layers. The package substrate includes a first plurality of substrate pads and a second plurality of substrate pads. The package substrate also includes an open cavity between the first plurality of substrate pads and the second plurality of substrate pads, the open cavity having a bottom and sides. The electronic apparatus also includes a bridge die in the open cavity, the bridge die including a first plurality of bridge pads, a second plurality of bridge pads, and conductive traces. An adhesive layer couples the bridge die to the bottom of the open cavity. A gap is laterally between the bridge die and the sides of the open cavity, the gap surrounding the bridge die. | 2021-09-30 |
20210305133 | OPEN CAVITY BRIDGE POWER DELIVERY ARCHITECTURES AND PROCESSES - Embodiments disclosed herein include multi-die packages with open cavity bridges. In an example, an electronic apparatus includes a package substrate having alternating metallization layers and dielectric layers. The package substrate includes a first plurality of substrate pads and a second plurality of substrate pads, and an open cavity. A bridge die is in the open cavity, the bridge die including a first plurality of bridge pads, a second plurality of bridge pads, a power delivery bridge pad between the first plurality of bridge pads and the second plurality of bridge pads, and conductive traces. A first die is coupled to the first plurality of substrate pads and the first plurality of bridge pads. A second die is coupled to the second plurality of substrate pads and the second plurality of bridge pads. A power delivery conductive line is coupled to the power delivery bridge pad. | 2021-09-30 |
20210305134 | METHOD OF PRODUCING ELECTRONIC COMPONENTS, CORRESPONDING ELECTRONIC COMPONENT - A method of producing electronic components including at least one circuit having coupled therewith electrical connections including metallic wire bondable surfaces encased in a packaging, the method including bonding stud bumps, in particular copper stud bumps, at determined areas of said wire bondable surfaces. | 2021-09-30 |
20210305135 | SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING A SEMICONDUCTOR PACKAGE - A semiconductor package is disclosed. In one example, the semiconductor package comprises a semiconductor chip, a molded body encapsulating the semiconductor chip and comprising a top face and an opposing bottom face and four side faces connecting the top and bottom faces, and a plurality of electrical contacts arranged on two of the side faces of the molded body, wherein the other two side faces are metal-free side faces, and wherein the molded body comprises a cut surface at no more than one of the side faces. | 2021-09-30 |
20210305136 | PACKAGE STRUCTURE - A package structure includes a leadframe, a semiconductor die and a plastic package material. The leadframe includes a die pad and a plurality of leads. The leads are disposed on four sides of the die pad, and each of the leads includes a plurality of plating surfaces. The semiconductor die is disposed on the die pad of the leadframe. The plastic package material is disposed on the leadframe. Each of the leads protrudes an outer region of the plastic package material. | 2021-09-30 |
20210305137 | IoT and AI System Package with Solid-State Battery Enhanced Performance - An energy storage device for an integrated circuit carrier package. One or more energy storage elements have contact elements arranged thereon that include an anode, a cathode, and an isolated common pad. The energy storage element is configured for arrangement in a stack of energy storage elements in which the isolated common pad is shorted to one of the anode or the cathode by bonded conductive interconnects. | 2021-09-30 |
20210305138 | PACKAGE LAND PAD IN CLOSED-LOOP TRACE FOR HIGH SPEED DATA SIGNALING - Embodiments disclosed herein include electronic packaged assemblies. In an embodiment, an electronic package comprises first and second surfaces. The second surface has a land pad in a land pad opening. The land pad is spaced away from the land pad opening by an outer gap. The land pad is a closed loop. In an embodiment, the electronic package is electrically coupled to a socket. The socket has an interconnect with a first connector and a second connector. The first connector of the interconnect is directly coupled to at least one portion of the closed loop. In an embodiment, when the first connector is coupled to at least two or more portions of the closed loop, the portions are spaced away from each other by a portion of the inner or outer gap. The closed loop comprises a conductive line continuously extending from a first end to a second end. | 2021-09-30 |
20210305139 | PACKAGED ELECTRONIC DEVICE WITH SPLIT DIE PAD IN ROBUST PACKAGE SUBSTRATE - In a described example, an apparatus includes a package substrate with a split die pad having a slot between a die mount portion and a wire bonding portion; a first end of the wire bonding portion coupled to the die mount portion at one end of the slot; a second end of the wire bonding portion coupled to a first lead on the package substrate. At least one semiconductor die is mounted on the die mount portion; a first end of a first wire bond is bonded to a first bond pad on the at least one semiconductor die; a second end of the first wire bond is bonded to the wire bonding portion; and mold compound covers the at least one semiconductor die, the die mount portion, the wire bonding portion, and fills the slot. | 2021-09-30 |
20210305140 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A semiconductor package and a manufacturing method are provided. The manufacturing method includes: forming a through via structure and a dipole structure over a carrier, wherein the through via structure and the dipole structure respectively include an insulating core and a conductive layer covering the insulating core; attaching a semiconductor die onto the carrier, wherein the through via structure and the dipole structure are located aside the semiconductor die; laterally encapsulating the though via structure, the dipole structure and the semiconductor die with an encapsulant; and removing the carrier. | 2021-09-30 |
20210305141 | HYBRID PACKAGE APPARATUS AND METHOD OF FABRICATING - Some features pertain to a hybrid package that includes a die, a first substrate structure, and a first metallization structure that is at least partially coplanar with the substrate. The die is electrically coupled to the first metallization structure and the first substrate through a second metallization structure. The first metallization structure is configured to provide an electrical path for data signaling. The second metallization structure is configured as a ground plane and is coupled to a ground signal. The first substrate structure is configured to provide an electrical path for power signaling. | 2021-09-30 |
20210305142 | PACKAGED INTEGRATED DEVICE - Disclosed is an integrated circuit die of a memory buffer integrated circuit that is placed aggregately closer to the solder balls that connect to the input (i.e., host command/address—C/A) signals than the output solder balls (i.e., memory device C/A) signals. This decreases the length of the host C/A signals from the memory controller to the memory buffer device when the memory module is placed in a system. | 2021-09-30 |
20210305143 | SEMICONDUCTOR STRUCTURE EMPLOYING CONDUCTIVE PASTE ON LEAD FRAME - A semiconductor structure is provided. The semiconductor structure includes a base, a seed layer, a compound semiconductor layer, a gate structure, a source structure, a drain structure, and a conductive paste. The seed layer is disposed on the base. The compound semiconductor layer is disposed on the seed layer. The gate structure is disposed on the compound semiconductor layer. The source structure and the drain structure are disposed on both sides of the gate structure. In addition, the conductive paste is disposed between the base and a lead frame, and the conductive paste extends to the side surface of the base. | 2021-09-30 |
20210305144 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device including an insulating circuit board. The insulating circuit board has an insulating plate, a plurality of circuit patterns disposed on a front surface of the insulating plate, any adjacent two of the circuit patterns having a gap therebetween, each circuit pattern having at least one corner, each corner being in a corner area that covers the corner and a portion of each gap adjacent to the corner, and a buffer material containing resin, applied at a plurality of corner areas, to fill the gaps in the plurality of corner areas. | 2021-09-30 |
20210305145 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least one semiconductor die, an interposer, a molding compound and connectors. The interposer has a first surface, a second surface opposite to the first surface and sidewalls connecting the first and second surfaces. The at least one semiconductor die is disposed on the first surface of interposer and electrically connected with the interposer. The molding compound is disposed over the interposer and laterally encapsulates the at least one semiconductor die. The molding compound laterally wraps around the interposer and the molding compound at least physically contacts a portion of the sidewalls of the interposer. The connectors are disposed on the second surface of the interposer, and are electrically connected with the at least one semiconductor die through the interposer. | 2021-09-30 |
20210305146 | CHIP-ON-WAFER STRUCTURE WITH CHIPLET INTERPOSER - A method of forming a semiconductor structure includes bonding a first die and a second die to a first side of a first interposer and to a first side of a second interposer, respectively, where the first interposer is laterally adjacent to the second interposer; encapsulating the first interposer and the second interposer with a first molding material; forming a first recess in a second side of the first interposer opposing the first side of the first interposer; forming a second recess in a second side of the second interposer opposing the first side of the second interposer; and filling the first recess and the second recess with a first dielectric material. | 2021-09-30 |
20210305147 | SEMICONDUCTOR DEVICE - A semiconductor device according to an embodiment includes: an insulating substrate having a first metal layer and a second metal layer on a surface of the insulating substrate; a semiconductor chip including an upper electrode and a lower electrode, the upper electrode being electrically connected to the first metal layer, the lower electrode being electrically connected to the second metal layer; a first main terminal including a first end and a second end, the first end being electrically connected to the first metal layer; a second main terminal including a third end and a fourth end, the third end being electrically connected to the second metal layer; a first detection terminal being electrically connected between the first end and the second end of the first main terminal; and a second detection terminal being electrically connected to the first metal layer. | 2021-09-30 |
20210305148 | ELECTRONIC PACKAGE, SUPPORTING STRUCTURE AND FABRICATION METHOD THEREOF - A supporting structure is provided, which forms a protective layer on a metal member having a plurality of conductive posts, and the protective layer is exposed from end surfaces of the conductive posts, such that conductors are formed on the end surfaces of the conductive posts, thereby avoiding damage of the protective layer. | 2021-09-30 |
20210305149 | Battery-free and Substrate-free IoT and AI System Package - A tetherless system-in-package includes a first integrated circuit (IC) chip having interconnects and energy harvesting elements. A super-capacitor is configured to store a charge output by the energy harvesting elements. At least a second IC chipset including a smart chip and an optical I/O or an RF I/O is aligned and bonded to at least one of the interconnects of the first IC chip. The first IC chip and the second IC chip are configured to receive a portion of the charge stored by the super-capacitor. | 2021-09-30 |
20210305150 | MEMORY DEVICE - A memory device including a substrate; a lower conductive layer on the substrate; a stacked structure including gate layers and interlayer insulating layers alternately stacked on the lower conductive layer; a channel structure in a channel hole that penetrates the stacked structure in a vertical direction; and a common source line structure in a common source line trench that penetrates the lower conductive layer and the stacked structure in the vertical direction. The common source line structure includes a side insulating layer on a side surface of the common source line trench, a central insulating layer at a central portion of the common source line trench, an intermediate conductive layer between the side insulating layer and the central insulating layer, and an upper conductive layer at an upper portion of the common source line trench. | 2021-09-30 |
20210305151 | SEMICONDUCTOR DEVICE - A semiconductor device of an embodiment includes: a plurality of power lines extending in a first direction; and a plurality of cells arrayed along the first direction and a second direction intersecting the first direction and having a cell height of an integer multiple of a distance between the power lines adjacent to each other in the second direction, the cell height being a dimension in the second direction, wherein the plurality of cells include: a functional cell that contributes to a function of the semiconductor device; and a capacitance cell including a diffusion region of a first conductivity type and a gate electrode stacked above the diffusion region, and functioning as a decoupling capacitor, the capacitance cell is configured as a multi-height cell having a cell height of two or more times the distance, the capacitance cell includes a plurality of overlapping regions that are regions of the gate electrode overlapping the diffusion region in a stacking direction, the overlapping regions being aligned in the second direction, and the plurality of overlapping regions are arranged in one continuous well of a second conductivity type different from the first conductivity type. | 2021-09-30 |
20210305152 | INVERTED, SELF-ALIGNED TOP-VIA STRUCTURES - A multilayered integrated circuit includes a first layer with a first conductive element overlaying a substrate, a second layer with a second conductive element overlaying the first layer, an intermediate layer between the first layer and the second layer, and a via structure. The via structure is partially embedded within the intermediate layer and is communicatively coupled to the first conductive element and the second conductive element. The via structure extends from the first conductive element and has a first end with a first end width and a second end with a second end width. The second end is further from the substrate than the first end and the first end width is greater than the second end width such that the via structure tapers between the first end and the second end of the via structure. | 2021-09-30 |
20210305153 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - The method includes forming a first dielectric layer on a substrate, forming a via in the first dielectric layer, sequentially forming a first metal pattern, a first metal oxide pattern, a second metal pattern, and an antireflective pattern on the first dielectric layer, and performing an annealing process to react the first metal oxide pattern and the second metal pattern with each other to form a second metal oxide pattern. The forming the second metal oxide pattern includes forming the second metal oxide pattern by a reaction between a metal element of the second metal pattern and an oxygen element of the first metal oxide pattern. | 2021-09-30 |
20210305154 | MAGNETIC STRUCTURES IN INTEGRATED CIRCUIT PACKAGE SUPPORTS - Disclosed herein are magnetic structures in integrated circuit (IC) package supports, as well as related methods and devices. For example, in some embodiments, an IC package support may include a conductive line, a magnetic structure around the conductive line, and material stubs at side faces of the magnetic structure. | 2021-09-30 |
20210305155 | VIA ZERO INTERCONNECT LAYER METAL RESISTOR INTEGRATION - An integrated circuit (IC) is described. The IC includes a substrate having an active device having an active region. The IC also includes a middle-of-line (MOL) interconnect layer having a contact merge (CM) layer on a trench contact coupled to the active region of the active device. The IC further includes back-end-of-line (BEOL) interconnect layers on the MOL interconnect layer. The IC also includes a metal resistor in a via zero interconnect layer between a first BEOL interconnect and the MOL interconnect layer. The metal resistor is coupled to the active region through a first via zero on the CM layer, a second via zero on the metal resistor, and the first BEOL interconnect on the first via zero and the second via zero. | 2021-09-30 |
20210305156 | FIELD EFFECT TRANSISTOR AND ASSOCIATED MANUFACTURING METHOD - A field effect transistor includes a substrate; a semiconductor structure formed on a main face of the substrate, the semiconductor structure including a channel area; a first electrode and a second electrode between which extends the channel area, the first electrode including a plurality of portions spaced apart from each other, each portion of the first electrode contributing to forming an elementary transistor referred to as island; connection tracks for electrically connecting the portions of the first electrode to one another; and in which each portion of the first electrode is connected to a connection track through a fuse area, each fuse area associated with the portion of the first electrode of an island being capable of being broken in such a way as to electrically insulate said island if it is defective. | 2021-09-30 |
20210305157 | ELECTRONIC COMPONENT - An electronic component includes a lower insulating layer, an upper insulating layer formed on the lower insulating layer, a first via electrode embedded in the lower insulating layer, a second via electrode embedded in the lower insulating layer at an interval from the first via electrode, and a resistance layer that is made of a metal thin film, is interposed in a region between the lower insulating layer and the upper insulating layer, and is electrically connected to the first via electrode and the second via electrode. | 2021-09-30 |
20210305158 | NOVEL WLCSP RELIABILITY IMPROVEMENT FOR PACKAGE EDGES INCLUDING PACKAGE SHIELDING - Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a redistribution layer (RDL) having a conductive layer in a first dielectric layer, and a second dielectric layer over the conductive and first dielectric layers. The RDL comprises an extended portion having a first thickness that vertically extends from a bottom surface of the first dielectric layer to a topmost surface of the second dielectric layer. The electronic package comprises a die on the RDL, where the die has sidewall surfaces, a top surface, and a bottom surface that is opposite from the top surface, and an active region on the bottom surface of the die. The first thickness is greater than a second thickness of the RDL that vertically extends from the bottom surface of the first dielectric layer to the bottom surface of the die. The extended portion is over and around the sidewall surfaces. | 2021-09-30 |
20210305159 | MICROELECTRONIC DEVICE INTERFACE CONFIGURATIONS, AND ASSOCIATED METHODS, DEVICES, AND SYSTEMS - Memory devices are disclosed. A memory device may include a first row of power supply pads and a first row of input/output (DQ) pads. The memory device may further include a row of vias, wherein the first row of DQ pads is positioned at least partially between the row of vias and the first row of power supply pads. The memory device may also include a number of conductors, wherein each via of the row of vias is coupled, via an associated conductor of the number of conductors, to either a power supply pad of the first row of power supply pads or a DQ pad of the first row of DQ pads. Methods of forming an interface region of a memory device, and electronic systems are also disclosed. | 2021-09-30 |
20210305160 | MULTI-METAL INTERCONNECTS FOR SEMICONDUCTOR DEVICE STRUCTURES - A semiconductor device structure includes a memory element disposed within an interlayer dielectric (ILD) layer. A contact is disposed within the ILD in contact with the memory element and includes a first metal. A logic element is disposed within the ILD and comprises a second metal that is different than the first metal. A method of forming the semiconductor structure includes forming at least one memory element within an interlayer dielectric (ILD) layer. A contact that includes a first metal is formed in contact with the memory element. At least one logic element is formed in the ILD layer, where the logic element includes a second metal that is different than the first metal. | 2021-09-30 |
20210305161 | DEPOSITION OF GRAPHENE ON A DIELECTRIC SURFACE FOR NEXT GENERATION INTERCONNECTS - An integrated circuit structure, comprises a dielectric material having an opening therein, the opening defined by sides and a bottom. A graphene barrier material is conformal to the sides and the bottom of the opening, and a conductive metal over the graphene barrier material that fills at least a portion of a remainder of the opening in the dielectric material. The graphene barrier is formed by applying a non-hydrogen based plasma pretreatment to the dielectric surface, including the sides and the bottom of the opening, to substantially remove any passivation and provide an activated dielectric surface. A carbon-based precursor is exposed to the activated dielectric surface at less than approximately 400° C. to form the graphene barrier. | 2021-09-30 |
20210305162 | MICROELECTRONIC COMPONENT HAVING MOLDED REGIONS WITH THROUGH-MOLD VIAS - Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic component may include a substrate having a first face and an opposing second face, wherein the substrate includes a through-substrate via (TSV); a first mold material region at the first face, wherein the first mold material region includes a first through-mold via (TMV) conductively coupled to the TSV; and a second mold material region at the second face, wherein the second mold material region includes a second TMV conductively coupled to the TSV. | 2021-09-30 |
20210305163 | EMBEDDED MULTI-DIE INTERCONNECT BRIDGE HAVING A MOLDED REGION WITH THROUGH-MOLD VIAS - Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; a microelectronic component embedded in the package substrate, the microelectronic component including: a substrate having a surface, where the substrate includes a conductive pathway and a mold material region at the surface, where the mold material region includes a through-mold via (TMV) electrically coupled to the conductive pathway, and where the mold material region is at the second surface of the package substrate; and a die conductively coupled, at the second surface of the package substrate, to the package substrate and to the TMV of the microelectronic component. | 2021-09-30 |
20210305164 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a stacked structure, first conductive terminals and second conductive terminals. The stacked structure includes a first semiconductor component having a first area and a second semiconductor component stacked on the first semiconductor component and having a second area smaller than the first area, wherein an extending direction of the first area and an extending direction of the second area are perpendicular to a stacking direction of the first semiconductor component and the second semiconductor component. The first conductive terminals are located on the stacked structure, electrically coupled to the first semiconductor component and aside of the second semiconductor component. The second conductive terminals are located on the stacked structure and electrically coupled to the second semiconductor component. | 2021-09-30 |
20210305165 | HYBRID READOUT PACKAGE FOR QUANTUM MULTICHIP BONDING - Systems and techniques that facilitate hybrid readout packaging for quantum multichip bonding are provided. In various embodiments, an interposer can have a first quantum chip and a second quantum chip. In various aspects, a readout resonator (e.g., input/output port) of one or more qubits on the first quantum chip can be routed to an inner portion of the interposer. In various instances, the inner portion can be located between the first quantum chip and the second quantum chip. In various aspects, routing the readout resonator to the inner portion can reduce a number of crossings and/or intersections between input/output lines on the interposer and connection buses between qubits on the interposer. | 2021-09-30 |
20210305166 | POWER SEMICONDUCTOR PACKAGE WITH IMPROVED PERFORMANCE - A power semiconductor package includes a power semiconductor die, a housing, a first lead, and a second lead. The housing includes a top side and a bottom side. The first lead is in contact with a first electrical contact of the power semiconductor die. Further, the first lead includes a heat exchanging portion on the top side of the housing and an electrical contact portion on the bottom side of the housing. At least 7.5 mm | 2021-09-30 |
20210305167 | Pillared Cavity Down MIS-SIP - A substrate is provided having a top side and a bottom side, having redistribution layers therein, having at least one copper pillar connected to the redistribution layers on the top side and at least one copper pillar connected to the redistribution layers on the bottom side, and having at least one cavity extending partially into the bottom side of the substrate. At least one passive component is mounted onto the copper pillar on the top side and embedded in a molding compound. At least one silicon die is mounted in the cavity wherein electrical connections are made between the at least one silicon die and the at least one passive component through the redistribution layers. At least one solder ball is mounted on the at least one copper pillar on the bottom side of the substrate to provide package output. | 2021-09-30 |
20210305168 | Semiconductor Device and Method of Providing High Density Component Spacing - A semiconductor device has a substrate and a first conductive layer formed over the substrate. A second conductive layer is formed over the first conductive layer. The first conductive layer can be copper, and the second conductive layer can be nickel. A thickness of the second conductive layer is greater than a thickness of the first conductive layer. A flux material is deposited over the second conductive layer by a printing process. An electrical component is disposed over the flux material, and the flux material is reflowed to make electrical connection between the electrical component and second conductive layer. The flux material substantially vaporizes during the reflow to reduce the occurrence of short circuits. The electrical components can be placed over the substrate with narrow spacing and higher density given the use of the flux material to make electrical connection. An encapsulant is deposited over the electrical component. | 2021-09-30 |
20210305169 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR SUBSTRATE - A method for manufacturing a semiconductor device includes forming an insulating film on a region of a substrate serving as a scribe line, forming a first semiconductor layer in a state where a cavity is provided on the insulating film, forming a second semiconductor layer on the first semiconductor layer, and dividing the substrate, the first semiconductor layer and the second semiconductor layer into a plurality of pieces by pressing the substrate at a position corresponding to the region serving as the scribe line on a surface of the substrate opposite to a surface on which the first semiconductor layer is formed. | 2021-09-30 |
20210305170 | Semiconductor Device and Method of Manufacture - Semiconductor devices and method of manufacture are provided. In embodiments a conductive connector is utilized to provide an electrical connection between a substrate and an overlying shield. The conductive connector is placed on the substrate and encapsulated with an encapsulant. Once encapsulated, an opening is formed through the encapsulant to expose a portion of the conductive connector. The shield is deposited through the encapsulant to make an electrical connection to the conductive connector. | 2021-09-30 |
20210305171 | ELECTROMAGNETIC WAVE ATTENUATOR, ELECTRONIC DEVICE, FILM FORMATION APPARATUS, AND FILM FORMATION METHOD - According to one embodiment, an electromagnetic wave attenuator includes a first structure body. The first structure body includes a first member, a second member, and a third member. The first member includes a first magnetic layer and a first nonmagnetic layer alternately provided in a first direction. The first nonmagnetic layer is conductive. The first direction is a stacking direction. The second member includes a second magnetic layer and a second nonmagnetic layer alternately provided in the first direction. The second nonmagnetic layer is conductive. The third member includes a third nonmagnetic layer. The third nonmagnetic layer is conductive. A direction from the third member toward the first member is along the first direction. A direction from the third member toward the second member is along the first direction. A first magnetic layer thickness is greater than a second magnetic layer thickness. | 2021-09-30 |
20210305172 | CORNER STRUCTURES FOR AN OPTICAL FIBER GROOVE - Structures for an optical fiber groove and methods of forming a structure for an optical fiber groove. A photonics chip includes a substrate and an interconnect structure over the substrate. The photonics chip has a first exterior corner, a second exterior corner, and a side edge extending from the first exterior corner to the second exterior corner. The substrate includes a groove positioned along the side edge between the first exterior corner and the second exterior corner. The groove is arranged to intersect the side edge at a groove corner, and the interconnect structure includes metal structures adjacent to the first groove corner. The metal structures extend diagonally in the interconnect structure relative to the side edge of the photonics chip. | 2021-09-30 |
20210305173 | PACKAGE STRUCTURE AND FABRICATING METHOD THEREOF - A semiconductor device including a first semiconductor die, a second semiconductor die, an insulating encapsulation and a warpage control pattern is provided. The first semiconductor die includes an active surface and a rear surface opposite to the active surface. The second semiconductor die is disposed on the active surface of the first semiconductor die. The insulating encapsulation is disposed on the active surface of the first semiconductor die and laterally encapsulates the second semiconductor die. The warpage control pattern is disposed on and partially covers the rear surface of the first semiconductor die. | 2021-09-30 |
20210305174 | SEMICONDUCTOR DEVICE - According to one aspect, a semiconductor device includes: a buffer layer disposed on a front surface of a second semiconductor layer, and having at least one opening in plan view; and an electrode disposed over the second semiconductor layer and the buffer layer, and being in contact with the second semiconductor layer through the at least one opening, wherein the buffer layer has a higher Vickers hardness than the electrode, and a width w of each of the at least one opening satisfies w2021-09-30 | |
20210305175 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor element, a lead frame, a conductive member, a resin composition and a sealing resin. The semiconductor element has an element front surface and an element back surface facing away in a first direction. The semiconductor element is mounted on the lead frame. The conductive member is bonded to the lead frame, electrically connecting the semiconductor element and the lead frame. The resin composition covers a bonded region where the conductive member and lead frame are bonded while exposing part of the element front surface. The sealing resin covers part of the lead frame, the semiconductor element, and the resin composition. The resin composition has a greater bonding strength with the lead frame than a bonding strength between the sealing resin and lead frame and a greater bonding strength with the conductive member than a bonding strength between the sealing resin and conductive member. | 2021-09-30 |
20210305176 | Surface-Mount Thin-Film Components having Terminals Configured for Visual Inspection - A surface-mountable component is disclosed. The surface-mountable component may include a substrate having a side surface and a top surface that is perpendicular to the side surface. The component may include an element layer formed on the top surface of the substrate. The element layer may include a thin-film element and a contact pad electrically connected with the thin-film element. The contact pad may extend to the side surface of the substrate. The component may include a terminal that is electrically connected with the contact pad at a connection area. The connection area may be parallel with the top surface of the substrate. The terminal may have a visible edge surface that is approximately aligned with the side surface of the substrate. The visible edge surface may be visible for inspection when the surface-mountable component is mounted to a mounting surface. | 2021-09-30 |
20210305177 | CHIP TAMPERING DETECTOR - A chip tampering detector is disclosed. The chip tampering detector includes a plurality of resistor-capacitor circuits. Each resistor-capacitor circuit includes a capacitor having a planar area that covers a sensitive area of an integrated circuit of the chip. The resistor-capacitor circuits can be probed with an input signal to generate output signals. The output signals can be measured to determine respective time-constants resistor-capacitor circuits. Tampering with a chip can alter the capacitance of a capacitor covering a sensitive area. Accordingly, a significant change of a time-constant of one or more of the resistor-capacitor circuits can be used to detect chip tampering. | 2021-09-30 |
20210305178 | HIGH VOLTAGE ISOLATION BARRIER WITH ELECTRIC OVERSTRESS INTEGRITY - An electronic device comprises a multilevel metallization structure over a semiconductor layer and including a first region, a second region, a pre-metal level on the semiconductor layer, and N metallization structure levels over the pre-metal level, N being greater than 3. The electronic device also comprises an isolation component in the first region, the isolation component including a first terminal and a second terminal in different respective metallization structure levels, as well as a conductive shield between the first region and the second region in the multilevel metallization structure, the conductive shield including interconnected metal lines and trench vias in the respective metallization structure levels that at least partially encircle the first region. | 2021-09-30 |
20210305179 | ISOLATOR - According to one embodiment, an isolator includes a first electrode, a second electrode, a conductive body, and a first insulating layer. The second electrode is provided on the first electrode and separated from the first electrode. The conductive body is provided around the first and second electrodes along a first plane perpendicular to a first direction. The first direction is from the first electrode toward the second electrode. The first insulating layer is provided on the second electrode. The first insulating layer includes silicon, carbon, and nitrogen. | 2021-09-30 |
20210305180 | SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME - The present disclosure provides a semiconductor device package. The semiconductor device package includes an antenna layer, a first circuit layer and a second circuit layer. The antenna layer has a first coefficient of thermal expansion (CTE). The first circuit layer is disposed over the antenna layer. The first circuit layer has a second CTE. The second circuit layer is disposed over the antenna layer. The second circuit layer has a third CTE. A difference between the first CTE and the second CTE is less than a difference between the first CTE and the third CTE. | 2021-09-30 |
20210305181 | DEVICE PACKAGE - An electronic device package includes a first substrate, a second substrate and a conductive layer. The first substrate includes a first bonding pad, and a cavity exposing the first bonding pad. The second substrate is laminated on the first substrate. The second substrate includes a second bonding pad at least partially inserting into the cavity of the first substrate. The conductive layer is disposed in the cavity and at least between the first bonding pad and the second bonding pad to connect the first bonding pad and the second bonding pad. | 2021-09-30 |
20210305182 | SEMICONDUCTOR DEVICE WITH COMPOSITE CONNECTION STRUCTURE AND METHOD FOR FABRICATING THE SAME - The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a first insulating layer positioned above the substrate, a second insulating layer positioned above the first insulating layer, a plurality of first conductive features positioned in the first insulating layer and the second insulating layer, and an alleviation structure positioned between the first insulating layer and the second insulating layer. The alleviation structure includes a first connecting interlayer respectively electrically coupled to the plurality of first conductive features positioned in the first insulating layer and the second insulating layer, and a plurality of alleviation structures positioned between the plurality of first conductive features in the first insulating layer and the plurality of first conductive features in the second insulating layer, wherein a porosity of the plurality of alleviation structures is between about 25% and about 100%. | 2021-09-30 |
20210305183 | BONDING DEVICE - A bonding device includes a stage supporting a display panel including a first area through which a pad is exposed, a sensor disposed on the stage and facing the first area, and a handler disposing a circuit board on the first area. The handler includes a body supporting the circuit board and a rod connected to the body and selectively in contact with a second area of the circuit board overlapping the first area. | 2021-09-30 |
20210305184 | CHIP, CIRCUIT BOARD AND ELECTRONIC DEVICE - A chip includes: a chip substrate including a central area and an edge area surrounding the central area; and a plurality of pads arranged on the chip substrate, the plurality of pads including a first pad and a second pad, wherein the first pad is arranged in the edge area and includes at least one straight side adjacent to a side of the chip substrate, and the second pad is arranged in the central area. | 2021-09-30 |
20210305185 | DISPLAY DRIVING SYSTEM, DISPLAY PANEL AND ELECTRONIC DEVICE - A display driving system includes a first chip and a second chip that are vertically docked; the first chip includes a first substrate and a first silicon wafer provided on a side of the first chip away from the first substrate; the second chip includes a second substrate and a second silicon wafer provided on a side of the second chip away from the second substrate; the first chip is docked with the second chip through docking of the first silicon wafer and the second silicon wafer; wherein, the first chip is configured to provide driving data, and the second chip is configured to process image data. | 2021-09-30 |
20210305186 | SEMICONDUCTOR STACK AND METHOD FOR MANUFACTURING THE SAME - A semiconductor stack and a method for manufacturing the same are disclosed. The semiconductor stack includes a lower chip, an upper chip disposed over the lower chip, an upper lateral-side passivation layer surrounding side surfaces of the upper chip, and a plurality of bonding pads and a bonding passivation layer disposed between the upper chip and the lower chip. | 2021-09-30 |
20210305187 | PROCESS FOR REMOVING BOND FILM FROM CAVITIES IN PRINTED CIRCUIT BOARDS - A process of fabricating an electromagnetic circuit includes providing a first sheet of dielectric material including a top surface having at least one conductive trace and depositing a solder bump on the at least one conductive trace. The process further includes applying a second sheet of dielectric material to the first sheet of dielectric material with bond film sandwiched in between, the second sheet of dielectric material having a through-hole providing access to the solder bump. The process further includes bonding the first and second dielectric materials to one another and removing bond film resin from the solder bump. The process further includes machining the solder bump by the drilling or milling process to achieve a desired amount of solder in the solder bump. | 2021-09-30 |
20210305188 | SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device comprising a semiconductor substrate, a conductive pad on a first surface of the semiconductor substrate, a passivation layer on the first surface of the semiconductor substrate, the passivation layer having a first opening that exposes the conductive pad, an organic dielectric layer on the passivation layer, the organic dielectric layer having a second opening, and a bump structure on the conductive pad and in the first and second openings. The organic dielectric layer includes a material different from a material of the passivation layer. The second opening is spatially connected to the first opening and exposes a portion of the passivation layer. The bump structure includes a pillar pattern in contact with the passivation layer and the organic dielectric layer. | 2021-09-30 |
20210305189 | SEMICONDUCTOR DEVICE - A semiconductor package including a semiconductor chip, a redistribution layer structure disposed under the semiconductor chip, a bump pad disposed under the redistribution layer structure and having an upper structure of a first width and a lower structure of a second width less than the first width, a metal seed layer disposed along a lower surface of the upper structure and a side surface of the lower structure, an insulating layer surrounding the redistribution layer structure and the bump pad, and a bump structure disposed under the bump pad. A first undercut is disposed at one end of the metal seed layer that contacts the upper structure, and a second undercut is disposed at an other end of the metal seed layer that contacts the lower structure. | 2021-09-30 |
20210305190 | SEMICONDUCTOR PACKAGES - Semiconductor packages may include a semiconductor chip on a substrate and an under-fill layer between the semiconductor chip and the substrate. The semiconductor chip may include a semiconductor substrate including first and second regions, and an interlayer dielectric layer that may cover the semiconductor substrate and may include connection lines. First conductive pads may be on the first region and may be electrically connected to some of the connection lines. Second conductive pads may be on the second region and may be electrically isolated from all of the connection lines. The semiconductor chip may also include a passivation layer that may cover the interlayer dielectric layer and may include holes that may expose the first and second conductive pads, respectively. On the second region, the under-fill layer may include a portion that may be in one of the first holes and contact one of the second conductive pads. | 2021-09-30 |
20210305191 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND CORRESPONDING SEMICONDUCTOR DEVICE - A method comprises molding laser direct structuring material onto at least one semiconductor die, forming resist material on the laser direct structuring material, producing mutually aligned patterns of electrically-conductive formations in the laser direct structuring material and etched-out portions of the resist material having lateral walls sidewise of said electrically-conductive formations via laser beam energy, and forming electrically-conductive material at said etched-out portions of the resist material, the electrically-conductive material having lateral confinement surfaces at said lateral walls of said etched-out portions of the resist material. | 2021-09-30 |
20210305192 | SEMICONDUCTOR DEVICE PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device package includes a first electronic device and a second electronic device. The first electronic device includes a first redistribution layer (RDL) including a circuit layer. The second electronic device is disposed on the first RDL of the first electronic device. The second electronic device includes an encapsulant and a patterned conductive layer. The encapsulant has a first surface facing the first RDL of the first electronic device, and a second surface opposite to the first surface. The patterned conductive layer is disposed at the second surface of the encapsulant, and is configured to be electrically coupled to the circuit layer of the first RDL of the first electronic device. | 2021-09-30 |
20210305193 | POWER MODULE OF DOUBLE-FACED COOLING - A power module according implementations of the present disclosure includes a bonding layer for bonding two adjacent members. The bonding layer is formed by melting, applying, and solidifying a bonding material that has excellent thermal conductivity and electrical conductivity. The melted bonding material includes a plurality of anti-tilting members. The two members bonded during the process of solidifying the melted bonding material are supported by the plurality of anti-tilting members. This may allow tilting caused during the formation of the bonding layer to be suppressed. | 2021-09-30 |
20210305194 | METAL JOINT, METAL JOINT PRODUCTION METHOD, SEMICONDUCTOR DEVICE, AND WAVE GUIDE PATH - Provided is a metal joint ( | 2021-09-30 |
20210305195 | ANISOTROPIC CONDUCTIVE FILM - An anisotropic conductive film in which conductive particles are disposed in an insulating resin layer has a particle disposition of the conductive particles such that a first orthorhombic lattice region being formed by arranging a plurality of arrangement axes of the conductive particles, disposed in an a direction at a predetermined pitch, in a b direction inclined with respect to the a direction at an angle, and a second orthorhombic lattice region being formed by arranging a plurality of arrangement axes of the conductive particles, disposed in the a direction at a predetermined pitch, in a c direction obtained by inverting the b direction with respect to the a direction are repeatedly disposed. Regardless of the shape of the terminal arrangements and the materials of electronic components, a good conduction state is ensured while the respective terminals hold conductive particles. Further, the occurrence of a short circuit is prevented. | 2021-09-30 |
20210305196 | ELECTRICAL CONNECTOR WITH INSULATED CONDUCTIVE LAYER - An interconnect that has an electrically conductive layer, where a first and second insulator layers are coupled with the conductive layer. A region of the conductive layer includes an opening of a portion of the first insulator layer the second insulator layer that are adjacent to the region. An electrical connector of a first device is electrically coupled to a portion of the region on a first side of the conductive layer and an electrical conductor of a second device is electrically coupled with a portion of the region on the second side. Also, an interconnect coupled with a substrate that includes a cylinder extending from a side of the substrate with a plate coupled at the end of the cylinder with an opening that includes two or more tabs of the plate extending into the opening to receive a connector. | 2021-09-30 |
20210305197 | METHOD FOR CONNECTING COMPONENTS DURING PRODUCTION OF POWER ELECTRONIC MODULES OR ASSEMBLIES - In a method for connecting components during production of power electronics modules or assemblies, surfaces of the components have a metallic surface layer upon supply, or are furnished therewith, wherein the layer has a surface that is smooth enough to allow direct bonding or is smoothed to obtain a surface that is smooth enough to allow direct bonding. The surface layers of the surfaces that are to be connected are then pressed against each other with a pressure of at least 5 MPa at elevated temperature, so that they are joined to each other, forming a single layer. The method enables simple, rapid connection of even relatively large contact surfaces, which satisfies the high requirements of power electronics modules. | 2021-09-30 |
20210305198 | METHOD FOR PROCESSING A SEMICONDUCTOR WAFER, SEMICONDUCTOR WAFER, CLIP AND SEMICONDUCTOR DEVICE - A method for processing a semiconductor wafer is provided. A semiconductor wafer includes a first main surface and a second main surface. Defects are generated inside the semiconductor wafer to define a detachment plane parallel to the first main surface. Processing the first main surface defines a plurality of electronic semiconductor components. A glass structure is provided which includes a plurality of openings. The glass structure is attached to the processed first main surface, each of the plurality of openings leaving a respective area of the plurality of electronic semiconductor components uncovered. A polymer layer is applied to the second main surface and the semiconductor wafer is split into a semiconductor slice and a remaining semiconductor wafer by cooling the polymer layer beneath its glass transition temperature along the detachment plane. The semiconductor slice includes the plurality of electronic semiconductor components. | 2021-09-30 |
20210305199 | METHODS OF OPTIMIZING CLAMPING OF A SEMICONDUCTOR ELEMENT AGAINST A SUPPORT STRUCTURE ON A WIRE BONDING MACHINE, AND RELATED METHODS - A method of adjusting a clamping of a semiconductor element against a support structure on a wire bonding machine is provided. The method includes: (a) detecting an indicia of floating of the semiconductor element with respect to the support structure at a plurality of locations of the semiconductor element; and (b) adjusting the clamping of the semiconductor element against the support structure based on the results of step (a). | 2021-09-30 |
20210305200 | Wafer Bonding Method - In an embodiment, a device includes: a first wafer including a first substrate and a first interconnect structure, a sidewall of the first interconnect structure forming an obtuse angle with a sidewall of the first substrate; and a second wafer bonded to the first wafer, the second wafer including a second substrate and a second interconnect structure, the sidewall of the first substrate being laterally offset from a sidewall of the second substrate and a sidewall of the second interconnect structure. | 2021-09-30 |
20210305201 | BONDING APPARATUS AND METHOD OF FABRICATING DISPLAY DEVICE USING THE SAME - A method of fabricating a display device may include disposing a display panel on a stage to be parallel to an XZ-plane defined by a horizontal X-axis and a vertical Z-axis, measuring a height of a first side surface of the display panel in a direction of the Z-axis, rotating the stage such that the first side surface is parallel to a reference horizontal line in case that a result of the measured height indicates that the first side surface includes an inclined surface, moving the display panel in a direction of the Z-axis such that a first pad disposed on the first side surface overlaps the reference horizontal line, and bonding a second pad of a printed circuit board with the first pad. | 2021-09-30 |
20210305202 | RELIABLE HYBRID BONDED APPARATUS - Reliable hybrid bonded apparatuses are provided. An example process cleans nanoparticles from at least the smooth oxide top layer of a surface to be hybrid bonded after the surface has already been activated for the hybrid bonding. Conventionally, such an operation is discouraged. However, the example cleaning processes described herein increase the electrical reliability of microelectronic devices. Extraneous metal nanoparticles can enable undesirable current and signal leakage from finely spaced traces, especially at higher voltages with ultra-fine trace pitches. In the example process, the extraneous nanoparticles may be both physically removed and/or dissolved without detriment to the activated bonding surface. | 2021-09-30 |
20210305203 | SEMICONDUCTOR DEVICE AND CORRESPONDING METHOD OF MANUFACTURE - Disclosed herein is a method, including attaching a semiconductor chip to a chip mounting portion on at least one leadframe portion, and attaching a passive component on a passive component mounting portion of the at least one leadframe portion. The method further includes forming a laser direct structuring (LDS) activatable molding material over the semiconductor chip, passive component, and the at least one leadframe portion. Desired patterns of structured areas are formed within the LDS activatable molding material by activating the LDS activatable molding material. The desired patterns of structured areas are metallized to form conductive areas within the LDS activatable molding material to thereby form electrical connection between the semiconductor chip and the passive component. A passivation layer is formed on the LDS activatable molding material. | 2021-09-30 |
20210305204 | SEMICONDUCTOR DEVICE - A semiconductor device according to an embodiment includes a semiconductor layer, a metal layer, and a bonding layer provided between the semiconductor layer and the metal layer, the bonding layer including a plurality of silver particles, and the bonding layer including a region containing gold existing between the plurality of silver particles. | 2021-09-30 |
20210305205 | EDGE-TRIMMING METHODS FOR WAFER BONDING AND DICING - A front-side peripheral region of a first wafer may be edge-trimmed by performing a first pre-bonding edge-trimming process. A second wafer to be bonded with the first wafer is provided. Optionally, a front-side peripheral region of the second wafer may be edge-trimmed by performing a second pre-bonding edge-trimming process. A front surface of the first wafer is bonded to a front surface of a second wafer to form a bonded assembly. A backside of the first wafer is thinned by performing at least one wafer thinning process. The first wafer and a front-side peripheral region of the second wafer may be edge-trimmed by performing a post-bonding edge-trimming process. The bonded assembly may be subsequently diced into bonded semiconductor chips. | 2021-09-30 |
20210305206 | DEVICE OF ACQUISITION OF A 2D IMAGE AND OF A DEPTH IMAGE OF A SCENE - A device of acquisition of a 2D image and of a depth image, including: first sensor formed inside and on top of a first semiconductor substrate including a front surface and a rear surface, the first sensor including a plurality of 2D image pixels and a plurality of transmissive windows, each transmissive window including a portion of the first substrate and an amorphous silicon region in contact with the rear surface of said portion of the first substrate; and against the first sensor on the rear surface side of the first substrate, a second sensor formed inside and on top of a second semiconductor substrate and including a plurality of depth pixels arranged opposite the transmissive windows of the first sensor. | 2021-09-30 |
20210305207 | MULTI-CHIP PACKAGE WITH REINFORCED ISOLATION - A multi-chip isolation (ISO) device package includes a leadframe including leads, an interposer substrate including a top copper layer and a bottom metal layer, with a dielectric layer in-between. A first IC die and a second IC die include circuitry including a transmitter or a receiver, and first and second bond pads are both attached top side up in the package. A laminate transformer is attached to the top copper layer positioned lateral to the IC die. Bondwires wirebond the first bond pads to first pads on the laminate transformer and to a first group of the leads or the lead terminals, and bondwires wirebond the second bond pads to second pads on the laminate transformer and to a second group of the leads or the lead terminals. A mold compound provides encapsulation. | 2021-09-30 |
20210305208 | SEMICONDUCTOR DEVICE WITH CONNECTION STRUCTURE AND METHOD FOR FABRICATING THE SAME - The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first semiconductor structure including a plurality of first conductive features adjacent to a top surface of the first semiconductor structure, a second semiconductor structure positioned above the first semiconductor structure and including a plurality of second conductive features adjacent to a bottom surface of the second semiconductor structure, and a connection structure positioned between the first semiconductor structure and the second semiconductor structure. The connection structure includes a connection layer electrically coupled to the plurality of first conductive features and the plurality of second conductive features, and a plurality of first porous interlayers positioned between the plurality of first conductive features and the plurality of second conductive features. A porosity of the plurality of first porous interlayers is between about 25% and about 100%. | 2021-09-30 |
20210305209 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor structure and the manufacturing method thereof are provided. A semiconductor structure includes a first semiconductor die, a second semiconductor die, an insulating layer, and a first dual-damascene connector electrically connected to the first semiconductor die. The first semiconductor die includes a first bonding surface including a die attaching region and a peripheral region connected to the die attaching region. The second semiconductor die is electrically connected to the first semiconductor die, and a second bonding surface of the second semiconductor die is bonded to the first bonding surface in the die attaching region. The insulating layer disposed on the first bonding surface in the peripheral region extends along sidewalls of the second semiconductor die. The first dual-damascene connector includes a first portion disposed on the insulating layer, and a second portion penetrating through the insulating layer and landing on the first bonding surface in the peripheral region. | 2021-09-30 |
20210305210 | DUAL-DIE SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - The present application provides a semiconductor package and a manufacturing method thereof. The semiconductor package includes a package substrate, a bottom device die, an interposing package substrate and a top device die. The bottom device die is bonded to the package substrate. The interposing package substrate is located over the bottom device die and bonded to the package substrate. The top device die is bonded to the interposing package substrate form above the interposing package substrate. | 2021-09-30 |
20210305211 | SEMICONDUCTOR DEVICES WITH REDISTRIBUTION STRUCTURES CONFIGURED FOR SWITCHABLE ROUTING - Semiconductor devices having redistribution structures, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor package includes a first semiconductor die including a first redistribution structure and a second semiconductor die including a second redistribution structure. The first and second semiconductor dies can be mounted on a package substrate such that the first and second redistribution structures are aligned with each other. In some embodiments, an interconnect structure can be positioned between the first and second semiconductor dies to electrically couple the first and second redistribution structures to each other. The first and second redistribution structures can be configured such that signal routing between the first and second semiconductor dies can be altered based on the location of the interconnect structure. | 2021-09-30 |
20210305212 | SEMICONDCUTOR PACKAGE AND MANUFACTURING METHOD OF SEMICONDCUTOR PACKAGE - A manufacturing method of a semiconductor package includes the following steps. At least one lower semiconductor device is provided. A plurality of conductive pillars are formed on the at least one lower semiconductor device. A dummy die is disposed on a side of the at least one lower semiconductor device. An upper semiconductor device is disposed on the at least one lower semiconductor device and the dummy die, wherein the upper semiconductor device reveals a portion of the at least one lower semiconductor device where the plurality of conductive pillars are disposed. The at least one lower semiconductor device, the dummy die, the upper semiconductor device, and the plurality of conductive pillars are encapsulated in an encapsulating material. A redistribution structure is formed over the upper semiconductor device and the plurality of conductive pillars. | 2021-09-30 |
20210305213 | INTEGRATED CIRCUIT, SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - An integrated circuit includes a first semiconductor wafer, a second semiconductor wafer, a first interconnect structure, an inductor, and a through substrate via. The first semiconductor wafer has a first device in a first side of the first semiconductor wafer. The second semiconductor wafer is over the first semiconductor wafer. The first interconnect structure is on a second side of the first semiconductor wafer opposite from the first side of the first semiconductor wafer. The inductor is below the first semiconductor wafer, and at least a portion of the inductor is within the first interconnect structure. The through substrate via extends through the first semiconductor wafer. The inductor is coupled to at least the first device by at least the through substrate via. | 2021-09-30 |
20210305214 | PACKAGE - A package includes a carrier substrate, a first die, and a second die. The first die includes a first bonding layer, a second bonding layer opposite to the first bonding layer, and an alignment mark embedded in the first bonding layer. The first bonding layer is fusion bonded to the carrier substrate. The second die includes a third bonding layer. The third bonding layer is hybrid bonded to the second bonding layer of the first die. | 2021-09-30 |
20210305215 | SEMICONDUCTOR MODULE - A semiconductor module includes a multilayer substrate having a main wiring layer formed therein, a main current flowing in the main wiring layer when the semiconductor device is turned on, a first and second semiconductor elements, each of which has a top electrode on a top surface thereof and a bottom electrode on a bottom surface thereof, and is disposed on a top surface of the main wiring layer to which the bottom electrode is conductively connected, a metal plate having an end portion, a bottom surface of the end portion being conductively connected to the top electrode of the first semiconductor element, and a control board including an insulating plate disposed on the top surface of the end portion and a control wiring layer disposed on a top surface of the insulating plate for controlling turning on and off of the first and second semiconductor elements. | 2021-09-30 |
20210305216 | LIGHT-EMITTING DEVICE - A light-emitting device according to the present invention comprises: a mounting board; a plurality of light-emitting elements that each include a supporting substrate and a semiconductor structure layer, the supporting substrate being disposed on the mounting board, and the semiconductor structure layer being formed on the supporting substrate and including a light-emitting layer, a wavelength conversion member that covers the plurality of light-emitting elements above the light-emitting elements and converts a wavelength of a light emitted from the light-emitting layer; a translucent member that covers a lower surface of the wavelength conversion member and covers the semiconductor structure layer on the supporting substrate; and a resin member filled between the plurality of light-emitting elements, the resin member being formed of a resin material containing particles having a light reflectivity. The translucent member includes a thin film portion having a constant film thickness between the wavelength conversion member and the resin member in a region between the plurality of light-emitting elements, and the constant film thickness is smaller than a distance between a top surface of the supporting substrate and a lower surface of the wavelength conversion member. | 2021-09-30 |
20210305217 | METHOD OF MANUFACTURING LIGHT-EMITTING DEVICE - A method of manufacturing a light-emitting device includes: providing a first intermediate structure including a substrate, light-emitting elements arrayed in a first direction, a protective element, and light-transmissive members; forming a resin wall including first and second walls extending in the first direction, and third and fourth walls, a first distance between the first wall and the light-emitting elements being larger than a second distance between the third or fourth wall and a corresponding one of light-emitting elements; applying a first resin to a first region between the first wall and the light-emitting elements in which the protective element is disposed, resulting in forming a first recess in the first region and a second recess in a second region between the second wall and the light-emitting elements; and forming a covering member by applying a second resin to the first and second recesses and curing the first and second resins. | 2021-09-30 |
20210305218 | LIGHT EMITTING DEVICE - A light emitting device includes light emitting elements, light-transmissive members, a covering member, at least one first protrusion, and two second protrusions. The light emitting elements are aligned in a first direction. The light-transmissive members are respectively disposed on upper surfaces of the light emitting elements. The covering member includes at least one first covering portion and two second covering portions. The at least one first covering portion is arranged between adjacent ones of the light-transmissive members, and the second covering portions are arranged at distal ends of the light emitting device in the first direction with the light-transmissive members being arranged between the second covering portions. The at least one first protrusion is arranged on an upper surface of the at least one first covering portion and being spaced apart from the light-transmissive members. The second protrusions respectively arranged on upper surfaces of the second covering portions. | 2021-09-30 |
20210305219 | METHOD OF MANUFACTURING LIGHT-EMITTING DEVICE - A method of manufacturing the light-emitting device includes providing a structure body, mounting the structure body, removing a third substrate region of a silicon substrate of the structure body, disposing a resin layer, disposing a first mask member, removing a first substrate region of the silicon substrate, disposing a first wavelength conversion layer, removing the first mask member, and removing a second substrate region of the silicon substrate. | 2021-09-30 |
20210305220 | Systems And Methods For Multi-Color LED With Stacked Bonding Structures - A single pixel multi-color LED device includes two or more LED structures for emitting a range of colors. The two or more LED structures are horizontally formed as sub-pixels to combine light. In some embodiments, two or more light emitting layers are formed on a substrate with integrated circuits and the two or more light emitting layers are bonded together with bonding layers. In some embodiments, the two or more LED structures are formed by utilizing a respective top light emitting layer of the respective LED structure and by removing extra top light emitting layer(s) with the respective LED structure. In some embodiments, the up and down orientation of the P-type region and the N-type region within the first light emitting layer is different from the up and down orientation of the P-type region and the N-type region within the second light emitting layer. | 2021-09-30 |
20210305221 | LED DISPLAY UNIT GROUP AND DISPLAY PANEL - Provided are a LED display unit group and a display panel. The LED display unit group includes a circuit board and pixel units arranged in an array of m rows and n columns on the circuit board. The circuit board includes N metal line layers stacked in sequence and an insulating plate located between adjacent metal line layers. The N metal line layers are electrically connected through a conductive via on the insulating plate, where N≥2. Each pixel unit includes at least two LED light-emitting chips with different light-emitting colors, where m≥2, n≥2. The first metal line layer includes m common A-electrode pads, multiple A-electrode pads and multiple B-electrode pads. | 2021-09-30 |
20210305222 | LIGHT-EMITTING DEVICE, METHOD FOR MANUFACTURING SAME, AND DISPLAY DEVICE COMPRISING SAME - A light emitting device may include a first electrode disposed on a substrate, and a second electrode spaced apart from the first electrode, the first electrode and the second electrode being disposed on a same layer; an insulating pattern disposed between the first electrode and the second electrode, and overlapping a portion of the first electrode and a portion of the second electrode; and at least one light emitting element disposed on the insulating pattern, and including a first end and a second end in a longitudinal direction of the at least one light emitting element; a first bank disposed on the first electrode, and a second bank disposed on the second electrode; a first reflective electrode disposed on the first bank and electrically connected with the first electrode; and a second reflective electrode disposed on the second bank and electrically connected with the second electrode. | 2021-09-30 |