39th week of 2021 patent applcation highlights part 69 |
Patent application number | Title | Published |
20210305023 | EDGE RING AND PLASMA PROCESSING APPARATUS - An edge ring formed of a material including boron carbide and silicon carbide is provided. The content by percentage of the boron carbide contained in the material is in a range between 30% and 50%. | 2021-09-30 |
20210305024 | PLASMA CLEANING FOR PACKAGING ELECTRONIC DEVICES - In a described example, a method includes loading at least one package substrate strip including electronic device dies mounted on the at least one package substrate strip into a plasma process chamber; positioning at least one E-field shield in the plasma process chamber spaced from and over the at least one package substrate strip; and plasma cleaning the at least one package substrate strip. | 2021-09-30 |
20210305025 | SUBSTRATE SUPPORT AND PLASMA PROCESSING APPARATUS - The disclosed substrate support includes a first region, a second region, a first electrode, and a second electrode. The first region is configured to hold a substrate placed thereon. The second region is provided to surround the first region and configured to hold an edge ring placed thereon. The first electrode is provided in the first region to receive a first electrical bias. The second electrode is provided in at least the second region to receive a second electrical bias. The second electrode extends below the first electrode to face the first electrode within the first region. | 2021-09-30 |
20210305026 | PLASMA POLYMERIZATION APPARATUS AND PLASMA POLYMERIZATION METHOD USING THE SAME - A plasma polymerization apparatus is provided for forming a polymerization coating on an inner surface of an object. The plasma polymerization apparatus comprises a chamber, a gas supply, a monomer source, a first electrode, a second electrode, a power source, and a metal foil. The gas supply is connected to the chamber for filling the chamber with a working gas. The monomer source is connected to the chamber for providing a vaporized monomer material into the chamber. The first electrode is located at a first side of the chamber. The second electrode is located at a second side of the chamber. The power source is electrically connected to the first electrode and the second electrode for generating plasma. The metal foil is wrapped around an outer surface of the object and placed between the first electrode and the second electrode. A plasma polymerization method is also provided. | 2021-09-30 |
20210305027 | PLASMA PROCESSING APPARATUS AND WEAR AMOUNT MEASUREMENT METHOD - A plasma processing apparatus including a processing container and a conductive member, includes a plasma generator configured to generate plasma in the processing container, a power application part configured to apply a DC power to the conductive member in a state in which plasma is generated in the processing container by the plasma generator, a measurement part configured to measure a physical quantity related to the DC power applied by the power application part, and a calculator configured to obtain a wear amount of the conductive member using the measured physical quantity related to the DC power in a correlation function between the wear amount of the conductive member and the physical quantity related to the DC power. | 2021-09-30 |
20210305028 | REMOTE PLASMA CLEANING OF CHAMBERS FOR ELECTRONICS MANUFACTURING SYSTEMS - A method of cleaning a chamber for an electronics manufacturing system includes flowing a gas mixture comprising oxygen and a carrier gas into a remote plasma generator. The method further includes generating a plasma from the gas mixture by the remote plasma generator and performing a remote plasma cleaning of the chamber by flowing the plasma into an interior of the chamber, wherein the plasma removes a plurality of organic contaminants from the chamber. | 2021-09-30 |
20210305029 | SUBSTRATE PROCESSING SYSTEM, SUBSTRATE PROCESSING METHOD, AND CONTROLLER - According to one embodiment of the present disclosure, there is provided a substrate processing system for processing a plurality of substrates including: a processor configured to perform a process on the substrate; a transport device configured to repeatedly transport the plurality of substrates with respect to the processor; and a controller configured to control the process of the substrate in the processor, wherein the controller is configured to: execute the process based on a process recipe, which is a control program for executing the process; and set an offset time, which is a function corresponding to a number of the substrates processed by the processor or a function corresponding to a parameter equivalent to the number of the processed substrates, with respect to a step time for a step of the process recipe. | 2021-09-30 |
20210305030 | SUBSTRATE PROCESSING DEVICE, SUBSTRATE PROCESSING SYSTEM, CONTROL METHOD FOR SUBSTRATE PROCESSING DEVICE, AND CONTROL METHOD FOR SUBSTRATE PROCESSING SYSTEM - Provided is a substrate processing apparatus comprising: a substrate support on which a substrate is mounted; a first radio frequency power supply that outputs first radio frequency power with a first frequency to the substrate support; a second radio frequency power supply that outputs second radio frequency power with a second frequency lower than the first frequency to the substrate support; a sensor that detects reflected waves received from the substrate support and a processor that controls the first radio frequency power supply so that an effective power, which is equal to a difference between the power of the reflected waves detected by the sensor and the output power of the first radio frequency power supply, reaches a set value. | 2021-09-30 |
20210305031 | METHOD FOR MANUFACTURING THIN FILM RESISTIVE LAYER - The present invention discloses a method for preparing a thin film resistive layer. A tantalum nitride layer is formed on the surface of a substrate by a magnetron sputtering method, then a tantalum pentoxide layer is formed on the tantalum nitride layer by same method. Finally, both the tantalum nitride layer and the tantalum pentoxide layer are treated with an annealing process to obtain the thin film resistive layer with a low resistance change rate. | 2021-09-30 |
20210305032 | SUBSTRATE PROCESSING METHOD AND APPARATUS - There is provided a substrate processing method of a substrate processing apparatus. The substrate processing apparatus includes at least two targets, magnet-moving mechanisms disposed in one-to-one correspondence with the at least two targets, each of the magnet-moving mechanisms being configured to reciprocate a magnet in a first direction on a back surface of each target, and a substrate moving mechanism configured to move a substrate in a second direction orthogonal to the first direction. The method includes causing the magnet-moving mechanisms to reciprocate the magnets at different phases with each other. | 2021-09-30 |
20210305033 | FIRST-STAGE DYNODE AND PHOTOMULTIPLIER TUBE - A first-stage dynode is a first-stage dynode to be used in a photomultiplier tube, and includes a bottom wall portion and a pair of side wall portions extending from both end portions of the bottom wall portion in a predetermined direction to one side. An electron emission surface is formed by a bottom surface of the bottom wall portion on the one side and a pair of side surfaces of the pair of side wall portions on the one side, and each of the pair of side surfaces is a curved surface that is curved in a concave shape in a cross section parallel to the predetermined direction. | 2021-09-30 |
20210305034 | MASS SPECTROMETRY DEVICE AND MASS SPECTROMETRY METHOD - A precursor ion selection processing unit ( | 2021-09-30 |
20210305035 | AMPLIFIER AMPLITUDE DIGITAL CONTROL FOR A MASS SPECTROMETER - Control of an amplitude of a signal applied to rods of a quadrupole is described. In one aspect, a mass spectrometer includes an amplifier circuit that causes a radio frequency (RF) signal to be applied to the rods of the quadrupole. A controller circuit can determine that the actual amplitude of the RF signal differs than the expected amplitude and, in response, identify current and past environmental and performance parameters to adjust the amplitude. | 2021-09-30 |
20210305036 | ION SOURCE - Provided herein is an ion source containing a plurality of components, at least one of which is partially coated with a layer of silicon. The ion source reduces reactivity between the sample and the carrier gas, reduces or eliminates tailing in ion chromatograms, and/or improves mass spectral fidelity. Also provided are methods of using the ion source in a mass spectrometer or gas chromatograph-mass spectrometer. | 2021-09-30 |
20210305037 | SYSTEMS AND APPROACHES FOR SEMICONDUCTOR METROLOGY AND SURFACE ANALYSIS USING SECONDARY ION MASS SPECTROMETRY - Systems and approaches for semiconductor metrology and surface analysis using Secondary Ion Mass Spectrometry (SIMS) are disclosed. In an example, a secondary ion mass spectrometry (SIMS) system includes a sample stage. A primary ion beam is directed to the sample stage. An extraction lens is directed at the sample stage. The extraction lens is configured to provide a low extraction field for secondary ions emitted from a sample on the sample stage. A magnetic sector spectrograph is coupled to the extraction lens along an optical path of the SIMS system. The magnetic sector spectrograph includes an electrostatic analyzer (ESA) coupled to a magnetic sector analyzer (MSA). | 2021-09-30 |
20210305038 | TOOL FOR REPLACING OBSTRUCTED, UPWARD-FACING LIGHTBULBS - The present invention is a device for installing and removing partially obstructed, upward-facing lightbulbs. It is comprised of a gripping element, a weight, a flexible rotary shaft having two ends, and an extension pole having two ends. The gripping element, itself, is comprised of a hollow, three-dimensional gripping element body having an inner and outer surface and a plurality of flexible, tactile members. The hollow, three-dimensional gripping element body is open at one end and closed at the other. At the open end, the plurality of flexible, tactile members are arranged about a peripheral rim at the opening. When the device is placed over a lightbulb, the flexible, tactile members capture the lightbulb. Rotating the extension pole will cause the lightbulb to rotate. | 2021-09-30 |
20210305039 | RESIDUE REMOVAL - In an example, a method may include removing a material from a structure to form an opening in the structure, exposing a residue, resulting from removing the material, to an alcohol gas to form a volatile compound, and removing the volatile compound by vaporization. The structure may be used in semiconductor devices, such as memory devices. | 2021-09-30 |
20210305040 | PHOTORESIST LAYER SURFACE TREATMENT, CAP LAYER, AND METHOD OF FORMING PHOTORESIST PATTERN - A method of forming a pattern in a photoresist layer includes forming a photoresist layer over a substrate, and reducing moisture or oxygen absorption characteristics of the photoresist layer. The photoresist layer is selectively exposed to actinic radiation to form a latent pattern, and the latent pattern is developed by applying a developer to the selectively exposed photoresist layer to form a pattern. | 2021-09-30 |
20210305041 | CATALYTIC FORMATION OF BORON AND CARBON FILMS - Exemplary methods of semiconductor processing may include providing a boron-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. The methods may include providing a carbon-containing precursor to the processing region of the semiconductor processing chamber. The carbon-containing precursor may be characterized by a carbon-carbon double bond or a carbon-carbon triple bond. The methods may include thermally reacting the boron-containing precursor and the carbon-containing precursor at a temperature below about 650° C. The methods may include forming a boron-and-carbon-containing layer on the substrate. | 2021-09-30 |
20210305042 | DUAL GATE DIELECTRIC LAYERS GROWN WITH AN INHIBITOR LAYER - A semiconductor device including a first dielectric layer and a second dielectric layer is formed by forming an inhibitor layer over a semiconductor material. The inhibitor layer includes at least silicon and nitrogen. The semiconductor material is heated in an oxygen-containing ambient which oxidizes the inhibitor layer and forms the first dielectric layer which includes the oxidized inhibitor layer, and oxidizes the semiconductor material to form the second dielectric layer. The second dielectric layer is thicker than, the first dielectric layer. The first dielectric layer and the second dielectric layer each include at least 90 weight percent silicon dioxide and less than 1 weight percent nitrogen. The first dielectric layer and the second dielectric layer may be used to form gate dielectric layers for a first MOS transistor and a second MOS transistor that operates at a higher voltage than the first MOS transistor. | 2021-09-30 |
20210305043 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING APPARATUS, AND RECORDING MEDIUM - There is provided a technique that includes: modifying a surface of first base exposed on a substrate by supplying modifying gas including the first base and second base exposed on the substrate; and selectively forming a film containing at least first element and second element different from the first element on a surface of the second base by supplying precursor gas to the substrate after the surface of the first base is modified, under condition that film-forming reaction by thermal decomposition of the precursor gas does not substantially occur, the precursor gas containing a compound in which atoms of the first element are contained in one molecule, at least one atom of the second element is interposed between two atoms of the first element, and each of the two atoms of the first element is directly bonded to one of the at least one atom of the second element. | 2021-09-30 |
20210305044 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING APPARATUS, AND RECORDING MEDIUM - There is provided a technique that includes: forming a first film to have a first predetermined film thickness over a substrate by performing a first cycle a first predetermined number of times, the first cycle including non-simultaneously performing: (a1) forming an oxynitride film by supplying a first film-forming gas to the substrate; and (a2) changing the oxynitride film into a first oxide film by supplying a first oxidizing gas to the substrate to oxidize the oxynitride film. | 2021-09-30 |
20210305045 | Method of Manufacturing Semiconductor Device, Substrate Processing Apparatus and Non-transitory Computer-readable Recording Medium - Described herein is a technique capable of capable of improving characteristics of an oxide film formed on a substrate in a process of modifying the oxide film. According to one aspect of the technique, there is provided a method of manufacturing a semiconductor device, including: modifying an oxide film formed on a substrate by performing: (a) supplying a reactive species containing an element of a rare gas generated by converting a gas containing the rare gas into a plasma state to the oxide film; and (b) after (a), supplying a reactive species containing oxygen generated by converting an oxygen-containing gas different from the gas containing the rare gas into a plasma state to the oxide film. | 2021-09-30 |
20210305046 | FIELD EFFECT TRANSISTOR USING TRANSITION METAL DICHALCOGENIDE AND A METHOD FOR FORMING THE SAME - In a method of forming a two-dimensional material layer, a nucleation pattern is formed over a substrate, and a transition metal dichalcogenide (TMD) layer is formed such that the TMD layer laterally grows from the nucleation pattern. In one or more of the foregoing and following embodiments, the TMD layer is single crystalline. | 2021-09-30 |
20210305047 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method of manufacturing semiconductor device includes forming a multilayer photoresist structure including a metal-containing photoresist over a substrate. The multilayer photoresist structure includes two or more metal-containing photoresist layers having different physical parameters. The metal-containing photoresist is a reaction product of a first precursor and a second precursor, and each layer of the multilayer photoresist structure is formed using different photoresist layer formation parameters. The different photoresist layer formation parameters are one or more selected from the group consisting of the first precursor, an amount of the first precursor, the second precursor, an amount of the second precursor, a length of time each photoresist layer formation operation, and heating conditions of the photoresist layers. The multilayer photoresist structure is selectively exposed to actinic radiation to form a latent pattern, and the latent pattern is developed by applying developer to the selectively exposed multilayer photoresist structure to form the pattern. | 2021-09-30 |
20210305048 | METHODS TO REDUCE MICROBRIDGE DEFECTS IN EUV PATTERNING FOR MICROELECTRONIC WORKPIECES - Embodiments reduce or eliminate microbridge defects in extreme ultraviolet (EUV) patterning for microelectronic workpieces. A patterned layer is formed over a multilayer structure using an EUV patterning process. Protective material is then deposited over the patterned layer using one or more oblique deposition processes. One or more material bridges extending between line patterns within the patterned layer are then removed while using the protective material to protect the line patterns. As such, microbridge defects caused in prior solutions are reduced or eliminated. For one embodiment, the oblique deposition processes include physical vapor deposition (PVD) processes that apply the same or different protective materials in multiple directions with respect to line patterns within the patterned layer. For one embodiment, the removing includes one or more plasma trim processes. Variations can be implemented. | 2021-09-30 |
20210305049 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes first and second electrodes, first, fourth, and sixth semiconductor regions of a first conductivity type, a junction region, a fifth semiconductor region of a second conductivity type, and a gate electrode. The junction region includes a second semiconductor region of the first conductivity type and a third second semiconductor region of the second conductivity type. The second semiconductor regions and the third semiconductor regions are alternately provided in a second direction perpendicular to a first direction. A concentration of at least one first element selected from the group consisting of a heavy metal element and a proton in the junction region is greater a concentration of the first element in the fourth semiconductor region, or a density of traps in the junction region is greater than that in the first semiconductor region and greater than that in the fourth semiconductor region. | 2021-09-30 |
20210305050 | METHOD OF REDUCING VOIDS AND SEAMS IN TRENCH STRUCTURES BY FORMING SEMI-AMORPHOUS POLYSILICON - A microelectronic device with a trench structure is formed by forming a trench in a substrate, forming a seed layer in the trench, the seed layer including an amorphous dielectric material; and forming semi-amorphous polysilicon on the amorphous dielectric material. The semi-amorphous polysilicon has amorphous silicon regions separated by polycrystalline silicon. Subsequent thermal processes used in fabrication of the microelectronic device may convert the semi-amorphous polysilicon in the trench to a polysilicon core. In one aspect, the seed layer may be formed on sidewalls of the trench, contacting the substrate. In another aspect, a polysilicon outer layer may be formed in the trench before forming the seed layer, and the seed layer may be formed on the polysilicon layer. | 2021-09-30 |
20210305051 | Metal Wiring Method for Reducing Gate Resistance of a Narrow Control Gate Structure - A metal wiring method for reducing gate resistance of a narrow control gate structure, wherein the gate structure is etched with first gate electrodes and second gate electrodes at regular intervals and kept with complete gate electrodes at regular intervals, thereby constituting a structure in which the first and second gate electrodes and the complete gate electrodes are spaced apart. A first contact hole is etched on the complete gate electrode to draw out metal as a first metal layer. A second contact hole is etched on a source region and a split gate to draw out metal as a second metal layer. These two metal layers are separated by a dielectric layer. A multi-point contact of the first layer of metal with the gate electrode in a Y direction reduces the gate resistance caused by an excessively long path in the Y direction of a control gate electrode. | 2021-09-30 |
20210305052 | ENHANCED SPATIAL ALD OF METALS THROUGH CONTROLLED PRECURSOR MIXING - Methods of depositing a film by atomic layer deposition are described. The methods comprise exposing a substrate surface to a first process condition comprising a first reactive gas and a second reactive gas and exposing the substrate surface to a second process condition comprising the second reactive gas. The first process condition comprises less than a full amount of the second reactive gas for a CVD process. | 2021-09-30 |
20210305053 | SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING METHOD - A substrate processing apparatus includes a substrate rotator, a processing liquid supply, an anode and a cathode, and a controller. The substrate rotator is configured to hold and rotate a substrate. The processing liquid supply is configured to supply a processing liquid to the substrate held by the substrate rotator. The anode and the cathode are configured to apply a voltage to the processing liquid supplied from the processing liquid supply. The controller is configured to control the substrate rotator, the processing liquid supply, and the anode and the cathode. The controller allows, by contacting the anode and the cathode with the processing liquid independently, the processing liquid in contact with the anode and the processing liquid in contact with the cathode to be supplied to the substrate while being spaced apart from each other when the substrate is rotated. | 2021-09-30 |
20210305054 | SEMICONDUCTOR STRUCTURE ETCHING SOLUTION AND METHOD FOR FABRICATING A SEMICONDUCTOR STRUCTURE USING THE SAME ETCHING SOLUTION - The present disclosure provides an etching solution, including an ionic strength enhancer having an ionic strength greater than 10 | 2021-09-30 |
20210305055 | CONTROLLED HARDMASK SHAPING TO CREATE TAPERED SLANTED FINS - Embodiments described herein relate to methods forming optical device structures. One embodiment of the method includes exposing a substrate to ions at an ion angle relative to a surface normal of a surface of the substrate to form an initial depth of a plurality of depths. A patterned mask is disposed over the substrate and includes two or more projections defining exposed portions of the substrate or a device layer disposed on the substrate. Each projection has a trailing edge at a bottom surface contacting the device layer, a leading edge at a top surface of each projection, and a height from the top surface to the device layer. Exposing the substrate to ions at the ion angle is repeated to form at least one subsequent depth of the plurality of depths. | 2021-09-30 |
20210305056 | ETCHING METHOD AND ETCHING APPARATUS - An etching method is provided. In the etching method, a protective film-forming gas including an amine gas is supplied to a substrate having a surface on which a first film and a second film are formed, the first film and the second film having respective properties of being etched by an etching gas, and a protective film is formed to cover the first film such that the first film is selectively protected between the first film and the second film when the etching gas is supplied. Further, the second film is selectively etched by supplying the etching gas to the substrate after the protective film is formed. | 2021-09-30 |
20210305057 | ETCHING METHOD AND PLASMA PROCESSING APPARATUS - An etching method includes: (a) providing, on a support, a substrate having the first region covering the second region and the second region defining a recess receiving the first region, (b) etching the first region until or immediately before the second region is exposed, (c) exposing the substrate to plasma generated from a first process gas containing C and F atoms using a first RF signal and forming a deposit on the substrate, (d) exposing the deposit to plasma generated from a second process gas containing an inert gas using a first RF signal and selectively etching the first region to the second region, and (e) repeating (c) and (d). (c) includes using the RF signal with a frequency of 60 to 300 MHz and/or setting the support to 100 to 200° C. to control a ratio of C to F atoms in the deposit to greater than 1. | 2021-09-30 |
20210305058 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING APPARATUS, AND RECORDING MEDIUM - There is provided a technique that includes etching a crystalline film formed on a substrate by performing a cycle a predetermined number of times, the cycle including non-simultaneously performing: (1) supplying a boron-containing gas to the crystalline film; and (2) supplying a halide gas to the crystalline film. | 2021-09-30 |
20210305059 | ATOMIC LAYER ETCHING OF TUNGSTEN FOR ENHANCED TUNGSTEN DEPOSITION FILL - Methods of depositing tungsten into high aspect ratio features using a dep-etch-dep process integrating various deposition techniques with alternating pulses of surface modification and removal during etch are provided herein. | 2021-09-30 |
20210305060 | Cyclic Self-Limiting Etch Process - A method of processing a substrate includes forming a channel through a substrate, depositing a layer of polycrystalline silicon on sidewalls of the channel, and oxidizing uncovered surfaces of the polycrystalline silicon with an oxidation agent. The oxidizing agent causes formation of an oxidized layer, the oxidized layer having a uniform thickness on uncovered surfaces of the polycrystalline silicon. The method includes removing the oxidized layer from the channel with a removal agent, and repeating steps of oxidizing uncovered surfaces and removing the oxidized layer until removing a predetermined amount of the layer of polycrystalline silicon. | 2021-09-30 |
20210305061 | METHODS AND SYSTEMS OF FORMING METAL INTERCONNECT LAYERS USING ENGINEERED TEMPLATES - Described herein are methods and systems for forming metal interconnect layers (MILs) on engineered templates and transferring these MILs to device substrates. This “off-device” approach of forming MILs reduces the complexity and costs of the overall process, allows using semiconductor processes, and reduces the risk of damaging the device substrates. An engineered template is specially configured to release a MIL when the MIL is transferred to a device substrate. In some examples, the engineered template does not include barrier layers and/or adhesion layers. In some examples, the engineered template comprises a conductive portion to assist with selective electroplating. Furthermore, the same engineered template may be reused to form multiple MILs, having the same design. During the transfer, the engineered template and device substrate are stacked together and then separated while the MIL is transitioned from the engineered template to the device substrate. | 2021-09-30 |
20210305062 | METHOD FOR FORMING A SEMICONDUCTOR SUBSTRATE ARRANGEMENT - A method for forming a semiconductor substrate arrangement includes: forming a mask on a semiconductor substrate, the semiconductor substrate including and a metallization layer arranged on an insulation layer, the metallization layer arranged between the mask and insulation layer; forming a layer of electrically conductive coating on the metallization layer, the electrically conductive coating formed in at least one opening of the mask on regions of the metallization layer that are not covered by the mask; and after forming the electrically conductive coating, removing the mask. Forming the mask includes either applying an even layer of material on the metallization layer, or applying the material of the mask on the metallization layer such that the thickness of the mask in a region adjacent to edges of the mask is greater than the thickness of the regions of the mask further away from the edges. | 2021-09-30 |
20210305063 | 3D SEMICONDUCTOR DEVICE AND STRUCTURE - A 3D semiconductor device, the device including: a first level, wherein said first level comprises a first layer, said first layer comprising first transistors, and wherein said first level comprises a second layer, said second layer comprising first interconnections; a second level overlaying said first level, wherein said second level comprises a third layer, said third layer comprising second transistors, and wherein said second level comprises a fourth layer, said fourth layer comprising second interconnections; and a plurality of connection paths, wherein said plurality of connection paths provides connections from a plurality of said first transistors to a plurality of said second transistors, wherein said second level is bonded to said first level, wherein said bonded comprises oxide to oxide bond regions, wherein said bonded comprises metal to metal bond regions, wherein said second level comprises at least one Electrostatic discharge (ESD) circuit. | 2021-09-30 |
20210305064 | METHOD OF PACKAGING CHIP AND CHIP PACKAGE STRUCTURE - The present disclosure discloses a method of packaging a chip and a chip package structure. The method of packaging the chip includes: forming a protective layer on a front surface of a chip to be packaged; mounting the chip to be packaged formed with the protective layer on the front surface on a first carrier, the back surface of the chip to be packaged facing upwards and a front surface thereof facing towards the first carrier; forming a first encapsulation layer, the first encapsulation layer being formed on the back surface of the chip to be packaged and the exposed first carrier; and detaching the first carrier to exposed the protective layer. In the present disclosure, when the chip to be packaged is mounted on the carrier after the protective layer is formed on the front surface thereof, and then the first encapsulation layer is formed on the chip to be packaged, the encapsulation material can be prevented from permeating to the gap between the chip to be packaged and the carrier and thereby damaging the circuit structure and/or the bonding pad on the chip to be packaged. | 2021-09-30 |
20210305065 | CONVEYING MECHANISM - A conveying mechanism includes a suction part that has a suction pad and sucks and holds a target object by the suction pad, a bracket connected to the suction part through a joint that is swingable, an elastic component in which one end part is fixed to the suction part and the other end part is fixed to the bracket, a negative pressure control unit that controls generation of a negative pressure at the suction part, and a movement unit that moves the bracket. The elastic component permits a swing of the suction part according to tilt or deformation of the target object that is sucked and held and, when suction holding of the target object is released, the elastic component returns the orientation of the suction pad to a predetermined orientation when the suction pad is not sucking and holding the target object. | 2021-09-30 |
20210305066 | SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING APPARATUS - A substrate processing method includes holding a substrate on which a boron-containing silicon film is formed; supplying an oxidative aqueous solution including hydrofluoric acid and nitric acid to the held substrate; and etching the boron-containing silicon film of the substrate with the oxidative aqueous solution. | 2021-09-30 |
20210305067 | SUBSTRATE PROCESSING APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - There is provided a technique that includes: a first processing module including a first process container in which at least one substrate is processed and a substrate loading port installed at a front side of the first processing module; a first utility system including a first supply system configured to supply a first processing gas into the first process container, a surface of the first utility system is connected or arranged close to a rear surface of the first processing module; and a first vacuum-exhauster arranged behind the first processing module and configured to exhaust an inside of the first process container, wherein the first vacuum-exhauster includes an outer side surface configured such that the outer side surface does not protrude more outward than an outer side surface of the first utility system. | 2021-09-30 |
20210305068 | SEMICONDUCTOR PROCESSING DEVICE - A semiconductor processing device, comprising: a first chamber; a second chamber movable with respect to the first chamber portion between an open position and a closed position, a micro-chamber being formed between the first chamber portion and the second chamber portion when the second chamber portion is in the closed position with respect to the first chamber portion. The first chamber portion has a first channel formed on an inner wall surface of the first chamber portion facing the micro-chamber. The second chamber portion has a second channel formed on an inner wall surface of the second chamber portion facing the micro-chamber. When the second chamber portion is in the closed position with respect to the first chamber portion and a semiconductor wafer is accommodated in the micro-chamber, the first channel and the second channel communicate with each other and form an edge micro-processing space together, such that the outer edge of the semiconductor wafer accommodated in the micro-chamber extends into the edge micro-processing space. The edge micro-processing space is able to realize processing of the outer edge of the semiconductor wafer. | 2021-09-30 |
20210305069 | CLEANING APPARATUS FOR CLEANING MEMBER, SUBSTRATE CLEANING APPARATUS AND CLEANING MEMBER ASSEMBLY - As an aspect of the present invention, a cleaning apparatus for cleaning member has a holding part | 2021-09-30 |
20210305070 | OBJECT PROCESSING APPARATUS - An object processing apparatus comprising a chamber that has an internal space able to be depressurized and is configured such that a target object is subjected to a plasma treatment in the internal space; a first electrode that is disposed in the chamber and on which the target object is to be mounted; a first power supply that applies a bias voltage of negative potential to the first electrode; a gas introduction device that introduces a processing gas into an inside of the chamber; and a pumping device that depressurizes the inside of the chamber. A cover is provided between the first electrode and the target object so as to cover the first electrode. A spacer is located between the first electrode and the cover, and is disposed so as to occupy a localized region. | 2021-09-30 |
20210305071 | Processing of Workpieces Using Flourocarbon Plasma - Methods for processing a workpiece are provided. conducting a thermal treatment on a workpiece are provided. The workpiece contains at least one layer of metal. The method can include generating one or more species from a process gas. The process gas can include hydrogen or deuterium. The method can include filtering the one or more species to create a filtered mixture and exposing the workpiece to the filtered mixture. an oxidation process on a workpiece are provided. The method can be conducted at a process temperature of less than 350° C. | 2021-09-30 |
20210305072 | SUBSTRATE COOLING DEVICE - A substrate cooling device is provided and includes a device body and a conduit block. The device body has a housing space, and a discharge portion for receiving and discharging a substrate into and out of the housing space. The conduit block includes an outlet port arranged in the device body across the housing space from the discharge portion, and a gas flow passage which is connected to the outlet port and receives a cooling gas. The conduit block outputs the cooling gas from the outlet port across the housing space in one direction such that the cooling gas flows across an upper surface of the substrate in the one direction and across a lower surface of the substrate in the one direction. | 2021-09-30 |
20210305073 | TRANSFER STRUCTURE AND MANUFACTURING METHOD THEREOF, TRANSFER DEVICE AND MANUFACTURING METHOD THEREOF - Provided in the embodiments are a transfer structure and a manufacturing method thereof, and a transfer device and a manufacturing method thereof. The transfer structure includes: a first electrode, a piezoelectric layer, a second electrode and an adhesive layer stacked on a substrate in sequence, wherein the first electrode and the second electrode are insulated from each other. The transfer structure further includes: a position-limiting layer, wherein the position-limiting layer includes a cavity; the piezoelectric layer and at least part of the adhesive layer are located in the cavity of the position-limiting layer; and in the direction perpendicular to the substrate, the distance between the surface, away from the substrate, of the position-limiting layer and the substrate is greater than the distance between the surface, away from the substrate, of the adhesive layer and the substrate. | 2021-09-30 |
20210305074 | METHOD AND SYSTEM FOR RECOGNIZING AND ADDRESSING PLASMA DISCHARGE DURING SEMICONDUCTOR PROCESSES - A plasma discharge detection system detects undesirable plasma discharge events within a semiconductor process chamber. The plasma discharge detection system includes one or more cameras positioned around the semiconductor process chamber. The cameras capture images from within the semiconductor process chamber. The plasma discharge detection system includes a control system that receives the images from the cameras. The control system analyzes the images and detects plasma discharge within the semiconductor process chamber based on the images. The control system can adjust a semiconductor process in real time responsive to detecting the plasma discharge. | 2021-09-30 |
20210305075 | TRANSFER ROBOT AND SUBSTRATE PROCESSING APPARATUS HAVING THE SAME - The present invention disclosed herein relates to a transfer robot and a substrate processing apparatus having the same, and more particularly, to a transfer robot for transferring a substrate through a transfer module and a substrate processing apparatus having the same. The substrate processing system according to the present invention includes: a transfer module ( | 2021-09-30 |
20210305076 | ON THE FLY AUTOMATIC WAFER CENTERING METHOD AND APPARATUS - Substrate processing apparatus including a wafer transport apparatus with a transport arm including an end effector, an arm pose deterministic feature integral to the substrate transport apparatus and disposed so that a static detection sensor of the substrate processing apparatus detects at least one edge of the at least one arm pose deterministic feature on the fly with radial motion of the transport arm, and a controller configured so that detection of the edge effects a determination of a proportion factor identifying at least a thermal expansion variance of the transport arm on the fly and includes a kinematic effects resolver configured to determine, from the detection of the edge on the fly, a discrete relation between the determined proportion factor and each different discrete variance respective to each different link of the transport arm determining at least the thermal expansion variance of the transport arm on the fly. | 2021-09-30 |
20210305077 | DEVICE FOR SUPPORTING SUBSTRATE HAVING THERMAL EXPANSION COEFFICIENT - A device for supporting a substrate having a thermal expansion coefficient, includes: a base; an electrostatic chuck disposed on the base and having a substrate supporting region, the electrostatic chuck having a thermal expansion coefficient different from the thermal expansion coefficient of the substrate; and an annular elastic seal disposed on the substrate supporting region so as to make contact with the substrate supported on the substrate supporting region. | 2021-09-30 |
20210305078 | METHOD FOR TRANSFERRING MICRO LIGHT EMITTING DIODES - A method for transferring micro light emitting diodes (micro-LEDs) includes forming a plurality of micro light emitting diode (micro-LED) chips having an epitaxial stacked layer and an electrode on a base; attaching the electrodes of the micro-LED chips to a temporary substrate and removing the base from the micro-LED chips; forming a light shielding layer on the temporary substrate; forming a light-transmissible packaging layer to cover the light shielding layer and the micro-LED chips; removing the temporary substrate to form a light emitting assembly; dividing the light emitting assembly to separate a plurality of pixels constituted by the micro-LEDs; and transferring the pixels to a permanent substrate. | 2021-09-30 |
20210305079 | METHODS FOR PRODUCING A 3D SEMICONDUCTOR MEMORY DEVICE AND STRUCTURE - A method for producing a 3D memory device, the method including: providing a first level including a first single crystal layer and control circuits; forming at least one second level above the first level; performing a first etch step including etching holes within the second level; forming at least one third level above the at least one second level; performing a second etch step including etching holes within the third level; and performing additional processing steps to form a plurality of first memory cells within the second level and a plurality of second memory cells within the third level, where each of the first memory cells include one first transistor, where each of the second memory cells include one second transistor, where at least one of the first or second transistors has a channel, a source, and a drain having a same doping type. | 2021-09-30 |
20210305080 | WAFER SURFACE PROCESSING DEVICE - A detachable etching tool for etching a plurality of silicon carbide pieces has a first supporting column and a second supporting column, both of which are fixed through a tool fixing block. A bracket is arranged on the tool fixing block, and a limiting rod is installed on the lower end surface of the bracket. The bracket is inserted into the tool fixing block through the limiting rod and fixed on the tool fixing block with a fastening mechanism that comprises a base, a fixing seat, a telescopic spring, a telescopic guide column, a sliding block, a guide block, an inserting rod and a push-pull mechanism. The etching tool addresses low productivity per unit time and reduced speed in wafer etching processing. | 2021-09-30 |
20210305081 | TRANSFER DEVICE - A transfer device is disposed in a vacuum transfer chamber. The transfer device includes a structure body having an inner space isolated from the vacuum transfer chamber, an arm that rotates with respect to the structure body, and a vacuum seal structure configured to airtightly seal a sliding portion between the structure body and the arm. Further, the vacuum seal structure includes one or more seal members disposed at the sliding portion; a sealing portion formed by the structure body, the arm, and the seal members, lubricant being sealed in the sealing portion; and a pressure adjusting unit configured to adjust a pressure in the sealing portion. | 2021-09-30 |
20210305082 | SUPERSTRATE AND METHOD OF MAKING IT - A superstrate can comprise a superstrate blank and a coating overlying an outer surface of the superstrate blank. The superstrate blank can comprises a central region and a tapered edge region, wherein the tapered edge region has an average taper angle of not greater than 20 degrees relative to a length direction of the superstrate blank. In one embodiment, the coating of the superstrate can be applied by spin coating and may have an edge bead below a plane of the coating surface within the central region. | 2021-09-30 |
20210305083 | STACKED STRUCTURE AND SEMICONDUCTOR MANUFACTURING APPARATUS MEMBER - A stacked structure includes a first structure formed of a composite sintered body that contains AlN and MgAl | 2021-09-30 |
20210305084 | Reducing Parasitic Capacitance In Field-Effect Transistors - A semiconductor structure includes a semiconductor fin protruding from a substrate, an S/D feature disposed over the semiconductor fin, and a first dielectric fin and a second dielectric fin disposed over the substrate, where the semiconductor fin is disposed between the first dielectric fin and the second dielectric fin, where a first air gap is enclosed by a first sidewall of the epitaxial S/D feature and the first dielectric fin, and where a second air gap is enclosed by a second sidewall of the epitaxial S/D feature and the second dielectric fin. | 2021-09-30 |
20210305085 | SEMICONDUCTOR STRUCTURE HAVING EPITAXIAL STRUCTURE - A semiconductor structure having an epitaxial structure is provided. The semiconductor structure includes a first fin and a second fin on a semiconductor substrate. The semiconductor structure also includes an isolation feature over the semiconductor substrate to surround the first fin and the second fin. The semiconductor structure further includes an epitaxial structure on the first fin and the second fin. In addition, the semiconductor structure includes outer spacers on opposite sides of the epitaxial structure. The semiconductor structure also includes an inner spacer structure between the first fin and the second fin, wherein the inner spacer structure has a U-shape and covers a sidewall of the epitaxial structure. | 2021-09-30 |
20210305086 | Wafer Level Chip Scale Packaging Intermediate Structure Apparatus and Method - Presented herein is a WLCSP intermediate structure and method forming the same, the method comprising forming a first redistribution layer (RDL) on a carrier, the first RDL having mounting pads disposed on the first RDL, and mounting interposer dies on a second side of the first RDL. A second RDL is formed over a second side of the interposer dies, the second RDL having a first side adjacent to the interposer dies, one or more lands disposed on the second RDL, at least one of the one or more lands in electrical contact with at least one of the interposer dies or at least one of the mounting pads. A molding compound is formed around the interposer dies and over a portion of the first RDL prior to the forming the second RDL and the second RDL is formed over at least a portion of the molding compound. | 2021-09-30 |
20210305087 | SELF-ALIGNMENT ETCHING OF INTERCONNECT LAYERS - A method for etching a metal containing feature is provided. Using a pattern mask, layers of material are etched to expose a portion of a metal containing feature. At least a portion of the exposed metal containing feature is etched, and is replaced by the growth of a filler dielectric. The etched portion of the metal containing feature and the filler dielectric reduce the unwanted conductivity between adjacent metal containing features. | 2021-09-30 |
20210305088 | METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE - The present disclosure provides a method for manufacturing a semiconductor structure having different filling layers. The method includes forming a multi-layer stack in a semiconductor substrate, wherein the multi-layer stack has a first filling layer and a second layer, the semiconductor substrate has two through vias, and two top portions of the multi-layer stack are respectively exposed through the two through vias. The method further includes recessing the multi-layer stack from the two through vias to respectively form two blind holes in the first filling layer and the second filling layer; selectively etching the second filling layer to form a global cavity between the two blind holes; filling the global cavity and the two blind holes with dielectric filling material to form an air void in the multi-layer stack; and forming a switch device over the semiconductor substrate, wherein the air void is formed under the switch device. | 2021-09-30 |
20210305089 | DOUBLE PATTERNED LITHOGRAPHY USING SPACER ASSISTED CUTS FOR PATTERNING STEPS - A method includes forming a dielectric layer on a semiconductor substrate, forming a first mandrel layer and a second mandrel layer on the dielectric layer and patterning the first mandrel layer and the second mandrel layer to form respective first and second patterns in the first and second mandrel layers. The first pattern includes a first line segment and a first wing segment. The first wing segment is filled with a first spacer material to form a first spacer. The method further includes removing exposed portions of the first and second mandrel layers, transferring an image of the first and second patterns, patterning the dielectric layer and depositing a metal into the patterned dielectric layer to form a metallic interconnect structure. The metallic interconnect structure includes first and second metallic lines with the second metallic line having a line break corresponding to the first spacer. | 2021-09-30 |
20210305090 | DUAL DAMASCENE FULLY ALIGNED VIA INTERCONNECTS - Dual damascene interconnect structures with fully aligned via integration schemes are formed using different dielectric materials having different physical properties. A low-k dielectric material having good fill capabilities fills nanoscopic trenches in such structures. Another dielectric material forms the remainder of the dielectric portion of the interconnect layer and has good reliability properties, though not necessarily good trench filling capability. The nanoscopic trenches may be filled with a flowable polymer using flowable chemical vapor deposition. A further dielectric layer having good reliability properties is deposited over the metal lines and dual damascene patterned to form interconnect line and via patterns. The patterned dielectric layer is filled with interconnect metal, thereby forming interconnect lines and fully aligned via conductors. The via conductors are electrically connected to previously formed metal lines below. | 2021-09-30 |
20210305091 | Methods For Controllable Metal And Barrier-Liner Recess - Methods of etching a metal layer and a metal-containing barrier layer to a predetermined depth are described. In some embodiments, the metal layer and metal-containing barrier layer are formed on a substrate with a first dielectric and a second dielectric thereon. The metal layer and the metal-containing barrier layer formed within a feature in the first dielectric and the second dielectric. In some embodiments, the metal layer and metal-containing barrier layer can be sequentially etched from a feature formed in a dielectric material. In some embodiments, the sidewalls of the feature formed in a dielectric material are passivated to change the adhesion properties of the dielectric material. | 2021-09-30 |
20210305092 | ION IMPLANT PROCESS FOR DEFECT ELIMINATION IN METAL LAYER PLANARIZATION - The present disclosure describes a method for the planarization of ruthenium metal layers in conductive structures. The method includes forming a first conductive structure on a second conductive structure, where forming the first conductive structure includes forming openings in a dielectric layer disposed on the second conductive structure and depositing a ruthenium metal in the openings to overfill the openings. The formation of the first conductive structure includes doping the ruthenium metal and polishing the doped ruthenium metal to form the first conductive structure. | 2021-09-30 |
20210305093 | LATE GATE CUT WITH OPTIMIZED CONTACT TRENCH SIZE - A semiconductor structure is provided including a gate cut region in which the contact trench size has been optimized to increase local interconnect connectivity. The semiconductor structure can include at least one gate structure located laterally adjacent to a gate cut region. At least one metal-containing contact structure is located in the gate cut region, wherein the at least one at least one metal-containing contact structure is confined by a pair of gate dielectric spacers, wherein a first gate dielectric spacer of the pair of gate dielectric spacers has a first width and is located laterally adjacent to the at least one gate structure, and a second gate dielectric spacer of the pair of gate dielectric spacers has a second width and is located laterally adjacent to the at least one metal-containing contact structure, wherein the first width is greater than the second width. | 2021-09-30 |
20210305094 | SEMICONDUCTOR DEVICE AND METHOD - An embodiment is a method including forming a first interconnect structure over a first substrate, the first interconnect structure comprising dielectric layers and metallization patterns therein, patterning the first interconnect structure to form a first opening, coating the first opening with a barrier layer, etching a second opening through the barrier layer and the exposed portion of the first substrate, depositing a liner in the first opening and the second opening, filling the first opening and the second opening with a conductive material, and thinning the first substrate to expose a portion of the conductive material in the second opening, the conductive material extending through the first interconnect structure and the first substrate forming a through substrate via. | 2021-09-30 |
20210305095 | METHOD FOR FORMING A PACKAGED SEMICONDUCTOR DEVICE - A semiconductor wafer having a plurality of die is attached to a support structure. The semiconductor wafer includes an active layer over a silicon layer, wherein the active layer is at a top side, and a bottom side exposes the silicon layer. While the wafer is attached to the support structure, an infrared laser beam is focused through a portion of the silicon layer to create a modification region along saw lanes located between neighboring die of the plurality of die. Afterwards, a metal layer is formed on the exposed silicon layer at the bottom side of the semiconductor wafer. The metal layer is attached to an expansion tape, and the wafer is singulated by extending the expansion tape to separate the die of the plurality of die along the saw lane. A first singulated die of the plurality of die is packaged to form a packaged semiconductor device. | 2021-09-30 |
20210305096 | FAN-OUT WAFER LEVEL PACKAGING OF SEMICONDUCTOR DEVICES - In a general aspect, a fan-out wafer level package (FOWLP) can include a semiconductor die having an active surface, a backside surface, a plurality of side surfaces, each side surface of the plurality of side surfaces extending between the active surface and the backside surface, a plurality of conductive bumps disposed on the active surface, and an insulating layer disposed on a first portion of the active surface between the conductive bumps. The FOWLP can also include a molding compound encapsulating the backside surface, the plurality of side surfaces, and a second portion of the active surface between the conductive bumps and a perimeter edge of the active surface. The FOWLP can also include a signal distribution structure disposed on the conductive bumps, the insulating layer and the molding compound. The signal distribution structure can be configured to provide respective electrical connections to the plurality of conductive bumps. | 2021-09-30 |
20210305097 | LOW-TEMPERATURE METHOD FOR TRANSFER AND HEALING OF A SEMICONDUCTOR LAYER - The invention relates to a method for creating a substrate of the type semiconductor on insulator, comprising the following steps: | 2021-09-30 |
20210305098 | STACKED TRANSISTOR STRUCTURES WITH ASYMMETRICAL TERMINAL INTERCONNECTS - Integrated circuitry comprising stacked first and second transistor structures. One of a source, drain or gate terminal of an upper-level transistor structure is coupled to one of a source, drain or gate terminal of a lower-level transistor structure through an asymmetrical interconnect having a lateral width that increases within a dimension parallel to a semiconductor sidewall of the upper-level transistor by a greater amount than in an orthogonal dimension. A dielectric material between the upper and lower transistor structures may be anisotropically etched asymmetrically by orienting a workpiece to be non-orthogonal to a reactive ion flux. Varying an angle between the reactive ion flux and a plane of the second transistor during an etch of the dielectric material may ensure an etched opening is of sufficient bottom dimension to expose a terminal of the lower-level transistor even if not perfectly aligned with the second transistor structure. | 2021-09-30 |
20210305099 | Integrated Circuit Devices with Well Regions and Methods for Forming the Same - A method includes forming a deep well region of a first conductivity type in a substrate, implanting a portion of the deep well region to form a first gate, and implanting the deep well region to form a well region. The well region and the first gate are of a second conductivity type opposite the first conductivity type. An implantation is performed to form a channel region of the first conductivity type over the first gate. A portion of the deep well region overlying the channel region is implanted to form a second gate of the second conductivity type. A source/drain implantation is performed to form a source region and a drain region of the first conductivity type on opposite sides of the second gate. The source and drain regions are connected to the channel region, and overlap the channel region and the first gate. | 2021-09-30 |
20210305100 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming a first semiconductor layer having a first composition over a semiconductor substrate, and forming a second semiconductor layer having a second composition over the first semiconductor layer. Another first semiconductor layer having the first composition is formed over the second semiconductor layer. A third semiconductor layer having a third composition is formed over the another first semiconductor layer. The first semiconductor layers, second semiconductor layer, and third semiconductor layer are patterned to form a fin structure. A portion of the third semiconductor layer is removed thereby forming a nanowire comprising the second semiconductor layer, and a conductive material is formed surrounding the nanowire. The first semiconductor layers, second semiconductor layer, and third semiconductor layer include different materials. | 2021-09-30 |
20210305101 | SEMICONDUCTOR STRUCTURE IMPLEMENTING SERIES-CONNECTED TRANSISTOR AND RESISTOR AND METHOD FOR FORMING THE SAME - A semiconductor structure includes an isolation structure disposed in a semiconductor substrate; a gate electrode and a resistor electrode disposed in the semiconductor substrate, wherein the isolation structure is disposed between the gate electrode and the resistor electrode, and the isolation structure is closer to the resistor electrode than the gate electrode. A source/drain (S/D) region is disposed in the semiconductor substrate and between the gate electrode and the isolation structure, wherein the S/D region is electrically connected to the resistor electrode. A conductive structure is disposed in the semiconductor structure and over the isolation structure, wherein the S/D region is electrically connected to the resistor electrode through the conductive structure. | 2021-09-30 |
20210305102 | METHOD OF FABRICATING A FINFET DEVICE - In an embodiment, a method for fabricating a FinFET device includes providing a semiconductor substrate, etching the semiconductor substrate to form dummy fins and active fins. The group of dummy fins is etched through a patterned mask layer. An isolation feature is formed on the semiconductor substrate after etching the first group of dummy fins. | 2021-09-30 |
20210305103 | TRANSISTORS WITH SOURCE/DRAIN REGIONS HAVING SECTIONS OF EPITAXIAL SEMICONDUCTOR MATERIAL - Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. First and second gate structures extend over the semiconductor body. A source/drain region is positioned laterally between the first gate structure and the second gate structure. The source/drain region includes a semiconductor layer having a first section, a second section, and a third section. A first portion of the semiconductor body is positioned between the first section of the semiconductor layer and the second section of the semiconductor layer. A second portion of the semiconductor body is positioned between the second section of the semiconductor layer and the third section of the semiconductor layer. | 2021-09-30 |
20210305104 | CMOS TOP SOURCE/DRAIN REGION DOPING AND EPITAXIAL GROWTH FOR A VERTICAL FIELD EFFECT TRANSISTOR - A method includes forming a p-type field effect transistor region and an n-type field effect transistor region into a semiconductor substrate. The method implements a process flow to fabricate highly doped top source/drains with minimal lithography and etching processes. The method permits the formation of VFETs with increased functionality and reduced scaling. | 2021-09-30 |
20210305105 | COMPACT AND EFFICIENT CMOS INVERTER - A structure for providing an inverter circuit employing two vertical transistor structures formed on a semiconductor substrate. The vertical semiconductor structures each include a semiconductor pillar structure and a surrounding gate dielectric. A gate structure is formed to at least partially surround the first and second vertical transistor structures. The semiconductor substrate is formed into first and section regions that are separated by a dielectric isolation structure. The first region includes a P+ doped portion and an N+ doped portion, and the second region includes an N+ doped portion and a P+ doped portion. The N+ and P+ doped portions of the first and second regions can be arranged such that the N+ doped portion of the first region is adjacent to the P+ doped portion of the second region, and the P+ doped portion of the first region is adjacent to the N+ doped portion of the second region. | 2021-09-30 |
20210305106 | SUBSTRATE INSPECTION SYSTEM AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING SUBSTRATE INSPECTION SYSTEM - A substrate inspection apparatus includes a light source unit, a pulsed beam matching unit, a substrate support unit, an incidence angle adjusting unit, and a detecting unit. The light source unit emits a first laser beam having a first wavelength and a second laser beam having a second wavelength. The pulsed beam matching unit matches the first laser beam and the second laser beam to superimpose a pulse of the first laser beam on a pulse of the second laser beam in time and space. The substrate support unit supports a substrate to be inspected. The incidence angle adjusting unit adjusts angles of incidence of the matched first laser beam and second laser beams to irradiate the first laser beam and the second laser beam on the substrate, and mixes the first laser beam and the second laser beam to generate an evanescent wave on the substrate. The evanescent wave generates scattered light due to a defect of the substrate. The detecting unit detects the scattered light generated due to the defect of the substrate. | 2021-09-30 |
20210305107 | POWER SEMICONDUCTOR MODULE - Provided is a power semiconductor module that can secure insulating properties. A semiconductor element is mounted on a resin-insulated base plate including a circuit pattern, a resin insulating layer, and a base plate. A case enclosing the resin-insulated base plate is bonded to the resin insulating layer with an adhesive. The resin insulating layer and the case are bonded together with a region enclosed by the resin insulating layer and a tapered portion of the case formed closer to the resin insulating layer being filled with the adhesive made of a material identical to that of the sealing resin. Air bubbles in the adhesive appear in the tapered portion opposite to the resin insulating layer. | 2021-09-30 |
20210305108 | EMBEDDED DIE ARCHITECTURE AND METHOD OF MAKING - Various examples provide a semiconductor patch. The patch includes a glass core having first and second opposed major surfaces extending in an x-y direction. The patch further includes a conductive via extending from the first major surface to the second major surface substantially in a z-direction. The patch further includes a bridge die embedded in a dielectric material in communication with the conductive via. The patch further includes an overmold at least partially encasing the glass core. | 2021-09-30 |
20210305109 | Module with Gas Flow-Inhibiting Sealing at Module Interface to Mounting Base - A module includes an electronic component, an enclosure at least partially enclosing the electronic component and defining a module interface at which the module is configured to be mounted on a mounting base, and a gas flow-inhibiting sealing at the module interface and configured to inhibit gas from propagating from an exterior of the module towards the electronic component. An electronic device that includes the module and a method of manufacturing the module are also described. | 2021-09-30 |
20210305110 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - An object is to provide a technique capable of improving heat dissipation while maintaining the workability of a product in a semiconductor device. A semiconductor device includes power chips, control chips configured to control the power chips, power side terminals, control side terminals, and a mold resin covering the power chips, the control chips, one ends side of the power side terminals, and one ends side of the control side terminals. An other ends side of the power side terminals and an other ends side of the control side terminals protrude horizontally from a side surface of the mold resin and bend downward at middle parts thereof. Of the power side terminals and the control side terminals, only on the other ends side of the power side terminals, heat dissipation portions protruding in a direction approaching or away from the mold resin from portions bent downward are formed. | 2021-09-30 |
20210305111 | SEMICONDUCTOR DEVICE - In a semiconductor device, on a heat dissipation portion of a lead frame opposite to a mounting portion on which a semiconductor element is mounted, a thin molding portion having a thickness of about 0.02 mm to 0.3 mm is formed by a second molding resin which is a high-heat-dissipation resin. A scale-like portion on which scale-shaped projections are consecutively formed is provided over both sides across a resin boundary portion of the heat dissipation portion. The scale-like portion reaches abutting surfaces of an upper die and a lower die of a mold used in a molding process. Thus, the same void inhibition effect as with an air vent is obtained. | 2021-09-30 |
20210305112 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD OF SEMICONDUCTOR PACKAGE - A semiconductor package includes a first integrated circuit structure, a first encapsulation material laterally encapsulating the first integrated circuit structure, a first redistribution structure, a solder layer, a second integrated circuit structure, a second encapsulation material second laterally encapsulating the second integrated circuit structure and a second redistribution structure. The first integrated circuit structure includes a first metallization layer. The first redistribution structure is disposed over the first integrated circuit structure and first encapsulation material. The first metallization layer faces away from the first redistribution structure and thermally coupled to the first redistribution structure. The solder layer is dispose over the first redistribution structure. The second integrated circuit structure is disposed on the first redistribution structure and includes a second metallization layer in contact with the solder layer. The second redistribution structure is disposed over the second integrated circuit structure and the second encapsulation material. | 2021-09-30 |
20210305113 | MANUFACTURING METHOD OF A SEMICONDUCTOR PACKAGE - A manufacturing method of a semiconductor package including the following steps is provided. A redistribution structure is formed over an encapsulated semiconductor device carried by a carrier, wherein the redistribution structure includes an organic polymer layer and a redistribution circuit layer electrically connected to the semiconductor device. An inorganic protection layer is formed to entirely cover an upper surface of the redistribution structure, wherein an oxygen and/or water vapor permeability of the inorganic protection layer is substantially lower than an oxygen and/or vapor permeability of the organic polymer layer. An adhesive is formed on the inorganic protection layer. An insulating cover is adhered on the inorganic protection layer through the adhesive. | 2021-09-30 |
20210305114 | SEMICONDUCTOR PACKAGES - A semiconductor package may include a base, a first chip on the base, and first connection patterns that connect and couple the base and the first chip. The first chip may include a substrate, pad patterns on the substrate, a passivation layer on the substrate and having openings, and pillars on the substrate, the pad patterns include a first signal pad and a second signal pad, the first connection patterns are in contact with the pillars, the pillars include a first signal pillar in contact with the first signal pad and a second signal pillar in contact with the second signal pad, the openings in the passivation layer include a first opening having a sidewall facing a side surface of the first signal pillar and surrounding the side surface of the first signal pillar, and a second opening having a sidewall facing a side surface of the second signal pillar and surrounding the side surface of the second signal pillar, and a maximum width of the second opening is greater than a maximum width of the first opening. | 2021-09-30 |
20210305115 | SEMICONDUCTOR DEVICE - A semiconductor device including a substrate including a chip region and an edge region; integrated circuit elements on the chip region; an interlayer insulating layer covering the integrated circuit elements; an interconnection structure on the interlayer insulating layer and having a side surface on the edge region; a first and second conductive pattern on the interconnection structure, the first and second conductive patterns being electrically connected to the interconnection structure; a first passivation layer covering the first and second conductive patterns and the side surface of the interconnection structure; and a second passivation layer on the first passivation layer, wherein the second passivation layer includes an insulating material different from the first passivation layer, and, between the first and second conductive patterns, the second passivation layer has a bottom surface that is located at a vertical level lower than a top surface of the first conductive pattern. | 2021-09-30 |
20210305116 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor structure includes a substrate comprising a die pad disposed over the substrate, and a passivation disposed over the substrate and surrounding the die pad, a redistribution layer (RDL) comprising a dielectric layer disposed over the passivation and an interconnect structure disposed within the dielectric layer and electrically connecting with the die pad, a conductive bump disposed over and electrically connected with the interconnect structure; and an isolation layer surrounding the substrate and the RDL. | 2021-09-30 |
20210305117 | SEMICONDUCTOR PACKAGE HAVING STIFFENER - A semiconductor package includes a substrate including an upper surface and a side surface, an adhesive layer disposed on an edge of the upper surface of the substrate, and a stiffener including a horizontal portion disposed on the adhesive layer and extending in an horizontal direction to an outside of the substrate in a plan view and a vertical portion connected to the horizontal portion and extending vertically downwards from the horizontal portion. The vertical portion is spaced apart from the side surface of the substrate with a vertical gap extending in a vertical direction therebetween, and the outer width of the stiffener is 40 mm or more. | 2021-09-30 |
20210305118 | HEAT SPREADER EDGE STANDOFFS FOR MANAGING BONDLINE THICKNESS IN MICROELECTRONIC PACKAGES - A microelectronic package may be fabricated to include a microelectronic substrate, at least one microelectronic device attached to the microelectronic substrate, a heat dissipation device in thermal contact with at least one microelectronic device and having at least one projection attached to the microelectronic substrate, and at least one standoff extending from the at least one projection, wherein the at least one standoff contacts the microelectronic substrate to control the bond line thickness between the heat dissipation device and at least one microelectronic device and/or to control the bond line thickness of a sealant which may be used to attached the at least one projection to the microelectronic substrate. | 2021-09-30 |
20210305119 | IC DIE WITH SOLDERABLE THERMAL INTERFACE STRUCTURES FOR ASSEMBLIES INCLUDING SOLDER ARRAY THERMAL INTERCONNECTS - Thermal heat spreaders and/or an IC die with solderable thermal structures may be assembled together with a solder array thermal interconnects. A thermal heat spreader may include a non-metallic material and one or more metallized surfaces suitable for bonding to a solder alloy employed as thermal interface material between the heat spreader and an IC die. An IC die may include a metallized back-side surface similarly suitable for bonding to a thermal interconnect comprising a solder alloy. Metallization on the IC die and/or heat spreader may comprise a plurality of solderable structures. A multi-chip package may include multiple IC die having different die thickness that are accommodated by a z-height thickness variation in the thermal interconnects and/or the solderable structures of the IC die or heat spreader. | 2021-09-30 |
20210305120 | IC DIE AND HEAT SPREADERS WITH SOLDERABLE THERMAL INTERFACE STRUCTURES FOR MULTI-CHIP ASSEMBLIES INCLUDING SOLDER ARRAY THERMAL INTERCONNECTS - Thermal heat spreaders and/or an IC die with solderable thermal structures may be assembled together with a solder array thermal interconnects. A thermal heat spreader may include a non-metallic material and one or more metallized surfaces suitable for bonding to a solder alloy employed as thermal interface material between the heat spreader and an IC die. An IC die may include a metallized back-side surface similarly suitable for bonding to a thermal interconnect comprising a solder alloy. Metallization on the IC die and/or heat spreader may comprise a plurality of solderable structures. A multi-chip package may include multiple IC die having different die thickness that are accommodated by a z-height thickness variation in the thermal interconnects and/or the solderable structures of the IC die or heat spreader. | 2021-09-30 |
20210305121 | IC DIE AND HEAT SPREADERS WITH SOLDERABLE THERMAL INTERFACE STRUCTURES FOR ASSEMBLIES INCLUDING SOLDER ARRAY THERMAL INTERCONNECTS - Thermal heat spreaders and/or an IC die with solderable thermal structures may be assembled together with a solder array thermal interconnects. A thermal heat spreader may include a non-metallic material and one or more metallized surfaces suitable for bonding to a solder alloy employed as thermal interface material between the heat spreader and an IC die. An IC die may include a metallized back-side surface similarly suitable for bonding to a thermal interconnect comprising a solder alloy. Metallization on the IC die and/or heat spreader may comprise a plurality of solderable structures. A multi-chip package may include multiple IC die having different die thickness that are accommodated by a z-height thickness variation in the thermal interconnects and/or the solderable structures of the IC die or heat spreader. | 2021-09-30 |
20210305122 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A semiconductor package includes a circuit substrate, a die, a frame structure, a heat sink lid and conductive balls. The die is disposed on a front surface of the circuit substrate and electrically connected with the circuit substrate. The die includes two first dies disposed side by side and separate from each other with a gap between two facing sidewalls of the two first dies. The frame structure is disposed on the front surface of the circuit substrate and surrounding the die. The heat sink lid is disposed on the die and the frame structure. The head sink lid has a slit that penetrates through the heat sink lid in a thickness direction and exposes the gap between the two facing sidewalls of the two first dies. The conductive balls are disposed on the opposite surface of the circuit substrate and electrically connected with the die through the circuit substrate. | 2021-09-30 |