39th week of 2021 patent applcation highlights part 53 |
Patent application number | Title | Published |
20210303423 | MANAGING PRIMARY REGION AVAILABILITY FOR IMPLEMENTING A FAILOVER FROM ANOTHER PRIMARY REGION - The present disclosure generally relates to managing a failover service. The regional management service can receive a list of primary regions and a list of rules for each primary region that must be satisfied for a primary region to be considered available for failover from the respective primary region. The regional management service can then determine the primary regions that satisfy each rule of the list of rules for one or more primary regions and are available for failover of the respective primary regions. The regional management service can then deliver this information to a client. The regional management service can determine the primary regions that do not satisfy one or more of the rules from the list of rules for one or more primary regions and deliver this information to a client. The regional management service can perform automatic remediation and client remediation to the unavailable primary regions. | 2021-09-30 |
20210303424 | SSD WITH COMPRESSED SUPERBLOCK MAPPING TABLE - An improved solid state drive (SSD). The SSD comprising a plurality of non-volatile memory dies, each configured to store at least one block of data associated with one of a plurality of superblocks each containing a plurality of blocks; a volatile memory; and a memory controller. The memory controller configured to store a bit map associated with a first superblock of the plurality of superblocks in the volatile memory, wherein the bit map is configured to indicate whether each of the plurality of blocks is a replacement block, store a block address list in the volatile memory, the block address list is configured to store an address of one or more replacement blocks, and store a replacement block index in the volatile memory associated with the first superblock of the plurality of superblocks, the replacement block index corresponding to the location of an address of a first replacement block of the first superblock in the block address list. | 2021-09-30 |
20210303425 | DYNAMIC MAPPING OF LOGICAL TO PHYSICAL MEMORY FOR INCREASED PERFORMANCE - Data protection systems and techniques that include: receiving data for storage in a non-volatile memory (NVM) array having a total number of physical packages that includes a number of spare physical packages, wherein each one of the physical packages is mapped to one of a plurality of logical packages; storing a respective portion of component codewords on the non-spare physical packages; and in response to one of the non-spare physical packages failing, dynamically remapping the failed physical package to one of the logical packages mapped to one of the available spare physical packages. In an aspect, reading at least the failed physical package and inserting virtual zeros into the respective portion of the component codewords corresponding to the failed physical package; performing erasure decoding to recover the data from the failed package; and rewriting the recovered data from the failed package into the one of the available spare physical packages. | 2021-09-30 |
20210303426 | SYSTEMS AND METHODS FOR TESTING MANY-CORE PROCESSORS BACKGROUND - Systems and methods are provided for testing many-core processors consisting of processing element cores. The systems and methods can include grouping the processing elements according to the dataflow of the many-core processor. Each group can include a processing element that only receives inputs from other processing elements in the group. After grouping the processing elements, test information can be provided in parallel to each group. The test information can be configured to ensure a desired degree of test coverage for the processing element that that only receives inputs from other processing elements in the group. Each group can perform testing operations in parallel to generate test results. The test results can be read out of each group. The processing elements can then be regrouped according to the dataflow of the many-core processor and the testing can be repeated to achieve a target test coverage. | 2021-09-30 |
20210303427 | SYSTEM FOR TESTING A BLOCKCHAIN ENABLED DEVICE-UNDER-TEST - The invention relates to a system for testing a blockchain enabled device-under-test, comprising: a blockchain data unit configured to receive and/or generate blockchain data, an interface unit configured to transmit a signal encoding said blockchain data to the blockchain enabled device-under-test via a preferably wireless communication channel, and a control unit configured to selectively adjust transmission parameters of said signal or said communication channel preferably to simulate mobile network characteristics. | 2021-09-30 |
20210303428 | ERROR RATE MEASURING APPARATUS AND ERROR COUNTING METHOD - An error rate measuring apparatus includes an operation unit that sets one Codeword length and one FEC Symbol length of FEC according to a communication standard of a device under test W, a storage unit that stores symbol string data obtained by receiving and converting a signal from the device under test W, data division means for dividing the stored symbol string data into MSB data and LSB data, a data comparison unit that compares each of the divided MSB data and LSB data with error data to detect each of MSB errors and LSB errors of each one Codeword length, and detects FEC Symbol Errors of each of the MSB data and the LSB data at one FEC Symbol interval, and error counting means for counting the detected MSB errors, LSB errors, and FEC Symbol Errors. | 2021-09-30 |
20210303429 | Multiple Name Space Test Systems and Methods - Presented embodiments facilitate efficient and effective flexible implementation of different types of testing procedures in a test system. In one embodiment, a multiple-name-space testing system comprises a load board, testing electronics, and a namespace testing tracker. The load board is configured to couple with a plurality of devices under test (DUTs). The testing electronics are configured to test the plurality of DUTs, wherein the testing electronics are coupled to the load board. The controller is configured to direct testing of multiple-name-spaces across the plurality of DUTs at least in part in parallel. The controller can be coupled to the testing electronics. The namespace testing tracker is configured to track testing of the plurality of DUTs, including the testing of the multiple-name-spaces across the plurality of DUTs at least in part in parallel. In one embodiment, the DUTs are NVMe SSD devices. | 2021-09-30 |
20210303430 | Enhanced Auxiliary Interface Systems and Methods - Presented embodiments facilitate efficient and effective flexible implementation of different types of testing procedures in a test system. Presented embodiments facilitate efficient and effective flexible implementation of different types of testing procedures in a test system. In one embodiment, an enhanced auxiliary interface test system comprises a load board, testing electronics, controller, and memory mapped interface. The load board is configured to couple with a plurality of devices under test (DUTs). The testing electronics is configured to test the plurality of DUTs, wherein the testing electronics are coupled to the load board. The controller is configured to direct testing of the DUTs, wherein the controller is coupled to the testing electronics. The memory mapped interface is configured to implement multiple paths to access a central processing unit (CPU) on the controller and enable testing of multiple DUTs in parallel. | 2021-09-30 |
20210303431 | METHODS AND SYSTEMS THAT IDENTIFY DIMENSIONS RELATED TO ANOMALIES IN SYSTEM COMPONENTS OF DISTRIBUTED COMPUTER SYSTEMS USING CLUSTERED TRACES, METRICS, AND COMPONENT-ASSOCIATED ATTRIBUTE VALUES - The current document is directed to methods and systems that employ distributed-computer-system metrics collected by one or more distributed-computer-system metrics-collection services, call traces collected by one or more call-trace services, and attribute values for distributed-computer-system components to identify attribute dimensions related to anomalous behavior of distributed-computer-system components. In a described implementation, nodes correspond to particular types of system components and node instances are individual components of the component type corresponding to a node. Node instances are associated with attribute values and node are associated with attribute-value spaces defined by attribute dimensions. A set of call traces is partitioned, by clustering. Using attribute values and call traces, attribute dimensions that are likely related to particular anomalous behaviors of distributed-computer-system components are determined by decision-tree-related analyses for each partition and are reported to one or more computational entities to facilitate resolution of the anomalous behaviors. | 2021-09-30 |
20210303432 | COMPUTER PROGRAM PRODUCT AND METHOD AND APPARATUS FOR CONTROLLING ACCESS TO FLASH MEMORY CARD - The invention is related to a non-transitory computer program product, a method and an apparatus for controlling access to a flash memory card. The method, performed by a processing unit of a bridge integrate circuit (IC), includes: determining whether a temperature of a motherboard has exceeded a threshold through a temperature sensor IC after receiving a host read or write command from a host side; requesting a flash memory card to enter a sleep state when the temperature of the motherboard has exceeded the threshold; and instructing the flash memory card to perform an operation corresponding to the host read or write command when the temperature of the motherboard hasn't exceeded the threshold. The bridge IC and the temperature sensor IC are disposed on the motherboard, the flash memory card is inserted into a card slot on the motherboard, and the bridge IC is coupled to the temperature sensor IC and the flash memory card through a circuit of the motherboard. | 2021-09-30 |
20210303433 | COMPONENT INSTALLATION VERIFICATION - In an approach for a component installation, a processor receives sensor data from a sensor scanning a component. The component is to be installed into a receptacle. A processor compares the sensor data to reference data. The reference data is pre-collected data associated with the type of the component and the type of the receptacle. The reference data defines the correct type of the component to be installed in the receptacle. The reference data defines a damage status of the type of the component. A processor determines whether the component has damage. A processor determines whether the component is a correct type of component to be installed in the receptacle. A processor provides an indication for installation. | 2021-09-30 |
20210303434 | Application Performance Management Information Display Method and Apparatus, Device and Storage Medium - A method, an apparatus, a device, and a storage medium for displaying application performance management information are provided. The method includes: separately obtaining first and second performance status information of services provided by a first application and a second application; determining first and second display specifications of respective graphics corresponding to the first and second performance status information, to enable a ratio of the first display specification to the second display specification to be not greater than a preset value; and displaying the respective graphics corresponding to the first and second performance status information according to the determined first and second display specifications. | 2021-09-30 |
20210303435 | METHOD, DEVICE, AND COMPUTER PROGRAM PRODUCT FOR OBTAINING DIAGNOSTIC INFORMATION - Techniques may involve determining, according to determination that a received system alarm corresponds to a predefined to-be-monitored alarm, the received system alarm as a target system alarm. The techniques may further involve determining a system module corresponding to the target system alarm based on a predefined mapping relationship between the system alarm and the system module. In addition, the techniques may further involve acquiring the system diagnostic information of the system module which is associated with the target system alarm. In this way, time for collecting system diagnostic information can be reduced and user experience can be improved. | 2021-09-30 |
20210303436 | MACHINE LEARNING BASED DATA MONITORING - An overall performance metric of a computer system may be determined for each bin of the set of analysis bins. In case one or more bins of the set of analysis bins do not have at least a predefined minimum number of records, a new set of analysis bins may be redefined by joining analysis bins of the set of analysis bins. For each bin of the redefined set of bins a machine learning (ML) performance metric of the ML model may be computed. The ML performance metric may be estimated for the set of analysis bins using the ML performance metrics of the redefined bins. The computer system may be configured based on a correlation over the set of analysis bins between the computed overall performance metric and the ML performance metric. | 2021-09-30 |
20210303437 | ANALYSING REACTIVE USER DATA - A method, a structure, and a computer system for analysing user reactive data is disclosed herein. Exemplary embodiments may include detecting interaction with data by a user and extracting one or more user features from the user. Exemplary embodiments may further include extracting one or more data features from the data and identifying one or more data features interacted with by the user of the one or more data features. Moreover, exemplary embodiments may further include matching the one or more user features with the one or more data features interacted with by the user, and determining an interest level in the one or more data features interacted with by the user based on the matched one or more user features. | 2021-09-30 |
20210303438 | Methods and Systems that Identify Dimensions Related to Anomalies in System Components of Distributed Computer Systems using Traces, Metrics, and Component-Associated Attribute Values - The current document is directed to methods and systems that employ distributed-computer-system metrics collected by one or more distributed-computer-system metrics-collection services, call traces collected by one or more call-trace services, and attribute values for distributed-computer-system components to identify attribute dimensions related to anomalous behavior of distributed-computer-system components. In a described implementation, nodes correspond to particular types of system components and node instances are individual components of the component type corresponding to a node. Node instances are associated with attribute values and node are associated with attribute-value spaces defined by attribute dimensions. Using attribute values and call traces, attribute dimensions that are likely related to particular anomalous behaviors of distributed-computer-system components are determined by decision-tree-related analyses and are reported to one or more computational entities to facilitate resolution of the anomalous behaviors. | 2021-09-30 |
20210303439 | INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, AND PROGRAM - Erroneous ignitions of a process of a device caused by characteristics of speeches/behaviors of a user are efficiently prevented. | 2021-09-30 |
20210303440 | CONTEXTUAL DRILL BACK TO SOURCE CODE AND OTHER RESOURCES FROM LOG DATA - A system receives real-time log messages from an executing process that experiences a runtime error. Information such as a filename and line number for the underlying source code may be embedded in the log messages using compiler macros. When the log messages are received, a developer URL may be generated that links a developer workstation directly to the underlying source code file and line number in a source code repository. A support URL may also be generated with a link to a support center and an embedded search string that retrieves resources that are known to address the process error. | 2021-09-30 |
20210303441 | SYSTEMS AND METHODS FOR DYNAMICALLY LOGGING APPLICATION DATA - Methods and systems are presented for dynamically configuring a software application to log different data variables without requiring re-deploying the software application. When a software application is executed, the software application may obtain and/or generate data variables. During runtime of the software application while processing a request, the software application may access a log script external to the software application. The software application may select a subset of data variables for logging, and may record only the subset of data variables in a log file. The log script may be modified without requiring the software application to be modified or re-deployed such that the software application may log different subset of data variables while processing different processes based on different versions of the log script. | 2021-09-30 |
20210303442 | SYSTEM AND METHOD FOR IDENTIFICATION OF APPROPRIATE TEST CASES USING ARTIFICIAL INTELLIGENCE FOR SOFTWARE TESTING - A method and a system of selecting test cases from existing test cases for a new software testing requirement are disclosed. In an embodiment, the method may include determining a confidence score associated with each of existing test cases, based on comparing a new software testing requirement with the existing test cases using a Recurrent Neural Network (RNN) model, and selecting a set of test cases from the existing test cases based on the confidence score and a predetermined threshold confidence score. The method may further include predicting a defect slippage rate associated with each test case using a linear regression model, and shortlisting a sub-set of test cases from the set of test cases based on the predicted defect slippage rate associated with each test case and a predetermined threshold defect slippage rate. | 2021-09-30 |
20210303443 | METHOD AND APPARATUS FOR PROTECTING TRACE DATA OF A REMOTE DEBUG SESSION - Methods and apparatus for protecting trace data of a remote debug session for a computing system. In one embodiment, a method includes storing trace data received from one or more trace interfaces to a storage location of a target device, where the trace data is generated from execution at the target device, and where the trace data is protected from an unauthorized access. The method continues with transmitting the trace data to a debug host computer with encryption through a communication channel between the target device and the debug host computer. | 2021-09-30 |
20210303444 | Method, apparatus and computer program and user interface and technique to debug software code - A method, program and a graphical user interface to navigate through different watch points at which a variable changes its value and look at instantaneous values of all the variables in the same stack at that point of time, while hovering on the code on a graphical integrated development environment. This method may also include a method to determine which data to store based on anomalies on both the data and the times at which this data was written. The anomalies might be calculated using standard anomaly detection techniques and/or machine learning | 2021-09-30 |
20210303445 | SCANNER SOFTWARE MODULE FOR HIGH SYSTEM UTILIZATION - A method is provided comprising: storing one or more tickets in a ticket database, each of the tickets being associated with a corresponding test system, and each of the tickets being associated with an error that is generated as a result of executing one of a plurality of tests on the ticket's corresponding test system; executing a reclamation agent that is configured to: retrieve a plurality of tickets from a ticket database, detect if each of the tickets satisfies a predetermined condition, and return the ticket's corresponding test system to a pool of available test systems when the predetermined condition is satisfied by the ticket. | 2021-09-30 |
20210303446 | ISSUE REPORTING CONTEXT SESSION IDENTIFIER FOR ISSUE TRACKING SYSTEMS - An issue tracking system includes a host device executing an issue tracking service in communication with a client device executing at least one of an issue reporting application and/or an application under test. The issue reporting application generates a session identifier that defines a debugging session. The application under test can receive the identifier and tag logs or other data generated during the debugging session. The issue reporting application can thereafter receive the debugging data and can populate an issue report template based on that data. | 2021-09-30 |
20210303447 | REAL-TIME CODE RECOMMENDATIONS USING MACHINE LEARNING AND REINFORCEMENT LEARNING - Methods, systems, and computer-readable storage media for receiving, from an integrated development environment (IDE), authored code, the authored code having been input by a developer to the IDE, receiving developer data representative of the developer, and context data and domain data associated with the authored code, determining, at least partially based on processing the authored code, the developer data, the context data, and the domain data through one or more machine learning (ML) models, that one or more code recommendations are to be displayed to the developer in the IDS, defining a sub-set of code recommendations at least partially based on the authored code and the context data, the sub-set of code recommendations comprising at least one code snippet, and displaying graphical representations of code recommendations in the sub-set of code recommendations to the developer within the IDE. | 2021-09-30 |
20210303448 | TEST CASE GENERATION FOR SOFTWARE DEVELOPMENT USING MACHINE LEARNING - A device configured to receive an impact report request that comprises a program identifier for a first program. The device is further configured to determine a location within a spatial domain for the first program. The device is further configured to determine a first distance threshold value that corresponds with a first distance away from the location of the first program within the spatial domain. The device is further configured to determine distances between the location of the first program and locations of other programs from the plurality of programs and to identify one or more programs from the plurality of programs that are less than the first distance threshold value. The device is further configured to generate an impact report that identifies the one or more programs from the plurality of programs that are less than the first distance threshold value and to output the generated impact report. | 2021-09-30 |
20210303449 | FLEXIBLE TEST PROGRAM GENERATION BY ALTERING PREVIOUSLY USED RESOURCES - A method for flexible test program generation is described that alters previously used resources. The method includes scanning, by a test generator, a set of instructions that have been executed by a system under test (SUT) using a reference model of the SUT. The method further includes identifying, by the test generator, a resource for using in a test program by determining an allocation of a first value to the resource by a subset of instructions from the set of instructions, wherein the first value of the resource is not used after the allocation. The method further includes modifying the subset of instructions to allocate a second value to the resource, and adding to the set of instructions, at least one instruction that uses the second value to perform a predetermined operation. The SUT is tested based on a result of the predetermined operation that uses the second value. | 2021-09-30 |
20210303450 | TEST CASE OPTIMIZATION AND PRIORITIZATION - Methods, systems, and apparatuses, including computer programs encoded on computer-storage media, for prioritizing test cases. Processes may include obtaining test artifacts that were generated based on testing one or more legacy versions of a software application using multiple test cases, generating a risk index based at least on the test artifacts that were generated based on testing the one or more legacy versions of the software application using the multiple test cases, and training an ensemble model that is configured to identify likely unnecessary or redundant test cases in connection with in testing an updated version of the software application, based at least on the risk index. | 2021-09-30 |
20210303451 | SYSTEMS AND METHODS FOR GENERATING MODIFIED APPLICATIONS FOR CONCURRENT TESTING - A device may receive parameters to test modifications to an application associated with a product and/or a service, and may process data identifying the parameters and the application, with a machine learning model, to generate test applications for testing corresponding modifications to the application. The device may define test group sizes of test groups for testing the test applications, and may receive, from user devices, requests for accessing the application. The device may assign, based on the test group sizes, sets of the user devices to the test groups for testing the test applications, and may provide the test applications concurrently to the corresponding sets of the user devices based on the test groups. The device may receive, from the corresponding sets of the user devices, feedback associated with the test applications, and may perform one or more actions based on the feedback. | 2021-09-30 |
20210303452 | VALIDATION OF A SUBSET OF A PLURALITY OF RESPONSES DURING PROTOCOL TESTING - A computer-implemented method according to one embodiment includes receiving, by a protocol server, a source code file. The source code file includes a TCDF. The TCDF includes parameters for a test case, preparation steps related to the test case, and a plurality of test case blocks. Each test case block of the plurality of test case blocks includes a set of testing steps and a certificate. The source code file is output by the protocol server to a SUT with an instruction for the SUT to execute the source code file in order to implement the set of testing steps for each of the plurality of test case blocks. A plurality of responses are received by the protocol server from the SUT. Each of the responses are compared against the certificates of the test case blocks. A test result is generated by the protocol server based on the comparisons. | 2021-09-30 |
20210303453 | KNOWLEDGE CENTRIC APPROACH TO AUTO-GENERATE TEST SPECIFICATIONS FOR IOT SOLUTIONS - This disclosure relates generally to a system and method for auto-generation of test specifications from internet of things (IoT) solution specifications of IoT-enabled components of an IoT network. Testing is the complementary and most important part of any IoT network. Herein, a domain specific language (DSL) is used to specify capability of IoT enabled components. IoT solution specifications are captured from capabilities of IoT enabled components using a predefined activity DSL. A flow of activity is captured to assert transitions among one or more activities based on guard conditions. The flow of activity is analyzed to generate test specifications automatically using a Test Specification DSL based on the asserted transitions. The test specifications are implemented automatically in a predefined target language corresponding to the IoT enabled components. | 2021-09-30 |
20210303454 | METHOD, DEVICE, AND PROGRAM PRODUCT FOR EVALUATING APPLICATION PROGRAM INTERFACE - A method, a device, and a program product for evaluating an application program interface (API) are provided in embodiments of the present disclosure. According to some embodiments, a method for evaluating an API includes determining a specification score of the API by comparing a definition description for the API with a predetermined specification corresponding to the API. The specification score indicates a degree of matching between the definition description and the predetermined specification. Additionally, the method for evaluating an API includes determining a test score for the API by applying a predetermined test case set to a code set of the API. The test score indicates a test status for the code set. Further, the method for evaluating an API includes determining a maturity metric of the API based on the specification score and the test score. | 2021-09-30 |
20210303455 | Dynamic Management and Control of Test Features in Native Applications - Techniques are described herein for enhancing software application development and software design-for-test (DFT) technology by facilitating dynamic management and control of embedded dynamic test features via an application development and optimization platform. In some embodiments, an application development and optimization platform is described that can track, manage and rollout features of native mobile applications without the need to wait for public app store releases. | 2021-09-30 |
20210303456 | MEMORY SYSTEM AND OPERATING METHOD THEREOF - A memory system includes a nonvolatile memory apparatus, and a write-same manager configured to perform a write-same operation on the nonvolatile memory apparatus, wherein the write-same manager merges a first write-same operation and a second write-same operation by comparing first operation information of the first write-same operation and second operation information of the second write-same operation. | 2021-09-30 |
20210303457 | PARALLEL OVERLAP MANAGEMENT FOR COMMANDS WITH OVERLAPPING RANGES - A storage device includes: one or more logical blocks to store host data received from a host device, the logical blocks having a logical block address (LBA); an LBA range table to store one or more LBA ranges associated with one or more commands received from the host device over a storage interface; and an overlap check circuit to compare an LBA range associated with an active request with the one or more LBA ranges associated with the one or more commands, and to determine an overlap between the LBA range associated with the active request and any of the one or more LBA ranges associated with the one or more commands | 2021-09-30 |
20210303458 | METHOD, DEVICE AND COMPUTER PROGRAM PRODUCT FOR BUILDING AND VERIFYING INDEX FILE - Embodiments of the present disclosure relate to establishing and verifying an index file. The method for establishing an index file includes: in response to receiving a data block to be stored, determining first verification information for verifying the data block and a first storage address for storing the data block. This method further includes: based on the first verification information, determining an index entry for the data block and a second storage address for storing the index entry, wherein the index entry includes the first verification information and the first storage address, and the index entry will be included in the index file. This method further includes: based on the index entry and the second storage address, determining second verification information. This method further includes: based on the second verification information and historical verification information for the index file, determining third verification information for verifying the index file. | 2021-09-30 |
20210303459 | MEMORY CONTROLLER AND METHOD FOR MONITORING ACCESSES TO A MEMORY MODULE - The application discloses a memory controller coupled between a memory module and a host controller to control accesses of the host controller to the memory module. The memory controller comprises a central buffer coupled between the memory module and the host controller via a command/address channel, wherein the central buffer is configured to receive a command/address signal from the host controller and provide the command/address signal to the memory module. The central buffer comprises: a recognition block coupled to the command/address channel to receive the command/address signal, wherein the recognition block is configured to generate access history information based on the received command/address signal; a compression block coupled to the recognition block to receive the access history information, wherein the compression block is configured to compress the access history information; and a transmission block, wherein the compressed access history information is transmitted out from the central buffer via the transmission block. | 2021-09-30 |
20210303460 | STORAGE SYSTEM HAVING A HOST DIRECTLY MANAGE PHYSICAL DATA LOCATIONS OF STORAGE DEVICE - A storage system includes a host including a processor and a memory unit, and a storage device including a controller and a non-volatile memory unit. The processor is configured to output a write command, write data, and size information of the write data, to the storage device, the write command that is output not including a write address. The controller is configured to determine a physical write location of the non-volatile memory unit in which the write data are to be written, based on the write command and the size information, write the write data in the physical write location of the non-volatile memory unit, and output the physical write location to the host. The processor is further configured generate, in the memory unit, mapping information between an identifier of the write data and the physical write location. | 2021-09-30 |
20210303461 | DEEP OBJECT GRAPH TRAVERSAL - A first thread of a garbage collector can determine fields, in class metadata assigned to objects contained in a local memory, that are self-referencing fields. For a plurality of the objects, recursively, the first thread can determine whether the object has at least one child object, indicated by a self-referencing field of the object, that has not been assigned to a destination cache or a previously generated source cache. If so, the first thread can assign the child object to the destination cache to indicate that the child object is live. The first thread can add the destination cache to a global scan queue as a source cache. A second thread of the garbage collector can initiate object scanning on objects indicated in the first source cache. Memory locations where live objects are not located can be reclaimed. | 2021-09-30 |
20210303462 | DEEP OBJECT GRAPH TRAVERSAL - A first thread of a garbage collector can determine fields, in class metadata assigned to objects contained in a local memory, that are self-referencing fields. For a plurality of the objects, recursively, the first thread can determine whether the object has at least one child object, indicated by a self-referencing field of the object, that has not been assigned to a destination cache or a previously generated source cache. If so, the first thread can assign the child object to the destination cache to indicate that the child object is live. The first thread can add the destination cache to a global scan queue as a source cache. A second thread of the garbage collector can initiate object scanning on objects indicated in the first source cache. Memory locations where live objects are not located can be reclaimed. | 2021-09-30 |
20210303463 | System and Method of Data Writes and Mapping of Data for Multiple Sub-Drives - A system and method is disclosed for managing data in a non-volatile memory. The system may include a non-volatile memory having multiple non-volatile memory sub-drives. A controller of the memory system is configured to route incoming host data to a desired sub-drive, keep data within the same sub-drive as its source during a garbage collection operation, and re-map data between sub-drives, separate from any garbage collection operation, when a sub-drive overflows its designated amount logical address space. The method may include initial data sorting of host writes into sub-drives based on any number of hot/cold sorting functions. In one implementation, the initial host write data sorting may be based on a host list of recently written blocks for each sub-drive and a second write to a logical address encompassed by the list may trigger routing the host write to a hotter sub-drive than the current sub-drive. | 2021-09-30 |
20210303464 | MEMORY SYSTEM, MEMORY CONTROLLER AND METHOD OF OPERATING THE SAME - Provided herein may be a memory controller configured to control a memory device. The memory controller may include a map buffer, a descriptor queue, and a descriptor controller. The map buffer may sequentially store map segments of a plurality of map segments stored in the memory device. The descriptor queue may store descriptors corresponding to the respective map segments, based on a plurality of addresses of the map buffer. The descriptor controller may search for a target descriptor among the stored descriptors based on a logical address received from a host, and reorder the stored descriptors while searching for the target descriptor. | 2021-09-30 |
20210303465 | CACHE MANAGEMENT METHOD, CACHE MANAGEMENT SYSTEM, AND INFORMATION PROCESSING APPARATUS - A cache management method performed by an information processing apparatus includes: in a case where a correspondence relation between a request and a response to the request is not stored in a first cache, executing a plurality of operations for generating the response to the request; in association with input data of each operation of the plurality of operations, storing a result of the operation in a second cache; storing the response generated based on results of the plurality of operations in the first cache in association with the request; and returning the response with respect to the request. | 2021-09-30 |
20210303466 | SERVICING QUERIES DURING DATA INGRESS - A method for execution by a temporary ingress storage system includes receiving a set of records to be processed for long-term storage. The set of records are temporarily stored in a set of memory resources of the temporary ingress storage system during a first temporal period. Execution of a query is facilitated by accessing a subset of the set of records from at least one memory resource of the set of memory resources during the first temporal period. The set of records are processed to generate a set of segments for long-term storage. Migration of the set of records from the temporary ingress storage system to a long-term storage system for during a second temporal period that begins after the first temporal period has elapsed by sending the set of records to the long-term storage system. | 2021-09-30 |
20210303467 | APPARATUSES, METHODS, AND SYSTEMS FOR DYNAMIC BYPASSING OF LAST LEVEL CACHE - Systems, methods, and apparatuses relating to circuitry to implement dynamic bypassing of last level cache are described. In one embodiment, a hardware processor includes a cache to store a plurality of cache lines of data, a processing element to generate a memory request and mark the memory request with a reuse hint value, and a cache controller circuit to mark a corresponding cache line in the cache as more recently used when the memory request is a read request that is a hit in the cache and the reuse hint value is a first value, and mark the corresponding cache line in the cache as less recently used when the memory request is the read request that is the hit in the cache and the reuse hint value is a second, different value. | 2021-09-30 |
20210303468 | APPARATUSES, METHODS, AND SYSTEMS FOR A DUPLICATION RESISTANT ON-DIE IRREGULAR DATA PREFETCHER - Systems, methods, and apparatuses relating to circuitry to implement a duplication resistant on-die irregular data prefetcher are described. In one embodiment, a hardware processor includes a cache to store a plurality of cache lines of data, a processing element to execute instructions to generate memory requests, and a prefetch circuit to track a first set of cache lines, requested to be accessed by the memory requests, that repeat in a first number of executed instructions, track a second set of cache lines, requested to be accessed by the memory requests, that repeat in a second, larger number of executed instructions, detect a memory request from an instruction for a cache line from the cache, determine if the cache line is within the first set of cache lines or the second set of cache lines, update first correlation data for the cache line when the cache line is within the first set of cache lines, and update second correlation data for the cache line when the cache line is within the second set of cache lines. | 2021-09-30 |
20210303469 | SECURE FAST REBOOT OF A VIRTUAL MACHINE - A system for managing a virtual machine is provided. The system includes a processor configured to initiate a session for accessing a virtual machine by accessing an operating system image from a system disk and monitor read and write requests generated during the session. The processor is further configured to write any requested information to at least one of a memory cache and a write back cache located separately from the system disk and read the operating system image content from at least one of the system disk and a host cache operably coupled between the system disk and the at least one processor. Upon completion of the computing session, the processor is configured to clear the memory cache, clear the write back cache, and reboot the virtual machine using the operating system image stored on the system disk or stored in the host cache. | 2021-09-30 |
20210303470 | SEQUENTIAL PREFETCHING THROUGH A LINKING ARRAY - Methods, systems, and devices for sequential prefetching through a linking array are described. A prefetch manager can detect that a set of tags occupying a queue of a memory sub-system corresponds to a single read descriptor indicating a sequential read pattern. The prefetch manager can determine that a number of the set of tags occupying the queue is below a queue threshold and store data associated with at least one tag of the set of tags in an internal performance memory of the memory sub-system based on the detecting and the determining. In such cases, the prefetch manager can prefetch data from a memory manager and store in the internal performance memory. | 2021-09-30 |
20210303471 | Secondary Prefetch Circuit that Reports Coverage to a Primary Prefetch Circuit to Limit Prefetching by Primary Prefetch Circuit - In an embodiment, a processor includes a plurality of prefetch circuits configured to prefetch data into a data cache. A primary prefetch circuit may be configured to generate first prefetch requests in response to a demand access, and may be configured to invoke a second prefetch circuit in response to the demand access. The second prefetch circuit may implement a different prefetch mechanism than the first prefetch circuit. If the second prefetch circuit reaches a threshold confidence level in prefetching for the demand access, the second prefetch circuit may communicate an indication to the primary prefetch circuit. The primary prefetch circuit may reduce a number of prefetch requests generated for the demand access responsive to the communication from the second prefetch circuit. | 2021-09-30 |
20210303472 | VIRTUAL MEDIA PERFORMANCE IMPROVEMENT - An information handling system may include a host system and a management controller configured to provide out-of-band management of the information handling system. The management controller may be configured to: receive, from a management console, a request to establish virtual media for the host system; cause the requested virtual media to be mounted as a drive accessible to the host system; receive read requests from the host system for data associated with the mounted drive; and cache data from the virtual media in a local cache such that at least some of the read requests from the host system are serviceable via the local cache instead of via a network request to the management console. | 2021-09-30 |
20210303473 | METHOD AND SYSTEM OF COPYING DATA TO A CLIPBOARD - Disclosed is a method and system method for bulk copying data from a cell grid to a workspace memory, such as a clipboard. According to an exemplary embodiment of this disclosure, the method includes displaying, in a user interface, a plurality of cell rows and a plurality of cell columns arranged in a grid form, a user selecting a plurality of rows of cell entries by selecting a respective selector indicator of all rows to be copied, the selected plurality of rows including a subset of a total number of rows displayed and a noncontinuous group of sequential rows where at least one nonselected row is located and displayed between two selected rows; and displaying, in the user interface, a drop-down menu including a plurality of user selectable options, the user selectable options including a user selectable command to copy the plurality of selected rows and a common predetermined subset of the associated column entries to a workspace memory such as a clipboard. | 2021-09-30 |
20210303474 | Command Optimization Through Intelligent Threshold Detection - Aspects of a storage device including a memory and a controller are provided which prevent retransmissions of set features commands with identical read voltage threshold offsets for the same die. When the controller receives a first read command for data stored in the memory, the controller identifies a first parameter to modify a first read threshold, and executes a first set features command for modifying the read threshold based on the first parameter. Subsequently, when the controller receives a second read command from the host device for data stored in the memory, the controller identifies a second parameter to modify a second read threshold, and determines whether the first and second parameters are the same. If the parameters are the same, the controller refrains from executing a second set features command for modifying the second read threshold. Thus, the read latency of the storage device may be reduced. | 2021-09-30 |
20210303475 | SELF-DETERMINATION FOR IN-PROGRESS VOLUME DRAINING - In an approach, a processor receives a request to vacate a first page volume of a plurality of page volumes. A processor causes data stored to the first page volume to be moved to a second page volume of the plurality of page volumes. A processor monitors paging rate between a primary storage device and the plurality of page volumes. A processor, responsive to the paging rate exceeding a first predetermined threshold, adjusts a rate of data transfer from the first page volume to the second page volume. | 2021-09-30 |
20210303476 | MEMORY CONTROLLER AND METHOD OF OPERATING THE SAME - A memory controller includes a map buffer and a map update controller. The map buffer includes storage areas that respectively correspond to one or more indices. The map update controller stores metadata in a storage area corresponding to a target index among the one or more indices, and updates the metadata based on an update of mapping data for a first logical address. The metadata includes history information of a physical address mapped to the first logical address. | 2021-09-30 |
20210303477 | MANAGEMENT OF DISTRIBUTED SHARED MEMORY - Examples described herein relate to a network interface device. In some examples, the network interface device includes a device interface; input/output circuitry to receive Ethernet compliant packets and output Ethernet compliant packets; circuitry to monitor a particular page for a rate of data copying among nodes within a group of two or more nodes; and circuitry to perform one or more actions based, at least in part, on the rate of data copying among the nodes within the group of two or more nodes to attempt to reduce a number of copy operations of the data among the nodes within the group of two or more nodes, wherein the group of two or more nodes are part of a distributed shared memory (DSM). | 2021-09-30 |
20210303478 | MEMORY MANAGEMENT - Memory management apparatus comprises input circuitry to receive a translation request defining a first memory address within a first memory address space; prediction circuitry to generate a predicted second memory address within a second memory address space as a predicted translation of the first memory address, the predicted second memory address being a predetermined function of the first memory address; control circuitry to initiate processing of the predicted second memory address; translation and permission circuitry to perform an operation to generate a translated second memory address for the first memory address associated with permission information to indicate whether memory access is permitted to the translated second memory address; and output circuitry to provide the translated second memory address as a response to the translation request when the permission information indicates that access is permitted to the translated second memory address. | 2021-09-30 |
20210303479 | APPARATUS AND METHOD - Apparatus comprises address translation circuitry configured to access translation data defining a set of memory address translations; transaction handling circuitry to receive translation transactions and to receive invalidation transactions, each translation transaction defining one or more input memory addresses in an input memory address space to be translated to respective output memory addresses in an output memory address space, in which the transaction handling circuitry is configured to control the address translation circuitry to provide the output memory address as a translation response; in which each invalidation transaction defines at least a partial invalidation of the translation data; transaction tracking circuitry to associate an invalidation epoch, of a set of at least two invalidation epochs, with each translation transaction and with each invalidation transaction; and invalidation circuitry to store data defining a given invalidation transaction and, for translation transactions having the same invalidation epoch as the given invalidation transaction and handled by the address translation circuitry subsequent to the invalidation circuitry storing the data defining the given invalidation transaction, to process those translation transactions to indicate that a translation transaction is invalidated when the invalidation defined by the given invalidation transaction applies to that translation transaction; the invalidation circuitry being configured to forward at least an acknowledgement of the invalidation transaction for further processing by other apparatus in response to storage of the data by the invalidation circuitry. | 2021-09-30 |
20210303480 | MANAGING LEAST RECENTLY USED CACHE USING REDUCED MEMORY FOOTPRINT SEQUENCE CONTAINER - Techniques are provided for managing a least recently used cache using a linked list with a reduced memory footprint. A cache manager receives an I/O request comprising a target address, wherein the cache manager manages a cache memory having a maximum allocated amount of cache entries, and a linked list having a maximum allocated amount of list elements which is less than the maximum allocated amount of cache entries. If the target address does correspond to a cache entry, the cache manager accesses the cache entry to obtain the cache data from cache memory, removes a list element from the linked list, which corresponds to the accessed cache entry, selects an existing cache entry which currently does not have a corresponding list element in the linked list, and adds a list element to a head position of the linked list which corresponds to the selected cache entry. | 2021-09-30 |
20210303481 | EFFICIENT DATA SHARING FOR GRAPHICS DATA PROCESSING OPERATIONS - An apparatus to facilitate efficient data sharing for graphics data processing operations is disclosed. The apparatus includes a processing resource to generate a stream of instructions, an L1 cache communicably coupled to the processing resource and comprising an on-page detector circuit to determine that a set of memory requests in the stream of instructions access a same memory page; and set a marker in a first request of the set of memory requests; and arbitration circuitry communicably coupled to the L1 cache, the arbitration circuitry to route the set of memory requests to memory comprising the memory page and to, in response to receiving the first request with the marker set, remain with the processing resource to process the set of memory requests. | 2021-09-30 |
20210303482 | SHARING MEMORY AND I/O SERVICES BETWEEN NODES - A shared memory controller is to service load and store operations received, over data links, from a plurality of independent nodes to provide access to a shared memory resource. Each of the plurality of independent nodes is to be permitted to access a respective portion of the shared memory resource. Interconnect protocol data and memory access protocol data are sent on the data links and transitions between the interconnect protocol data and memory access protocol data can be defined and identified. | 2021-09-30 |
20210303483 | MULTIPLE PIN CONFIGURATIONS OF MEMORY DEVICES - An apparatus configured to allow data values to be written into the plurality of memory cells of the memory device at a first speed upon connecting to a first host via a first configuration of the plurality of connectors; and allow data values to be written into the plurality of memory cells at a second speed faster than the first speed, upon connecting to a second host via a second configuration of the plurality of connectors. | 2021-09-30 |
20210303484 | Advanced CE encoding for bus multiplexer grid for SSD - The present disclosure generally relates to a method and device for accessing more dies per channel in a data storage device. Each flash interface module (FIM) can have any number of bus multiplexers coupled thereto, and each bus multiplexer can have any number of memory devices coupled thereto. The bus multiplexers can be connected in series or in parallel to the FIM. The individual bus multiplexers can be addressed by a chip enable (CE) command that identifies the specific bus multiplexer as well as the specific memory device of the specific bus multiplexer. The information in the CE command allows more dies per channel without creating signal interference (SI) or limiting transmission performance. | 2021-09-30 |
20210303485 | ELECTRONIC DEVICE, CONTROL METHOD THEREOF, AND NON-TRANSITORY COMPUTER-READABLE STORAGE MEDIUM - An electronic device capable of attaching/detaching a device including an arithmetic processing unit: divides data that is a processing target of the arithmetic processing unit to obtain a plurality of divided data; determines a first command group that is a combination of a plurality of types of commands used to transmit each of the plurality of divided data to the device; and transmits the divided data using the determined first command group. The electronic device changes a combination of commands that form the first command group between a case in which certain divided data of the plurality of divided data is transmitted and a case in which another divided data is transmitted. | 2021-09-30 |
20210303486 | Inter Cluster Snoop Latency Reduction - In one embodiment, a cache coherent system includes one or more agents (e.g., coherent agents) that may cache data used by the system. The system may include a point of coherency in a memory controller in the system, and thus the agents may transmit read requests to the memory controller to coherently read data. The point of coherency may determine if the data is cached in another agent, and may transmit a copy back request to the other agent if the other agent has modified the data. The system may include an interconnect between the agents and the memory controller. At a point on the interconnect at which traffic from the agents converges, a copy back response may be converted to a fill for the requesting agent. | 2021-09-30 |
20210303487 | PROGRAMMABLE LOGIC CONTROLLER, EXTERNAL APPARATUS, METHOD, AND RECORDING MEDIUM - A programmable logic controller performs execution of a program in each set period and repeats the execution of the program. The first device storage stores a device value that is an input value and an output value of the program. The second device storage stores the device value stored in the first device storage in a previous period. In a case in which a reading target preset for a device designated by a monitor request received from an engineering tool is the first device storage, the command processor reads the device value stored in the first device storage after execution of the program in a current period is completed, and in a case in which the reading target is the second device storage, the command processor immediately reads the device value stored in the second device storage. The command transmission/reception element transmits the device value to the engineering tool. | 2021-09-30 |
20210303488 | Real-Time Automation Device having a Real-Time Data Bus - A real-time automation. device includes a real-time databus, and a memory device, wherein the databus is configured to transmit values associated with defined bus variables and configured to communicate a value associated with a bus variable from a bus variable source in accordance with a bus database via a databus to a bus variable receiver associated with the bus variable in accordance with the bus database such that, following transfer of the value from the bus variable source to the databus, the value is transferred within a predefined time period to the bus variable receiver, wherein the memory device also includes a software application which receives values associated with the bus variable from the databus or sends values associated with the bus variable to the databus, and wherein the automation device registers the software application as a bus variable receiver or as a bus variable source for the bus variables. | 2021-09-30 |
20210303489 | LEGACY-COMPATIBLE 8-BIT ADDRESSING ON RFFE BUS FOR INCREASED DEVICE CONNECTIONS - Systems, methods, and apparatus increase the number of slave devices that can be connected to a serial bus. The bus protocol may be an RFFE protocol, an SPMI protocol, an I3C protocol or another protocol usable on a serial bus. In various aspects of the disclosure, a method performed at a device coupled to a serial bus includes receiving a first datagram at a slave device coupled to a serial bus, where the first datagram includes a 4-bit broadcast address indicative of a broadcast datagram, a first command directed to an invalid register address, and a payload, determining an encapsulation protocol associated with the invalid register address, and responding to a second command carried in the payload when an 8-bit slave address in the payload matches an 8-bit slave identifier allocated to the slave device. | 2021-09-30 |
20210303490 | INTEGRATED CIRCUIT HAVING LANES INTERCHANGEABLE BETWEEN CLOCK AND DATA LANES IN CLOCK FORWARD INTERFACE RECEIVER - An integrated circuit in a transmitter includes a multilane interface, N signal generating circuits, a lane selection circuit and a control circuit. The multi lane interface has N lanes. M of the N signal generating circuits are configured to generate M clock signals respectively, (N-M) of the N signal generating circuits are configured to generate (N-M) data signals respectively. The lane selection circuit is configured to select M of the N lanes as M clock lanes by coupling the M clock signals to the M clock lanes respectively, and couple one of the (N-M) data signals to one of remaining (N-M) lanes, serving as (N-M) data lanes, according to a data select signal. The control circuit is configured to generate a data select signal according to a lane identifier of the one of the (N-M) lanes. The data select signal has a signal value mapping to the lane identifier, | 2021-09-30 |
20210303491 | NETWORK-ON-CHIP FOR INTER-DIE AND INTRA-DIE COMMUNICATION IN MODULARIZED INTEGRATED CIRCUIT DEVICES - Systems or methods of the present disclosure may provide high-bandwidth, low-latency connectivity for inter-die and/or intra-die communication of a modularized integrated circuit system. Such an integrated circuit system may include a first die of fabric circuitry sector(s), a second die of modular periphery intellectual property (IP), a passive silicon interposer coupling the first die to the second die, and a modular interface that includes a network-on-chip (NOC). The modular interface may provide high-bandwidth, low-latency communication between the first die and the second, between the fabric circuitry sector(s), and between the first die and a third die. | 2021-09-30 |
20210303492 | FAULT TOLERANT SYSTEM - A fault tolerant system includes a primary virtual machine and a secondary virtual machine. The primary virtual machine includes a synchronizing information generator and a first interrupt blocker. The synchronizing information generator executes bytecode and outputs synchronizing information based on information related to the executed bytecode. The first interrupt blocker blocks an interrupt inputted from an external location. The secondary virtual machine includes a synchronous execution unit that executes the bytecode based on the synchronizing information and a second interrupt blocker that blocks the interrupt. When the interrupt is acquired, the synchronizing information generator executes the bytecode based on the interrupt. The first interrupt blocker outputs the interrupt to the synchronizing information generator when the interrupt is inputted during execution of an instruction, included in the bytecode, to accept the interrupt. | 2021-09-30 |
20210303493 | DIRECT ACCESS TO A HARDWARE DEVICE FOR VIRTUAL MACHINES OF A VIRTUALIZED COMPUTER SYSTEM - In a virtualized computer system in which a guest operating system runs on a virtual machine of a virtualized computer system, a computer-implemented method of providing the guest operating system with direct access to a hardware device coupled to the virtualized computer system via a communication interface, the method including: (a) obtaining first configuration register information corresponding to the hardware device, the hardware device connected to the virtualized computer system via the communication interface; (b) creating a passthrough device by copying at least part of the first configuration register information to generate second configuration register information corresponding to the passthrough device; and (c) enabling the guest operating system to directly access the hardware device corresponding to the passthrough device by providing access to the second configuration register information of the passthrough device. | 2021-09-30 |
20210303494 | COMPUTING APPARATUS UTILIZING PROGRAMMABLE LOGIC CIRCUIT TO IMPLEMENT DIRECT MEMORY ACCESS ENGINE AND AT LEAST ONE PHYSICAL ENGINE AND PROVIDING DATA TO BE PROCESSED TO AT LEAST ONE PHYSICAL ENGINE THROUGH DIRECT MEMORY ACCESS ENGINE - A computing apparatus includes a first processing circuit and a second processing circuit. The first processing circuit includes a programmable logic circuit. The second processing circuit includes a general purpose processor that is used to execute an application program to download a bitstream to the first processing circuit for programming the programmable logic circuit to implement a direct memory access (DMA) engine and at least one physical engine (PE). The DMA engine is used to access a first memory through a DMA manner. The at least one PE is used to read data to be processed from the first memory through the DMA engine. The first processing circuit and the second processing circuit are disposed in one chip. | 2021-09-30 |
20210303495 | SETTING ASSISTANCE DEVICE, SETTING ASSISTANCE METHOD, AND PROGRAM - A setting assistance device ( | 2021-09-30 |
20210303496 | ACTUATION OF DATA TRANSMISSION LANES BETWEEN STATES - A host device may include a port, a pair of data transmission lanes extending from the port, a switch to selectively actuate the pair of data transmission lanes between a data transmitting state and a data receiving state and a host interface controller to control the switch to selectively actuate the pair of data transmission lanes to one of the data transmitting state and the data receiving state based upon at least one data transfer request. | 2021-09-30 |
20210303497 | METHOD OF OPERATING AUDIO SUBSYSTEM FOR USB MODULE, SYSTEM-ON-CHIP PERFORMING THE SAME AND METHOD OF OPERATING SYSTEM-ON-CHIP USING THE SAME - In a method of operating an audio subsystem and a universal serial bus (USB) module, the audio subsystem receives a reference clock signal from the USB module. A USB direct memory access (UDMA) block included in the audio subsystem performs an automatic restart every predetermined period in synchronization with the reference clock signal. The UDMA block transmits data having a predetermined size to the USB module by performing a direct memory access (DMA) operation whenever the automatic restart is performed. | 2021-09-30 |
20210303498 | MECHANISM TO IDENTIFY FPGA AND SSD PAIRING IN A MULTI-DEVICE ENVIRONMENT - A system is disclosed. The system may include a Solid State Drive (SSD) and a co-processor. The SSD may include storage for data, storage for a unique SSD identifier (ID), and storage for a unique co-processor ID. The co-processor include storage for the unique SSD ID, and storage for the unique co-processor ID. A hardware interface may permit communication between the SSD and the co-processor. | 2021-09-30 |
20210303499 | ON-PROCESS MIGRATION OF CONTROLLER(S) TO UTILIZE AN IO POOL - A process control system includes a first process controller coupled to a first set of input/output (I/O) modules that provided first channels, including an I/O software agent coupled to an I/O module pool that includes a first and at least a second I/O module collectively providing pooled channels. The first channels and the pooled channels are each coupled by a respective field device to first and second processing equipment, respectively. The I/O software agent is configured for enabling addition of the first set of I/O modules to the LO module pool, coupling of a plurality of additional process controllers in a controller pool to the first process controller, and enabling at least one of i) making any of the first channels available to any of the process controllers in the controller pool, and ii) making any of the pooled channels available to the first process controller. | 2021-09-30 |
20210303500 | SCALING PERFORMANCE IN A STORAGE SERVER WITH STORAGE DEVICES - Provided is a method of packet processing, the method including receiving an input/output (IO) request from a host, selecting a drive corresponding to the IO request using a hashing algorithm or a round-robin technique, and establishing a connection between the host and the drive. | 2021-09-30 |
20210303501 | METHOD FOR PROGRAMMING A PROGRAMMABLE GATE ARRAY IN A DISTRIBUTED COMPUTER SYSTEM - To program a first programmable gate array, for example a first FPGA, in a distributed computer system, a configuration of a first configuration logic on the first programmable gate array is provided. The first configuration logic is configured to receive a first user bitstream from a configuration software for configuring a first user logic on the first programmable gate array and to store the first user bitstream on a non-volatile memory of the first programmable gate array for the purpose of subsequently configuring a first user logic on the first programmable gate array according to the specifications from the first user bitstream. In an expansion stage of the invention, a configuration of a programming logic on the first programmable gate array is also provided for programming a second programmable gate array, which is connected to the first programmable gate array to form a daisy chain. | 2021-09-30 |
20210303502 | DATA COMMUNICATION DEVICE AND DATA COMMUNICATION MODULE - A data communication device includes: a fixed value memory that stores a fixed value; a received data memory that stores received data inputted through a bus; an output data memory that stores output data; a comparison determination unit that outputs a comparison determination result signal indicating a determination result of comparing the fixed value and a value of the received data; a data output unit that has a first state of outputting the output data to the bus and a second state of not outputting the output data to the bus; a command analyzing unit that outputs a data output control signal based on a command; and an output controller that outputs a control signal for controlling the data output unit to enter the first state or the second state based on the comparison determination result signal and the data output control signal. | 2021-09-30 |
20210303503 | METHOD AND SYSTEM FOR ENHANCED SPI COMMUNICATION - A slave device includes an SPI bus with a mode detection circuit configured to detect an SPI operating mode that has been applied by a master device. The slave device is configurable to operate in a first or a second mode depending on the detection of the SPI operating mode as applied by the master device. | 2021-09-30 |
20210303504 | PROCESSING SYSTEM COMPRISING A QUEUED SERIAL PERIPHERAL INTERFACE, RELATED INTEGRATED CIRCUIT, DEVICE AND METHOD - An embodiment processing system comprises a queued SPI circuit, which comprises a hardware SPI communication interface, an arbiter and a plurality of interface circuits. Each interface circuit comprises a transmission FIFO memory, a reception FIFO memory and an interface control circuit. The interface control circuit is configured to receive first data packets and store them to the transmission FIFO memory. The interface control circuit sequentially reads the first data packets from the transmission FIFO memory, extracts at least one transmission data word, and provides the extracted word to the arbiter. The interface control circuit receives from the arbiter a reception data word and stores second data packets comprising the received reception data word to the reception FIFO memory. The interface control circuit sequentially reads the second data packets from the reception FIFO memory and transmits them to the digital processing circuit. | 2021-09-30 |
20210303505 | Network Computer with Two Embedded Rings - A computer comprising a plurality of interconnected processing nodes arranged in a configuration in which multiple layers of interconnected nodes are arranged along an axis, each layer comprising at least four processing nodes connected in a non-axial ring by at least respective intralayer link between each pair of neighbouring processing nodes, wherein each of the at least four processing nodes in each layer is connected to a respective corresponding node in one or more adjacent layer by a respective interlayer link, the computer being programmed to provide in the configuration two embedded one dimensional paths and to transmit data around each of the two embedded one dimensional paths, each embedded one dimensional path using all processing nodes of the computer in such a manner that the two embedded one dimensional paths operate simultaneously without sharing links. | 2021-09-30 |
20210303506 | SYNCHRONIZATION IN MULTI-CHIP SYSTEMS - Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for determining, for each pair of adjacent chips in a plurality of chips connected in a series-ring arrangement of a semiconductor device, a corresponding loop latency for round trip data transmissions between the pair of chips. Identifying, from among the loop latencies, a maximum loop latency. Determining a ring latency for a data transmission originating from a chip of the plurality chips to be transmitted around the series-ring arrangement and back to the chip. Comparing half of the maximum loop latency to one N-th of the ring latency, where N is the number of chips in the plurality of chips, and storing the greater value as an inter-chip latency of the semiconductor device, the inter-chip latency representing an operational characteristic of the semiconductor device. | 2021-09-30 |
20210303507 | Methods and Systems for Transmitting Arrays of Sequenced Data Blocks - An exemplary method includes establishing, by a sending device, a communication session with a receiving device, the communication session configured to transfer an array of related, sequenced data blocks from the sending device to the receiving device. The method includes sending one or more parameter messages including parameters associated with the array of data blocks. The method includes receiving one or more parameter acknowledgement messages to the one or more parameter messages, the one or more parameter acknowledgement messages including a plurality of memory addresses of the receiving device, the plurality of memory addresses including a respective memory address for each data block of the array of data blocks. The method includes sending the array of data blocks to the receiving device, each data block of the array of data blocks sent to the respective memory address using a remote direct memory access (RDMA) protocol. | 2021-09-30 |
20210303508 | NOC RELAXED WRITE ORDER SCHEME - Embodiments herein describe a SoC that includes a NoC that supports both strict and relax ordering requests. That is, some applications may require strict ordering where requests transmitted from the same ingress logic to different egress logic blocks are performed sequentially. However, other applications may not require strict ordering, such as interleaved writes to memory. In those applications, relax ordering can be used were the same ingress logic block can transmit multiple requests to different egress logic blocks in parallel. For example, an ingress logic block may receive a first request that is indicated as being a relaxed ordered request. After transmitting the request to an egress logic block, the ingress logic block may receive a second request. The ingress logic block can transmit the second request to a different egress logic block without waiting for a response for the first request. | 2021-09-30 |
20210303509 | CONFIGURABLE NETWORK-ON-CHIP FOR A PROGRAMMABLE DEVICE - An example programmable integrated circuit (IC) includes a processor, a plurality of endpoint circuits, a network-on-chip (NoC) having NoC master units (NMUs), NoC slave units (NSUs), NoC programmable switches (NPSs), a plurality of registers, and a NoC programming interface (NPI). The processor is coupled to the NPI and is configured to program the NPSs by loading an image to the registers through the NPI for providing physical channels between NMUs to the NSUs and providing data paths between the plurality of endpoint circuits. | 2021-09-30 |
20210303510 | Assigning Identifiers to Processing Units in a Column to Repair a Defective Processing Unit in the Column - A method of recording tile identifiers in each of a plurality of tiles of a multitile processor is described. Tiles are arranged in columns, each column having a plurality of processing circuits, each processing circuit comprising one or more tiles, wherein a base processing circuit in each column is connected to a set of processing circuit identifier wires. A base value is generated on each of the set of processing circuit identifier wires for the base processing circuit in each column. At the base processing circuit, the base value on the set of processing circuit identifier wires is read and incremented by one. The incremented value is propagated to a next processing circuit in the column, and at the next processing circuit a unique identifier is recorded by concatenating an identifier of the column and the incremented value. | 2021-09-30 |
20210303511 | Cloning a Managed Directory of a File System - An illustrative data storage system efficiently clones a managed directory of a file system. For example, the storage system generates a virtual clone of a managed directory of a file system such that modifications made to either of the managed directory or the virtual clone of the managed directory after the generation of the virtual clone of the managed directory are distinct from the other of the managed directory or the virtual clone of the managed directory. The managed directory and the virtual clone of the managed directory initially share block objects representing files and directories of a directory tree of the managed directory, such by including distinct references to the block objects. The system clones one or more of the block objects as needed when trigger events occur. | 2021-09-30 |
20210303512 | DATA PROCESSING SYSTEMS FOR PROCESSING DATA SUBJECT ACCESS REQUESTS - In various embodiments, an organization may be required to comply with one or more legal or industry requirements related to the storage of personal data (e.g., which may, for example, include personally identifiable information) even when responding to and fulfilling Data Subject Access Requests. In particular, when responding to a DSAR, the system may compile one or more pieces of personal data for provision to a data subject. The system may store this compilation of personal data at least temporarily in order to provide access to the data to the data subject. As such, the system may be configured to implement one or more data retention rules in order to ensure compliance with any legal or industry requirements related to the temporary storage of the collected data while still fulfilling any requirements related to providing the data to data subjects that request it, deleting the data upon request, etc. | 2021-09-30 |
20210303513 | JSON TO BPMN CONVERSION SYSTEM - A system for converting a data file in a first format for data serialization into a second format for workflow specification is disclosed. The system comprises one or more processors and non-transitory memory storing instructions. When executed by the one or more processors, the instructions cause the one or more processors to receive a data file in the first format representing a workflow; automatically generate a functionally equivalent workflow specified according to the second format, via consultation with a correspondence table and replacing a set of elements from the first format with a corresponding set of elements from the second format; automatically fill in any default values required in the second format and not specified within the first format; and output the functionally equivalent workflow in the second format. In a preferred embodiment, the first format is JSON and the second format is BPMN 2.0. | 2021-09-30 |
20210303514 | DATA INGESTION SYSTEM - A device automatically extracts a data file from an upstream source based on ingestion parameters. The data file is in a first format that is not readable by a downstream data analysis utility and includes a plurality of data records. Each record includes one or more entries. The ingestion parameters include a file identifier, transformation instructions, and storage instructions for the extracted data file. The device generates table(s) based on the extracted data file by, determining, based on the transformation instructions, a table in which to store each entry and a row and column of the determined table in which to store the entry. Entries are input into the determined tables, rows, and columns. The table(s) are stored in a second format that is readable by the downstream data analysis utility. | 2021-09-30 |
20210303515 | DATA LABELING AWARENESS FOR BACKUP SYSTEMS - Embodiments for a method performing data migration such as backups and restores in a network by identifying characteristics of data in a data saveset to separate the data into defined types based on respective characteristics, assigning a data label to each defined type, defining migration rules for each data label, discovering assigned labels during a migration operation; and applying respective migration rules to labeled data in the data saveset. The migration rules can dictate storage location, access rights, replication periods, retention periods, and similar parameters. | 2021-09-30 |
20210303516 | FORMAT AGNOSTIC DATABASE MIGRATION - A staging engine of a staging server receives a request to change a production database from a client device. The staging engine of the staging server accesses one or more schemas corresponding to the production database and determines one or more migration commands based on the received request and the accessed one or more schemas. The one or more migration commands correspond to a difference between a current structure of the production database and a final structure of the production database after the production database is updated. The staging engine transmits the one or more migration commands to a migration engine, wherein the migration engine asynchronously applies changes to the production database according to the one or more migration commands. | 2021-09-30 |
20210303517 | Dual Relationship-Based Hash Structure for Non-Volatile Memory Technology - Methods, apparatus, and processor-readable storage media for implementing dual relationship-based hash structures for non-volatile memory technology are provided herein. An example computer-implemented method includes generating a hash storage structure by: creating multiple layers of storage components, wherein a first layers comprise a first number of storage components and at least a second layer comprises at least a second number of storage components less than the first number of storage components; configuring the at least a second layer to share at least a portion of the storage components therein with at least a portion of the storage components in the first layer; partitioning each of the storage components in each of the multiple layers into multiple portions; configuring a respective status value space for each of the multiple portions of each of the storage components in the multiple layers; and implementing the hash storage structure in at least one storage system. | 2021-09-30 |
20210303518 | METHOD AND APPARATUS FOR OPENING FILE, AND ELECTRONIC DEVICE - Embodiments of the present disclosure provide a method and an apparatus for opening a file, and an electronic device. Embodiments of the present disclosure receive the file opening request, obtain the format information of the file to be opened indicated by the file opening request, search for application information of the target application for opening the file to be opened according to the format information, provide the application entry of the target application in the current interface according to the application information, obtain the configuration file corresponding to the target application when the application entry is triggered, and generate the native interface of the target application according to the configuration file and open the file to be opened in the native interface. | 2021-09-30 |
20210303519 | Optimizing a Transfer of a File System - An illustrative system is configured to optimize a transfer of a file system from a source storage system to a target storage system. For example, the system, in association with the transfer, determines that a copy of a collection of blocks containing data of block objects of the file system is already stored at the target storage system. In certain examples, an identifier referencing the collection of blocks is shared by the source and target storage systems and is used to determine that the copy of the collection of blocks containing data of block objects of the file system is already stored at the target storage system. The system uses the copy of the collection of blocks already stored at the target storage system instead of transferring the collection of blocks from the source storage system to the target storage system as part of the transfer. | 2021-09-30 |
20210303520 | FILE SHARING SERVICE CONTROLLER - A tracking engine may respond to a first user requesting to pin a link included in a message received from a second user by storing the link in a database table associated with the first user. Alternatively, if the first user requests to clone the link, the tracking engine may store the link in the database table as well as generate a local copy of a file associated with the link. The tracking engine may generate, based on the database table, a user interface for displaying, at a client associated with the first user, one or more links received by the first user. The tracking engine may update the database table to mark or remove invalid links. As such, the user interface that is generated based on the database table may exclude invalid links or include unselectable user interface elements for the invalid links. | 2021-09-30 |
20210303521 | DEVICE SEARCHING SYSTEM AND METHOD FOR DATA TRANSMISSION - A device searching system and method for data transmission are provided. A method of searching for another device in a first device for data transmission includes outputting a widget window for a device search, receiving an address book stored in a second device connected to the first device, and if the widget window is selected, searching for a device included in the received address book, wherein the searching of the device includes searching for at least one of devices included in the received address book based on a keyword input through the widget window. | 2021-09-30 |
20210303522 | Copying a File System - An illustrative data storage system is configured to use pods to efficiently copy files systems constructed of block objects. In certain examples, the storage system generates, based on a pod that includes a file system constructed of block objects, a virtual copy of the pod such that modifications made to the pod (e.g., modifications to contents of the block objects by way of the pod) after the generation of the virtual copy of the pod are distinct from the virtual copy of the pod. In certain examples, the virtual copy of the pod is a writeable clone of the pod and modifications made to the clone (e.g., modifications to contents of the block objects by way of the clone) after the generation of the clone are distinct from the pod. | 2021-09-30 |