39th week of 2011 patent applcation highlights part 35 |
Patent application number | Title | Published |
20110235377 | Circuit and Method for Generating an AC Voltage from a Plurality of Voltage Sources Having a Temporally Variable DC Output Voltage - A circuit comprising at least one parallel-connected partial circuit for feeding at least one inverter circuit. A partial circuit consists of an unregulated voltage source having a temporally varying DC output voltage, a voltage doubling circuit and a voltage regulating circuit with an associated regulating device. In the inventive method, the voltage doubling circuit doubles the voltage of the unregulated voltage source. The regulation of the current/voltage characteristic curve, the MPP tracking, of the unregulated voltage source is effected by the regulating device of the voltage regulating circuit. | 2011-09-29 |
20110235378 | POWER SUPPLY SYSTEM FOR ELECTRONIC DEVICE - A power supply system includes an AC power source, a converter, a relay switch, and a waveform monitoring circuit. The AC power source provides an AC voltage. The converter is capable of converting the AC voltage into a DC voltage. The relay switch is connected between the AC power source and the converter. The waveform monitoring circuit is connected to the AC power source, and monitors a waveform of the AC voltage provided by the AC power source. The waveform monitoring circuit is connected to the relay switch, and turns on the relay switch when an absolute value of an instantaneous voltage of the AC voltage is not bigger than a threshold voltage. | 2011-09-29 |
20110235379 | CURRENT SHARING POWER SYSTEM - A power system controller includes multiple channels and each channel has a current sharing controller that is coupled to a shared current signal bus and a shared voltage signal bus. | 2011-09-29 |
20110235380 | POWER CONVERSION - Exemplary embodiments are directed to power conversion. A device may include a controllable switch coupled between an AC network and a DC network. The device may further include control circuitry configured to modify a configuration of the switch based on a detected difference between a reference signal and an output signal at the DC network. | 2011-09-29 |
20110235381 | ACTIVATION OF A SYNCHRONOUS RECTIFIER - A rectifier bridge circuit is described for rectifying the phase voltage generated by a generator, including a positive half-bridge having multiple rectifier elements and a negative half-bridge having multiple rectifier elements. The rectifier elements each have a controllable switch having a diode connected in parallel. A control circuit is provided for switching the switches on and off. The switch-on time t | 2011-09-29 |
20110235382 | HIGH VOLTAGE INVERTER DEVICE - The high voltage inverter device receives, as an input voltage, a DC voltage or a voltage within Safety Extra Low Voltage composed of a DC component with a pulsating flow superposed thereon. The input voltage is switched by a switching element to pass an exciting current to excitation windings on a primary side of a plurality of separate transformers having same characteristics to simultaneously excite the excitation windings. Output windings of the plurality of transformers are connected in parallel or in series with one another, and time axes of waveforms of output voltages of the output windings are synchronized. Thereby, a high-power high voltage is outputted continuously, stably, and safely from both ends of the output windings connected in parallel or in series. | 2011-09-29 |
20110235383 | FREQUENCY SYNCHRONIZING METHOD FOR DISCHARGE TUBE LIGHTING APPARATUS, DISCHARGE TUBE LIGHTING APPARATUS, AND SEMICONDUCTOR INTEGRATED CIRCUIT - An oscillator generates a triangular wave signal whose inclination for charging a capacitor and inclination for discharging the same are the same and which is used to turn on/off FETs Qp | 2011-09-29 |
20110235384 | POWER CONVERTER AND POWER CONDITIONER - A power converter enhances conversion efficiency from DC power to AC power. A first chopper circuit chops DC voltage from a photovoltaic panel at a system frequency producing a first square-wave whose voltage level changes positively. A second chopper circuit chops the first square-wave at a frequency double the system frequency producing a second square-wave whose voltage level changes negatively and adds the first square-wave and the second square-wave to produce a third square-wave that changes positively and negatively in a sine-wave manner. A third chopper circuit charges and discharges by chopping the third square-wave at a third frequency fixed by timing according to a difference between the third square-wave and a sine-wave voltage. PWM control is performed on the charge and discharge outputs such that the difference is corrected, producing a sine-wave voltage that continuously changes positively and negatively. A spike noise of an output voltage is suppressed. | 2011-09-29 |
20110235385 | SEMICONDUCTOR MEMORY APPARATUS WITH POWER-MESHED STRUCTURE - A semiconductor memory apparatus includes a plurality of banks each having a plurality of cell mats; a plurality of power lines disposed over predetermined portions of each of the plurality of banks; a column control region disposed adjacent to at least one of sides of each bank which are perpendicular to an extending direction of the power lines; and a conductive plate disposed over the column control region and electrically connected to the plurality of power lines. | 2011-09-29 |
20110235386 | Semiconductor Memory Device and Manufacturing Method of the Same - The invention provides a voltage applying structure having a reduced area penalty with respect to a data line. A wiring forming a global data line and a local data line formed in a p-type well region are connected via a select transistor. Two select lines are formed on a gate electrode of the select transistor. One select line is electrically connected to the gate electrode of the select transistor, however, the other select line is not connected to the select transistor. That is, an insulator film is formed between the select line and the gate electrode. As mentioned above, two select lines shorter than a gate length are provided on one select transistor. The select line is structured such as to be connected to the other select transistor. | 2011-09-29 |
20110235387 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device provided with a new bit line hierarchization method that enables further reduction of power consumption is provided. The semiconductor memory device includes multiple memory blocks provided in a matrix configuration and multiple main bit lines provided in correspondence with the memory blocks. Each of the memory blocks includes: multiple memory cells provided in a matrix configuration; multiple sub bit lines provided on a column-by-column basis; multiple word lines provided with respect to each of columns and rows and common to multiple memory blocks; and a switch circuit that couples a corresponding main bit line to any of the sub bit lines. In the operation of reading a target cell as the target of read, a main bit line corresponding to the target cell is selected, a sub bit line corresponding to the column of the target cell is selected through the switch circuit; and a word line corresponding to the column and the row of the target cell is selected from among the word lines. | 2011-09-29 |
20110235388 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE - According to an embodiment of the invention, a nonvolatile semiconductor storage device includes a first memory cell and a second memory cell. A first fuse element in which data can be electrically written only once is provided in the first memory cell. A second fuse element in which data can be electrically written only once is provided in the second memory cell to repair a defect of the first memory cell. | 2011-09-29 |
20110235389 | SEMICONDUCTOR DEVICE - An object is reduction in power consumption of a semiconductor device including a memory circuit. In the semiconductor device including a memory circuit, the memory circuit includes a memory cell including a semiconductor element and a memory cell that does not include a semiconductor element in a region defined by a word line and a bit line which intersect with each other. A transistor formed using an oxide semiconductor so as to have extremely low off-state current is used as the semiconductor element, so that the reading precision is improved and thus low voltage operation can be performed. The memory cells store data high or data low. The memory cell comprising a semiconductor element stores minor data of high and low, and the memory cell that does not comprise the semiconductor element stores major data of high and low. | 2011-09-29 |
20110235390 | HIGH DENSITY MEMORY DEVICE - A memory device and a method of forming the same are provided. The memory device includes a substrate; a set of electrodes disposed on the substrate; a dielectric layer formed between the set of electrodes; and a transition metal oxide layer formed between the set of electrodes, the transition metal oxide layer configured to undergo a metal-insulator transition (MIT) to perform a read or write operation. | 2011-09-29 |
20110235391 | Reference Cell Write Operations At A Memory - A method of selecting a reference circuit for a write operation is disclosed. The method comprises selecting a reference circuit for a write operation based on an output of a row decode circuit and a column decode circuit. The reference circuit is programmed concurrently with a write operation of at least one of a plurality of memory cells in a memory array without requiring an external reference circuit write command. | 2011-09-29 |
20110235392 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE - According to one embodiment, a nonvolatile semiconductor storage device having a plurality of operation modes, includes: a plurality of first lines; a plurality of second lines; a plurality of memory cells; a first selection unit that charges the first line to a first selection voltage; and a second selection unit that charges a second line to an unselection voltage and discharges the second line to a second selection voltage after the first line is charged to the first selection voltage by the first selection unit, wherein the second selection unit adjusts at least one of a level of the second selection voltage to which the second line to be selected is to be discharged and a time constant when discharging the second line to be selected, in accordance with an operation mode in which the nonvolatile semiconductor storage device operates among the plurality of operation modes. | 2011-09-29 |
20110235393 | Nonvolatile storage device - A nonvolatile storage device includes: a plurality of memory mats each including a plurality of memory cells; a plurality of plate electrodes each provided for every individual one of the memory mats and each used for applying a voltage to the memory cells; a power-supply section configured to apply a voltage to each of the plate electrodes; a switch circuit having a plurality of switches provided between the power-supply section and each of the plate electrodes and between the plate electrodes; and a control section configured to control the switch circuit in order to disconnect the plate electrodes from the power-supply section and to connect the plate electrodes to each other in order to carry out electrical charging and discharging operations among the plate electrodes. | 2011-09-29 |
20110235394 | SEMICONDUCTOR MEMORY DEVICE - A control circuit applies a first voltage to selected one of first lines and applies a second voltage having a voltage value smaller than that of the first voltage to selected one of second lines, such that a certain potential difference is applied across a memory cell disposed at an intersection of the selected one of the first lines and the selected one of the second lines. A current limiting circuit sets a compliance current defining an upper limit of a cell current flowing in the memory cell, and controls such that the cell current flowing in the memory cell does not exceed the compliance current. The current limiting circuit comprises a current generating circuit and a first current mirror circuit. The current generating circuit generates a first current having a current value equal to a current value of the cell current at a certain timing multiplied by a certain constant. The first current mirror circuit mirrors the first current to a current path supplying the first voltage to the first lines. | 2011-09-29 |
20110235395 | SEMICONDUCTOR MEMORY DEVICE AND WRITING METHOD THEREOF - A memory cell array includes memory transistors each including a gate insulating film formed on a semiconductor substrate, a gate electrode formed on the gate insulating film, and a variable resistance film formed on the gate electrode and made of a variable resistance material having variable resistance and is configured by plural memory strings disposed with longer direction extending in a first direction and including plural series-connected memory transistors. Word lines are disposed with a longer direction extending in a second direction orthogonal to the first direction, and connected commonly to the gate electrodes of the plural memory transistors lined up in the second direction. A plate line is disposed to sandwich the variable resistance film with the gate electrode. First voltage terminals supply a certain voltage to first ends of the plural memory strings. Second voltage terminals supply a certain voltage to second ends of the plural memory strings. | 2011-09-29 |
20110235396 | SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR DEVICE - A semiconductor memory device includes a memory cell array, a first control circuit, and a second control circuit. The first control circuit is configured to apply a first voltage to a selected first line. The second control circuit is configured to apply a second voltage having a voltage value higher than that of the first voltage to a selected second line. The first control circuit includes a detecting circuit. The detecting circuit is configured to detect a leak current to flow from the second line to the first line through a memory cell during a forming operation for bringing the memory cell into a state that allows the memory cell to shift between a high resistance state and a low resistance state. The second control circuit includes a current supply circuit, and a compensating circuit. The current supply circuit is configured to supply a constant current to the second line during the forming operation. The compensating circuit is configured to supply a compensating current having the same current value as that of the leak current to the second line during the forming operation based on the leak current detected by the detecting circuit. | 2011-09-29 |
20110235397 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A memory cell array includes a memory cell having a variable resistance element and disposed between first and second wirings. A control circuit provides a selected first wiring with a first voltage and provide a selected second wiring with a second voltage having a lower voltage value than the first voltage. A current limitation circuit controls a cell current below a first current. It includes a first current generation circuit for storing a cell current at a first point of time and generating a first current of α times the stored cell current. It also includes a second current generation circuit for generating a second current of (β/α) times the cell current at a second point of time. A determination circuit outputs a control signal when the second current exceeds the stored current. The first current generation circuit newly stores a stored current according to the control signal. | 2011-09-29 |
20110235398 | SEMICONDUCTOR MEMORY DEVICE AND OPERATION METHOD THEREOF - A semiconductor memory device in accordance with an embodiment includes: a memory cell array having memory cells disposed at an intersection of first lines and second lines; and a control circuit configured to execute a read operation, thereby determining a resistance state of the selected one of the memory cells. The read operation is an operation configured to execute a sensing operation multiple times and aggregate determination results thereof. The sensing operation is configured such that a first voltage is applied to selected ones of the first lines and a second voltage lower than the first voltage is applied to a single selected one of the second lines. The control circuit suspends application of the first voltage to the first line connected to the selected one of the memory cells determined to be in a first resistance state in one of the sensing operations, and executes the next sensing operation. | 2011-09-29 |
20110235399 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device according to an embodiment includes a memory cell array configured by plural memory cells each including a variable resistor and each provided between first and second lines. A control circuit applies to a memory cell through the first and second lines a writing voltage for writing data or a reading voltage for reading data. A sense amplifier circuit senses data retained in a memory cell based on a current flowing through the first line. In a data writing operation, the control circuit applies a writing voltage to each of n number of memory cells configuring one unit such that the memory cells may be supplied with different resistance values. In a data reading operation, the sense amplifier circuit compares level relationship of the resistance values of n number of memory cells configuring one unit and reads out n! patterns of data from the one unit. | 2011-09-29 |
20110235400 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR CONTROLLING THE SAME - According to one embodiment, a method for controlling a semiconductor device comprises determining a select bit number for a group of memory cells each includes a variable-resistance element, setting a first voltage corresponding to the select bit number, applying the set first voltage to the memory cell group, and performing verify read on the memory cell group to which the first voltage has been applied and determining whether or not the memory cell group passes the verify read. If the memory cell group is determined not to pass the verify read, the number of bits corresponding to passed memory cells is subtracted from the select bit number, and the first voltage corresponding to the decreased select bit number is set again. | 2011-09-29 |
20110235401 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device according to an embodiment herein includes a memory cell array. The memory cell array includes memory cells each provided between a first line and a second line and each including a variable resistor. A control circuit applies through the first and second lines a voltage necessary for a forming operation of the memory cell. A current limiting circuit limits a value of a current flowing across the memory cell during the forming operation to a certain limit value. The control circuit repeats an operation of applying the voltage by setting the limit value to a certain value and an operation of changing the limit value from the certain value, until forming of the memory cell is achieved. | 2011-09-29 |
20110235402 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a first cell array includes memory cells and reference cells, a second cell array located adjacent to the first cell array in a first direction, a third cell array located adjacent to the first cell array in a second direction crossing the first direction, a fourth cell array located adjacent to the second cell array in the second direction, and a sense amplifier connected to the first to fourth cell array and configured to compare a current through a memory cell with a current through a reference cell to determine the data of the memory cell. A reference cell is selected from a cell array which is diagonally opposite to a cell array as a read target. | 2011-09-29 |
20110235403 | METHOD AND APPARATUS MANAGING WORN CELLS IN RESISTIVE MEMORIES - A method and apparatus for management worn resistive memory cells are presented. A normal read mode or worn memory cell detecting mode are used depending on the wear state of a resistive memory cell. A detection reference point is changed upon wear indication to detect the resistance of the resistive memory cell. The resistance of the resistive memory cell is detected using the changed detection reference point to determine whether or not the resistive memory cell is worn by comparing the detected resistance to a wear reference level. | 2011-09-29 |
20110235404 | PULSE RESET FOR NON-VOLATILE STORAGE - A non-volatile storage system includes a substrate, control circuitry on the substrate, a three dimensional memory array (above the substrate) that includes a plurality of memory cells with reversible resistance-switching elements, and circuits to SET and RESET the resistance-switching elements. The circuits that RESET the resistance-switching elements provide a pulse to the memory cells that is large enough in magnitude to SET and RESET the memory cells, and long enough to potentially RESET the memory cell but not long enough to SET the memory cells. | 2011-09-29 |
20110235405 | PROGRAMMING NON-VOLATILE STORAGE ELEMENT USING CURRENT FROM OTHER ELEMENT - A non-volatile storage apparatus includes a set of Y lines, a common X line, multiple storage elements each of which is connected to the common X line, and control circuitry in communication with the common X line and the set of Y lines. The multiple data storage elements are capable of being in a first state or a second state. The control circuitry provides control signals to the common X line and the set of Y lines to change a first data storage element of the multiple data storage elements from the first state to the second state by passing a current into the first data storage element from a different Y line through a different storage element. The control circuitry provides control signals to the common X line and the set of Y lines to sequentially change additional data storage elements of the multiple data storage elements from the first state to the second state by passing currents into the additional data storage elements from data storage elements of the multiple data storage elements that were previously changed to the second state and their associated different Y lines. | 2011-09-29 |
20110235406 | Low-Power 5T SRAM with Improved Stability and Reduced Bitcell Size - A 5 Transistor Static Random Access Memory (5T SRAM) is designed for reduced cell size and immunity to process variation. The 5T SRAM includes a storage element for storing data, wherein the storage element is coupled to a first voltage and a ground voltage. The storage element can include symmetrically sized cross-coupled inverters. A single access transistor controls read and write operations on the storage element. Control logic is configured to generate a value of the first voltage a write operation that is different from the value of the first voltage for a read operation. | 2011-09-29 |
20110235407 | SEMICONDUCTOR MEMORY DEVICE AND A METHOD OF MANUFACTURING THE SAME - A semiconductor memory device including a substrate, wherein the substrate includes first, second and third well regions, the first well region is disposed between the second and third well regions, the first well region includes a first type conductor and the second and third well regions each include a second type conductor. The semiconductor memory device includes first and second pull-up devices disposed in a line in the first well region and sharing a power supply voltage terminal, a first pull-down device disposed in the second well region, wherein the first pull-down device is adjacent to the first pull-up device, a second pull-down device disposed in the third well region, wherein the second pull-down device is adjacent to the second pull-up device, a first access device disposed in the second well region, wherein the first access device is adjacent to the second pull-up device, and a second access device disposed in the third well region, wherein the second access device is adjacent to the first pull-up device. | 2011-09-29 |
20110235408 | SEMICONDUCTOR MEMORY DEVICE - For decreasing a recording current and suppressing a cross erase simultaneously, a three-dimensional phase-change memory for attaining higher sensitivity and higher reliability by the provision of a chalcogenide type interface layer is provided, in which an electric resistivity, a thermal conductivity, and a melting point of the material of the interface layer are selected appropriately, thereby improving the current concentration to the phase-change material and thermal and material insulation property with Si channel upon writing. | 2011-09-29 |
20110235409 | SEMICONDUCTOR MEMORY DEVICE FOR WRITING DATA TO MULTIPLE CELLS SIMULTANEOUSLY AND REFRESH METHOD THEREOF - A semiconductor memory device includes a read/write bit line configured to supply a cell driving voltage. A selecting unit is connected to the read/write bit line and is controlled by a word line. A plurality of cells are connected between the selecting unit and a source line, and the cells are configured to read and write data according to a cell driving voltage. Each switching element of a plurality of switching elements are connected in parallel with a single cell of the plurality of cells, and the plurality of switching elements are controlled selectively by a plurality of bit lines. | 2011-09-29 |
20110235410 | DEVICE AND METHOD TO READ DATA SUBJECT TO A DISTURB CONDITION - A storage device includes a plurality of memory elements and a controller. The controller is configured to receive measured characteristics of the memory elements. The measured characteristics correspond to a plurality of values including a first value stored at a first memory element of the plurality of memory elements and a second value stored at a second memory element of the plurality of memory elements. The controller is configured to test whether at least some of the plurality of values match a particular pattern correlated to a disturb condition at the first memory element. The controller is configured to provide a data value corresponding to the first memory element, where the data value is determined at least in part based on a result of the test. | 2011-09-29 |
20110235411 | FAST PROGRAMMING MEMORY DEVICE - In an embodiment of a memory device including a matrix of memory cells wherein the memory cells are arranged in a plurality of memory cells strings each one including at least two serially-connected memory cells, groups of at least two memory cells strings being connected to a respective bit line, and wherein said memory cells are adapted to be programmed into at least a first programming state and a second programming state, a method of storing data comprising exploiting a single memory cell for each of the memory cells string for writing the data, wherein said exploiting includes bringing the single memory cell to the second programming state, the remaining memory cells of the string being left in the first programming state. | 2011-09-29 |
20110235412 | CONTROLLING AC DISTURBANCE WHILE PROGRAMMING - A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation. | 2011-09-29 |
20110235413 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A control circuit of a nonvolatile semiconductor memory device according to an embodiment of the present invention sets the lower limit of an intermediate distribution in a page writing operation such that an amount of shift from a first threshold voltage distribution to a second threshold voltage distribution is substantially equal to an amount of shift from the intermediate distribution to a fourth threshold voltage distribution, and raises the lower limit of the intermediate distribution as the number of times writing has been executed increases. When the threshold voltage distribution of a second memory cell adjoining a reading target first memory cell and subject to data write after the first memory cell is the second or fourth threshold voltage distribution, the control circuit executes control of applying a second reading pass voltage higher than the first reading pass voltage to the second memory cell. | 2011-09-29 |
20110235414 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device comprises a memory cell array, a controller. A memory cell array comprises bit lines, and memory cells configured to store different states, i.e., m values or n values. When storing the n values in a memory cell, the controller performs a first method of applying a bit-line voltage to a first bit line connected to the memory cell, and setting a second bit line adjacent to the first bit line at 0 V, in a read operation and in a verify operation. When storing the m values in the memory cell, the controller performs a second method of applying the bit-line voltage to all the bit lines in a read operation, and setting the first bit line and the second bit line at the bit-line voltage or 0 V in a verify operation, in accordance with whether the write is complete. | 2011-09-29 |
20110235415 | READ METHOD FOR NONVOLATILE MEMORY DEVICE, AND DATA STORAGE SYSTEM USING THE SAME - Provided is a method for reading data from a nonvolatile memory device. In the method, a read method includes a first read step including reading a first memory cell of the nonvolatile memory device by applying a first set of read voltages to the first memory cell. The read method further includes a second read step including reading the first memory cell by applying a second set of read voltages and none of the voltages in the first set to the first memory cell when it is determined that the first read step results in an error and cannot be corrected with error correction. The second read step is performed by using data resulting from the first read step. | 2011-09-29 |
20110235416 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device for raising operating speed is provided. The nonvolatile semiconductor memory device includes plural bit lines extending in a first direction, and a memory cell that includes plural blocks each having plural NAND strings each of which includes a group of memory cells connected in series with one another and selecting transistors connected to the respective ends of the memory cell group. One ends of current paths in ones of the selecting transistors are connected to the bit lines, while one ends of current paths in the other selecting transistors are connected to a source line. The nonvolatile semiconductor memory device further includes a memory cell array and a voltage control circuit that is disposed in the memory cell array in a manner of bisecting the memory cell array and that charges or discharges the bit lines. | 2011-09-29 |
20110235417 | NAND FLASH MEMORY - A NAND flash memory that is read while a selected bit line and a non-selected bit line are adjacent to each other, has a memory cell array having a plurality of blocks each of which is composed of a plurality of memory cell units, each of said memory cell units having a plurality of electrically rewritable memory cells that are connected to each other and composed of a p-type well surrounded by an n-type well formed in a p-type semiconductor substrate, drain-side select gate transistors each of which connects a memory cell unit to a bit line and is connected to a drain-side select gate line at the gate thereof, and source-side select gate transistors each of which connects a memory cell unit to a source line and is connected to a source-side select gate line at the gate thereof; a row decoder that is connected to word lines, the drain-side select gate lines and the source-side gate line of said memory cell array, and applies a signal voltage to word lines, the drain-side select gate lines and the source-side gate line of said memory cell array for selecting a block; and a sense amplifier that is controlled by a column decoder and makes a selection from said bit lines of said memory cell array, wherein, in a block that is not selected by said row decoder, said bit line selected by said sense amplifier is charged in a state where the drain-side select gate line, the source-side select gate line and the p-type semiconductor substrate are set at a ground potential, and the source lines, the n-type wells, the p-type wells and a bit line that is not selected by said sense amplifier are in a floating state. | 2011-09-29 |
20110235418 | DETERMINING MEMORY PAGE STATUS - The present disclosure includes methods, devices, modules, and systems for operating semiconductor memory. One method embodiment includes determining a status of a page of memory cells without using input/output (I/O) circuitry, and outputting the status through the I/O circuitry. | 2011-09-29 |
20110235419 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE - In a split gate MONOS memory which carries out rewrite by hot carrier injection, retention characteristics are improved. A select gate electrode of a memory cell is connected to a select gate line, and a memory gate electrode is connected to a memory gate line. A drain region is connected to a bit line, and a source region is connected to a source line. Furthermore, a well line is connected to a p type well region in which the memory cell is formed. When write to the memory cell is to be carried out, write by a source side injection method is carried out while applying a negative voltage to the p type well region via the well line. | 2011-09-29 |
20110235420 | SIMULTANEOUS MULTI-STATE READ OR VERIFY IN NON-VOLATILE STORAGE - Methods and devices for simultaneously verifying or reading multiple states in non-volatile storage are disclosed. Methods and devices for efficiently reducing or eliminating cross-coupling effects in non-volatile storage are disclosed. Methods and devices for efficiently performing reads at a number of voltages to search for the threshold voltage of a memory cell are disclosed. Memory cells on different NAND strings that are read at the same time may be tested for different threshold voltage levels. Memory cells may be tested for different threshold voltages by applying different gate-to-source voltages to memory cells being tested for different threshold voltages. Memory cells may be tested for different threshold voltages by applying different drain to source voltages to the memory cells. Different amounts of compensation for cross-coupling affects may be applied to memory cells on different NAND strings that are read or programmed at the same time. | 2011-09-29 |
20110235421 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, in the case of performing an operation for increasing a threshold voltage of a first transistor or a third transistor, a control circuit is configured to apply a first voltage to a bit line, and apply a second voltage greater than the first voltage to a gate of a second transistor, thereby rendering the second transistor in a conductive state to transfer the first voltage to a second semiconductor layer, and then apply a program voltage to a gate of the first transistor or the third transistor to store a charge in a second charge storage layer. | 2011-09-29 |
20110235422 | APPARATUS HAVING A STRING OF MEMORY CELLS - Apparatus having a string of memory cells are useful in semiconductor memory. Some apparatus have circuitry configured to program memory cells of the string in a particular sequence. Some apparatus have circuitry configured to program a threshold voltage of a selected memory cell in the string to match a target voltage compensating, at least in part, for a voltage drop across any unselected memory cells in the string on a source side of the selected memory cell during a sensing operation. Some apparatus have circuitry configured to maintain a resistance presented by source-side unselected memory cells of the string the same between a program verify operation and a later read operation. | 2011-09-29 |
20110235423 | VERIFICATION PROCESS FOR NON-VOLATILE STORAGE - When erasing non-volatile storage, a verification process is used between erase operations to determine whether the non-volatile storage has been successfully erased. The verification process includes separately performing verification for different subsets of the non-volatile storage elements. | 2011-09-29 |
20110235424 | HIERARCHICAL COMMON SOURCE LINE STRUCTURE IN NAND FLASH MEMORY - Each memory cell string in a generic NAND flash cell block connects to a Common Source Line (CLS). A value for applying to the CSL is centrally generated and distributed to a local switch logic unit corresponding to each NAND flash cell block. For source-line page programming, the distribution line may be called a Global Common Source Line (GCSL). In an array of NAND flash cell blocks, only one NAND flash cell block is selected at a time for programming. To reduce power consumption, only the selected NAND flash cell block receives a value on the CSL that is indicative of the value on the GCSL. Additionally, the CSLs of non-selected NAND flash cell blocks may be disabled through an active connection to ground. | 2011-09-29 |
20110235425 | METHOD OF DIRECTLY READING OUTPUT VOLTAGE TO DETERMINE DATA STORED IN A NON-VOLATILE MEMORY CELL - An NVM cell design enables direct reading of cell output voltage to determine data stored in the cell, while providing low current consumption and a simple program sequence that utilizes reverse Fowler-Nordheim tunneling. | 2011-09-29 |
20110235426 | FLASH MEMORY SYSTEM HAVING A PLURALITY OF SERIALLY CONNECTED DEVICES - A semiconductor memory device and system are disclosed. The memory device includes a memory, a plurality of inputs, and a device identification register for storing register bits that distinguish the memory device from other possible memory devices. Circuitry for comparing identification bits in the information signal with the register bits provides positive or negative indication as to whether the identification bits match the register bits. If the indication is positive, then the memory device is configured to respond as having been selected by a controller. If the indication is negative, then the memory device is configured to respond as having not been selected by the controller. A plurality of outputs release a set of output signals towards a next device. | 2011-09-29 |
20110235427 | Channel Hot Electron Injection Programming Method and Related Device - A nonvolatile memory device for reducing programming current and improving reliability comprises a memory cell array, a write circuit, and a verification circuit. The memory cell array comprises memory cells arranged at crossing points of a bit-line and word-line matrix of the memory cell array. The write circuit provides multiple variable pulses to each word-line for programming. The multiple variable pulses have predetermined amplitude for keeping gate injection current roughly maximum while lowering conduction current during programming operation. The verification circuit senses variation of the conduction current during the programming operation, and disables the programming operation if the sensed conduction current during the programming operation reaches a predetermined value. | 2011-09-29 |
20110235428 | COMPENSATION OF NON-VOLATILE MEMORY CHIP NON-IDEALITIES BY PROGRAM PULSE ADJUSTMENT - To program a set of non-volatile storage elements, a set of programming pulses are applied to the control gates (or other terminals) of the non-volatile storage elements. The programming pulses have pulse widths that vary as a function of simulated pulse magnitude data. The programming pulses can also have pulse magnitudes that vary based on measurements taken while testing the set of non-volatile storage elements. In one embodiment, the pulse widths are determined after simulation performed prior to fabrication of the non-volatile storage elements. In another embodiment, the pulse magnitudes are calculated after fabrication of the non-volatile storage elements. | 2011-09-29 |
20110235429 | METHOD AND APPARATUS FOR PROGRAMMING FLASH MEMORY - A method and apparatus that provides the ability to control programming pulses having different widths and/or voltages in a flash memory device. The widths and/or voltage levels of programming pulses are set to achieve programming of all memory cells of an array using a minimum number of programming pulses. | 2011-09-29 |
20110235430 | MEMORY DEVICE AND METHOD - During first portion of a first read cycle determining that a first input of a sense amplifier is to receive information based upon a state of a storage cell during a first portion of a read cycle, and determining that a conductance at the first input is substantially equal to a conductance at a second input of the sense amplifier during the first portion. A plurality of NAND string modules are connected to a global bit line of a memory device that includes a memory column where a plurality of NAND strings and a buffer are formed. | 2011-09-29 |
20110235431 | NONVOLATILE SEMICONDUCTOR MEMORY AND METHOD OF OPERATING THE SAME - According to one embodiment, a nonvolatile semiconductor memory includes memory cells arranged in a memory cell array in the form of a matrix, the memory cell storing data having two or more levels associated with two or more threshold levels, respectively, a buffer circuit including latch circuits and sense amplifier circuits, each latch circuit and each sense amplifier being associated with each column in the memory cell array, and a control circuit configured to control operations of the memory cells and the buffer circuit, the control circuit executing data writing with respect to the memory cells and first verification using judgment information indicative of a result of the data writing in a write sequence with respect to data from the outside. The judgment information is assigned to two or more threshold levels, which are not adjacent to each other, in common. | 2011-09-29 |
20110235432 | METHOD OF ERASING IN NON-VOLATILE MEMORY DEVICE - An erasing method of post-programming in a nonvolatile memory device. The method includes post-programming dummy memory cells; verifying whether threshold voltages of the dummy memory cells are greater than or equal to a first voltage; post-programming normal memory cells; and verifying whether threshold voltages of the normal memory cells are greater than or equal to a second voltage. The first voltage is different from the second voltage. | 2011-09-29 |
20110235433 | VERIFYING AN ERASE THRESHOLD IN A MEMORY DEVICE - In one or more embodiments, a memory device is disclosed as having an erase verify operation that includes a negative bias on the p-well in which the memory cell or cells being erased are formed. After an erase pulse is applied to the selected cells to be erased, the p-well is biased with the negative voltage and the erase verify operation is performed to determine the erased state of the cell(s). | 2011-09-29 |
20110235434 | SYSTEMS AND METHODS FOR REFRESHING NON-VOLATILE MEMORY - Systems and methods are disclosed for managing a non-volatile memory (“NVM”), such as a flash memory. To prevent data errors due to leakage effects, the NVM may be refreshed. For example, a reserved portion of the NVM may be selected, and a predetermined pattern can be stored into the reserved portion. The reserved portion can then be monitored for storage deterioration over time. After determining that storage deterioration of the reserved portion has occurred, the NVM can be refreshed. In some embodiments, a controller can attempt to distinguish data errors due to leakage effects from data errors due to disturb issues. | 2011-09-29 |
20110235435 | Non-Volatile Memory and Method for Power-Saving Multi-Pass Sensing - A non-volatile memory device and power-saving techniques capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has features to reduce power consumption during sensing, which is included in read, and program/verify operations. A sensing verify operation includes one or more sensing cycles relative to one or more demarcation threshold voltages to determine a memory state. In one aspect, coupling of the memory cells to their bit lines are delayed during a precharge operation in order to reduced the cells' currents working against the precharge. In another aspect, a power-consuming precharge period is minimized by preemptively starting the sensing in a multi-pass sensing operation. High current cells not detected as a result of the premature sensing will be detected in a subsequent pass. | 2011-09-29 |
20110235436 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device according to one embodiment of the present invention includes a dielectric film configured to store information depending on presence or absence of a conductive path therein, and a plurality of electrodes provided to contact a first surface of the dielectric film. The conductive path can be formed between two electrodes arbitrarily selected form the plurality of electrodes. The conductive path has a rectifying property of allowing a current to flow more easily in a first direction connecting arbitrary two electrodes than in a second direction opposite to the first direction. The largest possible number of the conductive paths that may be formed is larger than the number of the plurality of electrodes. | 2011-09-29 |
20110235437 | Single-Polycrystalline Silicon Electrically Erasable and Programmable Memory Device of Varied Gate Oxide Thickness, Using PIP or MIM Coupling Capacitor for Cell Size Reduction and Simultaneous VPP and VNN for Write Voltage Reduction - A single polycrystalline silicon floating gate nonvolatile memory device has a storage MOS transistor and at least one polycrystalline-insulator-polycrystalline (PIP) or metal-insulator-metal (MIM) capacitor manufactured with dimensions that can be fabricated using current low voltage logic integrated circuit process. The PIP or MIM capacitor is a coupling capacitor with a first plate connected to a floating gate of the storage MOS transistor to form a floating gate node. The coupling PIP or MIM capacitor couples the voltage level applied to a second plate of the PIP or MIM capacitor to the floating gate node with a large coupling ratio approximately 90% so as to initiate Fowler-Nordheim tunneling effect for erasing or programming the memory device. The memory device may also have another PIP or MIM capacitor with a first pate connected to the floating gate of the storage MOS transistor for serving as a tunneling capacitor. | 2011-09-29 |
20110235438 | TEMPORAL ALIGNMENT OF DATA UNIT GROUPS IN A SWITCH - Consistent with the present disclosure, a plurality of FIFO buffers, for example, are provided in a switch, which also includes a switch fabric. Each of the plurality of FIFOs is pre-filled with data for a duration based on a skew or time difference between the time that a data unit group is supplied to its corresponding FIFO and a reference time. The reference time is the time, for example, after a delay period has lapsed following the leading edge of a synch signal, the timing of which is a known system parameter and is used to trigger switching in the switch fabric. Typically, the delay period may be equal to the latency (often, another known system parameter) or length of time required for the data unit to propagate from an input circuit, such as a line card of the switch or another switch, to the FIFO that receives the data unit. At the reference time, temporally aligned data unit groups may be read or output from each FIFO and supplied to the switch fabric. Since the timing of the output from the FIFOs is based on known system parameters, instead of the actual arrival of the slowest data unit group at its corresponding FIFO, time aligned data unit groups may be output regardless of whether the slowest data unit group is available. | 2011-09-29 |
20110235439 | STATIC MEMORY CELL HAVING INDEPENDENT DATA HOLDING VOLTAGE - A static memory cell, composed of cross-coupled MOS transistors having a relatively high threshold voltage, is equipped with MOS transistors for controlling the power supply line voltage of the memory cell. To permit the voltage difference between two data storage nodes in the inactivated memory cell to exceed the voltage difference between the two nodes when write data is applied from a data line pair DL and /DL to the two nodes in the activated memory cell, the power supply line voltage control transistors are turned on to apply a high voltage VCH to the power supply lines after the word line voltage is turned off. The data holding voltage in the memory cell can be activated to a high voltage independent of the data line voltage, and the data holding voltage can be dynamically set so that read and write operations can be performed at high speed with low power consumption. | 2011-09-29 |
20110235440 | Nonvolatile semiconductor memory device - A nonvolatile semiconductor memory device includes: a sense amplifier; bit lines coupled to the sense amplifier; memory cell transistors and dummy cell transistors coupled in parallel with the bit lines; and a current generating circuit that supplies a test current to current nodes. Either of the source and the drain of each of the dummy cell transistors is coupled to a bit line and the other is coupled to a current node. In a read operation test, the current generating circuit is activated and then the dummy cell transistors are turned on. The sense amplifier compares the test current passed through a bit line with a reference current and outputs output data corresponding to the result of the comparison. | 2011-09-29 |
20110235441 | High voltage generating circuit and semiconductor memory device having the same and method thereof - A high voltage generating circuit may include a pulse signal generator, a counter, a plurality of transmitters, and/or a plurality of pumpers. The pulse signal generator may be configured to be enabled in response to a refresh command signal to output a pulse signal. The counter may be configured to count the pulse signal and sequentially output a plurality of selection signals. The plurality of transmitters may be configured to be sequentially enabled in response to individual selection signals of the plurality of selection signals to transmit the pulse signal. The plurality of pumpers may correspond to the plurality of transmitters. Each of the plurality of pumpers may be configured to collectively generate a high voltage based on the transmitted pulse signal from a corresponding transmitter of the plurality of transmitters. | 2011-09-29 |
20110235442 | Integrated Circuit with Separate Supply Voltage for Memory That is Different from Logic Circuit Supply Voltage - In one embodiment, an integrated circuit includes at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method includes a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use. | 2011-09-29 |
20110235443 | VOLTAGE STABILIZATION CIRCUIT AND SEMICONDUCTOR MEMORY APPARATUS USING THE SAME - A voltage stabilization circuit of a semiconductor memory apparatus includes an operation speed detecting unit configured to detect an operation speed of the semiconductor memory apparatus to generate a detection signal, and a voltage line controlling unit configured to interconnect a first voltage line and a second voltage line in response to the detection signal. | 2011-09-29 |
20110235444 | SRAM WRITING SYSTEM AND RELATED APPARATUS - SRAM writing system and related apparatus are provided. The writing system of the invention has a dummy replica writing circuit, a negative pulse controller and at least a normal writing circuit; each normal writing circuit includes a write driver and a negative pulse supplier. While writing, the dummy replica writing circuit drives a dummy replica bit-line, such that the negative pulse controller generates a negative pulse control signal according to level of the dummy replica bit-line. In each writing circuit, when the write driver conducts to connect an associated bit-line to a bias end for driving a level transition, the negative pulse supplier switches the bias end from an operation voltage to a different negative pulse voltage according to the received negative pulse control signal. | 2011-09-29 |
20110235445 | METHOD AND SYSTEM TO LOWER THE MINIMUM OPERATING VOLTAGE OF REGISTER FILES - A method and system to lower the minimum operating voltage of a register file without increasing the area of each bit cell of the register file. In one embodiment of the invention, the register file is coupled to logic that reduces the contention between the NMOS devices and the PMOS devices in each bit cell of the register file during write and/or read operations of the register file. By doing so, the register file is able to operate at a lower minimum operating voltage. | 2011-09-29 |
20110235446 | WRITE STROBE GENERATION FOR A MEMORY INTERFACE CONTROLLER - A memory controller includes a circuit to generate a strobe signal for write operations to a DDR SDRAM. The circuit efficiently generates a glitch free strobe signal for a group of data lines. In one implementation, the memory controller includes a write data generation circuits to each transmit a data signal to the memory on a data line, the write data generation circuits being controlled by write enable signals. A write strobe generation circuit generates the strobe signal and the write enable signals, the strobe signal including a preamble window to signal the beginning of the data burst, a data transfer window, and a postamble window to signal the end of the data burst, the write strobe generation circuit generating the write enable signals a half memory cycle early and terminating the write enable signals a half memory cycle late with respect to the data signals generated by the write data generation circuits. | 2011-09-29 |
20110235447 | LOW POWER MEMORY ARRAY COLUMN REDUNDANCY MECHANISM - A low power memory array column redundancy mechanism includes a memory unit having a memory array and a multiplexer unit. The memory array includes a plurality of columns, which includes a plurality of data columns and one or more unused columns. The multiplexer unit may selectively provide a constant value to the one or more unused columns of the memory array, and provide write data to the plurality of data columns during each write operation of the plurality of columns. | 2011-09-29 |
20110235448 | USING DIFFERENTIAL SIGNALS TO READ DATA ON A SINGLE-END PORT - In some embodiments related to reading data in a memory cell, the data is driven to a local bit line, which drives a local sense amplifier. Depending on the logic level of the data in the memory cell and thus the local bit line, the local sense amplifier transfers the data on the local bit line to a global bit line. A neighbor global bit line is used as a reference for a global sense amplifier to read the differential data on the global bit line and the neighbor global bit line. | 2011-09-29 |
20110235449 | Dual Sensing Current Latched Sense Amplifier - A sense amplifier and method thereof are provided. The sense amplifier includes first and second transistors coupled to first and second bit lines, respectively. The first and second transistors are configured to connect the first and second bit lines to a differential amplifier during a first state (e.g., when a differential voltage is present on the first and second bit lines and prior to a sense signal transition) and to isolate the first and second bit lines from the differential amplifier during a second state (e.g., after the sense signal transition). The sense amplifier further includes a third transistor configured to deactivate the differential amplifier during the first state and configured to activate the differential amplifier during the second state. | 2011-09-29 |
20110235450 | CURRENT MODE SENSE AMPLIFIER WITH PASSIVE LOAD - Memories, current mode sense amplifiers, and methods for operating the same are disclosed, including a current mode sense amplifier including cross-coupled p-channel transistors and a load circuit coupled to the cross-coupled p-channel transistors. The load circuit is configured to provide a resistance to control at least in part the loop gain of the current mode sense amplifier, the load circuit including at least passive resistance. | 2011-09-29 |
20110235451 | DYNAMIC RANDOM ACCESS MEMORY AND METHOD OF DRIVING DYNAMIC RANDOM ACCESS MEMORY - A dynamic RAM which includes a first inverter, a second inverter, a sense amplifier, a first pair of switches, a pair of bit lines, and a dynamic RAM cell. The first inverter receives a first driving signal. A power end of the first inverter is coupled to a first voltage source. The second inverter receives a second driving signal output from the first inverter. A power end of the second inverter is coupled to a second voltage source. The sense amplifier senses and amplifies a voltage difference between a first sensing signal and a second sensing signal. A power end of the sense amplifier is coupled to a third voltage source, wherein a voltage value of the second voltage source is between a voltage value of the first voltage source and a voltage value of the third voltage source. | 2011-09-29 |
20110235452 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor memory device including an information storage unit comprising a fuse configured to store information, a control unit configured to control a node of a blown fuse to become a floating state in response to a control pulse signal, and an output unit configured to output the information. | 2011-09-29 |
20110235453 | FUSE CIRCUIT AND REPAIR CONTROL CIRCUIT USING THE SAME - A fuse circuit includes a fuse driving unit, a separation/connection unit, a voltage equalization unit, and a latching unit. The fuse driving unit is configured to drive an output terminal in response to a fuse reset signal, depending on data programmed in a fuse. The separation/connection unit is disposed between the fuse and the output terminal and configured to separate or connect the fuse from or to the output terminal in response to a control signal. The voltage equalization unit is configured to equalize both ends of the fuse to the same voltage in response to the control signal. The latching unit is configured to latch and output the output terminal driven by the fuse driving unit. | 2011-09-29 |
20110235454 | High-voltage selecting circuit which can generate an output voltage without a voltage drop - A high-voltage selecting circuit generates an output voltage with no voltage drop by means of an auxiliary NMOS transistor turning on the corresponding selecting PMOS transistor of the high-voltage selecting circuit when the voltage levels of a first input voltage and a second input voltage are equal. In addition, when one of the first input voltage and the second input voltage is higher than the other one, the high-voltage selecting circuit avoids the leakage current by means of an auxiliary PMOS transistor turning off the corresponding selecting PMOS transistor of the high-voltage selecting circuit. In this way, the high-voltage selecting circuit can correctly generate the output voltage according to the first input voltage and the second input voltage, and avoid the leakage current at the same time. | 2011-09-29 |
20110235455 | VOLTAGE REGULATORS, AMPLIFIERS, MEMORY DEVICES AND METHODS - Circuits, devices and methods are provided, such as an amplifier (e.g., a voltage regulator) that includes a feedback circuit that supplies negative feedback through a feedback path. One such feedback path includes a capacitance coupled in series with a “one-way” isolation circuit through which a feedback signal is coupled. The “one-way” isolation circuit may allow the feedback signal to be coupled from a “downstream” node, such as an output node, to an “upstream” node, such as a node at which an error signal is generated to provide negative feedback. However, the “one-way” isolation circuit may substantially prevent variations in the voltage at the upstream node from being coupled to the capacitance in the isolation circuit. As a result, the voltage at the upstream node may quickly change since charging and discharging of the capacitance responsive to voltage variations at the upstream node may be avoided. | 2011-09-29 |
20110235456 | POWER SUPPLY CONTROL CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME - A power supply control circuit includes a power supply control unit configured to receive a rank mode signal and generate a plurality of power supply enable signals based on a rank mode designated by the rank mode signal, a chip selection signals and bank address signals; and a plurality of power blocks configured to supply power to a plurality of memory banks of a plurality of chips based on the plurality of power supply enable signals. | 2011-09-29 |
20110235457 | SEMICONDCUTOR INTEGRATED CIRCUIT DEVICE - According to one embodiment, a semiconductor integrated circuit device is provided. The semiconductor integrated circuit device is provided with a plurality of booster circuits, a regulator and a plurality of switches. Each of the booster circuit receives an input voltage, boosts the input voltage, and generates a boosted voltage having a different value. The regulator is capable of generating a plurality of dropped voltages by dropping each boosted voltage from the booster circuits. The switches are connected between the booster circuits and the regulator. The switches provide the boosted voltages outputted from the booster circuits selectively to the regulator as a power-supply voltage. | 2011-09-29 |
20110235458 | ELECTRIC DEVICE - In one embodiment, an electric device includes a memory, first and second generators, a limit unit, and a reduction unit. The first generator generates the chip select signal representing an inactive mode or an active mode according to a potential of an enable terminal and a input potential The second generator generates an enable signal which is a first level, a second level or a level having the first value as a maximum value. The limit unit limits the potential of the terminal to a potential lower than the first potential during first and second periods, and does not prevent from the enable signal from being input to the terminal during other periods. The reduction unit reduces the level of the enable signal at a predetermined rate, and then inputs the reduced enable signal to the terminal. | 2011-09-29 |
20110235459 | CLOCK-FORWARDING LOW-POWER SIGNALING SYSTEM - In a low-power signaling system, an integrated circuit device includes an open loop-clock distribution circuit and a transmit circuit that cooperate to enable high-speed transmission of information-bearing symbols unaccompanied by source-synchronous timing references. The open-loop clock distribution circuit generates a transmit clock signal in response to an externally-supplied clock signal, and the transmit circuit outputs a sequence of symbols onto an external signal line in response to transitions of the transmit clock signal. Each of the symbols is valid at the output of the transmit circuit for a symbol time and a phase offset between the transmit clock signal and the externally-supplied clock signal is permitted to drift by at least the symbol time. | 2011-09-29 |
20110235460 | METHOD AND APPARATUS TO OPTIMIZE THE MIXING PROCESS - A system for mixing a liquid material and a solid material comprises (i) a base unit for the liquid material and the solid material; (ii) a liquid material supply; (iii) a solid material supply; (iv) a liquid/solid mixing output; (v) an injection unit connected to the liquid material supply and to the solid material supply and the injection unit injecting the liquid material and the solid material in the base unit; (vi) a separation and extraction unit simultaneously separating and extracting surplus gas arising from the mixing of the liquid material and the solid material. | 2011-09-29 |
20110235461 | FUNCTIONING SECTION OF A HAND BLENDER AND/OR MIXER WITH MULTIPLE ROTATING BLADES - The invention refers to the functioning section of a hand blender and/or a hand mixer having more than one rotating blade enabling users to blend dry and/or liquid food. The functioning section includes a rotating blade, a transmission shaft, a guard surrounding the blade, and transmission/coupling elements. By virtue of more than one rotating blade, it allows the fulfillment of blending, mixing and homogenization procedures of dry and/or liquid food. | 2011-09-29 |
20110235462 | Shaft-actuated Spindle Mixer - The disclosed apparatus, system and method relate to a shaft-actuated spindle mixer where the spindle mixer includes a motor and at least one motor switch enclosed in a mixer housing. A spindle shaft extends from the housing and is mechanically connected to the motor. The motor is mounted to a moveable mixer component such that the spindle shaft can be displaced to thereby causing the associated movement of the enclosed motor and moveable mixer component to which the motor is mounted. Movement of the movable mixer component actuates a switch. Actuating the switch causes the selective activation of the mixer motor. Activating the mixer motor rotates the spindle shaft. The disclosed apparatus and method provide for the optional one-handed operation of a spindle mixer, eliminate the need for a user or a cup to directly contact a switch to engage the spindle mixer, and further provides for the sanitary operation of a spindle mixer. | 2011-09-29 |
20110235463 | MIXING APPARATUS - A mixer according to the present disclosure may include a container for receiving material to be mixed, and a mixing assembly configured to extend into the container. The mixing assembly may include a rotatable shaft and multiple blade units connected to the shaft. Furthermore, each blade unit may include multiple parallel blades. | 2011-09-29 |
20110235464 | Method of imaging the earth's subsurface during marine seismic data acquisition - Marine seismic data are acquired, using a seismic vessel. The acquired marine seismic data are transferred in near-real time to a programmable computer. The programmable computer is used to perform the following. An acoustic 3-D full-waveform inversion is applied to the transferred marine seismic data, generating a high-resolution 3-D velocity field in near-real time. The velocity field is used to apply migration to the transferred marine seismic data, generating an image of the earth's subsurface in near-real time. | 2011-09-29 |
20110235465 | PRESSURE AND FREQUENCY MODULATED NON-LETHAL ACOUSTIC WEAPON - An acoustic weapon comprises a sonic pulse generator configured to generate discrete sonic pulses at a repetition rate. A sensor is configured to measure a range-to-target. A controller is configured to control the sonic pulse generator to generate a single shot including a burst of multiple pulses at a fixed repetition rate, to adjust the fixed repetition rate to shift the frequency content of the burst in accordance with a target coupling efficiency towards improving energy transfer to the target and to adjust the peak pressure of the burst in accordance with the range-to-target towards applying a specified peak pressure to the target. The controller may incorporate the target coupling efficiency as well as other parameters such as target apparent area and beam width when adjusting the weapon peak pressure. A pulse detonation engine (PDE) or pulse manifold (PM) may be modified and controlled to provide the large discrete peak pressures required at a periodic repetition rate. | 2011-09-29 |
20110235466 | ULTRASOUND DETECTORS - A method of receiving data coded on an ultrasonic signal comprising: detecting said ultrasonic signal using a microphone ( | 2011-09-29 |
20110235467 | MAN-PORTABLE NON-LETHAL PRESSURE SHIELD - A man-portable non-lethal pressure shield provides both a physical as well as pressure shield. The pressure shield addresses the concerns of military, police and human rights organizations and international law as regards effectiveness, efficiency and safety and efficiency. A folded acoustic horn is incorporated into the physical shell of the shield. The horn couples acoustic pulses from a sonic pulse generator to an acoustic aperture to output a pulsed pressure beam that approximates a plane wave to produce a pressure barrier. The operator may specify a desired effect on its human target that is maintained as range-to-target changes or a desired effect at a specified perimeter range. The shields may be networked to facilitate coordinated action among multiple pressure shields as a force multiplier or to provide a more sophisticated pressure barrier. | 2011-09-29 |
20110235468 | Electronic Perpetual Calendar With Erasable And Tackable Surfaces - An electronic perpetual calendar erasable board with a tackable surface, such as a bulletin bar. In one embodiment, the calendar may include a front panel having a graphic that includes cells each representing a calendar day, e.g., a month grid of cells arranged in rows and columns or a weekly planner table with cells arranged in a row. The front panel may include a plurality of electronic displays so that the calendar is capable of displaying an accurate number and configuration of days for any month or week. Other embodiments may include a markable and erasable write-on/wipe-off surface and a frame that has a tackable surface integrated therein. The tackable surface may be cork, foam, fiber, or a composite. | 2011-09-29 |
20110235469 | PORTABLE AND PERSONAL ALARM CLOCK SYSTEM - A portable and personal alarm clock system which incorporates the use of wireless technology to wake a person up through a personal earpiece alarm. This device comprises two main components including an earpiece alarm and a receiving base. The earpiece alarm is integrated with a small rechargeable battery and charging portal and is designed to automatically turn on after removing from receiving base. The receiving base resembles an electric alarm clock having an LED face, two speakers, a snooze button, buttons for setting the clock and alarm, and an alarm sound selector function. There is a charging means for the earpiece(s) and a volume control for the ear piece and base speakers. The base could also include a backup power source. | 2011-09-29 |
20110235470 | Electronic Timepiece and Control Method for an Electronic Timepiece - An electronic timepiece includes a reception unit that receives satellite signals transmitted from positioning information satellites; a manual reception process unit that starts operation of the reception unit and executes a manual reception process when an external operating member is operated; an automatic reception process unit that automatically operates the reception unit and executes an automatic reception process when a predetermined condition is satisfied; a simple time adjustment process unit that executes such a process to receive a satellite signal from one positioning information satellite, acquire time information from the received satellite signal, and adjust an internal time; and a high precision time adjustment process unit that executes such a process to receive satellite signals from a plurality of positioning information satellites, acquire time and positioning information from the received satellite signals and determine the location, and adjust the internal time to the time acquired based on the positioning result. The simple time adjustment process is executed when the automatic reception process executes. The high precision time adjustment process is executed when the manual reception process executes, after voltage detection of the battery is detected and if the so detected voltage is greater than a prescribed voltage. | 2011-09-29 |
20110235471 | Timepiece with Multi-Functional Actuator - An analog timepiece includes a casing, a time displaying device, an electronic device received in the casing, a main control unit (MCU) communicated with the time displaying device and the electronic device for selectively controlling an operation of the time displaying device and sad electronic device and a multi-functional actuator. The multi-function actuator includes an actuator button movably provided on the casing to selectively move between an idle position, a time adjustment position and a triggering position, wherein in the idle position, the actuator button disengages with the MCU to allow normal operation of the electronic device, wherein in the time adjustment position, the actuator button is moved from the idle position to allow adjustment of the time displaying device, and wherein in the triggering position, the actuator is moved to engage with the MCU for triggering an operation of the electronic device. | 2011-09-29 |
20110235472 | Stepping motor control circuit and analog electronic timepiece - A stepping motor control circuit and an analog electronic timepiece which can detect a rotation state including intermediate stopping more accurately are provided. A rotation detection circuit, in detecting whether or not an induction signal generated by the rotation of a stepping motor exceeds a predetermined reference threshold voltage during a detection period having a plurality of sections, detects whether or not the induction signal with inverted polarity exceeds a predetermined reference threshold voltage during a predetermined section, and a control unit immediately performs a drive control of the stepping motor with a correction drive pulse when it is determined that there is a sign of intermediate stopping of the stepping motor based on a result of detection by the rotation detection circuit. | 2011-09-29 |
20110235473 | Switch structure, and chronograph mechanism and electronic timepiece using the same - A switch structure of a chronograph mechanism of an electronic timepiece includes: a terminal plate equipped with a plate-like main body portion and elastic switch lever portions, each switch lever portion being equipped with an arm portion which is and bent with respect to the outer peripheral edge portion of the plate-like main body portion at one side of the proximal end portion thereof, and which extends in a direction along the outer peripheral edge portion of the plate-like main body portion, and which is equipped with an elastic contact portion further extending from the pressing force receiving portion; and an elastic switch lever supporting rigid support lever which is movably provided behind the pressing force receiving portion in order to receive a pressing force behind the pressing force receiving portion and to guide displacement of the pressing force receiving portion when a pressing force is applied to the pressing force receiving portion. | 2011-09-29 |
20110235474 | CLOCK MOVEMENT CONTAINING A CONSTANT FORCE DEVICE - A clock movement is provided that contains a constant force device. In accordance with one implementation, the clock movement includes a spiral spring, and a train, having a first kinematic chain arranged to connect a main energy source to a first end of the spiral spring and a second kinematic chain for connecting a time base to a second end of the spiral spring. One of the first and second kinematic chains may contain an adjustment mobile comprising first and second members connected to each other by a friction such that a rotation of one member drives the other member during routine working of the clock movement. One of these members may include an adjustment member having at least one bearing surface arranged such that it is possible to act upon the latter so as to rotate the adjustment member without rotating the other member by dint of friction, in order to adjust the load state of the spiral spring. | 2011-09-29 |
20110235475 | SHOCK ABSORBING MEMBER FOR WRISTWATCH AND WRISTWATCH - A shock absorbing member for a wristwatch including a wristwatch case whose side portions are provided with a pair of bands and an operation member positioned avoiding the pair of bands, and back surface has a case back attached thereto. This shock absorbing member is made of a flexible resin, and includes a peripheral side portion that surrounds the wristwatch case and projects further outward than a top surface of the wristwatch case, and a bottom portion to which the case back is attached. In addition, the peripheral side portion is provided with band holes into which the pair of bands are inserted and an operation hole corresponding to the operation member. Accordingly, even when a strong shock of falling from a high place or the like is received, the shock is unfailingly absorbed. | 2011-09-29 |
20110235476 | Portable timepiece - To provide a portable timepiece in which water is not easily allowed to enter the timepiece exterior assembly with the completion of venting, the timepiece is equipped with a vent valve mounted to a timepiece exterior assembly. The vent valve is equipped with a valve body holder fixed to the timepiece exterior assembly, a ring-shaped packing supported by the holder and elastically deformable, and a valve body movable between a valve-closed position and a valve-open position. The valve body has a valve body shaft portion, a valve body head integral with this shaft portion, and an exhaust recess formed in the valve body shaft portion. The valve body shaft portion axially extends through the valve body holder while in contact with the inner peripheral portion of the packing. Through movement of the valve body, the exhaust recess is detached from the packing at the valve-closed position, and, at the valve-open position, the exhaust recess is arranged so as to be astride and cross apart of the inner peripheral portion of the packing. | 2011-09-29 |