39th week of 2017 patent applcation highlights part 57 |
Patent application number | Title | Published |
20170278843 | LARGE AREA DIODE CO-INTEGRATED WITH VERTICAL FIELD-EFFECT-TRANSISTORS - An integrated circuit is provided having a semiconductor structure, the semiconductor structure including a vertical field-effect transistor; and a diode wherein the vertical field-effect transistor and the diode are co-integrated in the semiconductor structure. | 2017-09-28 |
20170278844 | METHODS, APPARATUS AND SYSTEM FOR STI RECESS CONTROL FOR HIGHLY SCALED FINFET DEVICES - At least one method, apparatus and system are disclosed for forming a fin field effect transistor (finFET) having an oxide level in a fin array region within a predetermined height of the oxide level of a field region. A first oxide process is performed for controlling a first oxide recess level in a field region adjacent to a fin array region comprising a plurality of fins in a finFET device. The first oxide process comprises depositing an oxide layer over the field region and the fin array region and performing an oxide recess process to bring the oxide layer to the first oxide recess level in the field region. A second oxide process is performed for controlling a second oxide recess level in the fin array region. The second oxide process comprises isolating the fin array region, depositing oxide material, and performing an oxide recess process to bring the oxide level in the fin array region to the second oxide recess level. The first oxide recess level is within a predetermined height differential of the second oxide recess level. | 2017-09-28 |
20170278845 | METHOD FOR FABRICATING FIN-SHAPED STRUCTURE AND BUMP MADE OF DIFFERENT MATERIAL - A method for fabricating semiconductor device is disclosed. First, a substrate is provided, a first fin-shaped structure and a bump are formed on the substrate, and an insulating layer is formed on the bump and around the first fin-shaped structure. Next, a part of the first fin-shaped structure is removed, an epitaxial layer is formed on the first fin-shaped structure, part of the epitaxial layer is removed, and part of the insulating layer is removed to form a shallow trench isolation (STI) and a second fin-shaped structure protruding from the STI. Preferably, the second fin-shaped structure includes a top portion and a bottom portion, in which the bottom portion and the bump are made of same material. | 2017-09-28 |
20170278846 | SEMICONDUCTOR MEMORY DEVICE HAVING AN ELECTRICALLY FLOATING BODY TRANSISTOR - An IC may include an array of memory cells formed in a semiconductor, including memory cells arranged in rows and columns, each memory cell may include a floating body region defining at least a portion of a surface of the memory cell, the floating body region having a first conductivity type; a buried region located within the memory cell and located adjacent to the floating body region, wherein the buried region has a second conductivity type, wherein the floating body region is bounded on a first side by a first insulating region having a first thickness and on a second side by a second insulating region having a second thickness, and a gate region above the floating body region and the second insulating region and is insulated from the floating body region by an insulating layer; and control circuitry configured to provide electrical signals to said buried region. | 2017-09-28 |
20170278847 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a substrate including a cell area and a background area, the background area surrounding the cell area, a plurality of active patterns in the cell area along a first direction, the active patterns being defined by a device isolation layer, and a background pattern filling the background area to surround the cell area, wherein the active patterns include a first active pattern most adjacent to an edge of the cell area, and a second active pattern separated from the first active pattern in a second direction intersecting the first direction, the second active pattern being separated from the background area. | 2017-09-28 |
20170278848 | Semiconductor Device Having a Memory Cell and Method of Forming the Same - There is provided an apparatus includes a substrate having a main surface, a wordline buried in the substrate and a bitline buried in a shallower area than the wordline in the substrate. | 2017-09-28 |
20170278849 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes the steps of: determining a first design dimension of a gate electrode of a selection MISFET, a second design dimension of a sidewall insulating film, and initial setting conditions for ion implantation for a high-concentration semiconductor region; forming the gate electrode; measuring a first processed dimension of the gate electrode; implanting ions to form a low-concentration semiconductor region at each end of the gate electrode; forming the sidewall insulating film over a sidewall of the gate electrode; measuring a second processed dimension of the sidewall insulating film; and implanting ions to form a high-concentration semiconductor region. In the former implantation step, execution conditions to the initial setting conditions are reset according to a deviation of the first processed dimension from the first design dimension and a deviation of the second processed dimension from the second design dimension, and the step is executed. | 2017-09-28 |
20170278850 | PADS AND PIN-OUTS IN THREE DIMENSIONAL INTEGRATED CIRCUITS - A three dimensional semiconductor device, comprising: a substrate including a plurality of circuits; a plurality of pads, each pad coupled to a circuit; and a memory array positioned above or below the substrate and coupled to a circuit to program the memory array. | 2017-09-28 |
20170278851 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device according to one embodiment includes a stacked body and a semiconductor layer. The stacked body includes a plurality of control gate electrodes stacked above a substrate. The semiconductor layer extends in a first direction intersecting with the substrate and faces the plurality of control gate electrodes. The semiconductor memory device further includes a gate insulating layer disposed between the control gate electrodes and the semiconductor layer. The gate insulating layer includes zirconium oxide at a position facing the control gate electrodes. | 2017-09-28 |
20170278852 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device according to an embodiment includes: a semiconductor substrata; a plurality of first insulating layers and first conductive layers stacked alternately in a first direction above the semiconductor substrate; a first semiconductor layer extending in the first direction; and a memory layer disposed between one of the first insulating layers and the first semiconductor layer and between one of the first conductive layers and the first semiconductor layer, the memory layer including a charge accumulation layer, the first semiconductor layer and the memory layer having a gap, between one of the first insulating layers and the first semiconductor layer, and the first semiconductor layer and the memory layer being contacted each other, between one of the first conductive layers and the first semiconductor layer. | 2017-09-28 |
20170278853 | INTEGRATION OF A MEMORY TRANSISTOR INTO HIGH-K, METAL GATE CMOS PROCESS FLOW - Memory cells including embedded SONOS based non-volatile memory (NVM) and MOS transistors and methods of forming the same are described. Generally, the method includes: forming a gate stack of a NVM transistor in a NVM region of a substrate including the NVM region and a plurality of MOS regions; and depositing a high-k dielectric material over the gate stack of the NVM transistor and the plurality of MOS regions to concurrently form a blocking dielectric comprising the high-k dielectric material in the gate stack of the NVM transistor and high-k gate dielectrics in the plurality of MOS regions. In one embodiment, a first metal layer is deposited over the high-k dielectric material and patterned to concurrently form a metal gate over the gate stack of the NVM transistor, and a metal gate of a field effect transistor in one of the MOS regions. | 2017-09-28 |
20170278854 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - In a MONOS memory, withstand voltage is increased between a control gate electrode over an ONO film having a charge accumulating part and a semiconductor substrate. When a silicon film is processed to form a control gate electrode, dry etching is performed for a relatively long time, thereby a recess is formed in a sidewall of the control gate electrode. Subsequently, the control gate electrode is subjected to dry oxidation treatment to form an insulating film on the sidewall of the control gate electrode including the recess, thereby an end of the bottom of the control gate electrode is separated from an end of the top of the ONO film. | 2017-09-28 |
20170278855 | ONE-TIME PROGRAMMING CELL - A one-time programing cell includes a first metal oxide semiconductor (MOS) structure and a second transistor having a common gate electrode electrically connected to a word line. The first MOS structure has a first gate dielectric layer and the second MOS structure has a second gate dielectric layer. The second gate dielectric layer is thicker than the first gate dielectric layer. Source nodes of the first MOS structure and the second MOS structure are electrically connected, and a drain node of the second MOS structure is electrically connected to a bit line. | 2017-09-28 |
20170278856 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - An MISFET has a gate electrode formed on a semiconductor substrate via a gate insulating film, and a source region and a drain region formed inside the semiconductor substrate so as to sandwich the gate electrode. And, a first silicide layer is formed on surfaces of the source region and the drain region, and a second silicide layer is formed on a surface of the gate electrode. Each of the first silicide layer and the second silicide layer is made of a first metal and silicon, and further contains a second metal different from the first metal. And, a concentration of the second metal inside the second silicide layer is lower than a concentration of the second metal inside the first silicide layer. | 2017-09-28 |
20170278857 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device according to an embodiment comprises: a semiconductor substrate; a stacked body having a plurality of first insulating layers and conductive layers stacked alternately on the semiconductor substrate; a columnar semiconductor layer contacting the semiconductor substrate in the stacked body being provided extending in a stacking direction of the stacked body and including a first portion and a second portion which is provided above the first portion; a memory layer provided on a side surface of the columnar semiconductor layer facing the stacked conductive layers and extending along the columnar semiconductor layer; and a second insulating layer provided between one of the first insulating layer and the conductive layers of the stacked body. The columnar semiconductor layer has a boundary of the first portion and the second portion, the boundary being close to the second insulating layer; and an average value of an outer diameter of the memory layer facing a side surface of the second insulating layer is larger than that of of the memory layer facing a side surface of a lowermost layer of the first insulating layers in the second portion. | 2017-09-28 |
20170278858 | MONOLITHIC 3-D DYNAMIC MEMORY AND METHOD - A monolithic 3-D dynamic memory structure includes independently addressable strings of dual-gate devices. In each dual-gate device charge is deliberately stored on one side of the dual-gate. Although the stored charge may leak away, the stored charge in a dual-gate device of the present invention need only be refreshed at much longer intervals than conventional DRAM cells. | 2017-09-28 |
20170278859 | THREE-DIMENSIONAL MEMORY DEVICE CONTAINING VERTICALLY ISOLATED CHARGE STORAGE REGIONS AND METHOD OF MAKING THEREOF - A memory opening can be formed through an alternating stack of insulating layers and sacrificial material layers provided over a substrate. Annular etch stop material portions are provided at each level of the sacrificial material layers around the memory opening. The annular etch stop material portions can be formed by conversion of surface portions of the sacrificial material layers into dielectric material portion, or by recessing the sacrificial material layers around the memory opening and filling indentations around the memory opening. After formation of a memory stack structure, the sacrificial material layers are removed from the backside. The annular etch stop material portions are at least partially converted to form charge trapping material portions. Vertical isolation of the charge trapping material portions among one another around the memory stack structure minimizes leakage between the charge trapping material portions located at different word line levels. | 2017-09-28 |
20170278860 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device according to an embodiment comprises: a memory cell array region including a plurality of conductive layers that are electrically connected to a plurality of memory cells arranged in a first direction on a semiconductor substrate, the first direction intersecting a surface of the semiconductor substrate; a stepped part for contacting the plurality of conductive layers to a wiring line; a contact extending in the first direction and being connected to the conductive layer in the stepped part; and a plurality of columnar bodies extending in the first direction and penetrates the conductive layer in the stepped part and including a first columnar body having a first height and a second columnar body having a second height which is lower than the first height. | 2017-09-28 |
20170278861 | SEMICONDUCTOR MEMORY DEVICE - According to embodiments, a semiconductor memory device includes a plurality of control gate electrodes laminated on a substrate. A first semiconductor layer has one end connected to the substrate, has a longitudinal direction in a direction intersecting with the substrate, and is opposed to the plurality of control gate electrodes. An electric charge accumulating layer is positioned between this control gate electrode and the first semiconductor layer. A first contact has one end connected to the substrate and another end connected to a source line. A second contact has one end connected to the substrate and another end connected to a wiring other than the source line. The first contact includes a first silicide layer arranged on the substrate. The second contact includes a second silicide layer arranged on the substrate. The first silicide layer has a higher temperature resistance than the second silicide layer. | 2017-09-28 |
20170278862 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device according to an embodiment comprises: a plurality of memory strings arranged in a first direction intersecting a surface of a semiconductor substrate, each of the memory strings including a plurality of memory transistors connected in series in a second direction along the surface of the semiconductor substrate; a source side select transistor connected to one end of the memory string; a drain side select transistor connected to the other end of the memory string; a plurality of source lines respectively connected, via the source side select transistor, to each of the plurality of memory strings arranged along the first direction; a bit line commonly connected, via the drain side select transistor, to the plurality of memory strings arranged along the first direction; a word line connected to a gate electrode of the memory transistor; and a layer selector disposed between the source line and the source side select transistor and commonly connected to the plurality of memory strings arranged along the first direction. | 2017-09-28 |
20170278863 | THREE-DIMENSIONAL SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate including a cell array region and a peripheral circuit region. The semiconductor device further includes a cell array disposed in the cell array region and including a plurality of cell strings connected to a bit line. The bit line extends in a first direction. The semiconductor device additionally includes a first cell row disposed in the peripheral circuit region and including a plurality of first cells arranged in a second direction crossing the first direction. The first and second directions being parallel to an upper surface of the substrate. The semiconductor device further includes a plurality of first interconnect lines each having a longitudinal axis in the first direction and connected to the plurality of first cells, and a plurality of first power lines extending in the second direction and connected to the plurality of first cells through the first interconnect lines. | 2017-09-28 |
20170278864 | 3D NAND DEVICE - A method for forming a 3D NAND structure includes providing a semiconductor substrate; forming a control gate structure having a plurality of staircase-stacked layers, each layer has a first end and a second end; forming a dielectric layer covering the semiconductor substrate, and the control gate structure; forming a hard mask layer on the dielectric layer; patterning the hard mask layer to form a plurality of openings above corresponding second ends of the layers of the control gate structure; forming a photoresist layer on the hard mask layer; repeating a photoresist trimming process and a first etching process to sequentially expose the openings, and to form a plurality of holes with predetermined depths in the dielectric layer; performing a second etching process to etch the plurality of holes until surfaces of the second ends are exposed to form through holes; and forming metal vias in the through holes. | 2017-09-28 |
20170278865 | METHOD OF TUNING SOURCE/DRAIN PROXIMITY FOR INPUT/OUTPUT DEVICE RELIABILITY ENHANCEMENT - A semiconductor device includes a first FinFET device and a second FinFET device. The first FinFET device includes a first gate, a first source, and a first drain. The first FinFET device has a first source/drain proximity. The second FinFET device includes a second gate, a second source, and a second drain. The second FinFET device has a second source/drain proximity that is smaller than the first source/drain proximity. In some embodiments, \the first FinFET device is an Input/Output (I/O) device, and the second FinFET device is a non-I/O device such as a core device. In some embodiments, the greater source/drain proximity of the first FinFET device is due to an extra spacer of the first FinFET device that does not exist for the second FinFET device. | 2017-09-28 |
20170278866 | THIN FILM TRANSISTOR SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME - A thin film transistor substrate includes: a thin film transistor including: a first insulating film covering a gate electrode; a semiconductor channel layer selectively provided on the first insulating film; a second insulating film provided on the semiconductor channel layer; a first source electrode and a first drain electrode selectively provided on the second insulating film, a second source electrode and a second drain electrode provided on the first source electrode and the first drain electrode, respectively, a third insulating film that covers the second source electrode and the second drain electrode; a third source electrode connected to the semiconductor channel layer via a first contact hole provided through the third insulating film, the second and the first source electrode; a third drain electrode connected to the semiconductor channel layer via a second contact hole provided through the third insulating film, the second drain electrode, and the first drain electrode. | 2017-09-28 |
20170278867 | DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF - A display device may include a substrate, an active pattern layer, a gate insulating layer, a first metal pattern layer, an interlayer insulating layer, a second metal pattern layer, and a passivation film. The active pattern layer may be disposed on the substrate. The gate insulating layer may be disposed on the active pattern layer. The first metal pattern layer may be disposed on the gate insulating layer. The interlayer insulating layer may be disposed on the first metal pattern layer. The second metal pattern layer may be disposed on the interlayer insulating layer. The passivation film may be disposed on the side wall of the second metal pattern layer. | 2017-09-28 |
20170278868 | ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, DISPLAY DEVICE - The present disclosure provides an array substrate comprising a plurality of gate lines, and a plurality of data lines that intersect the plurality of gate lines. A plurality of pixel units are defined by the plurality of gate lines and the plurality of data lines which intersect each other. Each pixel unit comprises a thin film transistor, a gate insulating layer, a passivation layer arranged on one side of the gate insulating layer, a pixel electrode and a common electrode, wherein a source and a drain of the thin film transistor are arranged between the passivation layer and the gate insulating layer, the common electrode is arranged on the other side of the gate insulating layer opposite to the passivation layer, and the pixel electrode is arranged on the passivation layer. The present disclosure further provides a method for manufacturing an array substrate and a display device. | 2017-09-28 |
20170278869 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A first semiconductor layer is formed on an insulating surface. A first insulating layer for covering an upper side of the first semiconductor layer is formed. On the first insulating layer, a second semiconductor layer is formed. A second insulating layer for covering an upper side of the second semiconductor layer is formed. A first contact hole extending through the first and second insulating layers to reach the first semiconductor, and a second contact hole extending through the second insulating layer to reach the second semiconductor layer but not reaching the first insulating layer are opened. After the step of forming the second insulating layer before the step of opening the first and second contact holes, laser or heat annealing process is executed. | 2017-09-28 |
20170278870 | FABRICATION OF FINS USING VARIABLE SPACERS - A method of fabricating semiconductor fins, including, patterning a film stack to produce one or more sacrificial mandrels having sidewalls, exposing the sidewall on one side of the one or more sacrificial mandrels to an ion beam to make the exposed sidewall more susceptible to oxidation, oxidizing the opposite sidewalls of the one or more sacrificial mandrels to form a plurality of oxide pillars, removing the one or more sacrificial mandrels, forming spacers on opposite sides of each of the plurality of oxide pillars to produce a spacer pattern, removing the plurality of oxide pillars, and transferring the spacer pattern to the substrate to produce a plurality of fins. | 2017-09-28 |
20170278871 | ARRAY SUBSTRATE ASSEMBLY AND TFT DISPLAY APPARATUS COMPRISING THE SAME - Embodiments of the present invention provide an array substrate assembly and a display apparatus including the array substrate assembly. The array substrate assembly includes a display region and a non-display region around the display region. A static electricity leading layer electrically insulated from the display region is disposed in the non-display region. | 2017-09-28 |
20170278872 | SEMICONDUCTOR DEVICE, DISPLAY DEVICE, AND METHOD FOR MANUFACTURING THE SAME - Provided is a semiconductor device including: a first transistor over a substrate, the first transistor having a gate electrode, an oxide semiconductor film, and a gate insulating film between the gate electrode and the oxide semiconductor film; an insulating film over the first transistor, the insulating film having a first film and a second film over the first film; and a terminal electrically connected to the oxide semiconductor film through an opening portion in the insulating film. The insulating film has a first region in contact with the terminal, and the first region has an oxygen composition larger than that in another region of the insulating film. | 2017-09-28 |
20170278873 | THIN FILM TRANSISTOR, THIN FILM TRANSISTOR PANEL, AND METHOD FOR MANUFACTURING THE SAME - A thin film transistor includes a gate electrode, a semiconductor layer, a source electrode, and a drain electrode. The semiconductor layer overlaps the gate electrode and includes a channel layer comprising an oxide semiconductor and an auxiliary layer comprising amorphous silicon. The source electrode and the drain electrode are separated from each other and connected to the semiconductor layer. A thin film transistor array panel and method of manufacturing same also is disclosed. | 2017-09-28 |
20170278874 | SEMICONDUCTOR DEVICE AND DISPLAY DEVICE INCLUDING THE SAME - To improve field-effect mobility and reliability in a transistor including an oxide semiconductor film. A semiconductor device includes a transistor including an oxide semiconductor film. The transistor includes a region where the maximum value of field-effect mobility of the transistor at a gate voltage of higher than 0 V and lower than or equal to 10 V is larger than or equal to 40 and smaller than 150; a region where the threshold voltage is higher than or equal to minus 1 V and lower than or equal to 1 V; and a region where the S value is smaller than 0.3 V/decade. | 2017-09-28 |
20170278875 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A more convenient and highly reliable semiconductor device which has a transistor including an oxide semiconductor with higher impact resistance used for a variety of applications is provided. A semiconductor device has a bottom-gate transistor including a gate electrode layer, a gate insulating layer, and an oxide semiconductor layer over a substrate, an insulating layer over the transistor, and a conductive layer over the insulating layer. The insulating layer covers the oxide semiconductor layer and is in contact with the gate insulating layer. In a channel width direction of the oxide semiconductor layer, end portions of the gate insulating layer and the insulating layer are aligned with each other over the gate electrode layer, and the conductive layer covers a channel formation region of the oxide semiconductor layer and the end portions of the gate insulating layer and the insulating layer and is in contact with the gate electrode layer. | 2017-09-28 |
20170278876 | SEMICONDUCTOR DEVICE, ELECTRONIC COMPONENT, AND ELECTRONIC DEVICE - To provide a semiconductor device including a small-area circuit with high withstand voltage, an oxide semiconductor (OS) transistor is used as some of transistors included in a circuit handling an analog signal in a circuit to which high voltage is applied. The use of an OS transistor with high withstand voltage as a transistor requiring resistance to high voltage enables the circuit area to be reduced without lowering the performance, as compared to the case using a Si transistor. Furthermore, an OS transistor can be provided over a Si transistor, so that transistors using different semiconductor layers can be stacked, resulting in a much smaller circuit area. | 2017-09-28 |
20170278877 | THIN FILM TRANSISTOR SUBSTRATE INCLUDING THIN FILM TRANSISTOR FORMED OF OXIDE SEMICONDUCTOR AND METHOD FOR MANUFACTURING THE SAME - A thin film transistor (TFT) located on a thin film transistor substrate includes a first insulating film formed so as to cover a gate electrode, a channel layer that is formed at a position on the first insulating film overlapping the gate electrode and formed of an oxide semiconductor, a second insulating film formed on the channel layer, and a third insulating film formed so as to cover the second insulating film. A source electrode and a drain electrode are formed on the third insulating film. Each of the source electrode and the drain electrode is connected to the channel layer through the corresponding one of contact holes penetrating the second insulating film and the third insulating film. | 2017-09-28 |
20170278878 | SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, AND SEPARATION APPARATUS - A technique is described in which a transistor formed using an oxide semiconductor film, a transistor formed using a polysilicon film, a transistor formed using an amorphous silicon film or the like, a transistor formed using an organic semiconductor film, a light-emitting element, or a passive element is separated from a glass substrate by light or heat. An oxide layer is formed over a light-transmitting substrate, a metal layer is selectively formed over the oxide layer, a resin layer is formed over the metal layer, an element layer is formed over the resin layer, a flexible film is fixed to the element layer, the resin layer and the metal layer are irradiated with light through the light-transmitting substrate, the light-transmitting substrate is separated, and a bottom surface of the metal layer is made bare. | 2017-09-28 |
20170278879 | METHOD FOR MANUFACTURING METAL LAMINATION FILM, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING LIQUID CRYSTAL DISPLAY DEVICE - The present invention includes: a multilayer film forming step of forming a multilayer film constituted by a plurality of metal films layered together; after the multilayer film forming step, a resist forming step of forming a resist film having patterned openings on the multilayer film; after the resist forming step, a dry etching step of dry etching the multilayer film to remove at least one metal film located at the top of the multilayer film and exposed by the openings; after the dry etching step, a wet etching step of wet etching the multilayer film to remove at least the metal films exposed by the openings. | 2017-09-28 |
20170278880 | Measuring Harvested Energy Using an Ultra-Low Duty Cycle Measurement System - A method for measuring energy harvested from at least one energy source for use in an access control system, comprising providing an access control device adapted to be at least partially powered by energy harvested from at least one energy source; providing at least one sensor receiving energy from the at least one energy source; providing an energy harvesting manager coupled to the at least one sensor, wherein the energy harvesting manager manages the amount of energy received by the at least one sensor; providing a capacitive storage device coupled to the energy harvesting manager, the capacitive storage device for storing energy harvested from the at least one sensor; charging the capacitive storage device to a voltage high threshold, V-HTH; applying a reference load to the capacitive storage device until the capacitive storage device discharges to a predetermined voltage value, Vo/e, the reference load having a predetermined resistance value; determining a time constant, the time constant defined as the length of time required for the capacitive storage device to discharge to the predetermined voltage value, Vo/e; and determining an exact or near exact capacitance of the capacitive storage device by comparing the time constant to the reference load predetermined value, by the expression: C=RC/RL, where C=capacitance (in farads), RC=time constant (in seconds), and RL=reference load resistance (in ohms). | 2017-09-28 |
20170278881 | BSI Image Sensor and Method of Forming Same - A backside illumination (BSI) image sensor and a method of forming the same are provided. A method includes forming a plurality of photosensitive pixels in a substrate, the substrate having a first surface and a second surface, the second surface being opposite the first surface, the substrate having one or more active devices on the first surface. A first portion of the second surface is protected. A second portion of the second surface is patterned to form recesses in the substrate. An anti-reflective layer is formed on sidewalls of the recesses. A metal grid is formed over the second portion of the second surface, the anti-reflective layer being interposed between the substrate and the metal grid. | 2017-09-28 |
20170278882 | IMAGE SENSOR AND METHOD FOR FABRICATING THE SAME - A method for fabricating an image sensor in accordance with an embodiment of the inventive concepts may include forming first and second photodiodes within a substrate, forming first and second gate electrodes over the substrate, the first gate electrode vertically partially overlapping the first photodiode and the second gate electrode vertically partially overlapping the second photodiode, forming an impurity injection region comprising first and second type impurities between the first and the second gate electrodes, and performing an annealing process to form a floating diffusion region comprising the first type impurities and a channel region comprising the second type impurities. The channel region surrounds lateral surfaces and a bottom surface of the floating diffusion region. | 2017-09-28 |
20170278883 | TRANSISTOR AND IMAGE SENSOR HAVING THE SAME - An image sensor includes: a light receiving section suitable for generating photocharges in response to incident light; and a driving section including a source follower transistor suitable for generating an output voltage corresponding to a reference voltage in response to the photocharges. The source follower transistor includes: a stack structure formed by sequentially stacking a first conductive layer, an insulating layer and a second conductive layer; an open portion to formed through the second conductive layer and the insulating layer so as to expose the first conductive layer; a channel layer formed along the surface of the open portion so as to be connected to the first conductive layer and the second conductive layer; and a gate is connected to the light receiving section and which is formed over the channel layer so as to overlap the second conductive layer. | 2017-09-28 |
20170278884 | IMAGE SENSOR AND METHOD FOR FABRICATING THE SAME - This technology relates to an image sensor. The image sensor may include a substrate including a photoelectric conversion element; a pillar formed over the photoelectric conversion element and having a concave-convex sidewall; a channel film formed along a surface of the pillar and for having at least one end coupled to the photoelectric conversion element; and a transfer gate formed over the channel film. | 2017-09-28 |
20170278885 | IMAGE SENSING DEVICE WITH CAP AND RELATED METHODS - An image sensing device includes an interconnect layer and a number of grid array contacts arranged on a bottom side of the interconnect layer. An image sensor integrated circuit (IC) is carried by the interconnect layer and has an image sensing surface. A number of electrical connections are coupled between the image sensor IC and an upper side of the interconnect layer. A transparent plate overlies the image sensing surface of the image sensor IC. A cap is carried by the interconnect layer and has an opening overlying transparent plate and the image sensing surface. The cap has an upper wall spaced above the interconnect layer and the image sensor IC to define an internal cavity and the cap defines an air vent coupled to the internal cavity. | 2017-09-28 |
20170278886 | OPTICAL DEVICE AND PRODUCTION METHOD FOR OPTICAL DEVICE | 2017-09-28 |
20170278887 | IMAGE SENSOR WITH INNER LIGHT-CONDENSING SCHEME - An image sensor may include: a photoelectric conversion layer suitable for converting light into an electrical signal; a spacer layer formed over the photoelectric conversion layer, and suitable for preventing light reflection while adjusting a focus; and a first condensing layer formed at the inner bottom of the spacer layer, and suitable for condensing incident light. | 2017-09-28 |
20170278888 | IMAGE SENSOR WITH INNER LIGHT-CONDENSING SCHEME - An image sensor may include: a photoelectric conversion layer; an anti-reflection layer formed over the photoelectric conversion layer so as to minimize reflectance of light; a guide layer formed over the anti-reflection layer, and suitable for guiding the light to the photoelectric conversion layer; and a first condensing layer buried at the inner top of the guide layer, and suitable for condensing incident light. | 2017-09-28 |
20170278889 | SOLID-STATE IMAGING DEVICE, METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC APPARATUS - The present disclosure relates to a solid-state imaging device that enables diffusion of components in the interfaces between microlenses and an antireflection film, a method of manufacturing the solid-state imaging device, and an electronic apparatus. Moisture permeation holes are formed between the microlenses of adjacent pixels. The moisture permeation holes are covered with an antireflection film. The antireflection film is formed on the surfaces of the microlenses excluding the diffusion holes. The refractive index of the antireflection film is higher than the refractive index of the microlenses. The present disclosure can be applied to complementary metal oxide semiconductor (CMOS) image sensors that are back-illuminated solid-state imaging devices, for example. | 2017-09-28 |
20170278890 | BACKSIDE ILLUMINATION IMAGE SENSOR AND IMAGE-CAPTURING DEVICE - A backside illumination image sensor that includes a semiconductor substrate with a plurality of photoelectric conversion elements and a read circuit formed on a front surface side of the semiconductor substrate, and captures an image by outputting, via the read circuit, electrical signals generated as incident light having reached a back surface side of the semiconductor substrate is received at the photoelectric conversion elements includes: a light shielding film formed on a side where incident light enters the photoelectric conversion elements, with an opening formed therein in correspondence to each photoelectric conversion element; and an on-chip lens formed at a position set apart from the light shielding film by a predetermined distance in correspondence to each photoelectric conversion element. The light shielding film and an exit pupil plane of the image forming optical system achieve a conjugate relation to each other with regard to the on-chip lens. | 2017-09-28 |
20170278891 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCTION OF SEMICONDUCTOR DEVICE - A semiconductor device with a connection pad in a substrate, the connection pad having an exposed surface made of a metallic material that diffuses less readily into a dielectric layer than does a metal of a wiring layer connected thereto. | 2017-09-28 |
20170278892 | INSULATING WALL AND METHOD OF MANUFACTURING THE SAME - A pixel includes a semiconductor layer with a charge accumulation layer extending in the semiconductor layer. A transistor has a read region penetrating into said semiconductor layer down to a first depth. An insulating wall penetrates into the semiconductor layer from an upper surface and containing an insulated conductor connected to a node of application of a potential. The insulating wall includes at least a portion provided with a deep insulating plug penetrating into the insulated conductor down to a second depth greater than the first depth. A continuous portion of the insulating wall laterally delimits, at least partially, a charge accumulation area and includes a wall portion with the deep insulating plug at least partially laterally delimiting the read region of the transistor. | 2017-09-28 |
20170278893 | Deep Trench Isolation Structure and Method of Forming Same - Deep trench isolation (DTI) structures and methods of forming the same are provided. A method includes forming a plurality of photosensitive regions in a substrate. A recess is formed in the substrate, the substrate comprising a first semiconductor material, the recess being interposed between adjacent photosensitive regions. The recess is enlarged by removing a damaged layer of the substrate along sidewalls of the recess, thereby forming an enlarged recess. An epitaxial region is formed on sidewalls and a bottom of the enlarged recess, at least a portion of the epitaxial region comprising a second semiconductor material, the second semiconductor material being different from the first semiconductor material. A dielectric region is formed on the epitaxial region, the epitaxial region extending along a sidewall of the dielectric region. | 2017-09-28 |
20170278894 | IMAGE DISPLAY DEVICE - It is an object of the present invention to provide an image display device in which it is possible to adjust the spectrum of light emitted by pixels and adjust the chromaticity of the light emitted by the pixels. Provided is an image display device having a pixel region in which each pixel comprises a plurality of subpixels and the pixels are arranged in a matrix, wherein each of the subpixels includes a plurality of light-emitting layers overlapping each other with an electrode sandwiched therebetween, and the plurality of light-emitting layers each contain a quantum dot material and have different peak emission wavelengths from each other. | 2017-09-28 |
20170278895 | MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A plurality of first conductive patterns is disposed on a substrate. Each of the plurality of first conductive patterns extends in a first direction. A first selection pattern is disposed on each of the plurality of first conductive patterns. A first barrier portion surrounds the first selection pattern. A first electrode and a first variable resistance pattern are disposed on the first selection pattern. A plurality of second conductive patterns is disposed on the first variable resistance pattern. Each of the plurality of second conductive patterns extends in a second direction crossing the first direction, | 2017-09-28 |
20170278896 | IMAGE SENSORS AND ELECTRONIC DEVICES INCLUDING THE SAME - Image sensors, and electronic devices including the image sensors, include a first photoelectronic device including at least one of a blue photoelectronic device sensing light in a blue wavelength region, a red photoelectronic device sensing light in a red wavelength region, and a green photoelectronic device sensing light in a green wavelength region, and a second photoelectronic device stacked on one side of the first photoelectronic device without being interposed by a color filter, wherein the second photoelectronic device senses light in an infrared region. | 2017-09-28 |
20170278897 | PACKAGE SUBSTRATE AND MANUFACTURING METHOD THEREOF, AND OLED DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF - A package substrate and a manufacturing method thereof, and an OLED display device and a manufacturing method thereof are provided. The package substrate comprises a base substrate ( | 2017-09-28 |
20170278898 | ORGANIC LIGHT EMITTING DISPLAY DEVICE - An organic light emitting diode (OLED) display device includes a substrate, reflection structure, and a sub-pixel structure. The substrate includes a plurality of sub-pixel regions and a reflection region surrounding the sub-pixel regions. The reflection structure is disposed on the substrate in the reflection region and has a plurality of openings exposing the sub-pixel regions. The reflection structure includes first reflection patterns, second reflection patterns, and connection patterns. The first reflection patterns extend in a first direction parallel to an upper surface of the substrate, and are spaced apart from each other in a second direction perpendicular to the first direction. The second reflection patterns are spaced apart from each other in the first direction between two adjacent first reflection patterns. The connection patterns electrically connect two adjacent second reflection patterns in the second direction. The sub-pixel structure is disposed on the substrate in the sub-pixel region. | 2017-09-28 |
20170278899 | FLEXIBLE DISPLAY DEVICE - A flexible display device includes a protection member, a first adhesion member, a display member, a second adhesion member, and a window member. A thickness of the display member is less than a sum of thicknesses of the protection member and the window member. The display member includes a display panel layer, a touch sensing layer, and a reflection prevention layer integrated with each other to reduce a thickness of the flexible display device. The reduction in thickness enables the flexible display device to be bent with a relatively small radius of curvature, as well as to be repeatedly bent (or otherwise flexed) with reduced potential for delamination of the first and second adhesion members. | 2017-09-28 |
20170278900 | FLEXIBLE DISPLAY DEVICE - A flexible display device includes a display panel layer, a touch sensing layer, a reflection prevention layer, and a window layer. The touch sensing layer is disposed directly on a first display panel surface, a second display panel surface facing the first display panel surface in a thickness direction, or a second base surface of the reflection prevention layer. The reflection prevention layer is disposed directly on the second display panel surface or a first base surface of the touch sensing layer. The window layer is disposed directly on the first base surface or the second base surface. | 2017-09-28 |
20170278901 | DISPLAY APPARATUS WITH BENDING AREA CAPABLE OF MINIMIZING MANUFACTURING DEFECTS - A display apparatus includes a substrate, an inorganic insulating layer, a first conductive layer, and an organic material layer. The substrate includes a first area, a second area, and a bending area located between the first area and the second area the bending area configured to be bent about a first bending axis extending in a first direction. The inorganic insulating layer is arranged over the substrate. The first conductive layer extends from the first area to the second area passing over the bending area, and is arranged over the inorganic insulating layer. The organic material layer is arranged between the inorganic insulating layer and the first conductive layer and includes a central portion overlapping the bending area and a peripheral portion extending from the central portion. An average thickness of the central portion is greater than an average thickness of the peripheral portion. | 2017-09-28 |
20170278902 | ANTI-REFLECTIVE OPTICAL FILM AND BENDABLE DISPLAY APPARATUS INCLUDING THE OPTICAL FILM - A display apparatus includes a display panel configured to display an image. The display panel has a folding axis extending in a first direction. An optical film is disposed over the display panel. The optical film includes a circular polarizer including at least two phase retarders and one polarizer. Slow axes of each of the at least two phase retarders are located in the same quadrant of four quadrants of the optical film. | 2017-09-28 |
20170278903 | DISPLAY SUBSTRATE, DISPLAY PANEL AND DISPLAY APPARATUS - A display substrate, a display panel and a display apparatus are provided. The display substrate includes a plurality of sub pixel units, the plurality of sub pixel units is arranged in an array, each row or each column of sub pixels includes a first sub pixel and a second sub pixel, a line segment formed by the row of sub pixels has a midpoint in a row direction or a line segment formed by the column of sub pixels has a midpoint in a column direction, the first sub pixel and the second sub pixel are configured for displaying a same color, a distance from the first sub pixel to the midpoint is less than a distance from the second sub pixel to the midpoint and an aperture area of the first sub pixel is greater than that of the second sub pixel. | 2017-09-28 |
20170278904 | DISPLAY APPARATUS - A display apparatus includes a substrate including a display region and a non-display region, a blue sub-pixel in the display region of the substrate, an imaginary line extending across the blue sub-pixel, a first sub-unit on a first side of the imaginary line, the first sub-unit including a red sub-pixel, a green sub-pixel, and a white sub-pixel, and a second sub-unit on a second side of the imaginary line, the second sub-unit including a red sub-pixel, a green sub-pixel, and a white sub-pixel, wherein the first sub-unit and the blue sub-pixel constitute a first pixel, and the second sub-unit and the blue sub-pixel constitute a second pixel, and wherein the blue sub-pixel emits light according to a data signal generated based on blue-related data of first pixel data corresponding to the first pixel and blue-related data of second pixel data corresponding to the second pixel. | 2017-09-28 |
20170278905 | DISPLAY DEVICE - A display device is disclosed, which includes: a pixel group including a first pixel having a red sub-pixel and a blue sub-pixel; a second pixel having a green sub-pixel and a blue sub-pixel; a third pixel having a green sub-pixel and a blue sub-pixel; and a fourth pixel having a red sub-pixel and a blue sub-pixel. The first pixel is adjacent to the second pixel in a row direction. The first pixel is adjacent to the second pixel in a column direction. The fourth pixel is diagonal to the first pixel, and the fourth pixel is adjacent to the second pixel and the third pixel. In the pixel group, the blue sub-pixels are quantitatively more than the red sub-pixels, and the blue sub-pixels are quantitatively more than the green sub-pixels. | 2017-09-28 |
20170278906 | ORGANIC LIGHT-EMITTING DISPLAY APPARATUS - An organic light-emitting display apparatus includes a substrate including a display area and a non-display area, a reference sub-pixel arranged on the display area to realize a first color, and a first sub-pixel arranged on the display area to realize the first color, the first sub-pixel being adjacent to the non-display area and having a shape different from a shape of the reference sub-pixel. | 2017-09-28 |
20170278907 | ORGANIC EL DISPLAY DEVICE - A display device preventing light leak to an adjacent pixel and thus to prevent color mixing to improve image quality is provided. An organic EL display device includes a plurality of pixels. The plurality of pixels each include a light emitting element; the light emitting element includes a pixel electrode, a common electrode, an EL common layer, and a light emitting layer; the EL common layer and the light emitting layer are provided between the pixel electrode and the common electrode; the EL common layer covers a main surface and an end of the pixel electrode; the pixel electrode is provided on an insulating layer; and the common electrode is in contact with the insulating layer between the plurality of pixels. | 2017-09-28 |
20170278908 | PIXEL ELEMENT STRUCTURE, ARRAY STRUCTURE AND DISPLAY DEVICE - A pixel element structure is disclosed. The pixel element structure includes first, second, and third sub-pixel elements, each including a light-emitting region. At least one of the first, second, and third sub-pixel elements includes a light-transmitting region, where the light-emitting region includes an organic light-emitting diode light-emitting structure, and where the organic light-emitting diode light-emitting structure includes a first substrate, and a nontransparent anode, a pixel defining layer, an organic layer and a cathode, sequentially arranged above the first substrate. | 2017-09-28 |
20170278909 | DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME - A display apparatus includes a first pixel, a second pixel, a light sensor, and a light shield. The first pixel has a first light-emitting device which includes a first emission layer that emits light in a first wavelength band in a first direction. The second pixel has a second light-emitting device which includes a second emission layer to emit light in a second wavelength band in a second direction different from the first direction. The second emission layer is below the first emission layer of the first light-emitting device. The light sensor senses light in the second wavelength band emitted from the second pixel and reflected by an object. The light shield is arranged along a light path incident to the light sensor. | 2017-09-28 |
20170278910 | ORGANIC LIGHT EMITTING DISPLAY DEVICE INCLUDING A TANDEM STRUCTURE AND METHOD OF MANUFACTURING THE ORGANIC LIGHT EMITTING DISPLAY DEVICE INCLUDING THE TANDEM STRUCTURE - An organic light emitting display (OLED) device includes a substrate including a light emitting region and a peripheral region. An auxiliary power supply wire is disposed in the peripheral region. A lower electrode is disposed in the light emitting region. A pixel defining layer, disposed on the substrate, exposes a portion of the lower electrode and a portion of the auxiliary power supply wire. A first common layer, disposed on the pixel defining layer and the lower electrode, exposes the auxiliary power supply wire. A light emitting structure is disposed on the first common layer. The light emitting structure exposes the auxiliary power supply wire. A second common layer is disposed on the light emitting structure, the second common layer covering the light emitting structure and exposing the auxiliary power supply wire. An upper electrode is disposed on the second common layer and contacts the auxiliary power supply wire. | 2017-09-28 |
20170278911 | DISPLAY DEVICE - A display device includes a pixel electrode, a pixel isolation insulating film in which an opening through which the pixel electrode is exposed at a bottom is formed, and a light-emitting layer formed inside the opening. The pixel isolation insulating film contains particles that receive light emitted from the light-emitting layer and propagate light in a direction different from that of the light emitted from the light-emitting layer. | 2017-09-28 |
20170278912 | ORGANIC LIGHT-EMITTING DISPLAY APPARATUS HAVING PROTECTED EMISSION LAYER - An organic light-emitting display apparatus prevents the quality of an image being displayed thereon from being deteriorated as a result of contamination of an organic emission layer. The display apparatus includes a substrate with a display area and a periphery area. A first insulating layer, disposed over the substrate, has a first opening in the periphery area. A first electrode is disposed within the display area, over the first insulating layer. A first bank is disposed over the first insulating layer and has a second opening through which a center of the first electrode is exposed. A second bank is disposed over the first insulating layer and is separated from the first bank. The first opening is disposed between the first bank and the second bank. An intermediate layer is disposed over the first electrode. A second electrode is disposed over the intermediate layer and the first bank. | 2017-09-28 |
20170278913 | ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF AND ORGANIC LIGHT-EMITTING DISPLAY APPARATUS - The present disclosure provides an array substrate and a manufacturing method thereof and an organic light-emitting display apparatus. The array substrate comprises a plurality of sub-pixel zones, each of which comprising a light-emitting unit provided above a base substrate, wherein the light-emitting unit is formed to comprise a concave or convex structure, so that the light-emitting area of the light-emitting unit is greater than the projected area of the light-emitting unit onto the base substrate. Compared to the prior art, the present disclosure can increase the amount of light emission in each sub-pixel zone, so that the view angle of the display may be increased and the display effect may be improved. | 2017-09-28 |
20170278914 | PIXEL DEFINITION LAYER AND OLED DEVICE - A pixel definition layer and an OLED device are provided. The pixel definition layer includes a plurality of openings, the openings each being provided with bottom surface opening, a top surface opening and a side wall. The openings at least include a first opening defining a first pixel unit and a second opening defining a second pixel unit. The first opening is filled with a first pixel luminescent material, and the second opening is filled with a second pixel luminescent material. A decay rate of the first pixel luminescent material is lower than that of the second pixel luminescent material. The area of the bottom surface opening of the first opening is smaller than that of the bottom surface opening of the second opening. The side wall of the opening is provided with a pre-set reference surface. The pixel definition layer can be used for preparing an OLED device. | 2017-09-28 |
20170278915 | ORGANIC LIGHT EMITTING DISPLAY DEVICE - An organic light emitting display device is disclosed. The organic light emitting display device includes a first sub-pixel that includes a first emission region which makes a first color, a second sub-pixel that is disposed adjacent to the first sub-pixel, and includes a second emission region which makes a second color, a third sub-pixel that is disposed adjacent to the first sub-pixel, and includes a third emission region which makes a third color, and a fourth sub-pixel that is disposed adjacent to the second sub-pixel and the third sub-pixel, and includes a fourth emission region which makes a fourth color. At least one of the first to fourth sub-pixels includes a transmission region which cannot emit light and through which external light is transmitted. The transmission region is surrounded by at least one of the first to fourth emission regions. | 2017-09-28 |
20170278916 | DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A plurality of thin film transistors provided in a peripheral region are first staggered thin film transistors where a first channel layer configured of low-temperature polysilicon is included, and the first channel layer is not interposed between a first source electrode and a first gate electrode, and between a first drain electrode and the first gate electrode. A plurality of thin film transistors provided in a display region are second staggered thin film transistors where a second channel layer configured of an oxide semiconductor is included, and the second channel layer is not interposed between a second source electrode and a second gate electrode, and between a second drain electrode and the second gate electrode. The first thin film transistor is located below the second thin film transistor. | 2017-09-28 |
20170278917 | ORGANIC LIGHT-EMITTING DISPLAY DEVICE - A display device includes a switching transistor, a driving transistor, a storage capacitor connected to the switching and driving transistors, and an organic light-emitting diode connected to the driving transistor. The driving transistor is connected to the switching transistor. The driving transistor includes a semiconductor layer having a channel region, first doped regions at sides of the channel region, and second doped regions doped with impurities of a concentration greater than the first doped regions. A first electrode layer is over an insulating layer, which covers the semiconductor layer. The electrode layer includes convex portions extending toward the first doped regions and covering an end of the channel region. At least one of the convex portions has a width greater than or equal to a width of the end of the channel region. | 2017-09-28 |
20170278918 | DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - A display device includes a substrate including a bending area, a display area. A plurality of first wires is disposed above the substrate. A second wire is disposed above the plurality of first wires. A third wire is disposed above the second wire. At least a portion of the second wire and at least a portion of the third wire are disposed in the bending area. | 2017-09-28 |
20170278919 | DISPLAY DEVICE, METHOD OF MANUFACTURING THE DISPLAY DEVICE, AND ELECTRONIC APPARATUS - A display device includes a base, an organic light-emitting element including a stacked structure that has a first electrode layer, an organic light-emitting layer, and a second electrode layer that are stacked in order on the base, a drive element that is provided on the base, and drives the organic light-emitting element, and an auxiliary electrode layer provided on the base, and including an end surface that is in contact with the second electrode layer. | 2017-09-28 |
20170278920 | DISPLAY APPARATUS - A display apparatus includes a substrate; a plurality of display units on the substrate, each including a thin film transistor including at least one inorganic layer, a passivation layer on the thin film transistor, and a display device electrically connected to the thin film transistor; and a plurality of encapsulation layers respectively encapsulating the plurality of display units. The substrate includes a plurality of islands spaced apart, a plurality of connection units connecting the plurality of islands, and a plurality of through holes penetrating through the substrate between the plurality of connection units. The plurality of display units are on the plurality of islands, respectively. The at least one inorganic layer and the passivation layer extend on the plurality of connection units. The passivation layer includes a trench exposing the at least one inorganic layer. The encapsulation layer contacts the at least one inorganic layer exposed via the trench. | 2017-09-28 |
20170278921 | Etching Process Control in Forming MIM Capacitor - A method includes forming a capacitor, which includes depositing a bottom electrode layer, depositing a capacitor insulator layer over the bottom electrode layer, depositing a top electrode layer over the capacitor insulator layer, and depositing a dielectric layer over the top electrode layer. The dielectric layer is etched using a process gas until the top electrode layer is exposed. In the etching of the dielectric layer, the dielectric layer has a first etching rate, and the top electrode layer has a second etching rate, and a ratio of the first etching rate to the second etching rate is higher than about 5.0. | 2017-09-28 |
20170278922 | HIGH VOLTAGE SEMICONDUCTOR DEVICE - A high voltage semiconductor device includes a gate electrode structure disposed on a substrate, a source region disposed in the substrate to be adjacent to one side of the gate electrode structure, a first drift region disposed in the substrate to be adjacent to another side of the gate electrode structure, a drain region electrically connected with the first drift region, and a device isolation region disposed on one side of the drain region. Particularly, the first drift region is spaced apart from the device isolation region. | 2017-09-28 |
20170278923 | SCHOTTKY BARRIER DIODE AND MANUFACTURING METHOD THEREOF - A technique stabilizing properties of SBDs is provided. An SBD is provided with a p-type contact region in contact with an anode electrode, and an n-type drift region in Schottky contact with the anode electrode. The p-type contact region includes a first p-type region having a corner portion, a second p-type region connected to the corner portion, and an edge filling portion located at a connection between the first p-type region and the second p-type region. First and second extended lines intersect at an acute angle, where the first extended line is a line extended from a contour of the first p-type region toward the connection and the second extended line is a line extended from a contour of the second p-type region toward the connection. An acute angle edge formed between the first extended line and the second extended line is filled with the edge filling portion. | 2017-09-28 |
20170278924 | SUPER-JUNCTION SEMICONDUCTOR POWER DEVICES WITH FAST SWITCHING CAPABILITY - A super junction (SJ) device may include one or more charge balance (CB) layers. Each CB layer may include an epitaxial (epi) layer having a first conductivity type and a plurality of charge balance (CB) regions having a second conductivity type. Additionally, the SJ device may include a connection region having the second conductivity type that extends from a region disposed in a top surface of a device layer of the SJ device to one or more of the CB regions. The connection region may enable carriers to flow directly from the region to the one or more CB regions, which may decrease switching losses of the SJ device. | 2017-09-28 |
20170278925 | INTRODUCING MATERIAL WITH A LOWER ETCH RATE TO FORM A T-SHAPED SDB STI STRUCTURE - A method of introducing SDB material with a lower etch rate during a formation of a t-shape SDB STI structure are provided. Embodiments include providing an STI region in a Si substrate; forming a hardmask over the STI region and the Si substrate; forming a cavity through the hardmask over the STI region, the cavity having a width greater than a width of the STI region; depositing a SDB material in the cavity with an etch rate lower than HDP oxide to form a t-shaped SDB STI structure; and removing the hardmask. | 2017-09-28 |
20170278926 | SHALLOW TRENCH ISOLATION TRENCHES AND METHODS FOR NAND MEMORY - A NAND memory is provided that includes a memory cell region and a peripheral region. The peripheral region includes a shallow trench isolation trench disposed in a substrate. The shallow trench isolation trench has a first tab extension and a second tab extension. The first tab extension is disposed at a top portion of the shallow trench isolation trench, and extends in a first direction from the shallow trench isolation trench. The second tab extension is disposed at a top portion of the shallow trench isolation trench, and extends in a second direction from the shallow trench isolation trench. | 2017-09-28 |
20170278927 | HIGH DENSITY MEMORY CELL STRUCTURES - The present disclosure relates to semiconductor structures and, more particularly, to vertical memory cell structures and methods of manufacture. The vertical memory cell includes a vertical nanowire capacitor and vertical pass gate transistor. The vertical nanowire capacitor composes of: a plurality of vertical nanowires extending from an insulator layer; a dielectric material on vertical sidewalls of the plurality of vertical nanowires; doped material provided between the plurality of vertical nanowire; the pass gate transistor composes of: high-k dielectric on top part of the nanowire, metal layer surrounding high-k material as all-around gate. And there is dielectric layer in between vertical nanowire capacitor and vertical nanowire transistor as insulator. At least one bitline extending on a top of the plurality of vertical nanowires and in electrical contact therewith; and at least one wordline formed on vertical sidewalls of the plurality of vertical nanowires and separated therefrom by the dielectric material. | 2017-09-28 |
20170278928 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - The present invention provides a semiconductor device, including a substrate, a first semiconductor layer, a plurality of first sub recess, a plurality of insulation structures and a first top semiconductor layer. The substrate has a first region disposed within an STI. The first semiconductor layer is disposed in the first region. The first sub recesses are disposed in the first semiconductor layer. The insulation structures are disposed on the first semiconductor layer. The first top semiconductor layer forms a plurality of fin structures, which are embedded in the first sub recesses, arranged alternatively with the insulation structures and protruding over the insulation structures. | 2017-09-28 |
20170278929 | SEMICONDUCTOR DEVICE - A semiconductor layer of a first conductivity type has a plurality of impurity concentration peaks that are differently positioned in a first direction extending from a first surface to a second surface, and an integrated concentration obtained by integrating an impurity concentration value in the first direction from (i) the first surface that is a junction interface between the semiconductor layer of the first conductivity type and the semiconductor layer of the second conductivity type to (ii) a boundary between a first impurity concentration peak of the plurality of impurity concentration peaks that is the closest to the first surface and a second impurity concentration peak of the plurality of impurity concentration peaks that is the second closest to the first surface is equal to or lower than a critical integrated concentration. | 2017-09-28 |
20170278930 | Semiconductor Device Having a Graphene Layer, and Method of Manufacturing Thereof - A method for manufacturing a semiconductor device includes: providing a carrier wafer and a silicon carbide wafer; bonding a first side of the silicon carbide wafer to the carrier wafer; splitting the silicon carbide wafer bonded to the carrier wafer into a silicon carbide layer thinner than the silicon carbide wafer and a residual silicon carbide wafer, the silicon carbide layer remaining bonded to the carrier wafer during the splitting; and forming a graphene material on the silicon carbide layer. | 2017-09-28 |
20170278931 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes assigning a plurality of chip regions on an epitaxial-growth layer of a semiconductor substrate where the epitaxial-growth layer is grown on a bulk layer and forming a plurality of device structures on the plurality of chip regions, respectively, thinning the semiconductor substrate from a bottom-surface side of the bulk layer, bonding a supporting-substrate on a bottom surface of the thinned semiconductor substrate, selectively removing the supporting-substrate so that the bottom surface of the semiconductor substrate is exposed, at locations corresponding to positions of each of main current paths in the plurality of device structures, respectively, dicing the semiconductor substrate together with the supporting-substrate along dicing lanes between the plurality of the chip regions so as to form a plurality of chips. | 2017-09-28 |
20170278932 | PLATFORM OF LARGE METAL NITRIDE ISLANDS WITH LATERAL ORIENTATIONS AND LOW-DEFECT DENSITY - The present invention provides a metal nitride platform for semiconductor devices, including, a pre-defined array of catalyst sites, disposed on a substrate. Metal nitride islands with lateral to vertical size ratios of at least greater than one (1) are disposed on the array of catalyst sites, where the surfaces of the metal nitride islands are with reduced dislocation densities and side walls with bending of dislocations. The platform of metal nitride islands is further used to build electrically and optically-active devices. The present invention also provides a process for the preparation of a metal nitride platform, selectively, on the array of catalyst sites, in the presence of a reactive gas and precursors and under preferred reaction conditions, to grow metal nitride islands with lateral to vertical size ratios of at least greater than one (1). | 2017-09-28 |
20170278933 | SEMICONDUCTOR ELEMENT AND CRYSTALLINE LAMINATE STRUCTURE - A semiconductor element includes a high-resistivity substrate that includes a β-Ga | 2017-09-28 |
20170278934 | SEMICONDUCTOR DEVICE - A semiconductor device according to an embodiment includes: a substrate having a first plane and a second plane provided on the opposite side of the first plane; a first nitride semiconductor layer provided on the first plane; source electrodes provided on the first nitride semiconductor layer; drain electrodes provided on the first nitride semiconductor layer, each of the drain electrodes provided between the source electrodes; gate electrodes provided on the first nitride semiconductor layer, each of the gate electrodes provided between each of the source electrodes and each of the drain electrodes; a first wire provided on the second plane and electrically connected to the source electrodes; a second wire electrically connected to the drain electrodes; a third wire provided on the second plane and electrically connected to the gate electrodes; and an insulating interlayer provided between the first nitride semiconductor layer and the second wire. | 2017-09-28 |
20170278935 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - A technique of manufacturing a semiconductor device of stable operation is provided. There is provided a method of manufacturing a semiconductor device comprising a first process of forming an insulating film from a nitrogen-containing organic metal used as raw material, on a semiconductor layer by atomic layer deposition; a second process of processing the insulating film by oxygen plasma treatment in an atmosphere including at least one of oxygen and ozone; and a third process of processing the insulating film by heat treatment in a nitrogen-containing atmosphere, after the second process. | 2017-09-28 |
20170278936 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - A semiconductor device includes a substrate, a tunnel insulation pattern on the substrate, a charge storage pattern on the tunnel insulation pattern, a dielectric pattern having a width smaller than a width of the charge storage pattern on the charge storage pattern, a control gate having a width greater than the width of the dielectric pattern on the dielectric pattern, and a metal-containing gate on the control gate. | 2017-09-28 |
20170278937 | SPLIT GATE DEVICE WITH DOPED REGION AND METHOD THEREFOR - A method of forming a semiconductor device using a substrate includes forming a first select gate over the substrate, a charge storage layer over the first select gate, over the second select gate, and over the substrate in a region between the first select gate and the second select gate, wherein the charge storage layer is conformal, and a control gate layer over the charge storage layer, wherein the control gate layer is conformal. The method further includes performing a first implant that penetrates through the control gate layer in a middle portion of the region between the first select gate and the second select gate to the substrate to form a doped region in the substrate in a first portion of the region between the first select gate and the second select gate that does not reach the first select gate and does not reach the second select gate. | 2017-09-28 |
20170278938 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor substrate ( | 2017-09-28 |
20170278939 | DUAL METAL INTERCONNECT STRUCTURE - Source/drain contact structures that exhibit low contact resistance and improved electromigration properties are provided. After forming a first contact conductor portion comprising a metal having a high resistance to electromigration such as tungsten at a bottom portion of source/drain contact trench to form direct contact with a source/drain region of a field effect transistor, a second contact conductor portion comprising a highly conductive metal such as copper or a copper alloy is formed over the first contact conductor portion. | 2017-09-28 |
20170278940 | MASK, MANUFACTURING METHOD THEREOF AND EXPOSURE SYSTEM - A mask, including a transparent substrate and mask patterns formed on a surface of the transparent substrate, wherein the mask patterns include a first area for forming film patterns in a display area and a second area for forming film patterns in a non-display area; both the first area and the second area are provided with a plurality of patterned sub-masks; a distribution density of the patterned sub-masks in the first area is less than a distribution density of the patterned sub-masks in the second area; each patterned sub-mask includes a first pattern for forming a source electrode of a transistor, a second pattern for forming a drain electrode of the transistor, and a slit interposed between the first pattern and the second pattern; and a width of the slit in the first area is greater than a width of the slit in the second area. | 2017-09-28 |
20170278941 | Metal Gate Structure with Device Gain and Yield Improvement - Methods for forming semiconductor structures are disclosed herein. An exemplary method includes forming a gate structure having a dummy gate stack over a substrate, performing a gate replacement process, such that the dummy gate stack is replaced with a metal gate stack, and forming a non-silane based oxide capping layer over the gate structure. The gate replacement process includes removing a portion of the dummy gate stack from the gate structure, thereby forming a gate trench. A work function layer is formed in the gate trench, a blocking layer is formed in the gate trench over the work function layer, and a metal layer (including, for example, aluminum) is formed in the gate trench over the blocking layer. The blocking layer includes titanium and nitrogen with a titanium to nitrogen ratio that is greater than one. In some implementations, the work function layer is formed over a dielectric layer. | 2017-09-28 |
20170278942 | EXTENDED CONTACT AREA USING UNDERCUT SILICIDE EXTENSIONS - The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a contact silicide on a source-drain (S-D) region of a field effect transistor (FET) having extensions by using an undercut etch and a salicide process. A method of forming a contact silicide extension is disclosed. The method may include: forming an undercut region below a dielectric layer and above a source-drain region, the undercut region located directly below a bottom of a contact trench and extending below the dielectric layer to a gate spacer formed on a sidewall of a gate stack; and forming a contact silicide in the undercut region, the contact silicide in direct contact with the source-drain region. | 2017-09-28 |