39th week of 2018 patent applcation highlights part 65 |
Patent application number | Title | Published |
20180277420 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor structure includes a semiconductive substrate including a first surface and a second surface opposite to the first surface, a shallow trench isolation (STI) including a first portion at least partially disposed within the semiconductive substrate and tapered from the first surface towards the second surface, and a second portion disposed inside the semiconductive substrate, coupled with the first portion and extended from the first portion towards the second surface, and a void enclosed by the STI, wherein the void is at least partially disposed within the second portion of the STI. | 2018-09-27 |
20180277421 | METHOD OF MANUFACTURING HIGH RESISTIVITY SEMICONDUCTOR-ON-INSULATOR WAFERS WITH CHARGE TRAPPING LAYERS - A method of preparing a single crystal semiconductor handle wafer in the manufacture of a semiconductor-on-insulator device is provided. The single crystal semiconductor handle wafer is prepared to comprise a charge trapping layer, which is oxidized. The buried oxide layer in the resulting semiconductor-on-insulator device comprises an oxidized portion of the charge trapping layer and an oxidized portion of the single crystal semiconductor device layer. | 2018-09-27 |
20180277422 | BONDED WAFER PRODUCTION METHOD AND BONDED WAFER - A bonded wafer production method for producing a bonded wafer having a thin film on a base wafer by forming an ion implanted layer in a bond wafer by implanting at least one of gas ion of a hydrogen ion and a rare gas ion from a surface of the bond wafer and, after directly bonding an ion implanted surface of the bond wafer and a surface of the base wafer together or bonding the ion implanted surface of the bond wafer and the surface of the base wafer together with an insulator film placed therebetween, delaminating the bond wafer at the ion implanted layer, wherein, as at least one of the bond wafer and the base wafer, an epitaxial wafer is used, and, as cleaning of the epitaxial wafer which is performed before the formation of an epitaxial layer, single wafer processing spin cleaning is performed. | 2018-09-27 |
20180277423 | SYSTEMS AND METHODS FOR PERFORMING EPITAXIAL SMOOTHING PROCESSES ON SEMICONDUCTOR STRUCTURES - Systems and methods for processing semiconductor structures are provided. The methods generally include determining a desired removal map profile for a device layer of a semiconductor structure, determining a set of process parameters for use in an epitaxial smoothing process based on the desired removal map profile, and selectively removing material from the device layer by performing an epitaxial smoothing process on an outer surface of the device layer. | 2018-09-27 |
20180277424 | SEMICONDUCTOR STRUCTURE WITH INTEGRATED PASSIVE STRUCTURES - A metal-oxide-semiconductor field-effect transistor (MOSFET) with integrated passive structures and methods of manufacturing the same is disclosed. The method includes forming a stacked structure in an active region and at least one shallow trench isolation (STI) structure adjacent to the stacked structure. The method further includes forming a semiconductor layer directly in contact with the at least one STI structure and the stacked structure. The method further includes patterning the semiconductor layer and the stacked structure to form an active device in the active region and a passive structure of the semiconductor layer directly on the at least one STI structure. | 2018-09-27 |
20180277425 | Power Semiconductor Package Having a Parallel Plate Waveguide - A power semiconductor package includes a first group of semiconductor dies attached to a first side of a substrate and evenly distributed over a width of the substrate and a second group of semiconductor dies attached to the first side of the substrate and evenly distributed over the substrate width. Each die in the first and second groups has all terminals at one side which is attached to the first side of the substrate and an insulated or isolated face at a side opposite the side with the terminals. A first intermediary metal layer of the substrate forms a first DC terminal. A second intermediary metal layer of the substrate forms a second DC terminal. These intermediary metal layers are insulated from one another and form a parallel plate waveguide. Additional power semiconductor package embodiments are described. | 2018-09-27 |
20180277426 | METHODS OF FORMING CONDUCTIVE STRUCTURES - One illustrative method disclosed herein includes, among other things, forming a first trench/via and a wider second trench/via in a layer of insulating material, forming a conductive adhesion layer in the first and second trench/vias and forming a conductive liner layer in the second trench/via such that the material of the conductive liner layer substantially fills the first trench/via. In this particular example, the method also includes removing portions of the conductive liner layer positioned within the second trench/via and above an upper surface of the conductive adhesion layer and removing portions of the conductive adhesion layer positioned above an upper surface of the layer of insulating material to define a conductive structure positioned in the first trench/via that comprises the material of the conductive adhesion layer and the material of the conductive liner layer. | 2018-09-27 |
20180277427 | STRUCTURE AND METHOD FOR CAPPING COBALT CONTACTS - A process for forming a conductive structure includes the formation of a self-aligned silicide cap over a cobalt-based contact. The silicide cap is formed in situ by the deposition of a thin silicon layer over exposed portions of a cobalt contact, followed by heat treatment to react the deposited silicon with the cobalt and form cobalt silicide, which is an effective barrier to cobalt migration and oxidation. | 2018-09-27 |
20180277428 | Doping Control of Metal Nitride Films - Described are methods for controlling the doping of metal nitride films such as TaN, TiN and MnN. The temperature during deposition of the metal nitride film may be controlled to provide a film density that permits a desired amount of doping. Dopants may include Ru, Cu, Co, Mn, Mo, Al, Mg, Cr, Nb, Ta, Ti and V. The metal nitride film may optionally be exposed to plasma treatment after doping. | 2018-09-27 |
20180277429 | SEMICONDUCTOR DEVICE AND FORMATION THEREOF - A semiconductor device and method of formation are provided. The semiconductor device comprises a metal plug in a first opening over a substrate, the metal plug is over a silicide layer, and the silicide layer is over a metal oxide layer. The metal oxide layer has an oxygen gradient, such that a percentage of oxygen increases from a top surface of the metal oxide layer to a bottom surface of the metal oxide layer. The metal oxide layer unpins the Fermi level of the interface between the metal plug and the substrate, which is exhibited by a lowered Schottky barrier height (SBH) and increased oxygen vacancy states between the V.B. and the C.B. of the metal oxide layer, which decreases the intrinsic resistivity between the metal plug and the substrate as compared to a semiconductor device that lacks such a metal oxide layer. | 2018-09-27 |
20180277430 | METHODS OF FORMING AN AIR GAP ADJACENT A GATE OF A TRANSISTOR AND A GATE CONTACT ABOVE THE ACTIVE REGION OF THE TRANSISTOR - One method includes performing an etching process to define a gate cavity that exposes an upper surface and at least a portion of the sidewalls of a gate structure and forming a replacement spacer structure adjacent the exposed sidewalls of the gate structure, wherein the replacement spacer structure exposes a portion of the upper surface of the gate structure and includes at least one air space. In this example, the method also includes forming a conformal etch stop layer and a replacement gate cap structure in the gate cavity, selectively removing a portion of the replacement gate cap structure and a portion of the conformal etch stop layer so as to thereby expose the upper surface of the gate structure, and forming a conductive gate contact structure (CB) in the conductive gate contact opening, wherein the entire conductive gate contact structure (CB) is positioned vertically above the active region. | 2018-09-27 |
20180277431 | FEATURE FILL WITH NUCLEATION INHIBITION - Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to a direct or remote plasma. Pre-inhibition and post-inhibition treatments are used to modulate the inhibition effect, facilitating feature fill using inhibition across a wide process window. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) wordlines. The methods may be used for both conformal fill and bottom-up/inside-out fill. Examples of applications include logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate and wordline fill, and 3-D integration using through-silicon vias. | 2018-09-27 |
20180277432 | REFLOW INTERCONNECT USING Ru - A method for forming conductive structures for a semiconductor device includes depositing a reflow liner on walls of trenches formed in a dielectric layer and depositing a reflow material on the reflow liner. The reflow material is reflowed to collect in a lower portion of the trenches. The depositing and the reflowing steps are repeated until the trenches are aggregately filled with the reflow material. The reflow material is planarized to form conductive structures in the trenches. | 2018-09-27 |
20180277433 | REFLOW INTERCONNECT USING Ru - A method for forming conductive structures for a semiconductor device includes depositing a reflow liner on walls of trenches formed in a dielectric layer and depositing a reflow material on the reflow liner. The reflow material is reflowed to collect in a lower portion of the trenches. The depositing and the reflowing steps are repeated until the trenches are aggregately filled with the reflow material. The reflow material is planarized to form conductive structures in the trenches. | 2018-09-27 |
20180277434 | PROCESS OF FORMING OHMIC ELECTRODE ON NITRIDE SEMICONDUCTOR MATERIAL - A process of forming an ohmic electrode containing aluminum (Al) on a nitride semiconductor material is disclosed. The process includes steps of: (a) depositing an ohmic metal on the semiconductor material; (b) forming an insulating film such that the insulating film covers a side of the ohmic metal but exposes a top of the ohmic metal; and (c) alloying the ohmic metal at a temperature higher than 500° C. for 30 to 60 seconds. | 2018-09-27 |
20180277435 | DICING METHOD AND LASER PROCESSING APPARATUS - According to one embodiment, a dicing method is provided. The dicing method includes detecting a first distance between a first portion of a substrate and a first substrate information detection unit. The method also includes detecting a second distance between a second portion of the substrate a second substrate information detection unit, the second portion different from the first portion. Distance information is calculated between the substrate and a processing lens, which is located farther from the second substrate information detection unit than from the first substrate information detection unit, based on the detected first distance and the detected second distance, and he substrate is irradiated with laser light from the processing lens based on the distance information. | 2018-09-27 |
20180277436 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - According to an embodiment, a method of manufacturing a semiconductor device includes forming a first modified zone in a wafer by irradiating the wafer with a laser having transmissivity with respect to the wafer along a part of a dicing line on the wafer, and forming a second modified zone in the wafer by irradiating the wafer with the laser along the dicing line on the wafer. The first modified zone is partially formed between a surface of the wafer and the second modified zone, a semiconductor interconnect layer being formed on the surface of the wafer. | 2018-09-27 |
20180277437 | SEMICONDUCTOR DEVICE - A main semiconductor element and a temperature sensing part are arranged on a single silicon carbide base. The main semiconductor element is a vertical MOSFET and the temperature sensing part is a horizontal diode. An anode region of the temperature sensing part and an n | 2018-09-27 |
20180277438 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - An object of the present invention is to provide a semiconductor device and a manufacturing method thereof that may achieve low power consumption in a digital circuit and reduce influence of noise in an analog circuit. The manufacturing method of the semiconductor device includes a first source/drain forming step of forming a first source region and a first drain region by implanting impurities of a second conductivity type into a digital side second conductivity type impurity layer using a gate electrode and a sidewall as a mask and a second drain/source forming step of forming a second source region and a second drain region by implanting impurities of the second conductivity type into an analog side second conductivity type impurity layer using a gate electrode and a sidewall as a mask more shallowly than the impurities of the second conductivity type implanted in the first source/drain forming step. | 2018-09-27 |
20180277439 | METHOD TO FORM HYBRID SIGE FIN - A method for manufacturing a semiconductor device includes providing a semiconductor structure having a semiconductor substrate, a dielectric layer on the semiconductor substrate, and a hardmask on a second portion of the dielectric layer while exposing a first portion of the dielectric layer; forming a copolymer on the semiconductor structure; performing an annealing treatment such that the copolymer forms a staggered configuration of a first monomer and a second monomer; removing the first monomer; performing a first etching process on the first portion using the second monomer as a mask to form a first trench extending to the semiconductor substrate; removing the second monomer and the first hardmask; and epitaxially growing a first semiconductor fin in the first trench. | 2018-09-27 |
20180277440 | GATE CUT METHOD - A method of manufacturing a FinFET structure involves forming gate cuts within a sacrificial gate layer prior to patterning and etching the sacrificial gate layer to form longitudinal sacrificial gate structures. By forming transverse cuts in the sacrificial gate layer before defining the sacrificial gate structures longitudinally, dimensional precision of the gate cuts at lower critical dimensions can be improved. | 2018-09-27 |
20180277441 | METHOD TO IMPROVE CMOS DEVICE PERFORMANCE - A method for manufacturing a semiconductor device includes providing a substrate including a first device region and a second device region spaced apart from each other, forming a first oxide layer on the first device region and the second device region, forming a second oxide layer below the first oxide layer, forming a mask layer on the first oxide layer on the first device region while exposing the first oxide layer on the second device region, removing the first and second oxide layers on the second device region using the mask layer as a mask, removing the mask layer, and forming a gate oxide layer on the second device region. The thus formed gate oxide layer structure has improved quality and reliability. | 2018-09-27 |
20180277442 | STACKED VERTICAL DEVICES - A semiconductor structure containing a plurality of stacked vertical field effect transistor (FETs) is provided. After forming a first vertical FET of a first conductivity type at a lower portion of a semiconductor fin, a second vertical FET of a second conductivity type is formed on top of the first vertical FET. The second conductivity type can be opposite to, or the same as, the first conductivity type. A source/drain region of the first vertical FET is electrically connected to a source/drain region of the second vertical FET by a conductive strip structure. | 2018-09-27 |
20180277443 | VERTICAL FIELD EFFECT TRANSISTORS - Vertical field effect transistors (FETs) with minimum pitch and methods of manufacture are disclosed. The structure includes at least one vertical fin structure and gate material contacting with the at least one vertical fin structure. The structure further includes metal material in electrical contact with the ends of the at least one vertical fin. | 2018-09-27 |
20180277444 | VARIABLE GATE LENGTHS FOR VERTICAL TRANSISTORS - The method includes prior to depositing a gate on a first vertical FET on a semiconductor substrate, depositing a first layer on the first vertical FET on the semiconductor substrate. The method further includes prior to depositing a gate on a second vertical FET on the semiconductor substrate, depositing a second layer on the second vertical FET on the semiconductor substrate. The method further includes etching the first layer on the first vertical FET to a lower height than the second layer on the second vertical FET. The method further includes depositing a gate material on both the first vertical FET and the second vertical FET. The method further includes etching the gate material on both the first vertical FET and the second vertical FET to a co-planar height. | 2018-09-27 |
20180277445 | VERTICAL TRANSISTOR TOP EPITAXY SOURCE/DRAIN AND CONTACT STRUCTURE - An nFET vertical transistor is provided in which a p-doped top source/drain structure is formed in contact with an n-doped semiconductor region that is present on a topmost surface of a vertical nFET channel. The p-doped top source/drain structure is formed utilizing a low temperature (550° C. or less) epitaxial growth process. | 2018-09-27 |
20180277446 | VERTICAL TRANSISTOR TOP EPITAXY SOURCE/DRAIN AND CONTACT STRUCTURE - An nFET vertical transistor is provided in which a p-doped top source/drain structure is formed in contact with an n-doped semiconductor region that is present on a topmost surface of a vertical nFET channel. The p-doped top source/drain structure is formed utilizing a low temperature (550° C. or less) epitaxial growth process. | 2018-09-27 |
20180277447 | METHOD FOR MANUFACTURING CMOS STRUCTURE - The present disclosure relates to a method for manufacturing a CMOS structure. A first gate stack is formed on a semiconductor substrate in a first region. A second gate stack is formed on the semiconductor substrate in a second region. A dopant of a first type is implanted with the first gate stack and the second gate stack as a hard mask to form a lightly-doped drain region of the first type. A dopant of a second type is implanted by using a first mask and with the second gate stack as a hard mask to form a lightly-doped drain region of the second type. The first mask blocks the first region and exposes the second region. When the lightly-doped drain region of the second type is formed, the dopant of the second type over dopes a predetermined region of the lightly-doped drain region of the first type. In such a process, over doping is used for reducing the number of masks. A doping concentration of a well region may be modified to adjust work function. | 2018-09-27 |
20180277448 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes at least one n-channel, at least one p-channel, at least one first high-k dielectric sheath, at least one second high-k dielectric sheath, a first metal gate electrode and a second metal gate electrode. The first high-k dielectric sheath surrounds the n-channel. The second high-k dielectric sheath surrounds the p-channel. The first high-k dielectric sheath and the second high-k dielectric sheath comprise different high-k dielectric materials. The first metal gate electrode surrounds the first high-k dielectric sheath. The second metal gate electrode surrounds the second high-k dielectric sheath. | 2018-09-27 |
20180277449 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE, INSPECTION DEVICE OF SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - A subject matter of this invention is that a manufacturing yield of a semiconductor device is improved. | 2018-09-27 |
20180277450 | MANUFACTURING METHOD AND EVALUATION METHOD OF SILICON EPITAXIAL WAFER - A manufacturing method of a silicon epitaxial wafer having an epitaxial layer grown on a mirror wafer of silicon, including: using a PL measuring apparatus to measure photoluminescence (PL) spectrum of the mirror wafer and adjusting the apparatus so emission intensity of a TO-line becomes 30000 to 50000 counts, irradiating the silicon epitaxial wafer with an electron beam, measuring PL spectrum from an electron beam irradiation region, and sorting out and accepting a silicon epitaxial wafer which has emission intensity resulting from a C | 2018-09-27 |
20180277451 | MANUFACTURING SYSTEM FOR SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND CONTROL DEVICE - According to an embodiment, a manufacturing system for a semiconductor device includes a first processing device and a second processing device, a measurement section, and an analysis section. The first processing device and the second processing device are adapted to perform a film formation process on a substrate in a wafer. The measurement section is adapted to measure a first value related to a shape of the wafer after film formation by the first processing device, and then measure a second value related to a distortion of the wafer based on the first value. The analysis section is adapted to change a film formation condition of the second processing device based on processing information of the first processing device, the second value, and information of the second processing device. | 2018-09-27 |
20180277452 | INSPECTION OF SUBSTRATES - Concepts presented herein relate to approaches for performing substrate inspection. In one aspect, the concepts relate to detecting anomalies or candidate defects on the substrate based on contrast in images obtained of the substrate. | 2018-09-27 |
20180277453 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - Semiconductor layer | 2018-09-27 |
20180277454 | SUBSTRATE TREATMENT APPARATUS AND SUBSTRATE TREATMENT METHOD - A substrate treatment method according to the present invention is a substrate treatment method of treating at least one substrate in a treatment tank with treatment liquid. The substrate treatment method includes the following processes of: acquiring in advance treatment information of the substrate to be treated in the treatment tank; specifying a predicted concentration change pattern corresponding to the acquired treatment information of the substrate by referencing correspondence information describing a plurality of situations possible for the treatment information and a plurality of concentration change patterns of the treatment liquid prepared in advance to respectively correspond to the plurality of situations of the treatment information; and carrying out concentration control of the treatment liquid based on the predicted concentration change pattern while the substrate is treated in the treatment tank. | 2018-09-27 |
20180277455 | METHOD FOR OPTIMIZING DRY ABSORBER EFFICIENCY AND LIFETIME IN EPITAXIAL APPLICATIONS - Increasing efficiency of absorbers is provided herein. In some embodiments, a method of processing a substrate may include determining a quantity of a removal species in an effluent stream flowing from a semiconductor processing chamber, wherein determining comprises: detecting or predicting a quantity of the removal species upstream of a chamber abatement apparatus in the effluent stream flowing from the semiconductor processing chamber; and removing the removal species from the effluent stream with the chamber abatement apparatus if the determined quantity of the removal species exceeds a threshold value of the removal species. | 2018-09-27 |
20180277456 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE - To divide a semiconductor wafer by stealth dicing, a test pad in a cutting region and an alignment target are collectively arranged along one side in a width direction of the cutting region, and a laser beam for forming a modified region is irradiated to a position away in plane from the test pad and the alignment target Am. In this manner, defects in cutting shape in a cutting process of a semiconductor wafer using stealth dicing can be reduced or prevented. | 2018-09-27 |
20180277457 | SHIELDED MODULE | 2018-09-27 |
20180277458 | THROUGH-MOLD STRUCTURES - Devices and methods include an electronic package having a through-mold interconnect are shown herein. Examples of the electronic package include a package assembly. The package assembly including a substrate having a first substrate surface. The first substrate surface including a conductive layer attached to the first substrate surface. The package assembly includes a die communicatively coupled to the conductive layer and a contact block. The contact block including a first contact surface on one end of the contact block, a second contact surface on an opposing side of the contact block, and a contact block wall extended therebetween. The contact block includes a conductive material. The first contact surface is coupled to the package assembly with a joint extended partially up the contact block wall. The electronic package further includes an overmold covering portions of the substrate, conductive layer, and die. The second contact surface of the contact block is exposed through the overmold. | 2018-09-27 |
20180277459 | SEMICONDUCTOR DEVICE - A semiconductor device with a FINFET, which provides enhanced reliability. The semiconductor device includes a first N channel FET and a second N channel FET which are coupled in series between a wiring for output of a 2-input NAND circuit and a wiring for a second power potential. In plan view, a local wiring is disposed between a first N gate electrode of the first N channel FET and a second N gate electrode of the second N channel FET which extend in a second direction, and crosses a semiconductor layer extending in a first direction and extends in the second direction. The local wiring is coupled to a wiring for heat dissipation. | 2018-09-27 |
20180277460 | ONBOARD CONTROL DEVICE - Provided is an inexpensive and highly reliable resin sealed-type onboard electronic control device is mounted in a vehicle such as an engine control unit and a control unit for automatic transmission, which have a heat dissipation structure for dissipating heat generated from an electronic component such as a semiconductor element. The onboard control device includes a circuit board, a member provided to face the circuit board, a heat generating electronic component mounted between the circuit board and the member, a heat dissipating material provided between the heat generating electronic component and the member, and a sealing resin to seal the circuit board and the heat generating electronic component. And a space between the member and the circuit board is at least a part of a range where the heat dissipating material is not provided, and is narrower than a range where the heat dissipating material is provided. | 2018-09-27 |
20180277461 | METHODS AND APPARATUS FOR A SEMICONDUCTOR DEVICE HAVING BI-MATERIAL DIE ATTACH LAYER - Described examples include a device including a semiconductor die having a first surface with bond pads and an opposite second surface attached to a substrate by an adhesive layer covering at least a portion of the surface area of the second surface. The adhesive layer includes first zones composed of a first polymeric compound and adding up to a first portion of the surface area, and second zones composed of a second polymeric compound and adding up to a second portion of the surface area, the first zones and the second zones being contiguous. The first polymeric compound has a first modulus and the second polymeric compound has a second modulus greater than the first modulus. | 2018-09-27 |
20180277462 | SEMICONDUCTOR DEVICE, MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE, AND ELECTRODE PLATE - A semiconductor device includes an electrode plate, a metallic member, and solder connecting the metallic member with the electrode plate. On a surface of the electrode plate, a first groove and a group of second grooves are provided. The first groove has first to fourth linear parts. The group of second grooves is arranged within a range surrounded by the first groove, and has end portions on an outer periphery side that are connected with the first groove. The group of second grooves includes first to fourth sets. Each of the sets includes a plurality of second grooves connected with the first to fourth linear parts. When the metallic member is seen in a lamination direction of the electrode plate and the metallic member, an outer peripheral edge of a region of the metallic member, the region being connected with the solder, goes across the first to fourth sets. | 2018-09-27 |
20180277463 | Methods and Apparatus for Semiconductor Device Having Bi-Material Die Attach Layer - Described examples include a device including a semiconductor die having a first surface with bond pads and an opposite second surface attached to a substrate by an adhesive layer covering at least a portion of the surface area of the second surface. The adhesive layer includes first zones composed of a first polymeric compound and adding up to a first portion of the surface area, and second zones composed of a second polymeric compound and adding up to a second portion of the surface area, the first zones and the second zones being contiguous. The first polymeric compound has a first modulus and the second polymeric compound has a second modulus greater than the first modulus. | 2018-09-27 |
20180277464 | SEMICONDUCTOR DEVICE HAVING CORRUGATED LEADS AND METHOD FOR FORMING - A semiconductor device includes a lead frame site including a die attach region and corrugated metal leads around the die attach region. Each of the corrugated metal leads includes two or more corrugations. Each of the two or more corrugations includes a first flat horizontal portion, a first vertical portion with a first end directly adjacent and connected to a first end of the first flat horizontal portion, a second flat horizontal portion with a first end directly adjacent and connected to a second end of the first vertical portion, and a second vertical portion with a first end directly adjacent and connected to a second end of the second flat horizontal portion. The first flat horizontal portion is in a different plane than the second flat horizontal portion. | 2018-09-27 |
20180277465 | SEMICONDUCTOR PACKAGE WITH INTERCONNECTED LEADS - A semiconductor package includes a semiconductor die and a ceramic package body covering the semiconductor die. The ceramic package body includes a plurality of contact pads. Each of a first plurality of leads includes a top portion and a bottom portion. The top portion of each of the first plurality of leads is electrically connected to a contact pad of the plurality of contact pads. Each of a second plurality of leads includes a top portion and a bottom portion and an interconnection portion between the top portion and the bottom portion. The top portion of each of the second plurality of leads includes separate finger portions that are electrically connected to at least two of the plurality of contact pads. | 2018-09-27 |
20180277466 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - To reduce a package size of a semiconductor device. According to embodiments, there is a semiconductor device comprising: a first die pad; a first inner lead arranged inside a molded resin; a second die pad; and a second inner lead arranged inside the resin, wherein a part of the first inner lead and a part of the second inner lead are adhered and electrically connected to each other, a first semiconductor chip mounted on the first die pad is electrically connected to a second semiconductor chip mounted on the second die pad via the first inner lead and the second inner lead, and an end face of one end of the first inner lead and the second inner lead that are adhered to each other is exposed to a side surface of the resin. | 2018-09-27 |
20180277467 | SEMICONDUCTOR DEVICE - A semiconductor device includes field-effect transistor having a gate, a drain, and a source. A first clamping circuit is connected between the drain and the gate. The first clamping circuit has a first clamp voltage that is lower than a source-to-drain breakdown voltage of the field-effect transistor. A first resistor in the device has a first end connected to a first node between the first clamping circuit and the gate. A second clamping circuit is connected between the drain and a second end of the first resistor. The second clamping circuit has a second clamp voltage is higher than the first clamp voltage and lower than the source-to-drain breakdown voltage. | 2018-09-27 |
20180277468 | SEMICONDUCTOR DEVICE - A semiconductor device | 2018-09-27 |
20180277469 | SEMICONDUCTOR DEVICE AND LEAD FRAME - A semiconductor device according to a first aspect of the present invention includes a device main body, a single power supply wiring board, a plurality of output wiring boards, and a plurality of semiconductor elements. In a long-side direction of the device main body, the narrow portion of one of any two adjacent wiring boards faces the wide portion of another one of the any two adjacent wiring boards. In a short-side direction of the device main body, the narrow portion and the wide portion of each of the output wiring boards respectively face the wide portion and the narrow portion, in a single pair, of the power supply wiring board. In the long-side direction of the device main body a width of each of the output wiring boards is smaller than a sum of widths of the narrow portion and the wide portion, in a single pair, of the power supply wiring board. | 2018-09-27 |
20180277470 | INTEGRATED PACKAGE ASSEMBLY FOR SWITCHING REGULATOR - In one embodiment, an IC package assembly for a switching regulator, can include: a power switch chip including a control electrode and a first electrode on an obverse side and a second electrode on a reverse side, where the second electrode is configured as a switching terminal of a switching regulator; a control chip including a driving electrode and a plurality of input and output electrodes on the obverse side; and a leadframe including an extension pin, a substrate, and a plurality of discrete pins, where the extension pin is formed integrally with the substrate, and where the reverse side of the power switch chip is arranged on the substrate of the leadframe by a conductive material to electrically connect the second electrode to the substrate. | 2018-09-27 |
20180277471 | THROUGH-HOLE ELECTRODE SUBSTRATE - A method of manufacturing a through-hole electrode substrate includes forming a plurality of through-holes in a substrate, forming a plurality of through-hole electrodes by filling a conductive material into the plurality of through-holes, forming a first insulation layer on one surface of the substrate, forming a plurality of first openings which expose the plurality of through-hole electrodes corresponding to each of the plurality of through-hole electrodes, on the first insulation layer and correcting a position of the plurality of first openings using the relationship between a misalignment amount of a measured distance value of an open position of a leaning through-hole among the plurality of through-holes and of a design distance value of the open position of the leaning through-hole among the plurality of through-holes with respect to a center position of the substrate. | 2018-09-27 |
20180277472 | LAMINATE AND MAKING METHOD - A laminate is provided comprising a support, a resin layer, a metal layer, an insulating layer, and a redistribution layer. The resin layer comprises a photo-decomposable resin having light-shielding properties and has a transmittance of up to 20% with respect to light of wavelength 355 nm. The laminate is easy to fabricate and has thermal process resistance, the support is easily separated, and a semiconductor package is efficiently produced. | 2018-09-27 |
20180277473 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a wiring substrate including wiring layers, a semiconductor chip including electrode pads and mounted on the wiring substrate, and a first capacitor including a first electrode and a second electrode, and mounted on the wiring substrate. The wiring layers include a first wiring layer including a first terminal pad electrically connected with the first electrode of the first capacitor and a second terminal pad electrically connected with the second electrode of the first capacitor; and a second wiring layer on an inner side by one layer from the first wiring layer of the wiring substrate and including a first conductor pattern having a larger area than each of the first terminal pad and the second terminal pad. The first conductor pattern includes a first opening in a region overlapping with each of the first terminal pad and the second terminal pad in the second wiring layer. | 2018-09-27 |
20180277474 | CIRCUIT BOARDS AND SEMICONDUCTOR PACKAGES INCLUDING THE SAME - A circuit board and a semiconductor packages therewith are disclosed. The circuit board may include a top surface, on which at least one semiconductor chip is mounted, and a bottom surface, to which at least one outer terminal is coupled. The top surface may include an upper window region, on which an upper conductive pattern electrically connected to the semiconductor chip is provided, and the bottom surface may include a lower window region, on which a lower conductive pattern electrically connected to the upper conductive pattern is provided. Here, a ratio of an area of the lower conductive pattern to an area of the upper conductive pattern may be less than or equal to 1.5. | 2018-09-27 |
20180277475 | A SEMICONDUCTOR POWER DEVICE COMPRISING ADDITIONAL TRACKS AND METHOD OF MANUFACTURING THE SEMICONDUCTOR POWER DEVICE - Some embodiments relate to a semiconductor power device that includes a first substrate, a second substrate, a stack and an interconnect structure. The first substrate includes a first patterned electrically conductive layer on a first surface and a switching semiconductor element. The second substrate includes a second surface facing the first surface and a second patterned electrically conductive layer on the second surface. The stack includes an electrically conductive track and a layer of a dielectric material. The layer of the dielectric material is provided on the first or second patterned electrically conductive layer and the layer of the dielectric material isolates the electrically conductive track from the patterned electrically conductive layer on which the stack is provided. The interconnect structure provides at least one electrical connection electrically conductive layers or areas of the substrates. | 2018-09-27 |
20180277476 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor memory device includes a first electrode film, a second electrode film group composed of a plurality of electrode films provided on the first electrode film, a third electrode film group composed of a plurality of electrode films provided on the first electrode film and spaced from the second electrode film group, a semiconductor member extending in a first direction in which the first electrode film and the second electrode film group are arranged, a charge storage member provided between the first electrode film and the semiconductor member, a first conductive film connecting the plurality of electrode films of the second electrode film group to each other and a second conductive film connecting the plurality of electrode films of the third electrode film group to each other. | 2018-09-27 |
20180277477 | STORAGE DEVICE - A storage device includes a first wiring layer, a second wiring layer spaced from the first wiring layer in a first direction, and a plurality of electrode layers stacked in the first direction between the first wiring layer and the second wiring layer. A semiconductor pillar penetrates the plurality of electrode layers in the first direction. The plurality of electrode layers includes a first electrode layer connected to a first wire in the first wiring layer and a second electrode layer connected to a second wire in the second wiring layer. | 2018-09-27 |
20180277478 | SEMICONDUCTOR DEVICE - There is provided a semiconductor device including a memory region and a logic region. The memory region includes a transistor (memory transistor) that stores information by accumulating charge in a sidewall insulating film. The width of the sidewall insulating film of the memory transistor included in the memory region is made larger than the width of a sidewall insulating film of a transistor (logic transistor) included in the logic region. | 2018-09-27 |
20180277479 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device in which the generation of a distortion of a signal is suppressed, and a method for manufacturing the semiconductor device are disclosed. The semiconductor device includes a transistor region in which a field effect transistor is provided; and an interconnection region in which a metal layer electrically connected to the field effect transistor is provided. The interconnection region includes an insulating layer provided between the metal layer and a substrate, and a low-permittivity layer provided in the insulating layer below the metal layer and having a lower permittivity than the insulating layer. | 2018-09-27 |
20180277480 | DIFFERENTIAL INDUCTOR AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - Provided are a differential inductor and a semiconductor device including the same, the differential inductor including first circular parts and second circular parts disposed on a first layer and composing a first spiral shape, a first semi-circular part disposed on the first layer and in the first circular part that is an innermost one of the first circular parts, and a second semi-circular part disposed outside the first circular part that is an outermost one of the first circular parts, third semi-circular parts and fourth semi-circular parts disposed on a second layer under the first layer and composing a second spiral shape, connection means configured to connect, to one, the first and second circular parts, and the first to fourth semi-circular parts, wherein the second circular parts are respectively interposed between the first circular parts, and a part of the fourth semi-circular parts is respectively interposed between the second semi-circular parts. | 2018-09-27 |
20180277481 | FABRICATION OF VERTICAL FUSES FROM VERTICAL FINS - A vertical fuse element, including, a conductive silicide base on a surface of a substrate, and a conductive silicide pillar extending in a direction perpendicular to the surface of the substrate, where the conductive silicide pillar is on the conductive silicide base, and wherein the conductive silicide pillar includes an upper portion having a width, W | 2018-09-27 |
20180277482 | REDUCING METALLIC INTERCONNECT RESISTIVITY THROUGH APPLICATION OF MECHANICAL STRAIN - Methods are provided for fabricating metallic interconnect structures having reduced electrical resistivity that is obtained by applying mechanical strain to the metallic interconnect structures, as well as semiconductor structures having metallic interconnect structures formed with permanent mechanical strain to provide reduced electrical resistivity. For example, a method includes forming a metallic interconnect structure in an interlevel dielectric (ILD) layer of a back-end-of-line (BEOL) structure of a semiconductor structure, and forming a stress layer in contact with the metallic interconnect structure. A thermal anneal process is performed to cause the stress layer to expand and apply compressive strain to the metallic interconnect structure and permanently deform at least a portion of the metallic interconnect structure into a stress memorized state of compressive strain. | 2018-09-27 |
20180277483 | CONTACT FORMATION IN SEMICONDUCTOR DEVICES - A technique relates to fabricating a semiconductor device. A contact trench is formed in an inter-level dielectric layer. The contact trench creates an exposed portion of a semiconductor substrate through the inter-level dielectric layer. A gate stack is on the semiconductor substrate, and the inter-level dielectric layer is adjacent to the gate stack and the semiconductor substrate. A source/drain region is formed in the contact trench such that the source/drain region is on the exposed portion of the semiconductor substrate. Tin is introduced in the source/drain region to form an alloyed layer on top of the source/drain region, and the alloyed layer includes the tin and a source/drain material of the source/drain region. A trench layer is formed in the contact trench such that the trench layer is on top of the alloyed layer. A metallic liner layer is formed on the trench layer and the inter-level dielectric layer. | 2018-09-27 |
20180277484 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first chip having a through via, a second chip having a first terminal that is electrically connected to the through via, and a substrate having a second terminal disposed on a first surface thereof and electrically connected to the first terminal. When viewed along a straight line that intersects a center axis that is perpendicular to the first surface and intersects a center point of the substrate, the first terminal is disposed further towards the center axis than the second terminal and the through via is disposed further towards the center axis than the first terminal. | 2018-09-27 |
20180277485 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF - A semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a semiconductor device comprising multiple encapsulating layers and multiple signal distribution structures, and a method of manufacturing thereof. | 2018-09-27 |
20180277486 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - Even if a via hole is displaced, erosion of a first layer made of titanium is suppressed when the via hole is cleaned. A semiconductor includes a wire layer, a side protective film, an interlayer insulating film, and via plugs. The wire layer includes a first layer made of titanium, a second layer that is arranged on the first layer and is made of titanium nitride, a third layer that is arranged on the second layer and contains aluminum, and a fourth layer that is arranged on the third layer and is made of titanium nitride. The side protective film is arranged on the side of the wire layer and has chemical resistance to hydroxylamine and conductivity. The interlayer insulating film covers the wire layer and the side protective film and has via holes. Via plugs are arranged in the via holes and are electrically coupled to the wire layer. | 2018-09-27 |
20180277487 | GRAPHENE WIRING STRUCTURE, SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING GRAPHENE WIRING STRUCTURE, AND METHOD FOR MANUFACTURING WIRING STRUCTURE - A graphene wiring structure of an embodiment has: an amorphous or polycrystalline insulating film; and a multilayer graphene on the insulating film. The multilayer graphene including a plurality of graphene crystals having a zigzag direction is oriented at 17 degrees or less with respect to an electric conduction direction on the insulating film. | 2018-09-27 |
20180277488 | SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR PACKAGE MANUFACTURING METHOD - A semiconductor package includes a substrate, a semiconductor element disposed on the substrate, an encapsulating layer covering side surfaces and a top surface of the semiconductor element, an electromagnetic shield layer covering side surfaces of the substrate and side surfaces and a top surface of the encapsulating layer, and a titanium oxide layer formed above a top surface of the electromagnetic shield layer, and including a first portion containing divalent titanium oxide and a second portion containing tetravalent titanium oxide. | 2018-09-27 |
20180277489 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF - A semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a semiconductor device comprising one or more conductive shielding members and an EMI shielding layer, and a method of manufacturing thereof. | 2018-09-27 |
20180277490 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A semiconductor package includes a ground electrode formed on an upper surface of a substrate, a first electronic component disposed on the upper surface of the substrate, a sealing member sealing the electronic component, and a shielding member surrounding the first electronic component and disposed in the sealing member. | 2018-09-27 |
20180277491 | POWER ELECTRONICS ASSEMBLIES AND VEHICLES INCORPORATING THE SAME - A power electronics assembly includes a semiconductor device, a metal substrate, and a cooling structure. The metal substrate includes a plurality of stress-relief features that extend at least partially through a thickness of the metal substrate. The plurality of stress-relief features are at least partially filled with a transient liquid phase (TLP) bonding material. The semiconductor device is positioned over the plurality of stress-relief features and thermally bonded to the metal substrate via TLP bonding material. Vehicles having power electronics assemblies with stress-relief through-features are also disclosed. | 2018-09-27 |
20180277492 | WARPAGE CONTROL FOR MICROELECTRONICS PACKAGES - Techniques for reducing warpage for microelectronic packages are provided. A warpage control layer or stiffener can be attached to a bottom surface of a substrate or layer that is used to attach the microelectronics package to a motherboard. The warpage control layer can have a thickness approximately equal to a thickness of a die of the microelectronics package. A coefficient of thermal expansion of the warpage control layer can be selected to approximately match a CTE of the die. The warpage control layer can be formed from an insulating material or a metallic material. The warpage control layer can comprise multiple materials and can include copper pillar segments to adjust the effective CTE of the warpage control layer. The warpage control layer can be positioned between the microelectronics package and the motherboard, thereby providing warpage control without contributing to the z-height of the microelectronics package. | 2018-09-27 |
20180277493 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes stacking a first substrate comprising a first surface having a semiconductor element and an opposing second surface and a second substrate comprising a third surface having a semiconductor element and an opposing fourth surface, forming a first contact hole extending from the second surface to the first surface of the first substrate and forming a first groove inwardly of a first region of the second surface of the first substrate by etching inwardly of the first substrate from the second surface thereof, forming a first patterned mask on the first substrate, so that the first groove is covered by the material of the first patterned mask, forming a first metal electrode in the first contact hole through an opening in the first mask as a mask, and removing the first mask and subsequently cutting through the first substrate in the first groove. | 2018-09-27 |
20180277494 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to an embodiment, a semiconductor memory device includes a substrate, a first stacked body, a columnar part, a second insulating film, and a second stacked body. The first stacked body is provided in a first region on the substrate. The second insulating film is provided in a second region on the substrate, and has a first thickness in a stacking direction of the first stacked body. The second stacked body is provided on the second insulating film. The second stacked body includes a first film and a third insulating film stacked alternately on one another. The uppermost first film in the first films of the second stacked body is located at a first distance in the stacking direction from the upper surface of the substrate. The first thickness is a thickness not less than | 2018-09-27 |
20180277495 | Packages with Interposers and Methods for Forming the Same - A package structure includes an interposer, a die over and bonded to the interposer, and a Printed Circuit Board (PCB) underlying and bonded to the interposer. The interposer is free from transistors therein (add transistor), and includes a semiconductor substrate, an interconnect structure over the semiconductor substrate, through-vias in the silicon substrate, and redistribution lines on a backside of the silicon substrate. The interconnect structure and the redistribution lines are electrically coupled through the through-vias. | 2018-09-27 |
20180277496 | INTEGRATED PHYSICALLY UNCLONABLE FUNCTION DEVICE AND METHOD OF PRODUCTION THEREOF - An integrated device for physically unclonable functions is based on a set of MOS transistors exhibiting a random distribution of threshold voltages which are obtained by lateral implantations of dopants exhibiting non-predictable characteristics, resulting from implantations through a polysilicon layer. A certain number of these transistors form a group of gauge transistors which makes it possible to define a mean gate source voltage making it possible to bias the gates of certain others of these transistors (which are used to define the various bits of the unique code generated by the function). All these transistors consequently exhibit a random distribution of drain-source currents and a comparison of each drain-source current of a transistor associated with a bit of the digital code with a reference current corresponding to the average of this distribution makes it possible to define the logical value 0 or 1 of this bit. | 2018-09-27 |
20180277497 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a first semiconductor circuit layer including a first conductive layer, a second semiconductor circuit layer including a second conductive layer, and a third semiconductor circuit layer between the first semiconductor circuit layer and the second semiconductor circuit layer, the third semiconductor circuit layer including a third conductive layer in contact with the first conductive layer, a fourth conductive layer in contact with the second conductive layer, and a fifth conductive layer in contact with the third conductive layer and electrically connected to the fourth conductive layer. The fifth conductive layer has a width that is narrower than a width of the third conductive layer. | 2018-09-27 |
20180277498 | SEMICONDUCTOR DEVICE - A semiconductor device includes a mounting substrate including an interface, which is connectable with a host, and a first ground layer, a surface-mounted component mounted on the mounting substrate, and a plurality of solder balls between the mounting substrate and the surface-mounted component. The surface-mounted component includes a semiconductor chip, a package substrate that is positioned between the semiconductor chip and the solder balls and includes a second ground layer, a sealing portion that covers the semiconductor chip, and has an opening, a first conductive portion on a top surface of the sealing portion, and a second conductive portion on a side surface of the opening and electrically connected to the first conductive portion and the second ground layer. The second ground layer is electrically connected to the first ground layer through one of the solder balls. | 2018-09-27 |
20180277499 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to an embodiment, a semiconductor memory device includes a substrate, an insulating film, a plurality of conductive films, an insulating member, a plurality of stacked bodies, and a first member. The insulating member is provided on the insulating film, is positioned between the conductive films in a first direction along the substrate, and extends in a second direction along the substrate, the second direction crossing the first direction. The first member is provided on the insulating member, is positioned between the stacked bodies in the first direction, and extends in a stacking direction of the plurality of electrode films of the stacked bodies. A width in the first direction of the insulating member is larger than a width in the first direction of the first member. | 2018-09-27 |
20180277500 | SEMICONDUCTOR ARRANGEMENT IN FAN OUT PACKAGING INCLUDING MAGNETIC STRUCTURE AROUND TRANSMISSION LINE - A semiconductor arrangement in fan out packaging has a molding compound adjacent a side of a semiconductor die. A magnetic structure is disposed above the molding compound, above the semiconductor die, and around a transmission line coupled to an integrated circuit of the semiconductor die. The magnetic structure has a top magnetic portion, a bottom magnetic portion, a first side magnetic portion, and a second side magnetic portion. The first side magnetic portion and the second side magnetic portion are coupled to the top magnetic portion and to the bottom magnetic portion. The first side magnetic portion and the second side magnetic portion have tapered sidewalls. | 2018-09-27 |
20180277501 | LDMOS Transistor Structure and Method of Manufacture - In an embodiment, a method includes forming a first opening in a front surface of a semiconductor substrate including a LDMOS transistor structure, and covering the first opening with a first layer to form an enclosed cavity defined by material of the semiconductor substrate and the first layer. The material of the first layer lines sidewalls of the enclosed cavity. | 2018-09-27 |
20180277502 | METHOD AND APPARATUS FOR BACK-BIASED SWITCH TRANSISTORS - An integrated radio frequency (RF) circuit structure may include an active device on a first surface of an isolation layer. The integrated RF circuit structure may also include a back-bias metallization on a second surface opposite the first surface of the isolation layer. A body of the active device is biased by the back-bias metallization. The integrated RF circuit structure may further include a handle substrate on a front-side dielectric layer on the active device. | 2018-09-27 |
20180277503 | LIQUID EJECTION HEAD SUBSTRATE AND SEMICONDUCTOR SUBSTRATE - A liquid ejection head substrate includes an electrode pad for receiving driving power for liquid ejection from an outside, the electrode pad including at least a conductor layer and a layer of gold. A portion of the conductor layer has an opening region, and an upper layer portion in a laminating direction above the conductor layer including the opening region has at least the layer of gold. An external connection portion connected to the outside is provided on top of the layer of gold corresponding to the opening region of the conductor layer. | 2018-09-27 |
20180277504 | METHODS FOR SURFACE ATTACHMENT OF FLIPPED ACTIVE COMPONENTS - An active substrate includes a plurality of active components distributed over a surface of a destination substrate, each active component including a component substrate different from the destination substrate, and each active component having a circuit and connection posts on a process side of the component substrate. The connection posts may have a height that is greater than a base width thereof, and may be in electrical contact with the circuit and destination substrate contacts. The connection posts may extend through the surface of the destination substrate contacts into the destination substrate connection pads to electrically connect the connection posts to the destination substrate contacts, | 2018-09-27 |
20180277505 | ANISOTROPIC CONDUCTIVE FILM AND CONNECTION STRUCTURE - An anisotropic conductive film includes an insulating adhesive layer and conductive particles disposed thereon. Arrangement axes of the conductive particles having a particle pitch extend in a widthwise direction of the film, and the axes are sequentially arranged with an axis pitch in a lengthwise direction of the film. The particle pitch, axis pitch of the axes, and an angle θ of the axes relative the widthwise direction of the film are determined according to external shapes of terminals so 3 to 40 conductive particles are present on each terminal when a terminal arrangement region of an electronic component is superimposed on the film so a lengthwise direction of each terminal is aligned with the widthwise direction of the film. By using the film, stable connection reliability is obtained and an excessive increase in the density of the conductive particles is suppressed even in the connection of fine pitches. | 2018-09-27 |
20180277506 | SOLDER JOINING - The present invention suppresses fracture at an interface between different materials, and provides a solder joining which includes: a solder joining layer | 2018-09-27 |
20180277507 | Thermal Bonding Sheet and Thermal Bonding Sheet with Dicing Tape - A thermal bonding sheet includes a layer, in which an average area of a pore portion in a cross section of the layer after being heated at a heating rate of 1.5° C./sec from 80° C. to 300° C. under pressure of 10 MPa, and then held at 300° C. for 2.5 minutes is in a range of 0.005 μm | 2018-09-27 |
20180277508 | PRESSURE CONTACT TYPE SEMICONDUCTOR APPARATUS - In a pressure contact type semiconductor apparatus, a second intermediate electrode on a second semiconductor chip has one or more second through holes. The one or more second through holes are fluidly separated from a space hermetically sealed by a cylindrical body, a first common electrode plate and a second common electrode plate. The pressure contact type semiconductor apparatus thereby has high reliability. | 2018-09-27 |
20180277509 | INJECTION MOLDED SOLDER BUMPING - Methods for depositing material on a chip include forming a mold layer. The mold layer includes one or more openings over respective contact areas, each of the one or more openings having an upper volume and a lower volume. The upper volume has a smaller diameter than a diameter of the lower volume. Each contact area is within the respective lower volume. A material is injected into the one or more openings under pressure. | 2018-09-27 |
20180277510 | SELECTIVELY CROSS-LINKED THERMAL INTERFACE MATERIALS - A process of forming a thermal interface material structure includes selectively masking a putty pad that includes ultraviolet (UV) curable cross-linkers to form a masked putty pad. The masked putty pad has a first area that is exposed and a second area that is masked. The process also includes exposing the masked putty pad to UV light to form a selectively cross-linked putty pad. The process includes disposing the selectively cross-linked putty pad between an electrical component and a heat spreader to form an assembly. The process further includes compressing the assembly to form a thermal interface material structure that includes a selectively cross-linked thermal interface material. | 2018-09-27 |
20180277511 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - To provide a semiconductor device having improved reliability. A method of manufacturing the semiconductor device includes connecting a wire comprised of copper with a conductive layer formed on the pad electrode of a semiconductor chip, heat treating the semiconductor chip, and then sealing the semiconductor chip and the wire with a resin. | 2018-09-27 |
20180277512 | EMBEDDED-BRIDGE SUBSTRATE CONNECTORS AND METHODS OF ASSEMBLING SAME - An embedded-bridge substrate connector apparatus includes a patterned reference layer to which a first module and a subsequent module are aligned and the two modules are mated at the patterned reference layer. At least one module includes a silicon bridge connector that bridges to two devices, through the patterned reference layer, to the mated module. | 2018-09-27 |
20180277513 | SEMICONDUCTOR PACKAGE FOR MULTIPHASE CIRCUITRY DEVICE - In some examples, a device includes a power supply element and a reference voltage element, wherein the reference voltage element is electrically isolated from the power supply element. The device further includes a high-side semiconductor die including at least two high-side transistors, wherein each high-side transistor of the at least two high-side transistors is electrically connected to the power supply element. The device also includes a low-side semiconductor die including at least two low-side transistors, wherein each low-side transistor of the at least two low-side transistors is electrically connected to the reference voltage element. The device includes at least two switching elements, wherein each switching element of the at least two switching elements is electrically connected to a respective high-side transistor of the at least two high-side transistors and to a respective low-side transistor of the at least two low-side transistors. | 2018-09-27 |
20180277514 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate having first and second principal surfaces, and a semiconductor chip disposed on the first principal surface. The substrate includes a first conductor layer disposed on the first principal surface, a second conductor layer disposed on the second principal surface, at least one third conductive layer between the first conductive layer and the second conductive layer, a detection interconnection disposed in either the first conductive layer or the third conductive layer, and first and second pads disposed on the second conductive layer and connected to the detection interconnection. The detection interconnection is not part of signal interconnections that are used during operation of the semiconductor chip and is not electrically connected to any circuit of the semiconductor chip. | 2018-09-27 |
20180277515 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A device includes a wiring substrate. A first semiconductor-chip has a first face, a second face, and a first side face between an outer edge of the first face and an outer edge of the second face, where the first side face is a first condition plane. The first semiconductor-chip is located above the wiring substrate. A second semiconductor-chip has a third face, a fourth face, a second side face between an outer edge of the third face and an outer edge of the fourth face, and a through electrode passing through at least a semiconductor substrate between the third face and the fourth face. The second side face is the first condition plane and a second condition plane having more irregularities than the first condition plane. The second semiconductor-chip is located between the wiring substrate and the first semiconductor-chip. The resin is located around the first and second semiconductor-chips. | 2018-09-27 |
20180277516 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first and a second chips. A first inductor is above a first surface or a second surface located on an opposite side to the first surface. A first metal electrode is between the first and second surface to penetrate through the first substrate and to be connected to the first inductor. The second chip includes a second element provided on a third surface of a second substrate. A second inductor provided above a third surface of the second substrate or a fourth surface located on an opposite side to the third surface. A second metal electrode is provided between the third surface and the fourth surface to penetrate through the second substrate and to be connected to the second inductor. The first and second chips are stacked. The first and second inductors are electrically connected via the first or second metal electrode, as one inductor. | 2018-09-27 |
20180277517 | SEMICONDUCTOR DEVICE - A semiconductor device comprises a first semiconductor chip comprising a first substrate. A first magnetic tunnel junction is on the first substrate. A second semiconductor chip comprises a second substrate. A second magnetic tunnel junction is on the second substrate. The second semiconductor chip is positioned on the first semiconductor chip to form a chip stack. A first critical current density required for magnetization reversal of the first magnetic tunnel junction is different than a second critical current density required for magnetization reversal of the second magnetic tunnel junction. | 2018-09-27 |
20180277518 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - An improvement is achieved in the reliability of a semiconductor device. A first semiconductor chip includes a semiconductor substrate, a wiring structure formed over the semiconductor substrate, an insulating film formed over the wiring structure, and a first insulating film formed over the insulating film. A second semiconductor chip includes a semiconductor substrate, a wiring structure formed over the semiconductor substrate, an insulating film formed over the wiring structure, and a second insulating film formed over the insulating film. The first insulating film forms an uppermost layer of the first semiconductor chip. The second insulating film forms an uppermost layer of the second semiconductor chip. Each of the first and second insulating films is made of a photosensitive resin film having an adhesive property. The first and second semiconductor chips are stacked such that the first insulating film of the first semiconductor chip and the second insulating film of the second semiconductor chip are in contact with each other. | 2018-09-27 |
20180277519 | Packages with Stacked Dies and Methods of Forming the Same - A method includes bonding a first plurality of device dies onto a wafer, wherein the wafer includes a second plurality of device dies, with each of the first plurality of device dies bonded to one of the second plurality of device dies. The wafer is then sawed to form a die stack, wherein the die stack includes a first device die from the first plurality of device dies and a second device die from the second plurality of device dies. The method further includes bonding the die stack over a package substrate. | 2018-09-27 |