39th week of 2018 patent applcation highlights part 62 |
Patent application number | Title | Published |
20180277120 | SIGNAL PROCESSING APPARATUS, SIGNAL PROCESSING METHOD AND AUDIO ASSOCIATION PRESENTATION APPARATUS - According to one embodiment, a signal processing apparatus includes a memory and a processes electrically coupled to the memory. The processor separates a plurality of signals by a separation filter, and outputs a plurality of separate signals. The plurality of signals includes signals which are received at different positions and come from different directions. The processor estimates incoming directions of the plurality of separate signals, respectively, and associates the plurality of separate signals with transmission sources of the signals, and present association between the plurality of separate signals and the transmission sources of the signals. | 2018-09-27 |
20180277121 | PASSIVE ENROLLMENT METHOD FOR SPEAKER IDENTIFICATION SYSTEMS - Techniques for passive enrollment of a user in a speaker identification (ID) device are provided. One technique includes: parsing, by a processor of the speaker ID device, a speech sample, spoken by the user, into a keyword phrase sample and a command phrase sample; identifying, by a text-dependent speaker ID circuit of the speaker ID device, the user as the speaker of the keyword phrase sample; associating the command phrase sample with the identified user; determining if the command phrase sample in conjunction with one or more earlier command phrase samples associated with the user is sufficient command phrase sampling to enroll the user in a text-independent speaker ID circuit of the speaker ID device; and enrolling the user in the text-independent speaker ID circuit using the command phrase samples associated with the user after determining there is sufficient command phrase sampling to enroll the user. | 2018-09-27 |
20180277122 | ARTIFICIAL INTELLIGENCE-BASED METHOD AND DEVICE FOR VOICEPRINT AUTHENTICATION - Disclosed are an artificial intelligence-based method and device for voiceprint authentication. The method comprises receiving a registration request of a user and providing a registration string to the user; receiving voice information of the user reading the registration string and producing N segments of voice on the basis of the voice information, where N is a positive integer; determining a gender tag of the user on the basis of a gender classification model and the N segments of voice; and producing a registration voiceprint model for the user on the basis of the gender tag and the N segments of voice. | 2018-09-27 |
20180277123 | GESTURE CONTROLLED MULTI-PERIPHERAL MANAGEMENT - A method for controlling an IoT from one or more wireless earpieces in embodiments of the present invention may have one or more of the following steps: (a) associating the one or more wireless earpieces with the IoT, (b) receiving user input from a user wearing the one or more wireless earpieces, (c) sending a command to a peripheral within the IoT to execute an instruction from the one or more wireless earpieces or a wireless device linked with the one or more wireless earpieces, (d) verifying the user is authorized to utilize the peripheral, (e) associating the user input with the command, and (f) automatically connecting to the peripheral as a nearest one of a plurality of peripherals. | 2018-09-27 |
20180277124 | SPEAKER VERIFICATION - Methods, systems, apparatus, including computer programs encoded on computer storage medium, to facilitate language independent-speaker verification. In one aspect, a method includes actions of receiving, by a user device, audio data representing an utterance of a user. Other actions may include providing, to a neural network stored on the user device, input data derived from the audio data and a language identifier. The neural network may be trained using speech data representing speech in different languages or dialects. The method may include additional actions of generating, based on output of the neural network, a speaker representation and determining, based on the speaker representation and a second representation, that the utterance is an utterance of the user. The method may provide the user with access to the user device based on determining that the utterance is an utterance of the user. | 2018-09-27 |
20180277125 | FRAME ERROR CONCEALMENT - A frame error concealment method based on frames including transform coefficient vectors including the following steps: It tracks sign changes between corresponding transform coefficients of predetermined sub-vectors of consecutive good stationary frames. It accumulates the number of sign changes in corresponding sub-vectors of a predetermined number of consecutive good stationary frames. It reconstructs an erroneous frame with the latest good stationary frame, but with reversed signs of transform coefficients in sub-vectors having an accumulated number of sign changes that exceeds a predetermined threshold. | 2018-09-27 |
20180277126 | METHOD AND SYSTEM FOR ENCODING A STEREO SOUND SIGNAL USING CODING PARAMETERS OF A PRIMARY CHANNEL TO ENCODE A SECONDARY CHANNEL - A stereo sound encoding method and system for encoding left and right channels of a stereo sound signal, down mix the left and right channels of the stereo sound signal to produce primary and secondary channels, encode the primary channel, and encode the secondary channel. Encoding the secondary channel comprises analyzing coherence between coding parameters calculated during the secondary channel encoding and coding parameters calculated during the primary channel encoding to decide if the coding parameters calculated during the primary channel encoding are sufficiently close to the coding parameters calculated during the secondary channel encoding to be re-used during the secondary channel encoding. | 2018-09-27 |
20180277127 | LAYERED CODING FOR COMPRESSED SOUND OR SOUND FIELD REPRESENTATIONS - The present document relates to a method of layered encoding of a compressed sound representation of a sound or sound field. The compressed sound representation comprises a basic compressed sound representation comprising a plurality of components, basic side information for decoding the basic compressed sound representation to a basic reconstructed sound representation of the sound or sound field, and enhancement side information including parameters for improving the basic reconstructed sound representation. The method comprises sub-dividing the plurality of components into a plurality of groups of components and assigning each of the plurality of groups to a respective one of a plurality of hierarchical layers, the number of groups corresponding to the number of layers, and the plurality of layers including a baselayer and one or more hierarchical enhancement layers, adding the basic side information to the base layer, and determining a plurality of portions of enhancement side information from the enhancement side information and assigning each of the plurality of portions of enhancement side information to a respective one of the plurality of layers, wherein each portion of enhancement side information includes parameters for improving a reconstructed sound representation obtainable from data included in the respective layer and any layers lower than the respective layer. The document further relates to a method of decoding a compressed sound representation of a sound or sound field, wherein the compressed sound representation is encoded in a plurality of hierarchical layers that include a base layer and one or more hierarchical enhancement layers, as well as to an encoder and a decoder for layered coding of a compressed sound representation. | 2018-09-27 |
20180277128 | Spectral Translation/Folding in the Subband Domain - The present invention relates to a new method and apparatus for improvement of High Frequency Reconstruction (HFR) techniques using frequency translation or folding or a combination thereof. The proposed invention is applicable to audio source coding systems, and offers significantly reduced computational complexity. This is accomplished by means of frequency translation or folding in the subband domain, preferably integrated with spectral envelope adjustment in the same domain. The concept of dissonance guard-band filtering is further presented. The proposed invention offers a low-complexity, intermediate quality HFR method useful in speech and natural audio coding applications. | 2018-09-27 |
20180277129 | METHOD AND SYSTEM FOR ESTABLISHING PERSONALIZED ASSOCIATION BETWEEN VOICE AND PATTERN - The present invention provides a method for establishing a personalized association between voice and pattern, comprising: acquiring voice data of a user; converting the voice data into a pattern and storing the pattern; and reading the voice data corresponding to a to-be-queried pattern according to a query instruction of the user. The present invention establishes a personalized association relationship between voice and pattern, and takes the pattern corresponding to the voice as a pattern capable of effectively propagated on the Internet. Moreover, the present invention can form a pattern-voice double medium by converting a pattern into a voice, thus improving propagation range and effectiveness. | 2018-09-27 |
20180277130 | SYSTEM AND METHOD FOR PROCESSING AUDIO DATA - A codec operable to process audio data and related data. The codec further operable to receive at least one of an audio, audio auxiliary, program configuration, and data signals from a program source, the audio signals including at least one of single channel audio and multi-channel audio signals, audio auxiliary signals including spatial and motion data and environmental characteristics, the data signals including program related data. The codec further operable to generate a non-transitory encoded bitstream, wherein the bitstream includes at least one of synchronization command data and at least one of a program command data, audio channel data, audio auxiliary data, program content data, and an end of stream data, wherein the encoded bitstream includes an identifier for defining packet type for each data component. The synchronization command data includes a stream start flag defining an entry point for decoding the bitstream and further provides sample rate for the encoded bitstream. | 2018-09-27 |
20180277131 | APPARATUS AND METHOD FOR SURROUND AUDIO SIGNAL PROCESSING - An apparatus for decoding a surround audio signal includes a Bitstream De-multiplexer for unpacking a bitstream into spatial parameters and core parameters, a set of core decoders for decoding the core parameters into a set of core signals, a matrix derivation unit for deriving the rendering matrix from the spatial parameters and playback speaker layout information, and a renderer for rendering of the decoded core signals to playback signals using the rendering matrix. | 2018-09-27 |
20180277132 | SYSTEMS AND METHODS FOR INCREASING LANGUAGE ACCESSABILITY OF MEDIA CONTENT - Systems and methods are described for increasing the language accessibility of media content by modifying accents in speech. For example, a particular character in a media asset may speak in a dialect (e.g., British English) that is difficult for some listeners to understand. The systems and methods, after detecting the dialect of the speech of the particular character, may determine a user preference for an amount to adjust the dialect toward another dialect that the user more easily understands (e.g., American English). For example, specific phonemes and/or words may be modified because they are different between the two dialects, while others may not need to be modified. The systems and methods replace phonemes and/or words determined to need modification with phonemes and/or words that are intermediate between the two dialects. | 2018-09-27 |
20180277133 | INPUT/OUTPUT MODE CONTROL FOR AUDIO PROCESSING - Systems and methods provide input and output mode control for audio processing on a user device. Audio processing may be configured by monitoring audio activity on a device having at least one microphone and a digital audio processing unit, collecting information from the monitoring of the activity, including an identification of at least one application utilizing audio processing, and determining a context for the audio processing, the context including at least one of a hardware, software, audio signal and/or environmental context. An audio signal processing configuration is determined based on the application and determined context, an associated audio signal processing mode is selected, and an optimized audio signal generated. | 2018-09-27 |
20180277134 | Key Click Suppression - Provided are systems and methods for suppressing key clicks in audio signals. An example method includes extracting features of an audio signal. The features are provided as inputs to a neural network. The neural network is trained to identify clicks in the audio signal and/or generate a multiplicative suppression mask suitable for removing key clicks from the audio signal. The suppression mask is applied to the audio signal to produce a clicks-removed audio signal. Comfort noise may be added to the clicks-removed audio signal to avoid noise pumping artifacts. The example method can be used without imposing keyboard activity restrictions on users. The key click suppression can be used in audio systems with a single microphone or with multiple microphones. | 2018-09-27 |
20180277135 | AUDIO SIGNAL QUALITY ENHANCEMENT BASED ON QUANTITATIVE SNR ANALYSIS AND ADAPTIVE WIENER FILTERING - An audio signal enhancement method includes: acquiring an audio signal; estimating a signal-to-noise ratio (SNR) of an audio frame of the audio signal; determining a SNR threshold for the audio frame; selecting an audio signal processing technique according to a comparison of the SNR threshold to the estimated SNR of the audio frame; filtering the audio frame using a Wiener filter applying the selected signal processing technique; and outputting the audio frame filtered using the Wiener filter applying the selected signal processing technique. A first-in, first-out (FIFO) signal processing technique is selected when the estimated SNR of the audio frame is less than the SNR threshold, and a log-energy voice activity detection (VAD) signal processing technique is selected when the estimated SNR of the audio frame is greater than the SNR threshold. | 2018-09-27 |
20180277136 | Image-Based Techniques for Audio Content - A method includes receiving, at a device from a first media device, audio data and image information. The audio information indicates vibrations of an object caused by sound in a vicinity of the object. The method includes generating, at the device, an audio signal based on the audio data. The method includes transmitting the audio signal from the device to a second media device conditioned upon a quality of the audio signal satisfying a threshold. Conditioned upon the quality of the audio signal failing to satisfy the threshold, the method further includes generating audio information based on the vibrations, generating audio content associated with the first media device from the audio information, and transmitting the audio content from the device to the second media device. | 2018-09-27 |
20180277137 | Reverberation Suppression Using Multiple Beamformers - In one embodiment, an audio processing system reduces reverberation in an audio signal. A first beamformer generates a first, directional beampattern, and a second beamformer generates a second beampattern. A signal-processing subsystem (i) processes the first and second beampatterns to generate suppression factors corresponding to the reverberation and (ii) applies the suppression factors to one of the first and second beampatterns to reduce the reverberation in the beampattern. In one implementation, the beampatterns are crossed-beam beampatterns, and the signal-processing subsystem generates the suppression factors based on coherence estimates for the beampatterns. In another implementation, the beampatterns are disjoint beampatterns, and the signal-processing subsystem generates the suppression factors based on short-time and long-time envelope estimates for the beampatterns. Depending on the implementation, the beamformers may be co-located with differently shaped beampatterns or non-co-located with differently or equally shaped beampatterns. | 2018-09-27 |
20180277138 | METHOD AND ELECTRONIC DEVICE FOR OUTPUTTING SIGNAL WITH ADJUSTED WIND SOUND - An electronic device and method for cancelling wind noise from a sound signal input through a microphone is provided. An electronic device of the present disclosure includes an input device comprising input circuitry, an output device comprising output circuitry, and a processor configured to control the input device to acquire a first signal corresponding to external sound of the electronic device, to generate a second signal by delaying the first signal for a predetermined amount of time, to detect a third signal corresponding to the wind sound in the first signal using a predetermined detection method based on the first and second signals, and to control the output device to output a fourth signal obtained by controlling the third signal in the first signal. | 2018-09-27 |
20180277139 | MULTI-BAND NOISE REDUCTION SYSTEM AND METHODOLOGY FOR DIGITAL AUDIO SIGNALS - The present invention relates to a multi-band noise reduction system for digital audio signals producing a noise reduced digital audio output signal from a digital audio signal. The digital audio signal comprises a target signal and a noise signal, i.e. a noisy digital audio signal. The multi-band noise reduction system operates on a plurality of sub-band signals derived from the digital audio signal and comprises a second or adaptive signal-to-noise ratio estimator which is configured for filtering a plurality of first signal-to-noise ratio estimates of the plurality of sub-band signals with respective time-varying low-pass filters to produce respective second signal-to-noise ratio estimates of the plurality of sub-band signals. A low-pass cut-off frequency of each of the time-varying low-pass filters is adaptable in accordance with a first signal-to-noise ratio estimate determined by a first signal-to-noise ratio estimator and/or the second signal-to-noise ratio estimate of the sub-band signal. | 2018-09-27 |
20180277140 | SIGNAL PROCESSING SYSTEM, SIGNAL PROCESSING METHOD AND STORAGE MEDIUM - According to one embodiment, a signal processing system senses and receives generated signals of a plurality of signal sources, estimates a separation filter based on the received signals of the sensor for each frame, separates the received signals based on the filter to obtain separated signals, computes a directional characteristics distribution for each of the separated signals, obtains a cumulative distribution indicating the directional characteristics distribution for each of the separated signals output in a previous frame, computes a similarity of the cumulative distribution to the directional characteristics distribution of the separated signals of a current frame, and connects to a signal selected from the separated signals based on the similarity. | 2018-09-27 |
20180277141 | SIGNAL PROCESSING APPARATUS, SIGNAL PROCESSING METHOD AND LABELING APPARATUS - According to one embodiment, a signal processing apparatus includes a processer. The processor separates a plurality of signals, which are received at different positions and come from different directions, by a separation filter. The processor estimates incoming directions of a plurality of separate signals respectively, and associates the plurality of separate signals with transmission sources of the plurality of signals. The processor associates either one of a first attribute and a second attribute with the separate signals which are associated with the transmission sources of the signals based on results of the estimation of the incoming directions in a first period, and add either one of first label information and second label information. | 2018-09-27 |
20180277142 | REAL TIME CLOSED CAPTIONING OR HIGHLIGHTING METHOD AND APPARATUS - Apparatuses, methods and storage medium associated with real time closed captioning or highlighting are disclosed herein. In embodiments, an apparatus may include an audio interceptor to intercept an audio portion of an audio/video output stream of a multi-media application; a speech recognizer coupled to the audio interceptor to, in real time, process the audio portion of the audio/video stream, recognize speech within the audio portion, and automatically generate text corresponding to recognized speech, or keywords within the recognized speech; and a controller coupled to the audio interceptor and the speech recognizer, to control operations of the audio interceptor and the speech recognizer. The automatically generated text or keywords may be outputted as closed captions or highlights to complement video content of the audio/video stream. Other embodiments may be disclosed or claimed. | 2018-09-27 |
20180277143 | METHOD AND APPARATUS FOR TRAINING ACOUSTIC MODEL - A training method of an acoustic model includes constructing window-level input speech data based on a speech sequence; inputting the window-level input speech data to an acoustic model; calculating a sequence level-error based on an output of the acoustic model; acquiring window-level errors based on the sequence level-error; and updating the acoustic model based on the window-level errors. | 2018-09-27 |
20180277144 | Technique Determination Device and Recording Medium - A technique determination device according to one embodiment of the present invention comprises an input sound acquisition unit acquiring an input sound, | 2018-09-27 |
20180277145 | INFORMATION PROCESSING APPARATUS FOR EXECUTING EMOTION RECOGNITION - An information processing apparatus comprises a learner and a processing unit. The learner learns a phoneme sequence generated from a voice as an emotion phoneme sequence, in accordance with relevance between the phoneme sequence and an emotion of a user. The processing unit executes processing pertaining to emotion recognition in accordance with a result of learning by the learner. The information processing apparatus suppresses execution of a process that does not conform to an emotion of a user. | 2018-09-27 |
20180277146 | SYSTEM AND METHOD FOR ANHEDONIA MEASUREMENT USING ACOUSTIC AND CONTEXTUAL CUES - This application provides a system for classifying a status of anhedonia, the system including an audio data collector adapted to collect a sample of speech, and a processing module including an audio feature extractor and a classification unit, wherein the audio feature extractor extracts a plurality of acoustic features from the sample of speech, and the classification unit classifies a status of anhedonia from the plurality of acoustic features. | 2018-09-27 |
20180277147 | Write Head Designs with Sandwich Trailing Shield (STS) and Funnel Trailing Shield (FTS) for High Data Rate Perpendicular Recording - A PMR writer is disclosed with an all wrap around (AWA) shield design in which one or more of the leading shield, side shields, and trailing shield (TS) structure (except the hot seed layer) at the air bearing surface (ABS) are comprised of an alloy having a damping parameter α of ≥0.04 to minimize wide area track erasure (WATE). The TS structure comprises two outer magnetic layers with an 8-16 kiloGauss (kG) saturation magnetic moment (Ms) on each side of a center stack with a lower write gap, a middle hot seed layer (Ms of 19-24 kG), and an upper magnetic layer (Ms of 16-24 kG). The hot seed layer, upper TS magnetic layer and overlying PP3 TS promote improved area density capability (ADC). A second TS layer with Ms of 16-24 kG and a full width at the ABS may be formed on the upper magnetic layer. | 2018-09-27 |
20180277148 | HYBRID DIELECTRIC GAP LINER AND MAGNETIC SHIELD LINER - In one embodiment, an apparatus includes a transducer structure. The transducer structure has a lower shield and an upper shield above the lower shield, the upper and lower shields providing magnetic shielding. A current-perpendicular-to-plane sensor is positioned between the upper and lower shields. An electrical lead layer is positioned between the sensor and one of the shields. The electrical lead layer is in electrical communication with the sensor. A resistance of the electrical lead layer along a direction orthogonal to a media facing surface is less than a resistance across the sensor along a direction parallel to the media facing surface. A spacer layer is positioned between the electrical lead layer and the one of the shields. One or both of the shields has at least one laminate pair comprising a magnetically permeable layer and a harder layer, where the harder layer has a mechanical hardness that is higher than a mechanical hardness of the magnetically permeable layer. | 2018-09-27 |
20180277149 | MAGNETIC HEAD HAVING ARRAYS OF TUNNEL VALVE READ TRANSDUCERS - An apparatus, according to one embodiment, includes: a module; and a plurality of tunnel valve read transducers arranged in an array extending along the module. Each of the tunnel valve read transducers includes: a sensor structure having a tunnel barrier layer and a free layer. Moreover, each of the tunnel valve read transducers includes a pair of hard bias magnets which sandwich the respective sensor structure therebetween, the hard bias magnets being positioned on opposite sides of the sensor structure along a cross-track direction. Furthermore, a thickness of each of the hard bias magnets at a thickest portion thereof is at least 10 times greater than a thickness of the free layer. Other systems, methods, and computer program products are described in additional embodiments. | 2018-09-27 |
20180277150 | SUSPENSION ASSEMBLY, HEAD SUSPENSION ASSEMBLY AND DISK DEVICE PROVIDED WITH THE SAME - A magnetic head suspension assembly includes a support plate coupled to a magnetic head, and a flexible wiring member disposed on the support plate. The flexible wiring member includes a metal plate fixed to the support plate, an insulating layer disposed on the metal plate, a conductive layer disposed on the insulating layer and forming a plurality of conductive lines and connection terminals, and a cover layer on the conductive layer. The connection end portion includes a plurality of the connection terminals, and each of the connection terminals includes a center hole, a first terminal surface that is a surface of the conductive layer and is covered with the cover layer so that the first terminal surface is not exposed during a solder-joining process performed on the connection terminals, and a second terminal surface that is a surface of the conductive layer and faces away from the first terminal surface. | 2018-09-27 |
20180277151 | MAGNETIC DISK DEVICE, CONTROLLER, AND METHOD - A magnetic disk device includes a magnetic disk that includes a plurality of tracks, a magnetic head for reading data from the magnetic disk, and a controller. The controller begins controlling the magnetic head to move to a second track of the plurality of tracks from a first track of the plurality of tracks before decoding of a first track signal output from the magnetic head is completed, wherein the first track signal is output from the magnetic head while the magnetic head is positioned over the first track. | 2018-09-27 |
20180277152 | TAPE HEAD HAVING SUB-AMBIENT CHANNEL AND METHODS OF MANUFACTURE - An apparatus according to one embodiment includes a module having a tape bearing surface, an array of magnetic transducers, and a channel in the tape bearing surface. The channel has a longitudinal axis oriented about parallel to a longitudinal axis of the array of magnetic transducers for inducing tenting of a moving magnetic recording tape above the array of magnetic transducers. A method according to one embodiment includes forming a channel in a tape bearing surface of a module. The channel is formed to have a longitudinal axis about parallel to a longitudinal axis of an array of magnetic transducers. The channel is formed proximate to the array of magnetic transducers for inducing tenting of a moving magnetic recording tape above the array of magnetic transducers. | 2018-09-27 |
20180277153 | COMPONENT ACCOMMODATING BODY MANAGING APPARATUS, COMPONENT ACCOMMODATING BODY STOREROOM, AND COMPONENT STORAGE INSTRUCTING METHOD - A component accommodating body managing apparatus includes a preparation component extractor, a management storage, and a storage instructing unit. The storage instructing unit generates and transmits storage instruction of the component accommodating body that is stored in the component accommodating body storeroom, based on the preparing number of components, which is extracted by the preparation component extractor, and the accommodating number of components, which is stored in the management storage. Further, the storage instructing unit instructs the component accommodating body storeroom that the accommodating number of components in the component accommodating body that is to be stored in the component accommodating body storeroom henceforth satisfies the preparing number of components. | 2018-09-27 |
20180277154 | SYSTEMS AND METHODS FOR INFORMATION CAPTURE - Disclosed herein are information capture systems and related methods. An information capture system includes a sensor secured to an object configured to be involved with a possible event. The sensor is configured to detect one or more stimuli that are associated with the possible event, and transmit a sensor signal indicating data corresponding to the one or more stimuli. The information capture system also includes a recording device configured to record information responsive to a triggering event determined from the sensor signal. A method includes analyzing sensor data from the sensor, determining, from the sensor data, that a triggering event occurred, and recording post-trigger information following the determination of the triggering event. | 2018-09-27 |
20180277155 | ASYNCHRONOUS ASYMMETRY COMPENSATION FOR DATA READ FROM A STORAGE MEDIUM - A computer program product, according to one embodiment, includes a computer readable storage medium having program instructions embodied therewith, wherein the computer readable storage medium is not a transitory signal per se, the program instructions executable by a processing circuit to cause the processing circuit to perform a method that includes reading data from a magnetic data storage medium. The processing circuit uses a tracking threshold module to detect and track positive peak amplitudes and negative peak amplitudes of a readback waveform during the data reading. Asymmetry compensation is performed on the data based on input from the tracking threshold module. The asymmetry compensation does not rely on an input except from the tracking threshold module in order to perform the asymmetry compensation. | 2018-09-27 |
20180277156 | INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, AND PROGRAM - Data reproduction is performed in a mode decided on the basis of disc type information which is record data of a disc. A reading rate compatible with a physical format of a disc is compared with a reading rate compatible with a disc type, and in a case where the reading rates do not coincide with each other, data read from the disc at the physical format compatible rate is stored in the buffer, and the reproduction process is performed using the data output from the buffer at the disc type compatible rate. In a case where the physical format is BD-R or BD-RE, and the logical format is a logical format compatible with BDMV-UHD, the emulation mode reproduction accompanied with the rate conversion using the buffer is performed. | 2018-09-27 |
20180277157 | SELECTIVE INDEX WRITING PRIOR TO UNTHREADING A MAGNETIC RECORDING TAPE - A drive-implemented method according to one embodiment includes determining that unthreading of a tape is to be performed, and in response to the determination that the unthreading of the tape is to be performed, determining whether to write an index on the tape prior to unthreading the tape. In response to a determination to write the index on the tape, the index is written on the tape prior to unthreading the tape. The tape is then unthreaded. The drive-implemented method further includes receiving a write request after the unthreading, rethreading the tape, and writing data corresponding to the write request on the tape. The index stored on the tape prior to the unthreading is overwritten with the data corresponding to the write request. | 2018-09-27 |
20180277158 | STORAGE DEVICE AND CONTROLLER - A storage device includes a recording medium, a first memory storing first data read from the recording medium, and a controller. The controller searches for read target data in the first data by executing a parity check on second data that is in the first data and starts at a first position, while executing the parity check, determining whether or not an interruption condition is satisfied, storing the second data in a second memory when the parity check completes without the interruption condition being satisfied and a result of a completed parity check satisfies a first condition, and executing a parity check on third data that is in the first data and starts at a second position, responsive to the interruption condition being satisfied and responsive to the result of the completed parity check not satisfying the first condition. | 2018-09-27 |
20180277159 | RADIATION IMAGE DISPLAY APPARATUS AND RADIATION IMAGE PHOTOGRAPHING SYSTEM - A radiation image display apparatus that includes: a hardware processor that generates the moving image for preview based on the pieces of image data of the plurality of frames obtained by moving image photographing of an object with radiation; and a holder that holds the moving image, wherein the hardware processor further: performs reproduction control on the moving image, performs image adjustment on the moving image, displays the moving image on the display during photographing the moving image, and displays the moving image according to the reproduction control or the moving image subjected to the image on the display. | 2018-09-27 |
20180277160 | TRACK PLAYBACK CONTROLLING APPARATUS - A track playback controlling apparatus includes at least one operation receiver, a driver, and a processor. The operation receiver receives operation to change a playback state of a track by a user. The driver causes a physical motion of the operation receiver. The processor changes a state of the motion of the operation receiver in response to a change in the playback state of the track through an operation of the operation receiver. | 2018-09-27 |
20180277161 | Accessing a Video Segment - A method comprising: causing provision of a visual access menu to enable a user to access video segments of a scene comprising: causing display of at least a portion an image of the scene; causing display, at a first location in the scene, of a first user-selectable menu option that when selected causes access to one or more first video segments of activity at the first location in the scene; and causing display, at a second location in the scene, of a second user-selectable menu option that when selected causes access to one or more second video segments of activity at the second location in the scene. | 2018-09-27 |
20180277162 | PRINTER - The disclosure discloses a printer including a memory storing computer-executable instructions. When the instruction is executed by a processor, a printer perform a read process and a printed matter production process. In the read process, process setting information stored in a cartridge memory of a cartridge of the specific type is read, triggered by attachment of the cartridge of the specific type to a cartridge holder. In the printed matter production process, at least a feeder and a printing head is controlled on the basis of a setting state included in the process setting information read in the read process. | 2018-09-27 |
20180277163 | IMAGE DECODING DEVICE, IMAGE DECODING METHOD, IMAGE ENCODING DEVICE, AND IMAGE ENCODING METHOD - Provided is an image decoding device including an acquisition unit configured to acquire clean random access (CRA) information used to identify one or more CRA pictures in an image sequence inserted into a data region from a header region of a file format including the header region and the data region, a control unit configured to specify one CRA picture in the image sequence as a decoding start picture using the CRA information when an instruction of random access is detected, and a decoding unit configured to decode the image sequence from the decoding start picture specified by the control unit. | 2018-09-27 |
20180277164 | SIGNALLING OF VIDEO CONTENT INCLUDING SUB-PICTURE BITSTREAMS FOR VIDEO CODING - In various implementations, modifications and/or additions to the ISOBMFF are provided to process video data. A plurality of sub-picture bitstreams are obtained from memory, each sub-picture bitstream including a spatial portion of the video data and each sub-picture bitstream being independently coded. In at least one file, the plurality of sub-picture bitstreams are respectively stored as a plurality of sub-picture tracks. Metadata describing the plurality of sub-picture tracks is stored in a track box within a media file in accordance with a file format. A sub-picture base track is provided that includes the metadata describing the plurality of sub-picture tracks. | 2018-09-27 |
20180277165 | Non-Greedy Hierarchical Segmentation of Serial Data. - Segmenting serial data by processing multiple candidate segmentation point sets associated with a serial data set, each candidate set including a different number of candidate segmentation points representing the serial data set as segments in accordance with segmentation criteria, where the processing includes determining, for each of the candidate points, a count of the candidate sets that include the candidate point, and creating, for each of the candidate sets, a corresponding alternative segmentation point set associated with the serial data set, where the alternative set includes n alternative segmentation points representing the serial data set as n+1 segments, where n equals the number of candidate points in the candidate set to which the alternative set corresponds, and where the n alternative points in the alternative set correspond to n of the candidate points having the greatest counts, and arranging the alternative sets in order of their numbers of segmentation points. | 2018-09-27 |
20180277166 | SYSTEMS AND METHODS FOR CREATING AND USING NAVIGABLE SPATIAL OVERVIEWS FOR VIDEO - Systems and methods for generating an overview for videos by reconstructing a representation of underlying content and linking from points in the overview to specific points in the video. Mechanisms are provided to create three different types of navigable overviews for different types of how-to and instructional videos. A two-dimensional overview is generated when content is two-dimensional, such as instructional videos on electronic whiteboard or other flat content. The three-dimensional overview is created when the content is three-dimensional, such as how-to videos illustrating the use of specific three-dimensional tangible articles. In three-dimensional case, when 3D model is available, the video segments are directly linked to corresponding points on the model. When a model is not available, a rough overview is first created from the captured video and camera orientation metadata. When the user selects a specific location within the overview, the related video segment is automatically played to the user. | 2018-09-27 |
20180277167 | VIDEO REPRODUCTION DEVICE AND METHOD - A video reproduction device includes a store computer configured to acquire a video data from a video data storage device. The video data is from multiple cameras. The store computer includes an video reproduction application that when executed cause a processor to reproduce video data acquired by a first camera, video data acquired by a second camera at a time shifted by a first offset time, and third video data acquired by a third camera at time shifted by a second offset time such that at least portions of first video data, the second video data, and the third video data are reproduced simultaneously. | 2018-09-27 |
20180277168 | DISK DEVICE AND METHOD OF MANUFACTURING DISK DEVICE - According to one embodiment, a disk device includes a disk-shaped recording medium, a head which processes data on the recording medium, and a housing accommodating the recording medium and the head. The housing includes a base with a side wall, and a cover having a welded portion welded to the side wall by laser welding. The welded portion includes a first welded portion welded to a first region of the side wall and having weld beads with a first shape, and a second welded portion welded to a second region of the side wall and having welded beads with a second shape different from the first shape. | 2018-09-27 |
20180277169 | DISK APPARATUS - A disk apparatus includes a base including a bottom wall and a sidewall disposed along a peripheral portion of the bottom wall, a cover including a ceiling plate and a side plate disposed along a periphery of the ceiling plate, the ceiling plate being fixed to the sidewall and the side plate facing an outer surface of the sidewall, and a rotatable recording medium disposed between the cover and the bottom wall. The sidewall of the base includes a first portion adjacent to the recording medium and a protruding portion that protrudes from the first portion outward and away from the recording medium, and at least a portion of a sidewall of the protruding portion faces an opening formed in the side plate. | 2018-09-27 |
20180277170 | SEMICONDUCTOR DEVICE AND ELECTRONIC EQUIPMENT - According to one embodiment, a semiconductor device includes an input/output circuit to which a signal is input or from which a signal is output; a first terminal connected to a power line of the input/output circuit; a second terminal connected to the power line; a resistance element connected between the second terminal and the power line; and a first capacitance element connected between the second terminal and a ground terminal. | 2018-09-27 |
20180277171 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a power source pad, a first bank including a plurality of memory cells, a second bank including a plurality of memory cells, the first bank being sandwiched between the power source pad and the second bank, first power supply lines connected to the power source pad and supplying power to the first bank and not to the second bank, and second power supply lines connected to the power source pad, passing over the first bank, and supplying power to the second bank and not to the first bank. | 2018-09-27 |
20180277172 | MEMORY MODULE INCLUDING BATTERY - A memory module may include a module substrate having first and second surfaces facing away from each other, a plurality of first memories mounted over one or more of the first and second surfaces, one or more second memories and a controller each mounted over one of the first and second surfaces of the module substrate, and a plurality of batteries mounted over one or more of the first and second surfaces of the module substrate. | 2018-09-27 |
20180277173 | CONTROL SYSTEM - According to one embodiment, a control system includes: a memory device; and a controller. The memory device includes a first cell transistor. The controller is configured to store information on a first temperature associated with a temperature of the memory device upon a write of data in the first cell transistor, obtain a second temperature of the memory device, determine an adjustment from adjustments based on a combination of the first temperature and the second temperature, and instruct the memory device to use for a first parameter a first value and a value which is based on the determined adjustment to read data from the first cell transistor. | 2018-09-27 |
20180277174 | Address Fault Detection In A Flash Memory System - A system and method are disclosed for performing address fault detection in a flash memory system. An address fault detection array is used to confirm that an activated word line or bit line is the word line or bit line that was actually intended to be activated based upon the received address, which will identify a type of fault where the wrong word line or bit line is activated. The address fault detection array also is used to indicate whether more than one word line or bit line was activated, which will identify a type of fault where two or more word lines or bit lines are activated. | 2018-09-27 |
20180277175 | SEMICONDUCTOR LAYERED DEVICE WITH DATA BUS - Apparatuses and methods of data communication between semiconductor chips are described. An example apparatus includes: a first die including a first switch circuit that receives a plurality of data signals, and further provides the plurality of data signals to a plurality of corresponding first ports among a plurality of first data ports and a first data redundancy port; and a second die including a second switch circuit that receives the plurality of data signals from the first die at a plurality of corresponding second ports among a plurality of second data ports and a second data redundancy port and further provides the plurality of data signals to a memory array. | 2018-09-27 |
20180277176 | MEMORY SYSTEM AND OPERATING METHOD THEREOF - A memory system includes: a memory device; and a controller suitable for controlling the memory device to perform a serial read operation by providing a serial read command and a start physical address for the serial read command when an external read command includes a request for the serial read operation, the serial read command includes consecutive physical address numbers information, in response to the serial read command, the memory device sets a read bias, reads data stored therein with the set read bias according to the start physical address and the consecutive physical address numbers information, and then discharges the read bias. | 2018-09-27 |
20180277177 | MEMORY DEVICE AND MEMORY SYSTEM - According to one embodiment, a memory device includes: a memory cell; a read driver configured to supply a read pulse to the memory cell at the time of a read operation for the memory cell; a filter circuit configured to output a second signal in a first frequency domain from a first signal, the first signal being outputted from the memory cell by the read pulse; a hold circuit configured to hold a peak value of the second signal; and a sense amplifier circuit configured to read data from the memory cell based on the peak value. | 2018-09-27 |
20180277178 | SEMICONDUCTOR DEVICE - A semiconductor device includes a buffer control circuit suitable for generating a buffer control signal in response to a power-down mode signal and a detection pulse, a first buffer circuit suitable for generating a first internal chip select signal by buffering a chip select signal depending on a select signal which is generated in response to the buffer control signal in a power-down mode, and a detection pulse generation circuit suitable for generating the detection pulse in response to the first internal chip select signal. | 2018-09-27 |
20180277179 | EMBEDDED MEMORY WITH SETUP-HOLD TIME CONTROLLED INTERNALLY OR EXTERNALLY AND ASSOCIATED INTEGRATED CIRCUIT - An embedded memory includes a memory interface circuit, a cell array, and a peripheral circuit. The memory interface circuit receives at least a clock signal, a non-clock signal, and a setup-hold time control setting, and includes a programmable path delay circuit that is used to set a path delay of at least one of a clock path and a non-clock path according to the setup-hold time control setting. The clock path is used to deliver the clock signal, and the non-clock path is used to deliver the non-clock signal. The peripheral circuit is used to access the cell array according to at least the clock signal provided from the clock path and the non-clock signal. | 2018-09-27 |
20180277180 | MEMORY SYSTEM - A memory system includes a semiconductor memory and a controller. The controller is configured to perform a read operation on the semiconductor memory in response to a read instruction received from a host. In response to the read instruction that includes a first logical address, the controller converts the first logical address into a first physical address, and issues a read command and a second physical address different from the first physical address, to the semiconductor memory. | 2018-09-27 |
20180277181 | MULTIPLE PLATE LINE ARCHITECTURE FOR MULTIDECK MEMORY ARRAY - Methods, systems, and devices for multiple plate line architecture for multideck memory arrays are described. A memory device may include two or more three-dimensional arrays of ferroelectric memory cells overlying a substrate layer that includes various components of support circuitry, such as decoders and sense amplifiers. Each memory cell of the array may have a ferroelectric container and a selector device. Multiple plate lines or other access lines may be routed through the various decks of the device to support access to memory cells within those decks. Plate lines or other access lines may be coupled between support circuitry and memory cells through on pitch via (OPV) structures. OPV structures may include selector devices to provide an additional degree of freedom in multideck selectivity. Various number of plate lines and access lines may be employed to accommodate different configurations and orientations of the ferroelectric containers. | 2018-09-27 |
20180277182 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a first memory cell including a first resistance change memory element and a first transistor, a first word line electrically coupled to a control terminal of the first transistor, and a first circuit configured to, in a reading, apply a first voltage to the first word line during a first period and apply a second voltage higher than the first voltage to the first word line during a second period after the first period. | 2018-09-27 |
20180277183 | MEMORY DEVICE - According to one embodiment, a memory includes a first MTJ element having a first area along a first plane; and second MTJ elements each having a second area along the first plane. The second area is larger than or equal to twice the first area and smaller than or equal to five times the first area. Each of the second MTJ elements includes a first ferromagnet, a second ferromagnet, and a first nonmagnet. Respective magnetizations of respective first ferromagnets of the second MTJ elements are oriented along a first direction. Respective magnetizations of respective second ferromagnets of the second MTJ elements are oriented along a second direction. One of the second MTJ elements is coupled to another one of the second MTJ elements in series or in parallel. | 2018-09-27 |
20180277184 | Data writing method of magnetic memory - A magnetic memory includes one or more magnetic tunnel junctions, a heavy metal or anti-ferromagnetic strip film, a first bottom electrode and a second bottom electrode. Every magnetic tunnel junction is located on the strip film and represents a memory cell; the first bottom electrode and the second bottom electrode are respectively connected with two ends of the heavy metal or anti-ferromagnetic strip film; every magnetic tunnel junction includes a first ferromagnetic metal, a first oxide, a second ferromagnetic metal, a first synthetic antiferromagnetic layer and an X | 2018-09-27 |
20180277185 | MAGNETIC MEMORY DEVICE - According to one embodiment, a magnetic memory device includes a conductive layer, a first magnetic layer, a first nonmagnetic layer, a second magnetic layer, a first conductive region, a first insulating region, and a controller. The conductive layer includes a first element. The conductive layer includes a first portion, a second portion, a third portion between the first portion and the second portion, and a fourth portion between the second portion and the third portion. The first conductive region includes a second element different from the first element. The first conductive region is provided between the second magnetic layer and the third portion. The first insulating region includes a first insulating substance. The first insulating substance is an insulating compound of the second element. The controller is electrically connected to the first portion and the second portion. The controller implements a first operation and a second operation. | 2018-09-27 |
20180277186 | MEMORY DEVICE - According to one embodiment, a memory device includes a memory cell; and a first circuit configured to perform first read for the memory cell and generate a first voltage, write first data to the memory cell that has undergone the first read, perform second read for the memory cell to which the first data is written and generate a second voltage, and determine data stored in the memory cell at the time of the first read based on the first voltage and the second voltage, wherein when writing the first data, the first circuit electrically sets a generation unit configured to generate the second voltage in a floating state. | 2018-09-27 |
20180277187 | COMPUTER SYSTEM AND MEMORY DEVICE - According to one embodiment, a system includes: a device including a memory cell array, the device configured to execute first read operation of a first read method and second read operation of a second read method on the memory cell array; a processor configured to receive a first data from the device, the first data from a selected region in the memory cell array by the first read operation, configured to execute first calculation processing using the first data during the second read operation to the selected region, and configured to acquire a result of the first calculation processing by a first signal based on a comparison result of the first data and a second data, the first signal indicating that the first data is valid, and the second data from the selected region by the second read operation. | 2018-09-27 |
20180277188 | MEMORY DEVICE - According to one embodiment, a memory device includes a memory cell; and a first circuit configured to perform first read for the memory cell and generate a first voltage, write first data to the memory cell that has undergone the first read, perform second read for the memory cell to which the first data written and generate a second voltage, generate a first current based on the first voltage, generate a second current based on the second voltage, and add a third current to one of the first current and the second current, thereby determining data stored in the memory cell at the time of the first read. | 2018-09-27 |
20180277189 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a first memory cell having a first variable resistance element, a second memory cell having a second variable resistance element, and a first circuit which controls writing to the first memory cell and the second memory cell. The first circuit receives a fir command instructing writing to the first memory cell, after receiving the first command, receives a second command instructing writing to the second memory cell, and after receiving the second command, performs writing to the second memory cell when performing writing to the first memory cell. | 2018-09-27 |
20180277190 | THERMALLY-ASSISTED SPIN TRANSFER TORQUE MEMORY WITH IMPROVED BIT ERROR RATE PERFORMANCE - Embodiments of the invention are directed to a magnetic tunnel junction (MTJ) storage element having a reference layer formed from a reference layer material having a fixed magnetization direction, along with a free layer formed from a free layer material having a switchable magnetization direction. The MTJ is configured to receive a write pulse having a write-pulse and spin-transfer-torque (WP-STT) start time, a WP-STT start segment duration and a write pulse duration. The WP-STT start segment duration is less than the write pulse duration. The fixed magnetization direction is configured to form an angle between the fixed magnetization direction and the switchable magnetization direction. The angle is sufficient to generate spin torque electrons in the reference layer material at the WP-STT start time. The spin torque electrons generated in the reference layer material is sufficient to initiate switching of the switchable magnetization direction at the WP-STT start time. | 2018-09-27 |
20180277191 | FERROELECTRIC MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A ferroelectric memory device according to an embodiment includes a substrate, a ferroelectric gate insulation layer disposed along an inner wall of a trench formed in the substrate, and a gate electrode layer disposed on the ferroelectric gate insulation layer. The ferroelectric gate insulation layer has a variable thickness on the inner wall of the trench. | 2018-09-27 |
20180277192 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a memory cell including a transistor formed of an oxide semiconductor, an insulation film, and a control electrode, and a capacitance element configured to store a charge, the memory cell being configured to store a coupling weight of a neuron model by a charge amount accumulated in the capacitance element; and a control circuit configured to output a signal as a sum of a product between input data of the memory cell and the coupling weight. | 2018-09-27 |
20180277193 | MEMORY CONTROLLER FOR STROBE-BASED MEMORY SYSTEMS - An integrated circuit (IC) memory controller is disclosed. The memory controller includes a receiver to receive a strobe signal and provide an internal strobe signal. An adjustable delay circuit delays an enable signal to generate a delayed enable signal. A gate circuit generates a gated strobe signal using the delayed enable signal that masks transitions of the internal strobe signal that occur prior to a valid region of the internal strobe signal. A sample circuit samples data using the gated strobe signal. | 2018-09-27 |
20180277194 | TIMING CONTROL FOR INPUT RECEIVER - Apparatuses for receiving an input signal in a semiconductor device are described. An example apparatus includes a signal receiver that receives information signal; a control circuit that provides a plurality of control signals; and a signal receiver replica circuit that receives a first reference signal. The signal receiver replica circuit includes a plurality of receivers. Each receiver of the plurality of receivers receives the first reference signal and a corresponding control signal of the plurality of control signals, and further provides an output signal. | 2018-09-27 |
20180277195 | DOUBLE DATA RATE (DDR) MEMORY CONTROLLER APPARATUS AND METHOD - In accordance with one embodiment, an apparatus is provided, comprising: a double data rate (DDR) memory controller that, when in operation, causes the apparatus to: generate a core clock; generate a capture clock; receive a data (DQ) signal that is driven by a DDR memory, or a signal derived from the DQ signal; clock a first core domain register, based, at least in part, on the capture clock; clock a second core domain register, based, at least in part, on the core clock; and set a delay of a core clock delay element, utilizing at least one of: the first core domain register, a signal derived from the first core domain register, the second core domain register, or a signal derived from the second core domain register; wherein the double data rate (DDR) memory controller is configured such that the delay of the core clock delay element is set during a power-on initialization calibration operation. | 2018-09-27 |
20180277196 | DOUBLE DATA RATE SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY AND OUTPUT DRIVING CIRCUIT THEREOF - A double data rate synchronous dynamic random access memory includes a control circuit and an output driving circuit. The control circuit provides a first voltage, a second voltage, a third voltage and a fourth voltage. The output driving circuit couples to the control circuit and includes a pull-up circuit, a pad and a pull-down circuit. When a voltage of the pad rises from the fourth voltage to the first voltage, a voltage between a drain and a source of a second driving transistor in the pull-down circuit is between the third voltage and the fourth voltage. When a voltage of the pad falls from the first voltage to the fourth voltage, a voltage between a drain and a source of a first driving transistor in the pull-up circuit is between the first voltage and the second voltage. | 2018-09-27 |
20180277197 | SRAM CELL - A SRAM cell, including, in a stack of layers, transistors including at least first and second access transistors connected to a word line, the first access transistor coupling a first bit line and a first storage node and the second access transistor coupling a second bit line and a second storage node, and a flip-flop including a first conduction transistor coupling the first storage node to a source of a first reference potential and having its gate coupled to the second storage node and a second conduction transistor coupling the second storage node to the source of the first reference potential and having its gate coupled to the first storage node. | 2018-09-27 |
20180277198 | SEMICONDUCTOR DEVICE AND APPARATUS INCLUDING THE SAME - A semiconductor device includes a programmable memory array comprising plural memory units disposed above a substrate. One of the memory units comprises a gate electrode disposed above the substrate, a conductive portion spaced apart from the gate electrode, and a dielectric layer contacting the conductive portion and separated from the gate electrode, and the dielectric layer defining a threshold voltage of the related memory unit, wherein at least two of the memory units have different threshold voltages. | 2018-09-27 |
20180277199 | SEMICONDUCTOR MEMORY WITH RESPECTIVE POWER VOLTAGES FOR MEMORY CELLS - A device is disclosed that includes a plurality of first memory cells, a plurality of second memory cells, a power circuit, and a header circuit. The power circuit us configured to provide the first power voltage for the plurality of first memory cells, and to provide the second power voltage, that is independent from the first power voltage, for the plurality of second memory cells. The header circuit is configured to provide, during the write operation, the first voltage smaller than the first power voltage, the second power voltage, or the combination thereof, for corresponding memory cells of the plurality of first memory cells and the plurality of second memory cells. | 2018-09-27 |
20180277200 | METHODS OF OPERATING A MEMORY WITH REDISTRIBUTION OF RECEIVED DATA - Methods of operating a memory include receiving data for programming to a plurality of memory cells of the memory, redistributing the received data in a reversible manner, programming the redistributed data to the plurality of memory cells, and programming respective second data to each memory cell of the plurality of memory cells containing the redistributed data, wherein the respective second data for any memory cell of the plurality of memory cells has a same data value as the respective second data for each remaining memory cell of the plurality of memory cells. | 2018-09-27 |
20180277201 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a first memory cell having a first end connected to a first wiring and a second end connected to a second wiring and a second memory cell having a first end connected to the first wiring and a second end connected to a third wiring. A sense amplifier is configured to: sense a first current flowing in the first wiring when a first voltage is applied to the second and third wirings and a second voltage, larger than the first voltage, is applied to the first wiring; and sense a second current flowing in the first wiring when a third voltage larger than the second voltage is applied to the first wiring, the first voltage to the second wiring, and the second voltage to the third wiring. The sense amplifier reads data according to a difference between the first current and the second current. | 2018-09-27 |
20180277202 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a first conductor extending in a first direction and a second conductor extending in a second direction and disposed above the first conductor in a third direction. Third and fourth conductors extend in the first direction and adjacent to each other in the second direction. The third and fourth conductors are above the second conductor. A fifth conductor includes a variable resistance unit and is between the first and second conductors. A sixth conductor includes a variable resistance unit and is between the third and second conductors. A seventh conductor includes a variable resistance unit and is between the fourth and second conductors. A center point of the fifth conductor along a width of the fifth conductor is does not fully overlap with either of the sixth or seventh conductors along the third direction. | 2018-09-27 |
20180277203 | STORAGE DEVICE AND CONTROL METHOD THEREOF - A storage device includes a first conductive layer, a second conductive layer, a first variable resistance layer, and a control circuit. The control circuit is configured to apply a first voltage between the first conductive layer and the second conductive layer for a first time and apply a second voltage less than the first voltage for a second time longer than the first time after the application of the first voltage when the first variable resistance layer is in a first high resistance state. The control circuit is further configured to apply the first voltage between the first conductive layer and the second conductive layer and apply a third voltage less than the second voltage between the first conductive layer and the second conductive layer after the application of the first voltage when the first variable resistance layer is in a first low resistance state. | 2018-09-27 |
20180277204 | MEMORY SYSTEM - A memory system according to one embodiment includes a memory device including a memory cell with a variable resistance value and a first controller, and a second controller. The first controller is configured to compare first read data read from the memory cell when a first voltage is applied to the memory cell with second read data read from the memory cell when a second voltage is applied to the memory cell. The first voltage is different from the second voltage. The first read data has a first value or a second value with the first value being different from the second value. The second read data has the first value or the second value. | 2018-09-27 |
20180277205 | MEMORY DEVICE AND CONTROL METHOD THEREOF - A memory device includes a control circuit configured to (i) start a first application of a first voltage between a first conductive layer and a third conductive layer, (ii) start a second application of the first voltage between a second conductive layer and the third conductive layer after a lapse of a first delay time since the start of the first application of the first voltage, and (iii) start an application of a second voltage, which is smaller than the first voltage, between the first conductive layer and the third conductive layer after a lapse of a second delay time since the start of the second application of the first voltage between the second conductive layer and the third conductive layer. | 2018-09-27 |
20180277206 | OPERATING METHOD OF MEMORY DEVICE - An operating method of a memory device is provided. Using a statistical model, a resistance R | 2018-09-27 |
20180277207 | VARIABLE RESISTANCE MEMORY - A semiconductor device according to an embodiment includes a memory cell array and a drive circuit section. The memory cell array includes memory cells. The drive circuit section adapted to control a driving voltage to be supplied to the memory cells. The memory cells each including a first variable resistance film and a second variable resistance film connected in series to the first variable resistance film. The driving voltage of the second variable resistance film is different from the driving voltage of the first variable resistance film. | 2018-09-27 |
20180277208 | METHODS AND APPARATUS FOR PROGRAMMING BARRIER MODULATED MEMORY CELLS - A memory device is provided that includes a memory controller coupled to a memory cell including a barrier modulated switching structure. The memory controller is adapted to program the memory cell to a first programming state, and program the memory cell to one of a plurality of target programming states from the first programming state. | 2018-09-27 |
20180277209 | WRITING MULTIPLE LEVELS IN A PHASE CHANGE MEMORY - Structures and methods for a multi-bit phase change memory are disclosed herein. A method includes establishing a write-reference voltage that incrementally ramps over a write period. The increments of the write-reference voltage correspond to discrete resistance states of a storage cell of the multi-bit phase change memory. | 2018-09-27 |
20180277210 | WRITING MULTIPLE LEVELS IN A PHASE CHANGE MEMORY - Structures and methods for a multi-bit phase change memory are disclosed herein. A method includes establishing a write-reference voltage that incrementally ramps over a write period. The increments of the write-reference voltage correspond to discrete resistance states of a storage cell of the multi-bit phase change memory. | 2018-09-27 |
20180277211 | METHOD, SYSTEM AND DEVICE FOR COMPLEMENTARY NON-VOLATILE MEMORY DEVICE OPERATION - Disclosed are methods, systems and devices for operation of dual non-volatile memory devices. In one aspect, a pair of non-volatile memory device coupled in series may be placed in complementary memory states any one of multiple memory states in write cycles by controlling a current and a voltage applied to terminals of the non-volatile memory device. | 2018-09-27 |
20180277212 | FERROELECTRIC MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - The ferroelectric memory device includes a substrate having a base doped region doped with a dopant of a first conductivity type and a trench disposed in the base doped region having an inner wall with a bottom and sidewalls. Also, the ferroelectric memory device includes a ferroelectric gate insulation layer, disposed along the inner wall of the trench, a gate electrode layer disposed on the ferroelectric gate insulation layer inside the trench, and a source region and a drain region, disposed in the substrate at respective ends of the trench and doped with a dopant of a second conductivity type. The ferroelectric memory device also includes a conductive well region, doped with a dopant of the second conductivity type. The conductive well region is disposed in the base doped region and spaced apart from the ferroelectric gate insulation layer. | 2018-09-27 |
20180277213 | SEMICONDUCTOR INTEGRATED CIRCUIT - According to one embodiment, a semiconductor integrated circuit includes a ROM, an SRAM, a memory and a selector. The ROM stores initialization data. At least part of the initialization data is writable to the SRAM. The memory stores information indicating whether data is written to the SRAM. The selector outputs one of data supplied from the SRAM and data supplied from the ROM in accordance with the information stored in the memory. | 2018-09-27 |
20180277214 | STORAGE DEVICE AND STORAGE METHOD - A storage device includes a data memory unit and a status memory unit. The data memory unit includes a pair of flash memory cells to be read by a complementary read mode, and 1-bit data is stored therein by the pair of flash memory cells. The status memory unit includes a flash memory cell to be read by a reference read mode, and a status flag is stored therein by the flash memory cell. | 2018-09-27 |
20180277215 | STORAGE DEVICE AND ELECTRONIC APPARATUS USING THE SAME - A SIM card is irradiated with quanta such as photons, electrons, quarks, or neutrinos over a predetermined cycle to be provided with quantum information, and the SIM card is inserted into a mobile information terminal having a liquid crystal screen. In response to the mobile information terminal being energized, energy of the quantum information is provided to the liquid crystal screen, causing resonance between the SIM card and the molecules (atomic nuclei) of liquid crystal, resulting in quantum energy being radiated to outside from the liquid crystal screen. | 2018-09-27 |
20180277216 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes: a first memory cell provided in a first semiconductor chip; a first output buffer circuit configured to output data of the first memory cell outside, the first output buffer circuit provided in the first semiconductor chip; a first calibration control circuit configured to calibrate an impedance of the first output buffer circuit, a first terminal connected to the first calibration control circuit, the first calibration control circuit provided in the first semiconductor chip; and a first resistance element connected to the first terminal, the first resistance element provided in the first semiconductor chip. | 2018-09-27 |
20180277217 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a plurality of blocks of memory cells, including first, second, and third blocks of a first group of blocks and fourth fifth and sixth blocks of a second group of blocks, a plurality of word lines for each of the blocks, a first decode circuit for the first group, and a second decode circuit for the second group. When the first block is selected, the first decode circuit transfers a first voltage to the word lines of the first block, transfers a second voltage lower than the first voltage to the word lines of the second block, and causes the word lines of the third block to go into an electrically floating state, and the second decode circuit causes the words lines of the fourth block, the fifth block, and the sixth block into the electrically floating state. | 2018-09-27 |
20180277218 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device includes a first memory cell electrically connected to a first bit line and a first word line, a second memory cell electrically connected to a second bit line and the first word line, and a first circuit configured to supply voltages to the first word line. During a reading operation to read a page of memory cells including the first memory cell and the second memory cell, the first circuit supplies a first voltage to the first word line while the first memory cell is selected as a read target during a first time period, and supplies a second voltage greater than the first voltage to the first word line while the second memory cell is selected as a read target during a second time period that is different from the first time period, and directly thereafter, supplies the first voltage to the first word line. | 2018-09-27 |
20180277219 | SEMICONDUCTOR MEMORY DEVICE - The present embodiment discloses a semiconductor memory device which includes a memory cell array, a signal pad, a first voltage pad, a first regulation circuit and a first operation circuit. The signal pad supplies an output signal associated with the memory cell array. The first voltage pad receives a first voltage. The first regulation circuit regulates a signal output from the signal pad. The first operation circuit operates the first regulation circuit. The first regulation circuit and the first operation circuit are provided between the signal pad and the first voltage pad. | 2018-09-27 |