39th week of 2012 patent applcation highlights part 62 |
Patent application number | Title | Published |
20120246416 | COMMUNICATION DEVICE AND CONTROL METHOD THEREOF - According to one embodiment, a communication device includes a first interface, a wireless communication unit, and a memory unit. The memory unit includes a first region used for first access from the first interface and a second region used for second access from the wireless communication unit. Writing to the second region by the first access and writing to the first region by the second access are inhibited. | 2012-09-27 |
20120246417 | INFORMATION PROCESSING SYSTEM, INFORMATION PROCESSING METHOD, AND NON-TRANSITORY COMPUTER READABLE MEDIUM STORING PROGRAM - An information processing system includes: a storage device that stores information including settings information which is configured to an information processing apparatus, attribute management information indicating whether each settings information item is limited information with an update limit to the settings information or non-limited information without an update limit to the settings information, and apparatus specification information for specifying the information processing apparatus; and an information processing apparatus including an input unit that reads information from the storage device when the storage device is connected, a determining unit that compares the apparatus specification information read by the input unit with the apparatus specification information for specifying the information processing apparatus which is stored in a storage unit and determines whether the apparatus settings information read by the input unit is identical to the apparatus settings information of the information processing apparatus, and an update unit that updates the settings information. | 2012-09-27 |
20120246418 | MEMORY ARCHITECTURE FOR DISPLAY DEVICE AND CONTROL METHOD THEREOF - A memory architecture for a display device and a control method thereof are provided. The memory architecture includes a display data memory and a memory controller. The display data memory includes N sub-memories and N×M arbiters, wherein N is a positive integer and M is a positive integer equal to or greater than 2. Each sub-memory includes M memory blocks divided by an address. Each M arbiters are coupled to the M memory blocks of each sub-memory. The memory controller, coupled to the N×M arbiters, generates N×M sets of request signals and output address signals according to a set of an input request signal and an input address signal, and transmits to the N×M arbiters to sequentially control the N×M arbiters. | 2012-09-27 |
20120246419 | CONCURRENT MEMORY BANK ACCESS AND REFRESH REQUEST QUEUING - An apparatus and system associated with memory are disclosed herein. In various embodiments, an apparatus may include first circuitry configured to queue pending refresh requests for a plurality of memory banks; and second circuitry coupled to the first circuitry and configured to set a refresh flag in response to a determination that a number of queued pending refresh requests for a memory bank from the plurality of memory banks exceeds a predetermined number. Other embodiments may be disclosed and/or claimed. | 2012-09-27 |
20120246420 | INTERACTING WITH DATA IN HIDDEN STORAGE - Unused storage space within a data storage is utilized to store data while effectively making it appear to the operating system, other programs, and the user that the space is still available or unused. The space used to store the hidden data remains available for use by the operating system, other programs and uses upon a request. File system requests are monitored such that the hidden storage area remains hidden from unauthorized processes as well as to restrict operations within the hidden storage area that are attempted by unauthorized processes. | 2012-09-27 |
20120246421 | System, Methods, and Apparatus for Subdividing Data for Storage in a Dispersed Data Storage Grid - An efficient method for breaking source data into smaller data subsets and storing those subsets along with coded information about some of the other data subsets on different storage nodes such that the original data can be recreated from a portion of those data subsets in an efficient manner. | 2012-09-27 |
20120246422 | SEMICONDUCTOR MEMORY DEVICE WHICH INCLUDES MEMORY CELL HAVING CHARGE ACCUMULATION LAYER AND CONTROL GATE - A semiconductor memory device includes a memory cell array, a power source circuit, a sense amplifier, a control circuit, and a processor. The memory cell array includes a nonvolatile memory cell. The power source circuit includes a first register and generates a voltage. The sense amplifier includes a second register, reads from the memory cell and amplifies the read data. The control circuit includes a third register and controls operations of the power source circuit and the sense amplifier. The processor controls the operations of the power source circuit, the sense amplifier and the control circuit by giving an instruction to the first to third registers. The control circuit decodes the instruction received at the third register so as to control the power source circuit and the sense amplifier directly based on a result of decoding. | 2012-09-27 |
20120246423 | Method and System for Data Replication - A method and system of replicating data where data is copied from a host server to a storage device in a first group of storage devices. A receipt is sent from the first group of storage devices to the host server when the data has been copied to all storage devices within the first group. The data is copied from the first group to at least one further group of storage devices. A receipt is sent from each further group of storage devices to the first group of storage devices when the data has been copied to all storage devices within each further group. | 2012-09-27 |
20120246424 | COMPUTER SYSTEM AND DATA BACKUP METHOD - The present invention proposes a computer system and data backup method which enable improvements in the response performance of a storage apparatus to a write request from a host apparatus. | 2012-09-27 |
20120246425 | STORAGE SYSTEM AND PERFORMANCE MANAGEMENT METHOD OF STORAGE SYSTEM - It is an object to use a storage region in an efficient manner and maintain a performance of a storage system. | 2012-09-27 |
20120246426 | METHOD FOR OPTIMIZING CLEANING OF MAPS IN FLASHCOPY CASCADES CONTAINING INCREMENTAL MAPS - A method for optimizing cleaning of maps in FlashCopy cascades includes determining whether a target disk of a map contains data unavailable to a downstream disk from an upstream disk in a FlashCopy cascade and detect whether the downstream disk has a copy of the data. Additionally, the method includes copying the data from the target disk to the downstream disk, if the target disk of the map contains data unavailable to the downstream disk from the upstream disk and the downstream disk does not have the copy of the data. Furthermore, the method includes copying the data from the target disk to the downstream disk, if the target disk of the map does not contain data unavailable to the downstream disk from the upstream disk or the downstream disk does have the copy of the data. Moreover, the method includes removing the map from the FlashCopy cascade. | 2012-09-27 |
20120246427 | MULTIPLE CASCADED BACKUP PROCESS - Provided are a method, system, and a computer program product handling a backup process. An instruction initiates a new backup from a source volume to a target volume using one of a plurality of backup processes. A cascade includes a cascade source volume and at least one cascade target volume, and a write to a storage location in one of the cascade volumes causes a copying of the storage location to be written in the cascade source volume to each of the cascade target volumes in the cascade according to a cascade order in which the at least one cascade target volume and the cascade source volume are linked in the cascade. The cascade is modified to include the target volume of the new backup in response to determining that there is an existing cascade, else a new cascade using the backup process of the new backup is created. | 2012-09-27 |
20120246428 | REDUCTION OF COMMUNICATION AND EFFICIENT FAILOVER PROCESSING IN DISTRIBUTED SHARED MEMORY-BASED APPLICATION - Various embodiments for reducing communication between cluster nodes and optimizing failover processing in a distributed shared memory (DSM)-based application by at least one processor device are provided. In one embodiment, for a data structure operable on a DSM, a read-mostly portion is maintained in a single copy sharable between the cluster nodes while an updatable portion is maintained in multiple copies, each of the multiple copies dedicated to a single cluster node. | 2012-09-27 |
20120246429 | STORAGE SYSTEM AND REMOTE COPY CONTROL METHOD FOR STORAGE SYSTEM - A storage system for managing a plurality of asynchronous remote copy proceedings between a plurality of first storage control devices and a plurality of second storage control devices, wherein each of a plurality of second storage control devices stores one or more update data corresponding to one or more update data related information including the same update reflection time information with the one that is received or older update reflection time information than this in a one or more second logical volume and changes status of the one or more second logical volumes to suspend status. | 2012-09-27 |
20120246430 | STORAGE SYSTEM AND DATA RELOCATION CONTROL DEVICE - The present invention achieves data relocation in accordance with a user's policies, in an environment where a plurality of storage devices coexist. The volumes belonging to storage devices A-D are managed virtually integrally. A host recognizes a plurality of storage devices A-D as a single virtual storage device. The user is able to group arbitrarily each volume belonging to the storage system, as a plurality of storage layers | 2012-09-27 |
20120246431 | ELECTRONIC EQUIPMENT SYSTEM AND STORAGE DEVICE - In electronic equipment | 2012-09-27 |
20120246432 | METHODS, SYSTEMS, AND APPARATUS TO PREVENT MEMORY IMPRINTING - In one implementation, a data set including a plurality of data values having an order is stored at a memory having a plurality of memory locations. Each data value from the data set stored a current memory location of that data value from the plurality of memory locations. Each data value from the data set is periodically moved from the current memory location of that data value from the plurality of memory locations to a next memory location of that data value from the plurality of memory locations. The next memory location of each data value from the plurality of memory locations is the current memory location of that data value from the plurality of memory locations after the moving. The plurality of data values is then provided in the order to a client in response to a request for the data set. | 2012-09-27 |
20120246433 | TECHNIQUES TO MANAGE A COLLECTION OF OBJECTS IN HETEROGENEOUS ENVIRONMENTS - Techniques to perform garbage collection in an environment where more than one software programming language is in use are described. A technique may include creating a managed proxy object in one language that creates an unmanaged object in memory in a different language. A collection of nodes is generated and maintained, where a node comprises: a reference to the managed proxy object, and a reference to the unmanaged object. A count of the nodes in the collection is maintained. When the count exceeds a threshold, the collection is traversed, and garbage collection is performed on any unmanaged object in a node when the managed proxy object in the same node has been collected. Other embodiments are described and claimed. | 2012-09-27 |
20120246434 | SYSTEM AND METHOD FOR DECODING COMMANDS BASED ON COMMAND SIGNALS AND OPERATING STATE - A system and method for decoding command signals that includes a command decoder configured to generate internal control signals to perform an operation based on the command signals and an operating state. The same combination of command signals can request different commands depending on the operating state. A command is selected from a first set of operations according to the command signals when the memory system is in a first operating state and a command is selected from a second set of operations according to the command signals when the memory system is in a second operating state. | 2012-09-27 |
20120246435 | STORAGE SYSTEM EXPORTING INTERNAL STORAGE RULES - A data storage method includes, in a memory controller that accepts memory access commands from a host for execution in one or more memory units, holding a definition of a policy to be applied by the memory controller in the execution of the memory access commands in the memory units. The policy is reported from the memory controller to the host so as to cause the host to format memory access commands based on the reported policy. | 2012-09-27 |
20120246436 | COMBINING MEMORY PAGES HAVING IDENTICAL CONTENT - In a device having a memory accessed as multiple pages, two or more pages of the multiple pages having identical content are identified. While the two or more pages are being identified, other processes running in the device are allowed to use the two or more pages, including being allowed to change cache attributes of each of the two or more pages. The two or more pages are combined into a single combined page (e.g., a newly allocated page of the multiple pages), and a process page record having multiple entries pointing to the multiple pages is updated so that entries that previously pointed to one of the two or more pages instead point to the single page. | 2012-09-27 |
20120246437 | METHOD AND APPARATUS FOR USING UNUSED BITS IN A MEMORY POINTER - The disclosed embodiments provide a system that uses unused bits in a memory pointer. During operation, the system determines a set of address bits in a address space that will not be needed for addressing purposes during program operation. Subsequently, the system stores data associated with the memory pointer in this set of address bits. The system masks this set of address bits when using the memory pointer to access the memory address associated with the memory pointer. Storing additional data in unused pointer bits can reduce the number of memory accesses for a program and improve program performance and/or reliability. | 2012-09-27 |
20120246438 | CAPACITY MANAGEMENT IN DEDUPLICATION STORAGE SYSTEMS - A deduplication storage capacity is estimated as a function of an expected deduplication ratio, the expected deduplication ratio being a combined average of a current deduplication ratio and a configured deduplication ratio, the current deduplication ratio depending on the data currently stored in the deduplication storage, and the configured deduplication ratio being an estimate made at a configuration stage of the deduplication computing storage environment. | 2012-09-27 |
20120246439 | METHOD AND SYSTEM FOR MEASURING THE PERFORMANCE OF A COMPUTER SYSTEM ON A PER LOGICAL PARTITION BASIS - Disclosed are a method and system for measuring the performance of individual logical partitions of a logically partitioned computer system. Preferably, the method and system both hardware and firmware to allow measurement samples to be collected only for user specified zones of interest. In one embodiment, the method comprises the steps of specifying a Zone or Zones of interest (a Zone being a logical partition), collecting measurement samples only from the one or more specified Zones of interest, and measuring the performance of each of these Zones using only the measurement samples collected from said each of the Zones. | 2012-09-27 |
20120246440 | CO-STORAGE OF DATA STORAGE PAGE LINKAGE, SIZE, AND MAPPING - A logical page identity for a logical page containing data storage application data can be mapped to a physical storage page location in a storage where the data of the logical page are stored. The mapping as well as additional page data can be retained within a persistence layer accessible to the data storage application. The additional page data can include at least one of a size of the page and a next page linkage indicating a second page that follows the page in a page sequence of related pages. The retained mapping and additional page data can be retrieved from the persistence layer to initiate a page operation on the related pages, and the page operation can be executed on the related pages based on the retrieved mapping and additional page data. Related methods, systems, and articles of manufacture are also disclosed. | 2012-09-27 |
20120246441 | INFORMATION PROCESSOR AND MULTI-CORE SYSTEM - According to one embodiment, an information processor includes an operator and an address protector. The address protector includes a register access interface, an address table, and an access determination module. The register access interface is configured to receive address protection information from the operator. The address table is configured to store the received address protection information. The access determination module is configured to determine whether an access to an address specified by the operator is allowable based on the address protection information, and configured to output an interrupt signal to the operator when the access is unallowable. | 2012-09-27 |
20120246442 | STORAGE DEVICE AND METHOD FOR UPDATING DATA IN A PARTITION OF THE STORAGE DEVICE - A storage device and method for updating data stored in a partition of the storage device are provided. In one embodiment, a storage device is provided that contains a logical-to-physical address map and a memory with a first partition storing original data and a second partition. The storage device receives from a host device (i) a command to write updated data to a first logical address and (ii) a signature for verifying integrity of the updated data, wherein the first logical address is mapped to a physical address of the first partition. The storage device then stores the updated data in the second partition instead of the first partition and attempts to verify the signature of the updated data. If the attempt to verify the signature is successful, the storage device updates the logical-to-physical address map to map the first logical address to a physical address of the second partition. | 2012-09-27 |
20120246443 | INDEPENDENT MANAGEMENT OF DATA AND PARITY LOGICAL BLOCK ADDRESSES - A data storage method includes identifying, in a set of data items associated with respective logical addresses for storage in a memory, a first subset of the logical addresses associated with the data items containing application data, and a second subset of the logical addresses associated with the data items containing parity information that has been calculated over the application data. The data items associated with the first identified subset are stored in one or more first physical memory areas of the memory, and the data items associated with the second identified subset are stored in one or more second physical memory areas of the memory, different from the first physical memory areas. A memory management task is performed independently in the first physical memory areas and in the second physical memory areas. | 2012-09-27 |
20120246444 | RECONFIGURABLE PROCESSOR, APPARATUS, AND METHOD FOR CONVERTING CODE - Provided is an apparatus and method capable of processing code to which a software pipelining is not applicable, in a CGA mode. The apparatus may include a processing unit that has a very long instruction word (VLIW) mode and a coarse-grained array (CGA) mode, and an adjusting unit configured to detect a target region to which software pipelining is not applicable, in code to be executed by the processing unit. The adjusting unit may selectively map the detected target region to one of the VLIW mode and the CGA mode according to a schedule length of the detected target region. | 2012-09-27 |
20120246445 | CENTRAL PROCESSING UNIT AND MICROCONTROLLER - A program data area | 2012-09-27 |
20120246446 | Dynamically Determining the Profitability of Direct Fetching in a Multicore Architecture - Technologies are generally described herein for determining a profitability of direct fetching in a multicore processor. The multicore processor may include a first and a second tile. The first tile may include a first core and a first cache. The second tile may include a second core, a second cache, and a fetch location pointer register (FLPR). The multicore processor may migrate a thread executing on the first core to the second core. The multicore processor may store a location of the first cache in the FLPR. The multicore processor may execute the thread on the second core. The multicore processor may identify a cache miss for a block in the second cache. The multicore processor may determine whether a profitability of direct fetching of the block indicates direct fetching or directory-based fetching. The multicore processor may perform direct fetching or directory-based fetching based on the determination. | 2012-09-27 |
20120246447 | Region-Weighted Accounting of Multi-Threaded Processor Core According to Dispatch State - According to one embodiment of the present disclosure, an approach is provided in which a thread is selected from multiple active threads, along with a corresponding weighting value. Computational logic determines whether one of the multiple threads is dispatching an instruction and, if so, computes a dispatch weighting value using the selected weighting value and a dispatch factor that indicates a weighting adjustment of the selected weighting value. In turn, a resource utilization value of the selected thread is computed using the dispatch weighting value. | 2012-09-27 |
20120246448 | MEMORY FRAGMENTS FOR SUPPORTING CODE BLOCK EXECUTION BY USING VIRTUAL CORES INSTANTIATED BY PARTITIONABLE ENGINES - A system for executing instructions using a plurality of memory fragments for a processor. The system includes a global front end scheduler for receiving an incoming instruction sequence, wherein the global front end scheduler partitions the incoming instruction sequence into a plurality of code blocks of instructions and generates a plurality of inheritance vectors describing interdependencies between instructions of the code blocks. The system further includes a plurality of virtual cores of the processor coupled to receive code blocks allocated by the global front end scheduler, wherein each virtual core comprises a respective subset of resources of a plurality of partitionable engines, wherein the code blocks are executed by using the partitionable engines in accordance with a virtual core mode and in accordance with the respective inheritance vectors. A plurality memory fragments are coupled to the partitionable engines for providing data storage. | 2012-09-27 |
20120246449 | METHOD AND APPARATUS FOR EFFICIENT LOOP INSTRUCTION EXECUTION USING BIT VECTOR SCANNING - A method, apparatus and computer program product for performing efficient loop instruction execution using bit vector scanning is presented. A bit vector is scanned, each bit in the bit vector representing at least one of a feature and a conditional status. The presence of a bit of said bit vector set to a first state is detected. The bit is set to a second state. An instruction address for a routine corresponding to said bit set to a first state is looked up using a bit position of said bit that was set to a first state. The routine is executed. The scanning, said detecting, said setting and said using are repeated until there are no remaining bits of said bit vector set to said first state. | 2012-09-27 |
20120246450 | REGISTER FILE SEGMENTS FOR SUPPORTING CODE BLOCK EXECUTION BY USING VIRTUAL CORES INSTANTIATED BY PARTITIONABLE ENGINES - A system for executing instructions using a plurality of register file segments for a processor. The system includes a global front end scheduler for receiving an incoming instruction sequence, wherein the global front end scheduler partitions the incoming instruction sequence into a plurality of code blocks of instructions and generates a plurality of inheritance vectors describing interdependencies between instructions of the code blocks. The system further includes a plurality of virtual cores of the processor coupled to receive code blocks allocated by the global front end scheduler, wherein each virtual core comprises a respective subset of resources of a plurality of partitionable engines, wherein the code blocks are executed by using the partitionable engines in accordance with a virtual core mode and in accordance with the respective inheritance vectors. A plurality register file segments are coupled to the partitionable engines for providing data storage. | 2012-09-27 |
20120246451 | PROCESSING LONG-LATENCY INSTRUCTIONS IN A PIPELINED PROCESSOR - There is provided a method and processor for processing a thread. The thread comprises a plurality of sequential instructions, the plurality of sequential instructions comprising some short-latency instructions and some long-latency instructions and at least one hazard instruction, the hazard instruction requiring one or more preceding instructions to be processed before the hazard instruction is processed. The method comprises the steps of: a) before processing each long-latency instruction, incrementing by one, a counter associated with the thread; b) after each long-latency instruction has been processed, decrementing by one, the counter associated with the thread; c) before processing each hazard instruction, checking the value of the counter associated with the thread, and i) if the counter value is zero, processing the hazard instruction, or ii) if the counter value is non-zero, pausing processing of the hazard instruction until a later time. The processor includes means for performing steps a), b) and c) of the method. | 2012-09-27 |
20120246452 | Signature Update by Code Transformation - Embodiments described herein provide an apparatus, computer readable digital storage medium and method for producing an instruction sequence for a computation unit which can be controlled by a program which includes at least the instruction sequence. | 2012-09-27 |
20120246453 | METHOD AND APPARATUS FOR ENHANCING SCHEDULING IN AN ADVANCED MICROPROCESSOR - Apparatus and a method for causing scheduler software to produce code which executes more rapidly by ignoring some of the normal constraints placed on its scheduling operations and simply scheduling certain instructions to run as fast as possible, raising an exception if the scheduling violates a scheduling constraint, and determining steps to be taken for correctly executing each set of instructions about which an exception is raised. | 2012-09-27 |
20120246454 | ELECTRONIC DEVICE AND METHOD FOR CONTROLLING TEST PROCESS - In a method controls a test process of an electronic device, a booting mode of a test program is set as a non-preemptible mode. The method invokes system service programs from a storage device of the electronic device upon the condition that an operating system (OS) of the electronic device is booted. The method further boots a user-defined service program, loads the test program to test a target object of the electronic device using the user-defined service program, then boots system application programs and user application programs of the electronic device. | 2012-09-27 |
20120246455 | PORT THROTTLING ACROSS AN OPERATING SYSTEM RESTART DURING A HOT UPGRADE - A method includes tagging, by a processor executing a first operating system kernel, a region of a volatile memory used by a first storage area network (SAN) adapter driver coupled to a SAN adapter, and decoupling the first SAN adapter driver from the SAN adapter. A boot of a second operating system kernel is then initiated while preserving in the tagged region of the volatile memory contents stored therein. After the boot, a second SAN adapter driver is then coupled to the SAN adapter. | 2012-09-27 |
20120246456 | MEMORY TAGGING AND PRESERVATION DURING A HOT UPGRADE - A method includes tagging, by a processor executing a first operating system kernel, a region of a volatile memory coupled to the processor, and initiating a boot of a second operating system kernel while preserving in the volatile memory contents stored therein. Following the boot of the second operating system kernel, a set of parameters referencing the tagged region is retrieved from the volatile memory, and the tagged region is then used, based on the retrieved set of parameters. | 2012-09-27 |
20120246457 | BARE METAL MACHINE RECOVERY - Provided herein are systems and methodologies for bare metal machine restoration of a client computing environment over a network-based backup system. System recovery can be performed by performing a network boot from a predetermined server or set of servers on the Internet and/or an associated local network, followed by retrieving information relating to an operating system and/or environment of a system being recovered, such as incremental or full operating system images. Upon retrieval of information, the information can be used to conduct a full restore of the operating environment of the computing device. Additionally, a user can restore personal or other system data following rebuilding of the system operating environment. A cloud-based structure is provided herein as well as a hybrid peer-to-peer/cloud-based structure, wherein information used in a restore can be obtained from a global network location (e.g., cloud server(s)) and/or from one or more local peers. | 2012-09-27 |
20120246458 | POWER OPTIMIZATION ON A THIN CLIENT DEVICE - Power allocated to a plurality of external ports of a thin client device is optimized based on power available to the thin client device that interoperates with a host device. A determination is made as to available power for the thin client device. Operational states of a plurality of external ports of the thin client device are configured based on the available power and operational settings for the thin client device. These operational settings could be user or administrator configured, pre-configured into the thin client device, or a combination thereof. | 2012-09-27 |
20120246459 | DYNAMIC CONFIGURATION OF A HOME MULTIPROCESSOR SYSTEM - A multiprocessor system used in home environment includes multiple processors that run different real-time applications. A dynamic configuration system runs on the multiple processors and includes a device manager, configuration manager, and data manager. The device manager automatically detects and adds new devices to the multiprocessor system, and the configuration manager automatically reconfigures the real-time applications. The data manager identifies the type of data generated by the new devices and identifies which devices in the multiprocessor system are able to process the data. | 2012-09-27 |
20120246460 | Encryption device and method for controlling download and access operations performed to a mobile terminal - An encryption device and method for controlling download and access operations performed to a mobile terminal are disclosed. A switch circuit ( | 2012-09-27 |
20120246461 | SYSTEM AND METHOD FOR SECURING WIRELESS DATA - Systems and methods for operation upon a data processing device for handling secure data stored on the device. The device is configurable to communicate over a data channel with an external security information source. User identification information is received from the external security information source which identifies a user of the device. The device, based upon the received user identification information, determines whether the secure data stored on the device is to be accessed by a user of the device. | 2012-09-27 |
20120246462 | SYSTEM AND METHODS FOR PROVIDING LIVE STREAMING CONTENT USING DIGITAL RIGHTS MANAGEMENT-BASED KEY MANAGEMENT - In the present disclosure, a DRM (in this case IPRM) system may be used to deliver media content keys to a player device in a live streaming environment and take advantage of all DRM related functionalities that come with it, such as proximity control, copy protection enforcement and rights verification. A playlist may be used to deliver a key identifier for encrypted live streaming content. | 2012-09-27 |
20120246463 | SYSTEMS AND METHODS FOR IMPLEMENTING TRANSPARENT ENCRYPTION - A method of providing transparent encryption for a web resource includes a key manager receiving an encryption key policy; receiving user identifiers and resource locators; defining an access control list based the user identifiers; generating an encryption key and a key identifier for a first resource locator; and establishing a secure communication channel between first and second watchdog modules. The method also includes the watchdog sending encryption information using the secure communication channel. The method also includes a transparent encryption module storing the encryption key and the access control list in protected memory; receiving an input comprising a request to access the first resource stored in the web resource; determining that the user identifier is included in the access control list; encrypting data using the encryption key; and decrypting data using the encryption key. | 2012-09-27 |
20120246464 | METHOD, SYSTEM AND APPARATUS FOR PROTECTING A BSF ENTITY FROM ATTACK - A method, system and apparatus for protecting a bootstrapping service function (BSF) entity from attack includes: a first temporary identity and a second temporary identity are generated after a BSF entity performs a mutual authentication with a user equipment (UE) by using an initial temporary identity sent from the UE; the BSF entity receives a re-authentication request carrying the first temporary identity from the UE; and the UE sends a service request carrying the second temporary identity to a network application function (NAF) entity. The present disclosure prevents attackers from intercepting the temporary identity at the Ua interface and using the temporary identity to originate a re-authentication request at the Ub interface, thus protecting the BSF entity from attack and avoiding unnecessary load on the BSF entity and saving resources. | 2012-09-27 |
20120246465 | INCORPORATING DATA INTO CRYPTOGRAPHIC COMPONENTS OF AN ECQV CERTIFICATE - During generation of an implicit certificate for a requestor, a certificate authority incorporates information in the public-key reconstruction data, where the public-key reconstruction data is to be used to compute the public key of the requestor. The information may be related to one or more of the requestor, the certificate authority, and the implicit certificate. The certificate authority reversibly encodes the public-key reconstruction data in the implicit certificate and sends it to the requestor. After receiving the implicit certificate from the certificate authority, the requestor can extract the incorporated information from the public-key reconstruction data. The implicit certificate can be made available to a recipient, and the recipient can also extract the incorporated information. | 2012-09-27 |
20120246466 | Flexible System And Method To Manage Digital Certificates In A Wireless Network - An infrastructure is provided for managing the distribution of digital certificates for network security in wireless backhaul networks. In embodiments, a root certificate management system (root CMS) processes requests for digital certificates, issues root certificates, automatically authenticates surrogate certificate management systems (sur-CMSs), and automatically processes certificate requests and issues certificate bundles to sur-CMSs that are successfully authenticated. The infrastructure includes sur-CMSs to which are assigned base stations within respective regions. Each sur-CMS automatically authenticates its own base stations and automatically processes certificate requests and issues certificate bundles to base stations that are successfully authenticated. A certificate bundle issued to a base station includes a digital certificate, signed by the issuing sur-CMS, of a public key of such base station, and at least one further digital certificate, including a self-signed certificate of the root CMS. | 2012-09-27 |
20120246467 | Verifying Cryptographic Identity During Media Session Initialization - An authentication agent may cryptographically identify a remote endpoint that sent a media initialization message even though intermediate devices may modify certain fields in the message after a signature is inserted. The originating endpoint's agent may create the signature over some fields of the message using an enterprise network's private key. The agent may insert the signature into the message and send the message to a recipient endpoint's authentication agent. The recipient agent may verify the signature, receive a certificate including a second public key, and challenge the identity of the originating endpoint in order to confirm that identity. This challenge may request a confirmation that the originating endpoint knows the private key corresponding to the second public key and may occur while running encrypted media at the endpoints. After the originating endpoint is authenticated, the endpoints may exchange encrypted and/or unencrypted media. | 2012-09-27 |
20120246468 | System, Method, and Apparatus for Performing Reliable Network, Capability, and Service Discovery - A system, method, and apparatus are provided for performing reliable network, capability, and service discovery. A method may include providing for transmission of a request for signed access point information. The request may be provided for transmission prior to authenticating with an access point when authentication is performed or prior to associating with an access point when authentication is not performed. The method may further include receiving a response including signed access point information. The method may additionally include verifying the signed access point information using a digital certificate. The method may also include selecting the access point for communication based in least in part on the verified signed access point information. A corresponding system and apparatus is also provided. | 2012-09-27 |
20120246469 | MASTER KEY TRUST GRANTS AND REVOCATIONS FOR MINOR KEYS - A method and apparatus is provided that allows code signed by a master key to grant trust to an arbitrary second key, and also allows code, referred to as an antidote and also signed by the master key to revoke permanently the trust given to the second key. | 2012-09-27 |
20120246470 | INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING SYSTEM, SOFTWARE ROUTINE EXECUTION METHOD, AND REMOTE ATTESTATION METHOD - Techniques for protecting memory locations within a stakeholder's engine according to the Multi-Stakeholder Model, and a protocol for remote attestation to a device supporting the Multi-Stakeholder Model that provides extra evidence of the identity of the three actors. | 2012-09-27 |
20120246471 | INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING SYSTEM, DISTRIBUTION METHOD, AND PROGRAM THEREOF - In order to assure security of classified information, in present invention, before data take-out, third and fourth distributed data are created from first and second distributed data, the first and the second distributed data are saved in a server, and the third and the fourth distributed data are used in take-out. | 2012-09-27 |
20120246472 | SYSTEM AND METHOD FOR SECURED BACKUP OF DATA - A system and method of selectively providing encrypted data is provided. Embodiments of the invention may store data in encrypted form on a storage device. Embodiments of the invention may selectively provide encrypted or decrypted data to a requestor of data based on configuration or other parameters. A filter driver or other module or unit may examine a request for, or communication of data from the storage device and may determine if data is to be provided in encrypted or decrypted form. Decrypted data may be provided to a caching system. A filter driver or other module or unit may examine a request for, or communication of data from the caching system. Data provided from the caching system may be selectively encrypted based on configuration or other parameters. | 2012-09-27 |
20120246473 | ENCRYPTION INFORMATION TRANSMITTING TERMINAL - The communication unit transmits and receives a communication message. The authentication processor performs an authentication process for establishing the network connection by transmitting and receiving an authentication message to and from an authentication server through the communication unit. The encryption information generator generates an encryption key shared with the authentication server when the authentication process is successfully completed. The first message generator generates a first communication message instructing the destination device to acquire the encryption key from the authentication server. The second message generator generates a second communication message including data to be transmitted to the destination device. The communication unit transmits the first communication message to the destination device, encrypts the second communication message with the encryption key, and transmits an encrypted second communication message to the destination device. | 2012-09-27 |
20120246474 | SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR PRODUCT LICENSE MANAGEMENT - According to one aspect of the present disclosure, a method and technique for product license management for a clustered environment having a plurality of nodes is disclosed. The method includes unlocking a product on a first node of the plurality of clustered nodes; responsive to unlocking the product on the first node, indicating an unlocked status of the product on a shared storage device accessible to the plurality of clustered nodes; and transmitting a self-unlock message from the first node to remaining nodes of the cluster to enable the remaining nodes of the cluster to self-unlock the product on the respective remaining nodes based on the status indication of the shared storage device. | 2012-09-27 |
20120246475 | CENTRAL AND IMPLICIT CERTIFICATE MANAGEMENT - Facilitating management of digital certificates is addressed. More specifically, digital certificates as well as public and private keys can be stored in a centrally accessible location and dynamically acquired from the location as needed. Additionally, binding of digital certificates and associated keys can be implicit and determined as a function of a host name provided during protocol negotiation, for example. | 2012-09-27 |
20120246476 | MULTI-APPLICATION SMART CARD, AND SYSTEM AND METHOD FOR MULTI-APPLICATION MANAGEMENT OF SMART CARD - A multi-application smart card and a multi-application management system and method for the smart card are provided. The multi-application smart card comprises a management device for the application security domain, and the management device is use to manage and maintain the application security domains in the multi-application smart card, and the application security domains comprise a plurality of issuer application security domains which share the control right of the multi-application smart card. Optionally, the application security domains also comprise at least one cardholder application security domain which is subordinate to the issuer application security domain that creates the cardholder application security domain, and wherein the at least one cardholder application security domain is used to manage and maintain the applications created by the cardholder. | 2012-09-27 |
20120246477 | Method for Validating a Road Traffic Control Transaction - A method for validating a road traffic control transaction. The method includes: storing a cryptographic key assigned to a transaction receiver, in the transaction receiver; recording an image of a vehicle; reading an identification of the vehicle in the recorded image by OCR and generating a control transaction thereof in the control station; generating a random key and encrypting the recorded image into authentication data with the random key and the cryptographic key in the control station; transmitting the recorded image, the control transaction, the random key and the authentication data to the transaction receiver; in the transaction receiver, encrypting the received recorded image into nominal authentication data with the received random key and the stored cryptographic key; and comparing the received authentication data with the nominal authentication data. The received control transaction is then validated when the received authentication data and the nominal authentication data are identical. | 2012-09-27 |
20120246478 | INFORMATION SHARING SYSTEM, COMPUTER, PROJECT MANAGING SERVER, AND INFOMATION SHARING METHOD USED IN THEM - A project managing unit | 2012-09-27 |
20120246479 | PRIMITIVE FUNCTIONS FOR USE IN REMOTE COMPUTER MANAGEMENT - The invention facilitates remote management of a computer via a network. Remote computer management capability can be expanded beyond that previously available through the addition of one or more new primitive functions that can be performed on a managed computer. | 2012-09-27 |
20120246480 | Method and Arrangement for Enabling Play-Out of Media - Methods and arrangements for enabling the use of a first device ( | 2012-09-27 |
20120246481 | VIRTUAL SUBSCRIBER IDENTITY MODULE - A mobile trusted platform (MTP) configured to provide virtual subscriber identify module (vSIM) services is disclosed. In one embodiment, the MTP includes: a device manufacturer-trusted subsystem (TSS-DM) configured to store and provide credentials related to a manufacturer of the MTP; a mobile network operator—trusted subsystem (MNO-TSS) configured to store and provide credentials related to a mobile network operator (MNO); and a device user/owner—trusted subsystem (TSS-DO/TSS-U) configured to store and provide credentials related to user of the MTP. The TSS-MNO includes a vSIM core services unit, configured to store, provide and process credential information relating to the MNO. The TSS-DO/TSS-U includes a vSIM management unit, configured to store, provide and process credential information relating to the user/owner of the MTP. The TSS-DO/TSS-U and the TSS-MNO communicate through a trusted vSIM service. | 2012-09-27 |
20120246482 | BUNDLE VERIFICATION - Systems, devices, and methods for modifying a signed bundle and verifying the modified bundle are disclosed. A signed bundle may be modified by removing a file specified in a server file list from a plurality of files in the bundle. The signed bundle comprises a catalog of files in the signed bundle and their associated hashes. The modified bundle includes the remaining files of the signed bundle that are not specified in the server file list and the catalog file of the signed bundle, the catalog signature of the signed bundle. The modified bundle may be verified by verifying the catalog signature of the modified signed bundle, and checking that the files specified in the catalog are either in the modified signed bundle or specified in the server file list. The hashes of the files in the modified signed bundle may also be checked to verify the modified signed bundle. | 2012-09-27 |
20120246483 | Authentication System With Time Attributes - An apparatus for managing access to a computing resource, comprises a clock configured to associate a datum arrival time with an authentication datum. The clock is further configured to calculate a datum elapsed time between a first datum arrival time associated with a first authentication datum and a second datum arrival time associated with a second authentication datum. The apparatus also comprises an authentication module configured to receive at least the first authentication datum and the second authentication datum; compare the datum elapsed time with a threshold elapsed time; and selectively provide access to a computing resource based at least in part upon successfully matching the received first authentication datum with a stored first authentication datum, successfully matching the received second authentication datum with a stored second authentication datum, and determining that the datum elapsed time exceeds the datum threshold time. | 2012-09-27 |
20120246484 | SECURE EXECUTION OF UNSECURED APPS ON A DEVICE - Given the volume of apps being developed and downloaded, performing operations to enable security for mobile devices, such as locating relevant classes and substituting different classes, can become very inefficient when done to a very high number of apps. In the invention, a device is enabled with an app security enforcement layer. The consumer can download unsecured apps and have the app execute on the phone in a secure manner, where potential data loss to the device, such as a smart phone or tablet, is minimized. To make the security wrapping process more efficient, an app template containing markers is created. This template is merged with data in an active user policy or is used to randomize or obfuscate the code to add more security. The process of security wrapping an app becomes more efficient. | 2012-09-27 |
20120246485 | ENCRYPTING METHOD, RECORDING MEDIUM OF ENCRYPTING PROGRAM, DECRYPTING METHOD, AND RECORDING MEDIUM OF DECRYPTING PROGRAM - An encrypting method including encrypting a first data segment of encryption target data on the basis of first key information, generating second key information on the basis of the first data segment by using a predetermined algorithm, and encrypting a second data segment of the encryption target data, which is different from the first data segment, on the basis of the second key information. | 2012-09-27 |
20120246486 | INFORMATION-PROCESSING DEVICE AND INFORMATION MANAGEMENT PROGRAM - [PROBLEMS] To prevent leak of information because loss or theft judgement is made whether or not read control information stored in a predetermined read control information storage area of an external storage is proper. If the judgment result shows that it is invalid, virtualized data stored in the external storage is decrypted, and genuine read control information virtualized in the virtualized data is extracted. Next judgement is made whether or not the extracted genuine read control information is proper. If the extracted genuine read control information is proper, the virtualized genuine data in the virtualized data along with the genuine read control information is made usable by decrypting and creating the virtualized data, and improper read control information is stored in the read control information storage area. | 2012-09-27 |
20120246487 | System and Method to Protect Java Bytecode Code Against Static And Dynamic Attacks Within Hostile Execution Environments - A method and system that provides secure modules that can address Java platform weaknesses and protect Java bytecode during execution time. The secure modules are implemented in C/C++ as an example. Because implementation of the security modules is made in C/C++, this enables use of security technology that secures C/C++ software code. | 2012-09-27 |
20120246488 | BORN ENCRYPTED OPTICAL DATA - A device for generating a born encrypted optical file includes a photovoltaic matrix for converting an optical image into a digital file. The digital file is a collection of digital data that has not been processed by any image processing logic and thus cannot be used to directly generate a reproduced image of the object. An encryption logic converts the digital file into an encrypted digital file that can be exported from the device to an authorized device to create a decrypted digital file. This decrypted digital file is capable of being used by a display logic to display an image of the object. | 2012-09-27 |
20120246489 | ENCRYPTING AND STORING CONFIDENTIAL DATA - Data storage circuitry for securely storing confidential data and a data processing apparatus for processing and storing the data and a method are disclosed. The data storage circuitry comprises: a data store comprising a plurality of data storage locations for storing data; an input for receiving requests to access the data store; renaming circuitry for mapping architectural data storage locations specified in the access requests to physical data storage locations within the data store; encryption circuitry for encrypting data prior to storing the data in the data store, the encryption circuitry being configured to generate an encryption key in dependence upon a physical data storage location the data is to be stored in; and decryption circuitry for decrypting data read from the data store, the decryption circuitry being configured to generate a decryption key in dependence upon the physical data storage location the data is read from. | 2012-09-27 |
20120246490 | TAMPERING MONITORING SYSTEM, PROTECTION CONTROL MODULE, AND DETECTION MODULE - Tampering monitoring system | 2012-09-27 |
20120246491 | SERVER SYSTEMS HAVING SEGREGATED POWER CIRCUITS FOR HIGH AVAILABILITY APPLICATIONS - According to one embodiment, a server system includes a motherboard partition that includes a motherboard and at least one processor coupled to the motherboard, with each processor being coupled to a memory. The server system also includes a storage partition that includes the memory, and a power circuit being capable of supplying current to the motherboard partition and the storage partition independently, the power circuit including at least two redundant power supplies in parallel in the power circuit, with each redundant power supply being capable of providing an amount of current necessary to operate the server system, and the motherboard partition is adapted to run a server OS. In another embodiment, an active cluster system may include two server systems, with the motherboard partition from each server system being capable of communicating with the other server system's storage partition even if power is removed from the other system's motherboard partition. | 2012-09-27 |
20120246492 | REMOTE POWER GROUP DISTRIBUTION CONTROL SYSTEM AND METHOD THEREFOR - A remote power group distribution control system has a host computer, at least one network server and multiple power distribution units (PDUs) connected to the host computer through the at least one network server. The host computer has a power distribution control module. Each PDU is connected with multiple power consuming equipment having identical or similar characteristics to supply an operating power and an uninterruptible power. When the power distribution control module is executed, the host computer searches the PDUs connected thereto through the at least one network server, displays all power-consuming equipment connected to each PDU, generates a group management window to assign each power-consuming equipment to a group, and remotely controls the power consuming equipment on a group basis. Accordingly, the present invention addresses a solution conveniently powering on or off remote power-consuming equipment pertaining to a group. | 2012-09-27 |
20120246493 | PROTOCOLS FOR REPORTING POWER STATUS OVER MULTIPLE BUSES - An automated power reporting system is provided in one aspect. The system includes one or more devices that can report or transmit power status information over a bus or network. A protocol component utilizes a generalized protocol to process or convert the power status information over the network in order to facilitate power management operations for a plurality of devices. In this manner, devices that send power information can interact and exploit personal computing resources in order to better help users manage limited power resources for their respective devices. | 2012-09-27 |
20120246494 | TEMPERATURE-PROFILED DEVICE FINGERPRINT GENERATION AND AUTHENTICATION FROM POWER-UP STATES OF STATIC CELLS - A method, system and computer program product for generating device fingerprints and authenticating devices uses initial states of internal storage cells after each of a number multiple power cycles for each of a number of device temperatures to generate a device fingerprint. The device fingerprint may include pairs of expected values for each of the internal storage cells and a corresponding probability that the storage cell will assume the expected value. Storage cells that have expected values varying over the multiple temperatures may be excluded from the fingerprint. A device is authenticated by a similarity algorithm that uses a match of the expected values from a known fingerprint with power-up values from an unknown device, weighting the comparisons by the probability for each cell to compute a similarity measure. | 2012-09-27 |
20120246495 | METHOD AND APPARATUS TO AUTHENTICATE A POWER SUPPLY - A power bus monitor for use in an electronic product is coupled to receive power from an external power supply. The power bus monitor includes a signal detector coupled to an output of the external power supply to receive and demodulate information encoded on the output of the external power supply into a sequence of bits. A decoder is coupled to receive the sequence of bits from the signal detector and decrypt the sequence of bits. A logical comparator is coupled to receive the sequence of bits decrypted by the decoder. The logical comparator is coupled to assert an authentication signal indicating the external power supply is authorized to provide power to the electronic product when the logical comparator recognizes the sequence of bits decrypted by the decoder as a key. | 2012-09-27 |
20120246496 | DEVICE FOR CONNECTING TWO APPARATUSES VIA AN ETHERNET LINK, AND DOCKING STATION FOR ONE OF SAID APPARATUSES - A connection device for connecting a piece of master electronic equipment to a piece of peripheral electronic equipment, each being provided with a respective external connection port of a first type, the device comprising a master connection unit and a peripheral connection unit, each of which is provided with an external connection port of the first type for connecting to the corresponding piece of equipment, and which are connected to each other via electrical isolation using a link of a second type, namely of the Ethernet type, having a transmit line and a receive line, each unit including a first type/Ethernet interface connected to said lines and a power supply module mounted in common mode between the transmit and receive lines in order to transmit or receive AC over the link. A docking station for peripheral equipment including such a device. | 2012-09-27 |
20120246497 | CONTROLLING AND MINIMIZING ELECTRICAL POWER CONSUMED BY ELECTRICAL COMPONENTS CONNECTED TO A NETWORKED COMPUTING ENVIRONMENT - Embodiments of the present invention provide an approach for controlling and minimizing electrical power consumption of a plurality of lights and electronic devices connected to a networked computing environment, wherein asset and space management software can be utilized to monitor and remotely turn off the electronic devices that are determined as not being utilized, based on observed indicators of inactivity associated with the electronic devices. Specifically, the location of the electronic devices are determined and then registered and stored in a database, wherein the electronic devices include desktop computers, laptops, phones, and heating ventilation and air conditioning (HVAC) systems that are connected to the networked computing environment. | 2012-09-27 |
20120246498 | MOTHERBOARD WITH OVERCLOCKING AND OVERVOLTING FUNCTIONS - A motherboard with overclocking and overvolting functions is provided. The motherboard with an overvolting function includes a specified component, a voltage regulator and a micro-controller. The specified component receives an operating voltage. The voltage regulator generates the operating voltage according to a reference voltage. The micro-controller is electrically connected to an external input device for receiving a control signal issued by the external input device and adjusting the reference voltage according to the control signal. | 2012-09-27 |
20120246499 | Self-Powered Devices and Methods - The self-powered device is configured to be powered by energy collected from a surrounding environment. The self-powered device includes an energy collector, and a memory having instructions for selecting one of a plurality of modes of operation. The energy collector is configured to collect energy to power the self-powered device from a surrounding environment in which the self-powered device is located. The plurality of modes of operation include: (i) a low-power mode of operation in which the self-powered device consumes less than a pre-determined or adaptively-determined amount of power and the self-powered device uses less than its full capabilities, and (ii) and a high-power mode of operation in which self-powered device consumes more than the pre-determined or adaptively-determined amount of power and the self-powered device uses its full capabilities. | 2012-09-27 |
20120246500 | COMPUTER POWER SAVING SYSTEM - A computer power saving system includes a computer, an UPS, a power detecting device, and an USB device. The computer includes a USB port and a power management module, and can work in a normal mode or in a STR mode. The UPS is connected to the computer and used for supplying power to the computer upon a condition that a commercial power supply stops supplying power to the computer. The power detecting device detects the state of the commercial power supply and sending out an abnormal power signal when the commercial power supply stops supplying power to the computer. The USB device sends the abnormal power signal to the USB port. When the computer works in the normal mode, the power management module detects the USB port, and controls the computer to shift to the STR mode if the USB port receives the abnormal power signal. | 2012-09-27 |
20120246501 | CONTROLLER AND PROGRAM PRODUCT - According to one embodiment, a controller includes a state detecting unit, a calculating unit, and a determining unit. The state detecting unit detects an idle state in which indicates there are no process that can execute on a processing device capable of performing one or more processes. The calculating unit calculates a resuming time, which indicates a time length until the next process starts, when the state detecting unit detects the idle state. The determining unit determines an operation mode of the processing device on the basis of the resuming time calculated by the calculating unit. | 2012-09-27 |
20120246502 | INFORMATION PROCESSING APPARATUS, CONTROL METHOD THEREFOR, AND STORAGE MEDIUM - The information processing apparatus generates and notifies, in the first power state, a prohibition condition for prohibiting the information processing apparatus from returning to the first power state even if an interface unit has received data from an external apparatus in the second power state and the received data matches a return condition for causing the information processing apparatus to return from the second power state to the first power state. When data is received from the external apparatus in the second power state, if the received data matches the prohibition condition, the interface unit does not transmit a return command to the power control unit, and if the received data does not match the prohibition condition, the interface unit transmits the return command to the power control unit. | 2012-09-27 |
20120246503 | INFORMATION PROCESSING APPARATUS AND JUDGING METHOD - According to one embodiment, an information processing apparatus includes a processor, a non-volatile storage unit, a receiving unit, a judging unit, and a transmitting unit. The receiving unit receives from the processor an inquiry about accessibility of the storage unit. The judging unit judges, upon receipt of the inquiry, whether the storage unit is accessible on the basis of a start-up time period between starting power supply to the storage unit and activation of the storage unit. The transmitting unit transmits a judgment result obtained by the judging unit to the processor. | 2012-09-27 |
20120246504 | ELECTRONIC DEVICE FOR DETECTING A TYPE OF A CHARGER DEVICE DURING A SLEEP MODE - An electronic device includes a microcontroller (MCU) and a central processing unit (CPU). The CPU enters a sleep mode. The MCU determines whether a charger device is inserted in the electronic device according to whether power is supplied from the charger device, and wakes up the CPU when the charger device is inserted in the electronic device. After being awakened, the CPU detects a type of the charger device, and adjusts charging current from the charger device to the electronic device according to the type of the charger device. | 2012-09-27 |
20120246505 | HSIC COMMUNICATION SYSTEM AND METHOD - A High Speed Inter Chip (HSIC) system and method for minimizing power consumption by controlling the state of the HSIC module through a control line are provided. The method between a host and a slave includes transitioning, when no communication request exists for a first reference time in an active state where all functions of the HSIC modules are enabled, to a suspend state where least functions used for maintaining a communication link of the HSIC modules and transitioning, when no communication request exists for a second reference time in the suspend state, to a power-off state where the HSIC modules turn off The HSIC communication method and apparatus are advantageous to minimize the electric current consumption of the HSIC consumption system. | 2012-09-27 |
20120246506 | Obtaining Power Profile Information With Low Overhead - In one embodiment, a method includes, upon occurrence of multiple power state transition events for a core of a multi-core processor, reading a value of a system counter of the core and values of low power counters of the core, without expiration of a timer or triggering of an interrupt. These values can be stored in a storage of the processor. Then, after collection is completed, the storage can be accessed to determine a power profile of the processor using the stored values. Other embodiments are described and claimed. | 2012-09-27 |
20120246507 | PARALLEL MEMORY ERROR DETECTION AND CORRECTION - A system implementing parallel memory error detection and correction divides data having a word length of K bits into multiple N-bit portions. The system has a separate error processing subsystem for each of the N-bit portions, and utilizes each error processing subsystem to process the associated N-bit portion of the K-bit input data. During memory write operations, each error processing subsystem generates parity information for the N-bit data, and writes the N-bit data and parity information into a separate memory array that corresponds to the error processing subsystem. During memory read operations, each error processing subsystem reads N-bits of data and the associated parity information. If, based on the parity information, an error is detected from the N-bit data, the error processing subsystem attempts to correct the error. The corrected N-bit data from each of the error processing subsystems are combined to reproduce the K-bit word. | 2012-09-27 |
20120246508 | METHOD AND SYSTEM FOR CONTINUOUSLY PROVIDING A HIGH PRECISION SYSTEM CLOCK - A method is presented for continuously providing a high precision system clock associated with a processing core, wherein the system clock includes a host clock register that is incremented via a high precision oscillator, the method includes: providing a firmware clock register, incrementing the firmware clock register based on the host clock register being incremented, monitoring for failures of the host clock register, and during a failure of the host clock register continuously incrementing the firmware clock register by means of timing signals of the processing core, and upon receipt of a request to provide a clock value, providing the content of the host clock register if no failure was detected, or if failure was detected, providing the content of the firmware clock register. | 2012-09-27 |
20120246509 | GLOBAL DETECTION OF RESOURCE LEAKS IN A MULTI-NODE COMPUTER SYSTEM - A process is disclosed for identifying and recovering from resource leaks on compute nodes of a parallel computing system. A resource monitor stores information about system resources available on a compute node in a clean state. After the compute node runs a job, the resource monitor compares the current resource availability to the clean state. If a resource leak is found, the resource monitor contacts a global resource manger to remove the resource leak. | 2012-09-27 |
20120246510 | INFORMATION PROCESSING APPARATUS, CONTROL DEVICE, AND ABNORMAL UNIT DETERMINATION METHOD - An information processing apparatus determines an abnormal unit by: determining whether or not there is an abnormal point in access to a slave unit by a first master unit that controls a plurality of slave units connected by a serial bus; requesting a second master unit having redundancy with the first master unit to access a specific slave unit when the abnormal point is determined to exist in access to the specific slave unit in the determining; and determining a unit having an abnormality by use of an access result relating to the abnormal point determined to have an abnormality in the determining and an access result indicating a result of the request made in the requesting. | 2012-09-27 |
20120246511 | STORAGE SYSTEM AND METHOD OF CONTROLLING THE SAME - A storage system, method and program product, the system comprising: storage devices; and a controller configured to: provide virtual volumes to a host computer; manage logical units on the storage device and storage pools; allocate, in response to receiving a write request to a virtual volume, a storage region of the storage pools; and store data related to the write request in the storage region allocated, wherein the controller is further configured to: allocate first storage region in first storage pool to first virtual volume based on first size of the first storage region or the first virtual volume; allocate a second storage region in a second storage pool to a second virtual volume of the plurality of virtual volumes based on a second size of the second storage region or the second virtual volume. | 2012-09-27 |
20120246512 | PARALLEL COMPUTER SYSTEM, CONTROL DEVICE, AND CONTROLLING METHOD - The control device detects a failed node in which a failure has occurred from a plurality of computation nodes included in a plurality of computation units included in the parallel computer. The control device chooses execution nodes for executing the program from the computation nodes of the parallel computer except the detected failed nodes based on the number of computation nodes needed to execute the program. The control device selects a paths to connect the computation nodes from a plurality of links each connecting two computation units adjacent to each other through a plurality of paths configured to connect computation nodes included in two computation units adjacent to each other in a one-to-one manner included in the links connecting two computation units adjacent to each other in the plurality of computation units including the choosed execution nodes except the path connected to the detected failed node. | 2012-09-27 |
20120246513 | System-directed checkpointing implementation using a hypervisor layer - While system-directed checkpointing can be implemented in various ways, for example by adding checkpointing support in the memory controller or in the operating system in otherwise standard computers, implementation at the hypervisor level enables the necessary state information to be captured efficiently while providing a number of ancillary advantages over those prior-art methods. This disclosure details procedures for realizing those advantages through relatively minor modifications to normal hypervisor operations. Specifically, by capturing state information in a guest-operating-system-specific manner, any guest operating system can be rolled back independently and resumed without losing either program or input/output (I/O) continuity and without affecting the operation of the other operating systems or their associated applications supported by the same hypervisor. Similarly, by managing I/O queues as described in this disclosure, rollback can be accomplished without requiring I/O operations to be repeated and I/O device failures can be circumvented without losing any I/O data in the process. | 2012-09-27 |
20120246514 | Adaptive Test Sequence for Testing Integrated Circuits - A method includes testing a first device and a second device identical to each other and comprising integrated circuits. The testing of the first device is performed according to a first test sequence of the first device, wherein the first test sequence includes a plurality of ordered test items, and wherein the first test sequence includes a test item. A test priority of the test item is calculated based on a frequency of fails of the test item in the testing of a plurality of devices having an identical structure as the first device. The first test sequence is then adjusted to generate a second test sequence in response to the test priority of the test item, wherein the second test sequence is different from the first test sequence. The second device is tested according to the second test sequence. | 2012-09-27 |
20120246515 | SCALABLE TESTING TOOL FOR GRAPHICAL USER INTERFACES OBJECT ORIENTED SYSTEM AND METHOD - The present invention involves an automated software testing system and method which specifies a screen of a program having a graphic user interface for testing; specifies an area of the screen for activation; specifies an activation procedure to invoke within the activation area, and an expected result of the activation; and runs the program including a display of the screen, activating the activation area with the activation procedure, and comparing the actual result with the expected result. | 2012-09-27 |