39th week of 2012 patent applcation highlights part 16 |
Patent application number | Title | Published |
20120241804 | LIGHT-EMITTING DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME - A light-emitting device package and method of manufacturing the same. The method includes: preparing a package main body comprising a plurality of cavities, wherein a light-emitting device chip is mounted in each of the cavities and a through hole is formed in a bottom of each of the cavities; preparing a fixed mold providing a first surface that blocks the cavity; coupling the package main body to the fixed mold such that an end portion of the cavity contacts the first surface; supplying an encapsulation material into the cavity through the through hole; hardening the encapsulation material; and separating the package main body from the fixed mold, and dicing the package main body into a plurality of light-emitting device packages using a singulation operation. The encapsulation material is supplied while disposing the package main body on the fixed mold so that the encapsulation material is supplied in a gravitational direction. | 2012-09-27 |
20120241805 | SEMICONDUCTOR LIGHT EMITTING ELEMENT AND MANUFACTURING METHOD THEREOF - A manufacturing method of a semiconductor light emitting element, includes forming sacrifice portions within the width of street portions in a semiconductor laminated body, and performing wet etching to remove the sacrifice portions together with their neighboring portions, thereby removing etching residuals in the streets. | 2012-09-27 |
20120241806 | LIGHT EMITTING DEVICE PACKAGE - Disclosed is a light emitting device package. The light emitting device package includes a Zener diode, a light emitting device including a light emitting diode, a body including lead frames on which the light emitting device and the Zener diode are disposed, and provided with a cavity formed on the lead frames, a first adhesive member disposed between the Zener diode and the lead frames, and a second adhesive member disposed between the light emitting device and the lead frames, and the thickness of the second adhesive member is equal to or less than the thickness of the first adhesive member. | 2012-09-27 |
20120241807 | Mounting Structure for Solid State Light Sources - A mounting structure for solid-state light sources, for example of the LED type, comprises a support board; a submount mounted on said support board and having at least one solid-state light radiation source mounted thereon; a drive board carrying drive circuitry for the light radiation source, the aforementioned drive board being mounted on the support board and extending peripherally with respect to the aforementioned submount; electrical interface connections between the submount and the drive board for connecting the light radiation source to the drive circuitry; and mechanical and thermal interface connections between the submount and the support board. | 2012-09-27 |
20120241808 | SEMICONDUCTOR LIGHT-EMITTING ELEMENT - A semiconductor light-emitting element with a counter electrode structure can include a first electrode including at least one linear first electrode piece that is disposed on a surface of a first semiconductor layer close to the support substrate and in ohmic contact with the first semiconductor layer, a second electrode including at least one linear second electrode piece that is disposed on a surface of a second semiconductor layer and in ohmic contact with the second semiconductor layer. A plurality of conical projections can be formed on the second semiconductor layer. The first electrode piece and the second electrode piece can be disposed so as not to overlap with each other in a stacked direction of the semiconductor light-emitting stacked body but to be parallel with each other when viewed from above. | 2012-09-27 |
20120241809 | MANUFACTURING PROCESS FOR SOLID STATE LIGHTING DEVICE ON A CONDUCTIVE SUBSTRATE - A method for fabricating a light emitting device includes forming a trench in a first surface on first side of a substrate. The trench comprises a first sloped surface not parallel to the first surface, wherein the substrate has a second surface opposite to the first surface of the substrate. The method also includes forming alight emission layer over the first trench surface, but not over the remainder of the first substrate surface, and removing at least a portion of the substrate from the second side of the substrate to expose the light emission layer and allow it to emit light out of the protrusion or protrusions on the second side of the substrate. These protrusions may be elongated pyramids. | 2012-09-27 |
20120241810 | PRINTING CIRCUIT BOARD WITH MICRO-RADIATORS - The present invention relates to a printing circuit board with micro-radiators. The printing circuit board includes a substrate, the substrate includes multi-layer copper clad plates and multi-layer prepregs, the multi-layer copper clad plates and the multi-layer prepregs are cross-laminated, the printing circuit board also includes at least one cylindrical micro-radiator embedded into a cylindrical hole of the substrate, the height of the insulating microradiator is equal to the thickness of the substrate, an upper surface and a lower surface of the micro-radiator are covered by copper foils, a heating element is installed on one of the surfaces of the insulating micro-radiator, the other surface of the insulating micro-radiator is isolated from other circuits of the printing circuit board. The present invention combines the micro-radiator with high thermal conductivity and traditional rigid printing circuit board. The present invention has the advantages of high thermal conductivity and stable heat transfer. | 2012-09-27 |
20120241811 | Organic Light Emitting Diode Display and Manufacturing Method of Organic Light Emitting Diode Display - An organic light emitting diode (OLED) display includes: a substrate; an organic light emitting diode on the substrate; and a thin film encapsulation layer including a first inorganic layer having a first density on the substrate and a second inorganic layer having a second density on the first inorganic layer, the second density being different from the first density, and the organic light emitting diode being encapsulated between the thin film encapsulation layer and the substrate. | 2012-09-27 |
20120241812 | LIGHT-EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - A light-emitting element is disclosed that can drive at a low driving voltage and that has a longer lifetime than the conventional light-emitting element, and a method is disclosed for manufacturing the light-emitting element. The disclosed light-emitting element includes a plurality of layers between a pair of electrodes; and at least one layer among the plurality of layers contains one compound selected from the group consisting of oxide semiconductor and a metal oxide, and a compound having high hole transportation properties. Such the light-emitting element can suppress the crystallization of a layer containing one compound selected from the group consisting of oxide semiconductor and a metal oxide, and a compound having high hole transportation properties. As a result, a lifetime of the light-emitting element can be extended. | 2012-09-27 |
20120241813 | POWER SEMICONDUCTOR DEVICE - A power semiconductor device includes a first semiconductor layer of a first conduction type, a second semiconductor layer of the first conduction type, a third semiconductor layer of a second conduction type, a fourth semiconductor layer of the first conduction type, a gate insulating film, a gate electrode, an interlayer insulating film, a fifth semiconductor layer of the second conduction type, a sixth semiconductor layer of the second conduction type, an insulative current narrowing body, a first electrode, and a second electrode. The sixth semiconductor layer of the second conduction type contains a second conduction type impurity in a concentration higher than a second conduction type impurity concentration of the fifth semiconductor layer. The insulative current narrowing body is provided in the fifth semiconductor layer. The insulative current narrowing body has a surface parallel to the surface of the fifth semiconductor layer and a space provided in the surface. | 2012-09-27 |
20120241814 | POWER SEMICONDUCTOR DEVICE - A power semiconductor device includes a p-type collector layer, an n-type base layer, a p-type base layer, an n-type source layer, and a gate electrode. The gate electrode is formed in a trench running from a surface of the n-type source layer through the n-type source layer and the p-type base layer to an interior of the n-type base layer via a gate insulating film. The gate electrode includes a first portion and a second portion. The first portion is opposed to a bottom end portion of the p-type base layer. The second portion is opposed to an upper end portion of the p-type base layer. The gate electrode is formed such that a threshold at the bottom end portion of the p-type base layer is not less than a threshold at the upper end portion of the p-type base layer. | 2012-09-27 |
20120241815 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - A method of fabricating one or more semiconductor devices includes forming a trench in a semiconductor substrate, performing a cycling process to remove contaminants from the trench, and forming an epitaxial layer on the trench. The cycling process includes sequentially supplying a first reaction gas containing germane, hydrogen chloride and hydrogen and a second reaction gas containing hydrogen chloride and hydrogen onto the semiconductor substrate. | 2012-09-27 |
20120241816 | Stabilization of Metal Silicides in PFET Transistors by Incorporation of Stabilizing Species in a Si/Ge Semiconductor Material - When forming sophisticated P-channel transistors, the metal silicide agglomeration in a germanium-containing strain-inducing semiconductor alloy may be avoided or at least significantly reduced by incorporating a carbon and/or nitrogen species in a highly controllable manner. In some illustrative embodiments, the carbon species or nitrogen species is incorporated during the epitaxial growth process so as to form a surface layer of the strain-inducing semiconductor alloy with a desired nitrogen and/or carbon concentration and with a desired thickness without unduly affecting any other device areas. | 2012-09-27 |
20120241817 | SEMICONDUCTOR DEVICE - According to an embodiment, a semiconductor device includes a first semiconductor layer, a second semiconductor layer, a control electrode, a third semiconductor layer, first and second main electrodes. The second semiconductor layer is provided on the first semiconductor layer, and has a higher impurity concentration than the first semiconductor layer. The control electrode is provided inside a first trench with an insulating film interposed, the first trench reaching the first semiconductor layer from a front surface of the second semiconductor layer. The third semiconductor layer is provided inside a second trench and including Si | 2012-09-27 |
20120241818 | TWO-DIMENSIONAL CONDENSATION FOR UNIAXIALLY STRAINED SEMICONDUCTOR FINS - Techniques are disclosed for enabling multi-sided condensation of semiconductor fins. The techniques can be employed, for instance, in fabricating fin-based transistors. In one example case, a strain layer is provided on a bulk substrate. The strain layer is associated with a critical thickness that is dependent on a component of the strain layer, and the strain layer has a thickness lower than or equal to the critical thickness. A fin is formed in the substrate and strain layer, such that the fin includes a substrate portion and a strain layer portion. The fin is oxidized to condense the strain layer portion of the fin, so that a concentration of the component in the strain layer changes from a pre-condensation concentration to a higher post-condensation concentration, thereby causing the critical thickness to be exceeded. | 2012-09-27 |
20120241819 | Composite Semiconductor Device with Turn-On Prevention Control - There are disclosed herein various implementations of composite III-nitride semiconductor devices having turn-on prevention control. In one exemplary implementation, a normally OFF composite semiconductor device comprises a normally ON III-nitride power transistor and a low voltage (LV) device cascoded with the normally ON III-nitride power transistor to form the normally OFF composite semiconductor device. The LV device is configured to have a noise-resistant threshold voltage to provide the turn-on prevention control for the normally OFF composite semiconductor device by preventing noise current from flowing through a channel of the normally ON III-nitride power transistor in a noisy system. | 2012-09-27 |
20120241820 | III-Nitride Transistor with Passive Oscillation Prevention - There are disclosed herein various implementations of semiconductor devices having passive oscillation control. In one exemplary implementation, such a device is implemented to include a III-nitride transistor having a source electrode, a gate electrode and a drain electrode. A damping resistor is configured to provide the passive oscillation control for the III-nitride transistor. In one implementation, the damping resistor includes at least one lumped resistor. | 2012-09-27 |
20120241821 | HETEROSTRUCTURE FOR ELECTRONIC POWER COMPONENTS, OPTOELECTRONIC OR PHOTOVOLTAIC COMPONENTS - A heterostructure that includes, successively, a support substrate of a material having an electrical resistivity of less than 10 | 2012-09-27 |
20120241822 | SEMICONDUCTOR DEVICE, DISTORTION GAUGE, PRESSURE SENSOR, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device may include a piezoresistive body of which a resistance value is changed by action of an external force. The piezoresistive body may include a surface layer of diamond. The surface layer may be hydrogen-terminated. | 2012-09-27 |
20120241823 | POWER SEMICONDUCTOR DEVICE - A power semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer provided thereon, mutually separated columnar third semiconductor layers of a second conductivity type extending within the second semiconductor layer, island-like fourth semiconductor layers of the second conductivity type provided on the third semiconductor layers, fifth semiconductor layers of the first conductivity type, sixth semiconductor layers of the second conductivity type, a gate electrode, a first electrode, and a second electrode. The fifth semiconductor layers are selectively provided on the fourth semiconductor layers. The sixth semiconductor layer electrically connects two adjacent fourth semiconductor layers. The first electrode is in electrical connection with the first semiconductor. The second electrode is in electrical connection with the fourth semiconductor layers and the fifth semiconductor layers via the openings in the gate electrode. | 2012-09-27 |
20120241824 | SPACER STRUCTURE WHEREIN CARBON-CONTAINING OXIDE FILM FORMED WITHIN - A spacer structure contains a carbon-containing oxide film positioned on a gate sidewall and a nitride film covering the carbon-containing oxide film. The carbon-containing oxide film has low etch rate so that the spacer structure can have a good profile during etching the carbon-containing oxide film. | 2012-09-27 |
20120241825 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A first thin film diode ( | 2012-09-27 |
20120241826 | ACCESS TRANSISTOR WITH A BURIED GATE - A magnetic memory cell is formed including a magneto tunnel junction (MTJ) and an access transistor, which is used to access the MTJ in operation. The access transistor, which is formed on a silicon substrate, includes a gate, drain and source with the gate position substantially perpendicular to the plane of the silicon substrate thereby burying the gate and allowing more surface area on the silicon substrate for formation of additional memory cells. | 2012-09-27 |
20120241827 | MAGNETORESISTIVE ELEMENT AND MAGNETIC MEMORY - A magnetoresistive element according to an embodiment includes: a first to third ferromagnetic layers, and a first nonmagnetic layer, the first and second ferromagnetic layers each having an axis of easy magnetization in a direction perpendicular to a film plane, the third ferromagnetic layer including a plurality of ferromagnetic oscillators generating rotating magnetic fields of different oscillation frequencies from one another. Spin-polarized electrons are injected into the first ferromagnetic layer and induce precession movements in the plurality of ferromagnetic oscillators of the third ferromagnetic layer by flowing a current between the first and third ferromagnetic layers, the rotating magnetic fields are generated by the precession movements and are applied to the first ferromagnetic layer, and at least one of the rotating magnetic fields assists a magnetization switching in the first ferromagnetic layer. | 2012-09-27 |
20120241828 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A method for manufacturing a semiconductor memory device includes forming a magnetic tunnel junction layer on a lower electrode, forming a spacer having an annular shape on the magnetic tunnel junction layer, forming upper electrodes on both sidewall surfaces of the annular shaped spacer, removing the spacer, and etching the magnetic tunnel junction layer by using the upper electrodes as an etch mask. | 2012-09-27 |
20120241829 | Low Leakage Capacitor for Analog Floating-Gate Integrated Circuits - An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, and includes portions serving as a transistor gate electrode, a plate of a metal-to-poly storage capacitor, and a plate of poly-to-active tunneling capacitors. Silicide-block silicon dioxide blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit are silicide-clad. | 2012-09-27 |
20120241830 | SEMICONDUCTOR DEVICE HAVING CELL CAPACITORS - A semiconductor device including: a bit line being arranged on top surfaces of first and second contact plugs via a first insulation layer and extending in a direction connecting a first impurity diffusion layer and a second impurity diffusion layer; a bit line contact plug being formed through the first insulation layer and electrically connecting the bit line to the first contact plug; a first cell capacitor having a first lower electrode beside one of side surfaces of the bit line; a first insulation film insulating the bit line and the first lower electrode from each other; and a first contact conductor electrically connecting a bottom end of the first lower electrode to a side surface of the second contact plug. | 2012-09-27 |
20120241831 | Methods of Forming Vertical Field Effect Transistors, Vertical Field Effect Transistors, and DRAM Cells - A method of forming a vertical field effect transistor includes etching an opening into semiconductor material. Sidewalls and radially outermost portions of the opening base are lined with masking material. A semiconductive material pillar is epitaxially grown to within the opening adjacent the masking material from the semiconductor material at the opening base. At least some of the masking material is removed from the opening. A gate dielectric is formed radially about the pillar. Conductive gate material is formed radially about the gate dielectric. An upper portion of the pillar is formed to comprise one source/drain region of the vertical transistor. Semiconductive material of the pillar received below the upper portion is formed to comprise a channel region of the vertical transistor. Semiconductor material adjacent the opening is formed to comprise another source/drain region of the vertical transistor. Other aspects and implementations are contemplated. | 2012-09-27 |
20120241832 | DRAM Arrays - The invention includes methods for utilizing partial silicon-on-insulator (SOI) technology in combination with fin field effect transistor (finFET) technology to form transistors particularly suitable for utilization in dynamic random access memory (DRAM) arrays. The invention also includes DRAM arrays having low rates of refresh. Additionally, the invention includes semiconductor constructions containing transistors with horizontally-opposing source/drain regions and channel regions between the source/drain regions. The transistors can include gates that encircle at least three-fourths of at least portions of the channel regions, and in some aspects can include gates that encircle substantially an entirety of at least portions of the channel regions. | 2012-09-27 |
20120241833 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, the storage device further includes: a first electrode that is formed in a reverse convex and in contact with an upper surface of a first region, parts of a side and an upper surface of a first isolation region that face a second isolation region, and parts of a side and an upper surface of the second isolation region that face the first isolation region; and a third electrode that is positioned in a different direction from a second direction with respect to the first electrode, formed in a reverse convex and in contact with an upper surface of a second region, parts of a side and the upper surface of the second isolation region that face a third isolation region, and parts of a side and an upper surface of the third isolation region that face the second isolation region. | 2012-09-27 |
20120241834 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes interconnects extending from a element formation area to the drawing area, and connected with semiconductor elements in the element formation area and connected with contacts in the drawing area. The interconnects are formed based on a pattern of a (n+1) | 2012-09-27 |
20120241835 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE INCLUDING RESISTIVE ELEMENT - According to one embodiment, a second conductive layer is provided on a second insulating film and connected to a first conductive layer via an opening portion in the second insulating film. A first contact is connected to the second conductive layer. A third conductive layer is provided on the second insulating film and connected to the first conductive layer via an opening portion in the second insulating film. A second contact is connected to the third conductive layer. A fourth conductive layer is provided on the second insulating film and connected to the first conductive layer via an opening portion in the second insulating film. A third contact is connected to the fourth conductive layer. The floating gate layer and the first conductive layer are made of the same material, and the control gate layer, the second, third and fourth conductive layers are made of the same material. | 2012-09-27 |
20120241836 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - According to one embodiment, a method of manufacturing a semiconductor device including a memory cell transistor in a first region of a substrate and a select gate transistor in a second region of the substrate includes: forming a gate insulating film, a lower gate electrode, an inter-electrode insulating film, an upper gate electrode, and a hard mask on the substrate; forming a groove passing through the hard mask, the upper gate electrode, and the inter-electrode insulating film and reaching the lower gate electrode in the second region; and forming a connection layer having a crystal structure which preferentially has a specific crystal orientation and that electrically connects between the lower gate electrode and the upper gate electrode by being selectively crystal-grown while being subjected to an influence from a crystal structure of the lower gate electrode in the groove | 2012-09-27 |
20120241837 | NON-VOLATILE MEMORY HAVING CHARGE STORAGE LAYER AND CONTROL GATE - According to one embodiment, a non-volatile memory includes a first non-volatile memory cell and a first selected transistor. A first cell block is formed by connecting a plurality of first non-volatile memory cells in series. An area S1 of the first insulating film at which the first floating gate is in contact with the first silicon channel is larger than an area S2 of the second insulating film at which the first floating gate is in contact with the first gate electrode. | 2012-09-27 |
20120241838 | SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor storage device includes: a plurality of word lines that are formed at predetermined intervals in a first direction on the element region; a select gate transistor that is arranged in each of both sides of the word lines and has a width in the first direction wider than the word line; a first air gap that is positioned between the word lines; and a second air gap that is formed on a side wall portion opposite to a side of the word line of the select gate transistor. Further, according to one embodiment, the semiconductor storage device is provided in which an oxide film is formed on a surface of a substrate between the select gate transistors that are adjacent to each other, and a cross-sectional surface in a direction perpendicular to the first direction under the oxide film has a convex shape. | 2012-09-27 |
20120241839 | SPLIT-GATE NON-VOLATILE MEMORY CELLS HAVING IMPROVED OVERLAP TOLERANCE - Embodiments include a split-gate non-volatile memory cell that is formed having a control gate and a select gate, where at least a portion of the control gate is formed over the select gate. A charge storage layer is formed between the select gate and the control gate. The select gate is formed using a first conductive layer and a second conductive layer. The second conductive layer is formed over the first conductive layer and has a lower resistivity than the first conductive layer. In one embodiment, the first conductive layer is polysilicon and the second conductive layer is titanium nitride (TiN). In another embodiment, the second conductive layer may be a silicide or other conductive material, or combination of conductive materials having a lower resistivity than the first conductive layer. | 2012-09-27 |
20120241840 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A nonvolatile memory device includes a substrate having active regions that are defined by an isolation layer and that have first sidewalls extending upward from the isolation layer, floating gates adjoining the first sidewalls of the active regions with a tunnel dielectric layer interposed between the active regions and the floating gates and extending upward from the substrate, an intergate dielectric layer disposed over the floating gates, and control gates disposed over the intergate dielectric layer. | 2012-09-27 |
20120241841 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - According to one embodiment, a semiconductor device, including a substrate, a stacked layer body provided above the substrate, the stacked layer body alternately stacking an insulator and an electrode film one on another, silicon pillars contained with fluorine, the silicon pillar penetrating through and provided in the stacked layer body, a tunnel insulator provided on a surface of the silicon pillar facing to the stacked layer body, a charge storage layer provided on a surface of the tunnel insulator facing to the stacked layer body, a block insulator provided on a surface of the charge storage layer facing to the stacked layer body, the block insulator being in contact with the electrode film, and an embedded portion provided in the silicon pillars. | 2012-09-27 |
20120241842 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a nonvolatile semiconductor memory device includes first and second stacked body, first and second semiconductor pillars, a connecting portion, a first memory film, and a dividing portion. The stacked bodies include a plurality of electrode films stacked along a first axis and as interelectrode insulating film provided between the electrode films. The first and second semiconductor pillars penetrate through the first and second stacked bodies along the first axis, respectively. The connecting portion electrically connects the first and second semiconductor pillars. The first memory film is provided between the electrode film and the semiconductor pillar. The dividing portion electrically divides the first and second electrode films from each other between the first semiconductor pillar and the second semiconductor pillar, is in contact with the connecting portion, and includes a stacked film including a material used for the first memory film. | 2012-09-27 |
20120241843 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array part, a first contact part, and a peripheral circuit part. The first contact part is juxtaposed with the memory cell array part in a first plane. The peripheral circuit part is juxtaposed with the memory cell array part in the first plane. The memory cell array part includes a first stacked body, a first semiconductor layer, and a memory film. The first contact part includes a first contact part insulating layer, and a plurality of first contact electrodes. The peripheral circuit part includes a peripheral circuit, a structure body, a peripheral circuit part insulating layer, and a peripheral circuit part contact electrode. A width along an axis perpendicular to the first axis of the peripheral circuit part insulating layer is smaller than a diameter of the first particle. | 2012-09-27 |
20120241844 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a nonvolatile semiconductor memory device includes: first and second stacked bodies, first and second semiconductor pillars, a connection portion, a memory film, and a partitioning insulating layer. The stacked bodes include electrode films stacked along a first axis and an inter-electrode insulating film provided between the electrode films. Through-holes are provided in the stacked bodies. The semiconductor pillars are filled into the through-holes. The connection portion electrically connects the semiconductor pillars. The memory film is provided between the semiconductor pillars and the electrode films. The partitioning insulating layer partitions the first and second electrode films. A side surface of the first through-hole on the partitioning insulating layer side and a side surface of the second through-hole on the partitioning insulating layer side have a portion parallel to a plane orthogonal to a second axis from the first stacked body to the second stacked body. | 2012-09-27 |
20120241845 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A first insulation film is on a substrate. A first resistance part is on the first insulation film. A boundary film is on the first resistance part. A second resistance part is on the boundary film. A second insulation film is on the second resistance part. A first conductive part and a second conductive part are on the second insulation film, and are isolated from each other. The first conductive part includes a first connection part penetrating the second insulation film and the second resistance part and contacting a surface of the boundary film. The second conductive part includes a second connection part penetrating the second insulation film and the second resistance part and contacting a surface of the boundary film. The first resistance part is connected to the first conductive part via the first connection part, and is connected to the second conductive part via the second connection part. | 2012-09-27 |
20120241846 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a nonvolatile semiconductor memory device comprises a first conductive layer, a second conductive layer, a first inter-electrode insulating film, and a third conductive layer stacked above the first conductive layer, a memory film, a semiconductor layer, an insulating member, and a silicide layer. The memory film and the semiconductor layer is formed on the inner surface of through hole provided in the second conductive layer, the first inter-electrode insulating film, and the third conductive layer. The insulating member is buried in a slit dividing the second conductive layer, the first inter-electrode insulating film, and the third conductive layer. The silicide layer is formed on surfaces of the second conductive layer and the third conductive layer in the slit. The distance between the second conductive layer and the third conductive layer along the inner surface of the slit is longer than that of along the stacking direction. | 2012-09-27 |
20120241847 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a first semiconductor layer of a first conductive type, and a periodic array structure having a second semiconductor layer of a first conductive type and a third semiconductor layer of a second conductive type periodically arrayed on the first semiconductor layer in a direction parallel with a major surface of the first semiconductor layer. The second semiconductor layer and the third semiconductor layer are disposed in dots on the first semiconductor layer. A periodic structure in the outermost peripheral portion of the periodic array structure is different from a periodic structure of the periodic array structure in a portion other than the outermost peripheral portion. | 2012-09-27 |
20120241848 | SEMICONDUCTOR ELEMENT AND METHOD OF MANUFACTURING SEMICONDUCTOR ELEMENT - A semiconductor element includes a drain layer, a drift region selectively provided in the drain layer, a base region selectively provided in the drift region, a source region selectively provided in the base region, first and/or second metal layers selectively provided in at least one of the source region and the drain layer from the front surface to the inside of at least one of the source region and the drain layer, a gate electrode in a trench shape extending in a direction substantially parallel to the front surface of the drain layer from a part of the source region through the base region adjacent to at least the part of the source region to a part of the drift region, a source electrode connected to the first metal layer, and a drain electrode connected to the drain layer or the second metal layer. | 2012-09-27 |
20120241849 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor device includes a first semiconductor region, a second semiconductor region, a third semiconductor region, a control electrode, a first main electrode, an internal electrode, and an insulating region. The control electrode is provided inside a trench. The first main electrode is in conduction with the third semiconductor region. The internal electrode is provided in the trench and in conduction with the first main electrode. The insulating region is provided between an inner wall of the trench and the internal electrode. The internal electrode includes a first internal electrode part included in a first region of the trench and a second internal electrode part included in a second region between the first region and the first main electrode. A spacing between the first internal electrode part and the inner wall is wider than a spacing between the second internal electrode part and the inner wall. | 2012-09-27 |
20120241850 | SEMICONDUCTOR DEVICE - A semiconductor device includes a drain layer, a drift region provided from a surface inside of the drain layer, a base region provided from a surface inside of the drift region, a source region provided in a trench form from a surface inside of the base region, and a gate electrode provided via a gate insulating film in a first trench. The gate electrode is extended from a part of the source region to a part of the drift region in a direction approximately parallel to a rear face of the drain layer. The semiconductor device further includes a first resistive body layer provided via a first insulating film in at least one of second trenches provided from a surface inside of the drain layer. | 2012-09-27 |
20120241851 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor device includes a drift layer. The device includes a base layer. The device includes a source layer selectively provided on a surface of the base layer. The device includes a gate electrode provided via a gate insulating film in a trench penetrating the source layer and the base layer to reach the drift layer. The device includes a field plate electrode provided under the gate electrode in the trench. The device includes a drain electrode electrically connected to the drift layer. The device includes a source electrode. The field plate electrode is electrically connected to the source electrode. An impurity concentration of a first conductivity type contained in the base layer is lower than an impurity concentration of the first conductivity type contained in the drift layer. And the impurity concentration of the first conductivity type contained in the drift layer is not less than 1×10 | 2012-09-27 |
20120241852 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor device includes a semiconductor substrate, plural stacked bodies, an insulating side wall, an interlayer insulating layer, and a contact. Plural stacked bodies are provided on the semiconductor substrate so as to extend in parallel to one another. Each of the plural stacked bodies includes a gate insulating layer, a gate electrode, and an insulating layer. The insulating side wall covers a side face of the gate electrode in an upper end part thereof and does not cover the side face of the gate electrode in a part thereof contacting the gate insulating layer. The interlayer insulating layer is provided on the semiconductor substrate and covers the stacked bodies. The contact is provided in the interlayer insulating layer between the stacked bodies and is connected to the semiconductor substrate. | 2012-09-27 |
20120241853 | SEMICONDUCTOR DEVICE - A semiconductor layer has a second impurity concentration. First trenches are formed in the semiconductor layer to extend downward from an upper surface of the semiconductor layer. Each of insulation layers is formed along each of the inner walls of the first trenches. Each of conductive layers is formed to bury each of the first trenches via each of the insulation layers, and extends downward from the upper surface of the semiconductor layer to a first position. A first semiconductor diffusion layer reaches a second position from the upper surface of the semiconductor layer, is positioned between the first trenches, and has a third impurity concentration lower than the second impurity concentration. A length from the upper surface of the semiconductor layer to the second position is equal to or less than half a length from the upper surface of the semiconductor layer to the first position. | 2012-09-27 |
20120241854 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, the semiconductor device includes a first semiconductor layer. The semiconductor device includes a plurality of base regions, the base regions are provided on a surface of the first semiconductor layer. The semiconductor device includes a source region selectively provided on each of surfaces of the base regions. The semiconductor device includes a gate electrode provided via a gate insulating film in each of a pair of trenches, each of the trenches penetrate the base regions from a surface of the source region to the first semiconductor layer. The semiconductor device includes a field plate electrode provided via a field plate insulating film in each of the pair of trenches under the gate electrode. A thickness of a part of the field plate insulating film is greater than a thickness of the gate insulating film. | 2012-09-27 |
20120241855 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - In a power MISFET having a trench gate structure with a dummy gate electrode, a technique is provided for improving the performance of the power MISFET, while preventing electrostatic breakdown of a gate insulating film therein. A power MISFET having a trench gate structure with a dummy gate electrode, and a protective diode are formed on the same semiconductor substrate. The protective diode is provided between a source electrode and a gate interconnection. In a manufacturing method of such a semiconductor device, a polycrystalline silicon film for the dummy gate electrode and a polycrystalline silicon film for the protective diode are formed simultaneously. A source region of the power MISFET and an n | 2012-09-27 |
20120241856 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - In a power MISFET having a trench gate structure with a dummy gate electrode, a technique is provided for improving the performance of the power MISFET, while preventing electrostatic breakdown of a gate insulating film therein. A power MISFET having a trench gate structure with a dummy gate electrode, and a protective diode are formed on the same semiconductor substrate. The protective diode is provided between a source electrode and a gate interconnection. In a manufacturing method of such a semiconductor device, a polycrystalline silicon film for the dummy gate electrode and a polycrystalline silicon film for the protective diode are formed simultaneously. A source region of the power MISFET and an n | 2012-09-27 |
20120241857 | DUAL STRESS DEVICE AND METHOD - A semiconductor device including semiconductor material having a bend and a trench feature formed at the bend, and a gate structure at least partially disposed in the trench feature. A method of fabricating a semiconductor structure including forming a semiconductor material with a trench feature over a layer, forming a gate structure at least partially in the trench feature, and bending the semiconductor material such that stress is induced in the semiconductor material in an inversion channel region of the gate structure. | 2012-09-27 |
20120241858 | SEMICONDUCTOR DEVICE - A first semiconductor layer extends from the element region to the element-termination region, and functions as a drain of the MOS transistor. A second semiconductor layer extends, below the first semiconductor layer, from the element region to the element-termination region. A third semiconductor layer extends from the element region to the element-termination region, and is in contact with the second semiconductor layer to function as a drift layer of the MOS transistor. A distance between a boundary between the first semiconductor layer and the field oxide film, and the end portion of the third semiconductor layer on the fifth semiconductor layer side in the element region is smaller than that between a boundary between the first semiconductor layer and the field oxide layer and an end portion of the third semiconductor layer on the fifth semiconductor layer side in the element-termination region. | 2012-09-27 |
20120241859 | SWITCH CIRCUIT USING LDMOS ELEMENT - The present invention relates to a switch circuit, and more particularly, to a switch circuit that uses an LDMOS (lateral diffusion metal oxide semiconductor) device inside an IC (Integrated Circuit). In the switch circuit that uses the LDMOS device according to an embodiment of the present invention, a gate-source voltage (V | 2012-09-27 |
20120241860 | SEMICONDUCTOR INTEGRATED CIRCUIT INCLUDING TRANSISTOR HAVING DIFFUSION LAYER FORMED AT OUTSIDE OF ELEMENT ISOLATION REGION FOR PREVENTING SOFT ERROR - A semiconductor integrated circuit device includes a gate electrode of at least one of a P-channel MISFET (metal-insulator-semiconductor field-effect transistor) and an N-channel MISFET provided in a direction parallel to a direction of a well isolation boundary phase between the P-channel MISFET and the N-channel MISFET, a first diffusion layer having a same conductivity type as that of a drain diffusion layer of one of a plurality of ones of the MISFET provided in two regions with a drain diffusion layer of the MISFET therebetween through an isolation respectively in a direction orthogonal to the gate electrode, and a second diffusion layer having a conductivity type different from that of the drain diffusion layer of the one of the plurality of ones of the MISFET provided between the well isolation boundary phase and one of a source diffusion layer and the drain diffusion layer. | 2012-09-27 |
20120241861 | Ultra-High Voltage N-Type-Metal-Oxide-Semiconductor (UHV NMOS) Device and Methods of Manufacturing the same - An ultra-high voltage n-type-metal-oxide-semiconductor (UHV NMOS) device with improved performance and methods of manufacturing the same are provided. The UHV NMOS includes a substrate of P-type material; a first high-voltage N-well (HVNW) region disposed in a portion of the substrate; a source and bulk p-well (PW) adjacent to one side of the first HVNW region, and the source and bulk PW comprising a source and a bulk; a gate extended from the source and bulk PW to a portion of the first HVNW region, and a drain disposed within another portion of the first HVNW region that is opposite to the gate; a P-Top layer disposed within the first HVNW region, the P-Top layer positioned between the drain and the source and bulk PW; and an n-type implant layer formed on the P-Top layer. | 2012-09-27 |
20120241862 | LDMOS DEVICE AND METHOD FOR MAKING THE SAME - The embodiments of the present disclosure disclose a LDMOS device and the method for making the LDMOS device. The LDMOS device comprises at least one capacitive region formed in the drift region. Each capacitive region comprises a polysilicon layer and a thick oxide layer separating the polysilicon layer from the drift region. The LDMOS device in accordance with the embodiments of the present disclosure can improve the breakdown voltage while a low on-resistance is maintained. | 2012-09-27 |
20120241863 | FIN FIELD-EFFECT TRANSISTOR STRUCTURE AND MANUFACTURING PROCESS THEREOF - A fin field-effect transistor structure includes a substrate, a fin channel and a high-k metal gate. The high-k metal gate is formed on the substrate and the fin channel. A process of manufacturing the fin field-effect transistor structure includes the following steps. Firstly, a polysilicon pseudo gate structure is formed on the substrate and a surface of the fin channel. By using the polysilicon pseudo gate structure as a mask, a source/drain region is formed in the fin channel. After the polysilicon pseudo gate structure is removed, a high-k dielectric layer and a metal gate layer are successively formed. Afterwards, a planarization process is performed on the substrate having the metal gate layer until the first dielectric layer is exposed, so that a high-k metal gate is produced. | 2012-09-27 |
20120241864 | Shallow Source and Drain Architecture in an Active Region of a Semiconductor Device Having a Pronounced Surface Topography by Tilted Implantation - In sophisticated semiconductor devices, a shallow drain and source concentration profile may be obtained for active regions having a pronounced surface topography by performing tilted implantation steps upon incorporating the drain and source dopant species. In this manner, a metal silicide may be reliably embedded in the drain and source regions. | 2012-09-27 |
20120241865 | INTEGRATED CIRCUIT STRUCTURE - One aspect of the present invention provides an integrated circuit structure including a semiconductor substrate, a bottom dielectric layer positioned on the substrate, at least two capping dielectric layers positioned on the bottom dielectric layer, and a metal layer positioned on the at least two capping dielectric layers, wherein one of the two capping dielectric layers is an aluminum oxide layer, and the other is a silicon oxide layer. Another aspect of the present invention provides an integrated circuit structure including a bottom electrode, a bottom dielectric layer positioned on the bottom electrode, at least two capping dielectric layers positioned on the bottom dielectric layer, and a top electrode positioned on the at least two capping dielectric layers, wherein one of the two capping dielectric layers is an aluminum oxide layer, and the other is a silicon oxide layer. | 2012-09-27 |
20120241866 | TRANSISTOR STRUCTURE AND MANUFACTURING METHOD WHICH HAS CHANNEL EPITAXIAL EQUIPPED WITH LATERAL EPITAXIAL STRUCTURE - A semiconductor device and methods of fabricating semiconductor devices are provided. Provided is an epitaxial layer equipped with a lateral epitaxial layer that can block a Shallow Trench Isolation (STI) edge from a downstream etching process step, which can result in a reduced STI divot. A method involves forming a semiconductor substrate on a source region and a drain region and forming a semiconductor region on the semiconductor substrate. The method also comprises creating at least a first isolation feature adjacent to the semiconductor region and depositing an epitaxial layer on the semiconductor region and laterally between the semiconductor region and the at least the first isolation feature. | 2012-09-27 |
20120241867 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND A MANUFACTURING METHOD THEREOF - In a non-volatile semiconductor memory device, first element isolation insulation layers in a memory cell area are formed by burying a first oxide film in first element isolation trenches of the memory cell area. The top surface of the first oxide film is positioned at a level between the top surface of a semiconductor substrate and the top surface of a first gate electrode. Each of second element isolation insulation layers in a peripheral area includes a first oxide film embedded in the entirety of second element isolation trenches of the peripheral area, and a second oxide film formed on the first oxide film. The top surface of the first oxide film is at a higher level than the top surface of the semiconductor substrate. The top surface of the second oxide film is at a higher level than the top surface of a first conductor film. | 2012-09-27 |
20120241868 | METAL-GATE CMOS DEVICE - A method for fabricating a metal-gate CMOS device. A substrate having thereon a first region and a second region is provided. A first dummy gate structure and a second dummy gate structure are formed within the first region and the second region respectively. A first LDD is formed on either side of the first dummy gate structure and a second LDD is formed on either side of the second dummy gate structure. A first spacer is formed on a sidewall of the first dummy gate structure and a second spacer is formed on a sidewall of the second dummy gate structure. A first embedded epitaxial layer is then formed in the substrate adjacent to the first dummy gate structure. The first region is masked with a seal layer. Thereafter, a second embedded epitaxial layer is formed in the substrate adjacent to the second dummy gate structure. | 2012-09-27 |
20120241869 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device includes forming a first and a second isolation insulating film to define a first, a second, a third and a fourth region, forming a first insulating film, implanting a first impurity of a first conductivity type through the first insulating film into the first, the second and the fourth region at a first depth, forming a second insulating film thinner than the first insulating film, implanting a second impurity of a second conductivity type through the second insulating film into the third region at a second depth in the semiconductor substrate, implanting a third impurity of the second conductivity type into the third region at a third depth shallower than the second depth, forming a first transistor of the first conductivity type in the third region, and forming a second transistor of the second conductivity type in the fourth region. | 2012-09-27 |
20120241870 | Bipolar junction transistor with surface protection and manufacturing method thereof - The present invention discloses a bipolar junction transistor (BJT) with surface protection and a manufacturing method thereof. The BJT includes: a first conductive type base, a second conductive type emitter, and a second conductive type collector, which are formed in a substrate, wherein the base is formed between and separates the emitter and the collector, and the base includes a base contact region functioning as an electrical contact node of the base; and a gate structure which is formed on the substrate between the base contact region and the second conductive type emitter. | 2012-09-27 |
20120241871 | INTEGRATING TRANSISTORS WITH DIFFERENT POLY-SILICON HEIGHTS ON THE SAME DIE - A method of fabricating an integrated circuit including a first region and a second region each having different poly-silicon gate structures is provided. The method includes depositing a first poly-silicon layer over the first and the second region and depositing, within the second region, an oxide layer over the first poly-silicon layer. A second poly-silicon layer is deposited over the first poly-silicon layer and the oxide region. A portion of the second poly-silicon layer that lies over the oxide region is then stripped away. | 2012-09-27 |
20120241872 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device in one embodiment includes a select gate switch transistor having a gate insulating film formed on a semiconductor substrate, a gate electrode formed on the gate insulating film, and first and second source/drain regions provided in the semiconductor substrate so as to face each other across the gate electrode. The first source/drain region includes a first n-type impurity layer and a second n-type impurity layer which has a higher impurity concentration and has a shallower depth than the first n-type impurity layer. The second source/drain region has a third n-type impurity layer which has a lower impurity concentration and has a shallower depth than the first n-type impurity layer and a fourth n-type impurity layer which has a higher impurity concentration and has a deeper depth than the third n-type impurity layer. | 2012-09-27 |
20120241873 | SEMICONDUCTOR DEVICE - A semiconductor device is disclosed. The semiconductor device includes: a substrate; a gate structure disposed on the substrate, wherein the gate structure comprises a high-k dielectric layer; and a first seal layer disposed on a sidewall of the gate structure, wherein the first seal layer is an oxygen-free seal layer. | 2012-09-27 |
20120241874 | GATE OXIDE FILM INCLUDING A NITRIDE LAYER DEPOSITED THEREON AND METHOD OF FORMING THE GATE OXIDE FILM - A method for forming a gate stack of a semiconductor device comprises depositing a gate oxide layer on a channel region of a semiconductor substrate using chemical vapor deposition, atomic layer deposition or molecular layer deposition, depositing a nitride layer on the gate oxide layer, oxidizing the deposited nitride layer, depositing a high-K dielectric layer on the oxidized nitride layer, and forming a metal gate on the high-K dielectric layer. | 2012-09-27 |
20120241875 | FIELD-EFFECT TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a field-effect transistor comprises a gate insulating film which is provided on a part of a Ge-containing substrate and the gate insulating film includes at least a GeO | 2012-09-27 |
20120241876 | SYSTEM AND METHOD FOR IMPROVING FREQUENCY RESPONSE - An electrical system and method for making the same includes a main circuit board and a plurality of contact pads located on a surface of the main circuit board. The contact pads are electrically conductive. Additionally, an integrated circuit package having at least one electrical device is attached to the surface of the main circuit board. A ball grid array made from a plurality of solder balls is located on a bottom side of the integrated circuit package. The ball grid array has a plurality of solder balls being electrically conductive and in electrical communication with the at least one electrical device. The solder balls further include solder balls of different material properties. | 2012-09-27 |
20120241877 | ACOUSTIC SEMICONDUCTOR DEVICE - According to one embodiment, an acoustic semiconductor device includes an element unit, and a first terminal. The element unit includes an acoustic resonance unit. The acoustic resonance unit includes a semiconductor crystal. An acoustic standing wave is excitable in the acoustic resonance unit and is configured to be synchronously coupled with electric charge density within at least one portion of the semiconductor crystal via deformation-potential coupling effect. The first terminal is electrically connected to the element unit. At least one selected from outputting and inputting an electrical signal is implementable via the first terminal. The electrical signal is coupled with the electric charge density. The outputting the electrical signal is from the acoustic resonance unit, and the inputting the electrical signal is into the acoustic resonance unit. | 2012-09-27 |
20120241878 | MAGNETIC TUNNEL JUNCTION WITH IRON DUSTING LAYER BETWEEN FREE LAYER AND TUNNEL BARRIER - A magnetic tunnel junction (MTJ) for a magnetic random access memory (MRAM) includes a magnetic free layer having a variable magnetization direction; an iron (Fe) dusting layer formed on the free layer; an insulating tunnel barrier formed on the dusting layer; and a magnetic fixed layer having an invariable magnetization direction, disposed adjacent the tunnel barrier such that the tunnel barrier is located between the free layer and the fixed layer; wherein the free layer and the fixed layer have perpendicular magnetic anisotropy and are magnetically coupled through the tunnel barrier. | 2012-09-27 |
20120241879 | MAGNETIC RANDOM ACCESS MEMORY AND METHOD OF FABRICATING THE SAME - According to one embodiment, a semiconductor device, includes a magneto resistive element including a first magnetic layer, a first interface magnetic layer, a nonmagnetic layer, a second interface magnetic layer and a second magnetic layer as a stacked structure in order; and a metal layer including first metal atoms, second metal atoms and boron atoms, the metal layer being provided at least one region selected from under the first magnetic, between the first magnetic layer and the first interface magnetic layer, between the second interface magnetic layer and the second magnetic layer, and upper the second magnetic layer. | 2012-09-27 |
20120241880 | MAGNETIC MEMORY AND MANUFACTURING METHOD THEREOF - According to one embodiment, a manufacturing method of a magnetic memory includes forming a magnetoresistive element in a cell array section on a semiconductor substrate, forming a dummy element in a peripheral circuit section on the semiconductor substrate, the dummy element having the same stacked structure as the magnetoresistive element and being arranged at the same level as the magnetoresistive element, collectively flattening the magnetoresistive element and the dummy element, applying a laser beam to the dummy element to form the dummy element into a non-magnetic body, and forming an upper electrode on the flattened magnetoresistive element. | 2012-09-27 |
20120241881 | MAGNETORESISTIVE ELEMENT AND MAGNETIC MEMORY - A magnetoresistive element according to an embodiment includes: a base layer; a first magnetic layer formed on the base layer, and including a first magnetic film having an axis of easy magnetization in a direction perpendicular to a film plane, the first magnetic film including Mn | 2012-09-27 |
20120241882 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device, the method comprising forming a magnetic tunnel junction pattern on a substrate, forming a spacer having a metal oxide layer on a sidewall of the magnetic tunnel junction pattern, forming a first interlayer insulating layer on the substrate having the spacer and the magnetic tunnel junction pattern formed thereon, forming a first damascene pattern by etching the first interlayer insulating layer so that a top portion of the magnetic tunnel junction pattern is exposed, and forming a first wire buried in the first damascene pattern. | 2012-09-27 |
20120241883 | SPIN TRANSPORT DEVICE AND MAGNETIC HEAD - The present invention provides a spin transport device having lowered areal resistance in its tunneling layer and a magnetic head. The spin transport device (magnetic sensor | 2012-09-27 |
20120241884 | MAGNETIC MEMORY - According to one embodiment, a magnetic memory includes a magnetoresistive element. The magnetoresistive element includes a reference layer having an invariable magnetization direction, a storage layer having a variable magnetization direction, and a spacer layer provided between the reference layer and the storage layer. The storage layer has a multilayered structure including first and second magnetic layers, the second magnetic layer is provided between the first magnetic layer and the spacer layer and has a magnetic anisotropy energy lower than that of the first magnetic layer, and an exchange coupling constant Jex between the first magnetic layer and the second magnetic layer is not more than 5 erg/cm | 2012-09-27 |
20120241885 | MAGNETIC DEVICES AND STRUCTURES - Magnetic devices, magnetoresistive structures, and methods and techniques associated with the magnetic devices and magnetoresistive structures are presented. For example, a magnetic device is presented. The magnetic device includes a ferromagnet, an antiferromagnet coupled to the ferromagnet, and a nonmagnetic metal proximate to the ferromagnet. The antiferromagnet provides uniaxial anisotropy to the magnetic device. A resistance of the nonmagnetic metal is dependent upon a direction of a magnetic moment of the ferromagnet. | 2012-09-27 |
20120241886 | MAGNETIC STACK WITH OXIDE TO REDUCE SWITCHING CURRENT - A magnetic stack having a ferromagnetic free layer, a metal oxide layer that is antiferromagnetic at a first temperature and non-magnetic at a second temperature higher than the first temperature, a ferromagnetic pinned reference layer, and a non-magnetic spacer layer between the free layer and the reference layer. During a writing process, the metal oxide layer is non-magnetic. For magnetic memory cells, such as magnetic tunnel junction cells, the metal oxide layer provides reduced switching currents. | 2012-09-27 |
20120241887 | VERTICAL HALL SENSOR AND METHOD FOR PRODUCING A VERTICAL HALL SENSOR - The invention relates to a vertical Hall sensor integrated in a semiconductor chip and a method for the production thereof. The vertical Hall sensor has an electrically conductive well of a first conductivity type, which is embedded in an electrically conductive region of a second conductivity type. The electrical contacts are arranged along a straight line on a planar surface of the electrically conductive well. The electrically conductive well is generated by means of high-energy ion implantation and subsequent heating, so that it has a doping profile which either has a maximum which is located at a depth T | 2012-09-27 |
20120241888 | SEMICONDUCTOR DEVICE USING CLOSE PROXIMITY WIRELESS COMMUNICATION - The present invention provides a semiconductor device capable of changing the setting of the internal operation mode without increasing the number of terminals of the semiconductor device. The semiconductor device | 2012-09-27 |
20120241889 | GAS BARRIER FILM, METHOD OF MANUFACTURING GAS BARRIER FILM, AND ORGANIC PHOTOELECTRIC CONVERSION ELEMENT - Disclosed is a gas barrier film which has both high gas barrier performance and high cracking (bending) resistance. Specifically disclosed is a gas barrier film which comprises, on a substrate in the following order, at least one silanol-containing layer and at least one gas barrier layer that contains silicon atoms and hydrogen atoms. The gas barrier film is characterized in that the relative SiOH ion strength in the central part of the silanol-containing layer in the film thickness direction as detected by time-of-flight secondary ion mass spectrometry (Tof-SIMS) is 0.02-1.0 when the relative Si ion strength is taken as 1. Also disclosed is an organic photoelectric conversion element which comprises the gas barrier film. | 2012-09-27 |
20120241890 | IR SENSOR USING REO UP-CONVERSION - A pumped sensor system includes a substrate with a first layer formed thereon and doped for a first type conduction and a second layer doped for a second type conduction, whereby the first and second layers form a silicon light detector at an up-conversion wavelength. A ternary rare earth oxide is formed on the second layer and crystal lattice matched to the second layer. The oxide is a crystalline bulk oxide with a controlled percentage of an up-conversion component and a majority component. The majority component is insensitive to any of pump, sense, or up-conversion wavelengths and the up-conversion component is selected to produce energy at the up-conversion wavelength in response to receiving energy at the pump and sense wavelengths. The layer of oxide defines a light input area sensitive to a pump wavelength and a light input area sensitive to a sense wavelength. | 2012-09-27 |
20120241891 | WIDE FIELD OF VIEW OPTICAL RECEIVER - Techniques are disclosed for creating optical systems and assemblies that provide increased field of view (FOV) for light detection by coupling a flip-chip light sensor directly to a condenser lens. According to certain embodiments of the invention, an optical assembly can include a condenser lens with a substantially flat surface optically contacted with a substantially flat surface of a substrate of a flip-chip light sensor. The thickness of the substrate is such that the active area of the light sensor is disposed on a focal plane of the optical system. This enables accurate light detection and increased FOV over conventional techniques. | 2012-09-27 |
20120241892 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - In a method for manufacturing a semiconductor device according to an embodiment, a trench is formed in an outer peripheral portion of a chip region on a bonding surface of a support substrate, and a semiconductor substrate having a chip ring in the outer peripheral portions of the chip regions on an inside of a dicing line respectively and the support substrate are bonded to position the trench from above the chip ring to the inside of the dicing line. In the method for manufacturing a semiconductor device, furthermore, the semiconductor substrate and the support substrate which are bonded to each other are subjected to dicing along the dicing line. | 2012-09-27 |
20120241893 | DEVICES INCLUDING BOND PAD HAVING PROTECTIVE SIDEWALL SEAL - A device having a detector includes a sensor package. The sensor package includes a light sensor, at least one filter located over the light sensor and at least one bond pad. The light sensor is formed on a semiconductor device that provides sensor information related to light incident upon the light sensor. A perimeter of each bond pad is covered by a protective layer forming a sidewall seal. The sensor package also includes a package that encases the light sensor, filter(s) and bond pad(s). Additionally, at least one package pin is communicatively coupled to the bond pad(s). The device also includes a functional circuit that is coupled to the sensor package and receives the sensor information from the light sensor. The device can be an ambient light sensor, camera, backlit mirror, handheld electronic device, filter device, light-to-digital output sensor, gain selection device, proximity sensor, or light-to-voltage non-linear converter. | 2012-09-27 |
20120241894 | PHOTOELECTRIC CONVERSION DEVICE AND METHOD FOR MANUFACTURING THE SAME - A circuit layer is formed on a surface of a substrate and includes a transistor. A photoelectric conversion element includes a photoelectric conversion layer of a chalcopyrite-type semiconductor provided between a first electrode and a second electrode. A supply layer is formed between the circuit layer and the photoelectric conversion layer and contains an Ia group element. Diffusion of the Ia group element to the photoelectric conversion layer improves the photoelectric conversion efficiency. A protective layer is formed between the supply layer and the circuit layer and prevents the diffusion of the Ia group element to the circuit layer. | 2012-09-27 |
20120241895 | SOLID-STATE IMAGING DEVICE, MANUFACTURING METHOD OF THE SAME AND ELECTRONIC APPARATUS - Disclosed herein is a solid-state imaging device including: an opto-electrical conversion section provided inside a semiconductor substrate to receive incident light coming from one surface of the semiconductor substrate; a wiring layer provided on the other surface of the semiconductor substrate; and a light absorption layer provided between the other surface of the semiconductor substrate and the wiring layer to absorb transmitted light passing through the opto-electrical conversion section as part of the incident light. | 2012-09-27 |
20120241896 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type, a plurality of second semiconductor regions of a second conductivity type, a third semiconductor region of the second conductivity type and a first electrode. The second regions are provided separately on a first major surface side of the first layer. The third region is provided on the first major surface side of the first layer so as to surround the second regions. The first electrode is provided on the first layer and the second regions. The first layer has a first portion and a second portion. The second portion has a lower resistivity than the first portion. The second portion is provided between the second regions and between the first portion and the first major surface and is provided outside the third region and between the first portion and the first major surface. | 2012-09-27 |
20120241897 | SEMICONDUCTOR SYSTEM INCLUDING A SCHOTTKY DIODE - A semiconductor system is described, which includes a trench junction barrier Schottky diode having an integrated p-n type diode as a clamping element, which is suitable for use in motor vehicle generator system, in particular as a Zener diode having a breakdown voltage of approximately 20V. In this case, the TJBS is a combination of a Schottky diode and a p-n type diode. Where the breakdown voltages are concerned, the breakdown voltage of the p-n type diode is lower than the breakdown voltage of Schottky diode. The semiconductor system may therefore be operated using high currents at breakdown. | 2012-09-27 |
20120241898 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a first semiconductor region of a first conductivity type, a first electrode, a second semiconductor region of the first conductivity type and a second electrode. The first semiconductor region includes a first portion including a first major surface and a second portion extending in a first direction perpendicular to the first major surface on the first major surface. The first electrode includes a third portion provided to face the second portion and is provided to be separated from the first semiconductor region. The second semiconductor region is provided between the second and third portions, includes a first concentration region having a lower impurity concentration than the first semiconductor region and forms a Schottky junction with the third portion. The second electrode is provided on an opposite side of the first major surface and in conduction with the first portion. | 2012-09-27 |
20120241899 | POWER SEMICONDUCTOR DEVICE - A power semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type, a third semiconductor layer of a second conductivity type, and a fourth semiconductor layer of the second conductivity type. The second semiconductor layer is provided on the first semiconductor layer and has a lower concentration of first conductivity type impurity than the first semiconductor layer. The third semiconductor layer is provided on a surface of the second semiconductor layer. The fourth semiconductor layer is selectively provided on a surface of the third semiconductor layer and has a higher concentration of second conductivity type impurity than the third semiconductor layer. The third semiconductor layer includes a carrier lifetime reducing region adjacent to a bottom surface of the fourth semiconductor layer. The carrier lifetime reducing region is spaced from the second semiconductor layer. | 2012-09-27 |
20120241900 | SELF DETECTION DEVICE FOR HIGH VOLTAGE ESD PROTECTION - An electrostatic discharge (ESD) protected device may include a substrate, an N-type well region disposed corresponding to a first portion of the substrate and having two N+ segments disposed at a surface thereof, an a P-type well region disposed proximate to a second portion of the substrate and having a P+ segment and an N+ segment. The two N+ segments may be spaced apart from each other and each may each be associated with an anode of the device. The N+ segment may be associated with a cathode of the device. A contact may be positioned in a space between the two N+ segments and connected to the P+ segment. The contact may form a parasitic capacitance that, in connection with a parasitic resistance formed in association with the N+ segment, provides self detection for high voltage ESD protection. | 2012-09-27 |
20120241901 | PACKAGE INTERCONNECTS - A method for forming a device is disclosed. A support substrate having first and second major surfaces is provided. An interconnect is formed through the first and second major surfaces in the support substrate. The interconnect has first and second portions. The first portion extends from one of the first or second major surfaces and the second portion extends from the other of the first and second major surfaces. The interconnect includes a partial via plug having a conductive material in a first portion of the interconnect. The via plug has a bottom at about an interface of the first and second portions. The second portion of the interconnect is heavily doped with dopants of a first polarity type. | 2012-09-27 |
20120241902 | SELF-ALIGNED DUAL DEPTH ISOLATION AND METHOD OF FABRICATION - FDSOI devices and methods for the fabrication thereof are provided. In one aspect, a method for fabricating a device includes the following steps. A wafer is provided having a substrate, a BOX and a SOI layer. A hardmask layer is deposited over the SOI layer. A photoresist layer is deposited over the hardmask layer and patterned into groups of segments. A tilted implant is performed to damage all but those portions of the hardmask layer covered or shadowed by the segments. Portions of the hardmask layer damaged by the implant are removed. A first etch is performed through the hardmask layer to form a deep trench in the SOI layer, the BOX and at least a portion of the substrate. The hardmask layer is patterned using the patterned photoresist layer. A second etch is performed through the hardmask layer to form shallow trenches in the SOI layer. | 2012-09-27 |
20120241903 | LOW CAPACITANCE TRANSIENT VOLTAGE SUPPRESSOR - A low capacitance transient voltage suppressor is disclosed. The suppressor comprises an N-type heavily doped substrate and an epitaxial layer formed on the substrate. At least one steering diode structure formed in the epitaxial layer comprises a diode lightly doped well and a first P-type lightly doped well, wherein a P-type heavily doped area is formed in the diode lightly doped well and a first N-type heavily doped area and a second P-type heavily doped area are formed in the first P-type lightly doped well. A second P-type lightly doped well having two N-type heavily doped areas is formed in the epitaxial layer. In addition, an N-type heavily doped well and at least one deep isolation trench are formed in the epitaxial layer, wherein the trench has a depth greater than or equal to depths of all the doped wells, so as to separate at least one doped well. | 2012-09-27 |