39th week of 2013 patent applcation highlights part 52 |
Patent application number | Title | Published |
20130252379 | METHOD FOR MAKING HIGH-SPEED CERAMIC MODULES WITH HYBRID REFERENCING SCHEME FOR IMPROVED PERFORMANCE AND REDUCED COST - A multi-layered ceramic package comprises: a signal layer with identified chip/device area(s) that require a supply of power; and a voltage power (Vdd) layer and a ground (Gnd) layer disposed on opposite sides directly above or below and adjacent to the signal layer and providing a first reference mesh plane and a second reference mesh plane configured utilizing a hybrid mesh scheme. The hybrid mesh scheme comprises: a full dense mesh in a first area directly above or below the identified chip/device area(s); a half dense mesh in a second area that is above or below the edge(s) of the chip/device area; and a wider mesh pitch in all other areas The Vdd traces are aligned to run parallel and adjacent to signal lines in those other areas. Wider traces are provided within the mesh areas that run parallel and adjacent to signal lines. | 2013-09-26 |
20130252380 | METHOD FOR FABRICATING PACKAGING STRUCTURE HAVING EMBEDDED SEMICONDUCTOR ELEMENT - A method for fabricating a packaging structure having an embedded semiconductor element includes: providing a substrate having opposite first and second surfaces and at least an opening penetrating the first and second surfaces; forming a first metallic frame around the periphery of the opening on the first surface; forming at least an opening inside the first metallic frame by laser ablation; disposing a semiconductor chip in the opening; forming a first dielectric layer on the first and second surfaces and the chip; forming a first wiring layer on the first dielectric layer of the first surface; and forming a first built-up structure on the first dielectric layer and the first wiring layer of the first surface. A shape of the opening is precisely controlled through the first metallic frame around the periphery of the predefined opening region, thereby allowing the chip to be precisely embedded in the substrate. | 2013-09-26 |
20130252381 | Electrically Isolated Power Semiconductor Package With Optimized Layout - A packaged power semiconductor device is provided with voltage isolation between a metal backside and terminals of the device. The packaged power semiconductor device is arranged in an encapsulant defining a hole for receiving a structure for physically coupling the device to an object. A direct-bonded copper (“DBC”) substrate is used to provide electrical isolation and improved thermal transfer from the device to a heatsink. At least one power semiconductor die is mounted to a first metal layer of the DBC substrate. The first metal layer spreads heat generated by the semiconductor die. In one embodiment, the packaged power semiconductor device conforms to a TO-247 outline and is capable of receiving a screw for physically coupling the device to a heatsink. | 2013-09-26 |
20130252382 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes providing an electrically conductive carrier and placing a semiconductor chip over the carrier. The method includes applying an electrically insulating layer over the carrier and the semiconductor chip. The electrically insulating layer has a first face facing the carrier and a second face opposite to the first face. The method includes selectively removing the electrically insulating layer and applying solder material where the electrically insulating layer is removed and on the second face of the electrically insulating layer. | 2013-09-26 |
20130252383 | FABRICATION METHOD OF WAFER LEVEL SEMICONDUCTOR PACKAGE AND FABRICATION METHOD OF WAFER LEVEL PACKAGING SUBSTRATE - A fabrication method of a wafer level semiconductor package includes: forming on a carrier a first dielectric layer having first openings exposing portions of the carrier; forming a circuit layer on the first dielectric layer, a portion of the circuit layer being formed in the first openings; forming on the first dielectric layer and the circuit layer a second dielectric layer having second openings exposing portions of the circuit layer; forming conductive bumps in the second openings; mounting a semiconductor component on the conductive bumps; forming an encapsulant for encapsulating the semiconductor component; and removing the carrier to expose the circuit layer. By detecting the yield rate of the circuit layer before mounting the semiconductor component, the invention avoids discarding good semiconductor components together with packages as occurs in the prior art, thereby saving the fabrication cost and improving the product yield. | 2013-09-26 |
20130252384 | TRENCH FORMING METHOD, METAL WIRING FORMING METHOD, AND METHOD OF MANUFACTURING THIN FILM TRANSISTOR ARRAY PANEL - A method of forming a thin film transistor array panel includes: forming a first insulating layer on a substrate; forming an amorphous carbon layer on the first insulating layer; forming a second insulating layer on the amorphous carbon layer; forming an opening in the amorphous carbon layer by patterning the second insulating layer and the amorphous carbon layer; and forming a trench in the first insulating layer by etching the first insulating layer, the etching the first insulating layer using the amorphous carbon layer including the opening as a mask. | 2013-09-26 |
20130252385 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - For forming a gate electrode, a conductive film with low resistance including Al or a material containing Al as its main component and a conductive film with low contact resistance for preventing diffusion of Al into a semiconductor layer are laminated, and the gate electrode is fabricated by using an apparatus which is capable of performing etching treatment at high speed. | 2013-09-26 |
20130252386 | METHODS OF FABRICATING NITRIDE-BASED TRANSISTORS WITH AN ETCH STOP LAYER - A III-Nitride field-effect transistor, specifically a HEMT, comprises a channel layer, a barrier layer on the channel layer, an etch stop layer on the cap layer, a dielectric layer on the etch stop layer, a gate recess that extends to the barrier layer, and a gate contact in the gate recess. The etch stop layer may reduce damage associated with forming the recessed gate by not exposing the barrier layer to dry etching. The etch stop layer in the recess is removed and the remaining etch stop layer serves as a passivation layer. | 2013-09-26 |
20130252387 | METAL-GATE CMOS DEVICE AND FABRICATION METHOD THEREOF - A method for fabricating a metal-gate CMOS device. A substrate having thereon a first region and a second region is provided. A first dummy gate structure and a second dummy gate structure are formed within the first region and the second region respectively. A first LDD is formed on either side of the first dummy gate structure and a second LDD is formed on either side of the second dummy gate structure. A first spacer is formed on a sidewall of the first dummy gate structure and a second spacer is formed on a sidewall of the second dummy gate structure. A first embedded epitaxial layer is then formed in the substrate adjacent to the first dummy gate structure. The first region is masked with a seal layer. Thereafter, a second embedded epitaxial layer is formed in the substrate adjacent to the second dummy gate structure. | 2013-09-26 |
20130252388 | METHOD OF MANUFACTURING NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A method of manufacturing a non-volatile semiconductor memory device of an embodiment includes: forming, on a semiconductor substrate, an element isolation region to be filled with a first insulating film; forming memory cell gate electrodes on element regions; etching the first insulating film so that the first insulating film remains in the element isolation region of a region in which a select gate electrode is to be formed; forming a second insulating film on the memory cell gate electrodes so that an air gap is created between the memory cell gate electrodes; forming two select gate electrodes; forming carbon side walls on the select gate electrodes; implanting ions of an impurity between the two select gate electrodes with the side walls as a mask; and removing the carbon side walls. | 2013-09-26 |
20130252389 | NONVOLATILE SEMICONDUCTOR MEMORY TRANSISTOR AND METHOD FOR MANUFACTURING NONVOLATILE SEMICONDUCTOR MEMORY - A nonvolatile semiconductor memory transistor includes an island-shaped semiconductor having a source region, a channel region, and a drain region formed in this order from the silicon substrate side, a floating gate arranged so as to surround the outer periphery of the channel region with a tunnel insulating film interposed between the floating gate and the channel region, a control gate arranged so as to surround the outer periphery of the floating gate with an inter-polysilicon insulating film interposed between the control gate and the floating gate, and a control gate line electrically connected to the control gate and extending in a predetermined direction. The inter-polysilicon insulating film is arranged so as to be interposed between the floating gate and the lower and inner side surfaces of the control gate and between the floating gate and the lower surface of the control gate line. | 2013-09-26 |
20130252390 | CAPACITOR-LESS MEMORY CELL, DEVICE, SYSTEM AND METHOD OF MAKING SAME - A capacitor-less memory cell, memory device, system and process of forming the capacitor-less memory cell includes forming the memory cell in an active area of a substantially physically isolated portion of the bulk semiconductor substrate. A pass transistor is formed on the active area for coupling with a word line. The capacitor-less memory cell further includes a read/write enable transistor vertically configured along at least one vertical side of the active area and operable during a reading of a logic state with the logic state being stored as charge in a floating body area of the active area, causing different determinable threshold voltages for the pass transistor. | 2013-09-26 |
20130252391 | NONVOLATILE MEMORY DEVICE, METHOD OF MANUFACTURING THE NONVOLATILE MEMORY DEVICE, AND MEMORY MODULE AND SYSTEM INCLUDING THE NONVOLATILE MEMORY DEVICE - A nonvolatile memory device includes a substrate, a channel layer protruding from the substrate, a gate conductive layer surrounding the channel layer, a gate insulating layer disposed between the channel layer and the gate conductive layer, and a first insulating layer spaced apart from the channel layer and disposed on the top and bottom of the gate conductive layer. The gate insulating layer extends between the gate conductive layer and the first insulating layer. | 2013-09-26 |
20130252392 | Performing Enhanced Cleaning in the Formation of MOS Devices - A method includes etching a semiconductor substrate to form a recess, wherein the recess extends from a top surface of the semiconductor substrate into the semiconductor substrate. An enhanced cleaning is then performed to etch exposed portions of the semiconductor substrate. The exposed portions are in the recess. The enhanced cleaning is performed using process gases including hydrochloride (HCl) and germane (GeH | 2013-09-26 |
20130252393 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - In a method of forming MOS transistor, a gate structure is formed on a substrate and a first spacer layer is formed on the substrate conformal to the gate structure. A second spacer layer is formed on the first spacer layer. A second spacer is formed on the first spacer layer corresponding to a sidewall of the gate structure by partially removing the second spacer layer from the first spacer layer. Impurities are implanted in the substrate by an ion implantation process using the gate structure including the first spacer layer and the second spacer as an ion implantation mask to form source/drain extension regions at surface portions of the substrate around the gate structure. | 2013-09-26 |
20130252394 | PREPARATION METHOD FOR RESISTANCE SWITCHABLE CONDUCTIVE FILLER FOR RERAM - Disclosed are methods for preparing a resistive random-access memory (ReRAM) based on resistive switching using a resistance-switchable conductive filler. When a resistance-switchable conductive filler prepared by coating a conductive filler with a material whose resistance is changeable is mixed with a dielectric material, the dielectric material is given the resistive switching characteristics without losing its inherent properties. Therefore, various resistance-switchable materials having various properties can be prepared by mixing the resistance-switchable conductive filler with different dielectric materials. The resulting resistance-switchable material shows resistive switching characteristics comparable to those of the existing metal oxide film-based resistance-switchable materials. Accordingly, a ReRAM device having the inherent properties of a dielectric material can be prepared using the resistance-switchable conductive filler. | 2013-09-26 |
20130252395 | RESISTIVE RANDOM ACCESS MEMORY AND METHOD OF MANUFACTURING THE SAME - Example embodiments relate to a resistive random access memory (RRAM) and a method of manufacturing the RRAM. A RRAM according to example embodiments may include a lower electrode, which may be formed on a lower structure (e.g., substrate). A resistive layer may be formed on the lower electrode, wherein the resistive layer may include a transition metal dopant. An upper electrode may be formed on the resistive layer. Accordingly, the transition metal dopant may form a filament in the resistive layer that operates as a current path. | 2013-09-26 |
20130252396 | CONFINED RESISTANCE VARIABLE MEMORY CELL STRUCTURES AND METHODS - Confined resistance variable memory cell structures and methods are described herein. One or more methods of forming a confined resistance variable memory cell structure includes forming a via in a memory cell structure and forming a resistance variable material in the via by performing a process that includes providing a germanium amidinate precursor and a first reactant to a process chamber having the memory cell structure therein and providing an antimony ethoxide precursor and a second reactant to the process chamber subsequent to removing excess germanium. | 2013-09-26 |
20130252397 | MANUFACTURING METHOD FOR HIGH CAPACITANCE CAPACITOR STRUCTURE - A manufacturing method of a capacitor structure is provided, which includes the steps of: on a substrate having a first oxide layer, (a) forming a first suspension layer on the first oxide layer; (b) forming a first shallow trench into the first oxide layer above the substrate; (c) forming a second oxide layer filling the first shallow trench; (d) forming a second suspension layer on the second oxide layer; (e) forming a second shallow trench through the second suspension layer into the second oxide layer above the first suspension layer; (f) forming at least one deep trench on the bottom surface of the second shallow trench through the second and the first oxide layers, (g) forming an electrode layer on the inner surface of the deep trench; and (h) removing the first and second oxide layers through the trench openings in the first and the second suspension layers. | 2013-09-26 |
20130252398 | Methods for Forming Semiconductor Constructions, and Methods for Selectively Etching Silicon Nitride Relative to Conductive Material - The invention includes methods for selectively etching insulative material supports relative to conductive material. The invention can include methods for selectively etching silicon nitride relative to metal nitride. The metal nitride can be in the form of containers over a semiconductor substrate, with such containers having upwardly-extending openings with lateral widths of less than or equal to about 4000 angstroms; and the silicon nitride can be in the form of a layer extending between the containers. The selective etching can comprise exposure of at least some of the silicon nitride and the containers to Cl | 2013-09-26 |
20130252399 | DIRECT BONDING PROCESS USING A COMPRESSIBLE POROUS LAYER - A method for direct bonding between a first element and a second element, including at least the following steps:
| 2013-09-26 |
20130252400 | METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - A single crystal substrate made of silicon carbide and a first support substrate having a size greater than a size of each of the single crystal substrates are prepared. The single crystal substrate is bonded onto the first support substrate. Process on the single crystal substrate bonded to the first support substrate is performed. The first support substrate is removed. The single crystal substrate is subjected to heat treatment. The single crystal substrate is bonded onto a second support substrate having a size greater than the size of the single crystal substrate. Process on the single crystal substrate bonded to the second support substrate is performed. | 2013-09-26 |
20130252401 | NITRIDE SEMICONDUCTOR SUBSTRATE, SEMICONDUCTOR DEVICE, AND METHODS FOR MANUFACTURING NITRIDE SEMICONDUCTOR SUBSTRATE AND SEMICONDUCTOR DEVICE - A nitride semiconductor substrate having a main surface serving as a semipolar plane and provided with a chamfered portion capable of effectively preventing cracking and chipping, a semiconductor device fabricated using the nitride semiconductor substrate, and a method for manufacturing the nitride semiconductor substrate and the semiconductor device are provided. The nitride semiconductor substrate includes a main surface inclined at an angle of 71° or more and 79° or less with respect to the (0001) plane toward the [1-100] direction or inclined at an angle of 71° or more and 79° or less with respect to the (000-1) plane toward the [−1100] direction; and a chamfered portion located at an edge of an outer periphery of the main surface. The chamfered portion is inclined at an angle θ | 2013-09-26 |
20130252402 | LASER PROCESSING METHOD - A laser processing method which can highly accurately cut objects to be processed having various laminate structures is provided. An object to be processed comprising a substrate and a laminate part disposed on the front face of the substrate is irradiated with laser light L while a light-converging point P is positioned at least within the substrate, so as to form a modified region due to multiphoton absorption at least within the substrate, and cause the modified region to form a starting point region for cutting. When the object is cut along the starting point region for cutting, the object | 2013-09-26 |
20130252403 | METHOD OF CUTTING SEMICONDUCTOR SUBSTRATE - Multiphoton absorption is generated, so as to form a part which is intended to be cut | 2013-09-26 |
20130252404 | KEYED WAFER CARRIER - A structure for a chemical vapor deposition reactor desirably includes a reaction chamber having an interior, a spindle mounted in the reaction chamber, and a wafer carrier releasably mounted onto the spindle for rotation therewith. The spindle desirably has a shaft extending along a vertical rotational axis and a key projecting outwardly from the shaft. The wafer carrier preferably has a body defining oppositely-facing top and bottom surfaces and at least one wafer-holding feature configured so that a wafer can be held therein with a surface of the wafer exposed at the top surface of the body. The wafer carrier desirably further has a recess extending into the body from the bottom surface of the body and a keyway projecting outwardly from a periphery of the recess along a first transverse axis. The shaft preferably is engaged in the recess and the key preferably is engaged into the keyway. | 2013-09-26 |
20130252405 | METHOD FOR MAKING SEMICONDUCTING SINGLE WALL CARBON NANOTUBES - A method for making semiconducting single walled carbon nanotubes (SWCNTs) includes providing a substrate. A single walled carbon nanotube film including metallic SWCNTs and semiconducting SWCNTs is located on the substrate. At least one electrode is located on the single walled carbon nanotube film and electrically connected with the single walled carbon nanotube film. A macromolecule material layer is located on the single walled carbon nanotube film to cover the single walled carbon nanotube film. The macromolecule material layer covering the metallic SWCNTs is removed by an electron beam bombardment method, to expose the metallic SWCNTs. The metallic SWCNTs and the macromolecule material layer covering the semiconducting SWCNTs are removed. | 2013-09-26 |
20130252406 | Techniques for drying and annealing thermoelectric powders - Embodiments of the invention include a method of producing a low contaminant, stoichiometrically controlled semiconductor material, the method comprising providing a colloidal suspension of a plurality of colloidally grown semiconductor nanocrystals, providing an inorganic ligand structure around a surface of the semiconductor nanocrystals of the plurality of semiconductor nanocrystals, drying the colloidal suspension into a powder, and pre-annealing the powder into a semiconductor material. | 2013-09-26 |
20130252407 | SILICON POLYMERS, METHODS OF POLYMERIZING SILICON COMPOUNDS, AND METHODS OF FORMING THIN FILMS FROM SUCH SILICON POLYMERS - Compositions and methods for controlled polymerization and/or oligomerization of hydrosilanes compounds including those of the general formulae Si | 2013-09-26 |
20130252408 | METHOD FOR FABRICATING SCHOTTKY DEVICE - A method for fabricating a Schottky device includes the following sequences. First, a substrate with a first conductivity type is provided and an epitaxial layer with the first conductivity type is grown on the substrate. Then, a patterned dielectric layer is formed on the epitaxial layer, and a metal silicide layer is formed on a surface of the epitaxial layer. A dopant source layer with a second conductivity type is formed on the metal silicide layer, followed by applying a thermal drive-in process to diffuse the dopants inside the dopant source layer into the epitaxial layer. Finally, a conductive layer is formed on the metal silicide layer. | 2013-09-26 |
20130252409 | HIGH-K GATE ELECTRODE STRUCTURE FORMED AFTER TRANSISTOR FABRICATION BY USING A SPACER - During a replacement gate approach, the inverse tapering of the opening obtained after removal of the polysilicon material may be reduced by depositing a spacer layer and forming corresponding spacer elements on inner sidewalls of the opening. Consequently, the metal-containing gate electrode material and the high-k dielectric material may be deposited with enhanced reliability. | 2013-09-26 |
20130252410 | SELECTIVE LOW-TEMPERATURE OHMIC CONTACT FORMATION METHOD FOR GROUP III-NITRIDE HETEROJUNCTION STRUCTURED DEVICE - A method for forming a selective ohmic contact for a Group III-nitride heterojunction structured device may include forming a conductive layer and a capping layer on an epitaxial substrate including at least one Group III-nitride heterojunction layer and having a defined ohmic contact region, the capping layer being formed on the conductive layer or between the conductive layer and the Group III-nitride heterojunction layer in one of the ohmic contact region and non-ohmic contact region, and applying at least one of a laser annealing process and an induction annealing process on the substrate at a temperature of less than or equal to about 750° C. to complete the selective ohmic contact in the ohmic contact region. | 2013-09-26 |
20130252411 | MANUFACTURING METHOD OF A SEMICONDUCTOR DEVICE - According one embodiment, a method for manufacturing a semiconductor device is provided, which includes forming a pair of element isolation insulation films on a semiconductor substrate, forming a gate electrode structure on sides of the gate electrode structure, selectively removing oxide films that are formed on a top surface of the diffusion layer and a top surface of the gate electrode by placing the substrate in a gas atmosphere selected from the group consisting of F, Cl, Br, I, H, O, Ar, or N; and irradiating the semiconductor substrate with microwave radiation. The method also includes depositing a metal film on a top surface of the diffusion layer and a top surface of the gate electrode, and a silicide film is formed by heating the substrate. | 2013-09-26 |
20130252412 | PROCESS FOR PRODUCING AN INTEGRATED CIRCUIT - A process for producing an integrated circuit on the surface of a substrate, the process including: producing a first layer, including active zones and insulating zones, on the surface of the substrate; producing gate zones on the surface of the first layer, the gate zones each being surrounded by insulating spacers; producing source/drain electrodes; producing a dielectric layer between the insulating spacers, the dielectric layer having an upper surface level with the upper surfaces of the gate zones; partially etching each gate zone so as to lower the upper surface of a first part of each gate zone; and depositing an insulating dielectric layer on the first parts of the gate zones. | 2013-09-26 |
20130252413 | SURROUND GATE CMOS SEMICONDUCTOR DEVICE - The semiconductor device includes: a columnar silicon layer on the planar silicon layer; a first n+ type silicon layer formed in a bottom area of the columnar silicon layer; a second n+ type silicon layer formed in an upper region of the columnar silicon layer; a gate insulating film formed in a perimeter of a channel region between the first and second n+ type silicon layers; a gate electrode formed in a perimeter of the gate insulating film, and having a first metal-silicon compound layer; an insulating film formed between the gate electrode and the planar silicon layer, an insulating film sidewall formed in an upper sidewall of the columnar silicon layer; a second metal-silicon compound layer formed in the planar silicon layer; and an electric contact formed on the second n+ type silicon layer. | 2013-09-26 |
20130252414 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR AFFIXING A POST TO A SUBSTRATE PAD - A system, method, and computer program product are provided for affixing a post to a substrate pad. In use, a post is affixed to each of one or more pads of a substrate, where each post receives a ball of a package during an assembly process. | 2013-09-26 |
20130252415 | STRUCTURE AND PROCESS FOR METALLIZATION IN HIGH ASPECT RATIO FEATURES - A high aspect ratio metallization structure is provided in which a noble metal-containing material is present at least within a lower portion of a contact opening located in a dielectric material and is in direct contact with a metal semiconductor alloy located on an upper surface of a material stack of at least one semiconductor device. In one embodiment, the noble metal-containing material is plug located within the lower region of the contact opening and an upper region of the contact opening includes a conductive metal-containing material. The conductive metal-containing material is separated from plug of noble metal-containing material by a bottom walled portion of a U-shaped diffusion barrier. In another embodiment, the noble metal-containing material is present throughout the entire contact opening. | 2013-09-26 |
20130252416 | METHOD OF MANUFACTURING A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - The TSV technology has been popular as one of stacking technologies of a plurality of semiconductor chips. It has however been revealed by the present inventors that when TSV is formed using a so-called first via process, via middle process, front-via via last process, or the like, there is a possibility of defects such as gate breakdown occurring due to electrostatic breakdown in the subsequent process. | 2013-09-26 |
20130252417 | THIN FILM FORMING METHOD - A thin film forming method in which a thin film is formed on a surface of a target object to be processed to fill a recess formed in the surface of the target object includes the steps of forming a metal layer for filling on the surface of the target object to fill the recess formed in the surface of the target object and forming a metal film for preventing diffusion on an entire surface of the target object to cover the metal layer for filling. The thin film forming method further includes the step of annealing the target object having the metal film for preventing diffusion formed thereon. | 2013-09-26 |
20130252418 | ELECTROMIGRATION-RESISTANT LEAD-FREE SOLDER INTERCONNECT STRUCTURES - Embodiments of the invention include a lead-free solder interconnect structure and methods for making a lead-free interconnect structure. The structure includes a semiconductor substrate having a last metal layer, a copper pedestal attached to the last metal layer, a barrier layer attached to the copper pedestal, a barrier protection layer attached to the barrier layer, and a lead-free solder layer contacting at least one side of the copper pedestal. | 2013-09-26 |
20130252419 | Metal Alloy Cap Integration - A metal interconnect structure, which includes metal alloy capping layers, and a method of manufacturing the same. The originally deposited alloy capping layer element within the interconnect features will diffuse into and segregate onto top surface of the metal interconnect. The metal alloy capping material is deposited on a reflowed copper surface and is not physically in contact with sidewalls of the interconnect features. The metal alloy capping layer is also reflowed on the copper. Thus, there is a reduction in electrical resistivity impact from residual alloy elements in the interconnect structure. That is, there is a reduction, of alloy elements inside the features of the metal interconnect structure. The metal interconnect structure includes a dielectric layer with a recessed line, a liner material on sidewalls, a copper material, an alloy capping layer, and a dielectric cap. | 2013-09-26 |
20130252420 | METHOD FOR FORMING FINE PITCH STRUCTURES - A mold having an open interior volume is used to define patterns. The mold has a ceiling, floor and sidewalls that define the interior volume and inhibit deposition. One end of the mold is open and an opposite end has a sidewall that acts as a seed sidewall. A first material is deposited on the seed sidewall. A second material is deposited on the deposited first material. The deposition of the first and second materials is alternated, thereby forming alternating rows of the first and second materials in the interior volume. The mold and seed layer are subsequently selectively removed. In addition, one of the first or second materials is selectively removed, thereby forming a pattern including free-standing rows of the remaining material. The free-standing rows can be utilized as structures in a final product, e.g., an integrated circuit, or can be used as hard mask structures to pattern an underlying substrate. The mold and rows of material can be formed on multiple levels. The rows on different levels can crisscross one another. Selectively removing material from some of the rows can from openings to form, e.g., contact vias. | 2013-09-26 |
20130252421 | METHOD OF PROCESSING SILICON AND GLASS SUBSTRATES USING A LASER PEELING TECHNIQUE - According to one embodiment, a method of manufacturing a semiconductor device including forming a metal film on aback surface of a glass substrate which supports a semiconductor substrate on a front surface thereof; forming a metal oxide film by oxidizing the whole or at least a portion of the metal film from the front surface; forming protective film, such as silicon nitride, on the metal oxide film; holding the front surface of the protective film with an electrostatic chuck; and forming a via for electrical connection in the semiconductor substrate while the front surface of the protective film is in contact with by the electrostatic chuck; then using a laser to delaminate the glass substrate from the semiconductor substrate. | 2013-09-26 |
20130252422 | METHODS OF FORMING SEMICONDUCTOR STRUCTURES - In a method of forming a semiconductor structure, a through-silicon-via (TSV) opening is formed in a substrate. A dielectric layer is formed to continuously extend over the substrate and into the TSV opening. At least one conductive material is formed over the dielectric layer and in the TSV opening. A portion of the at least one conductive material that is over the dielectric layer is removed to form a TSV structure in the substrate. A metallic line is formed in the dielectric layer. A portion of the substrate is removed, such that the TSV structure continuously extends through the substrate and the dielectric layer. | 2013-09-26 |
20130252423 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device and semiconductor device. One embodiment provides a semiconductor substrate with an active region and a margin region bordering on the active region. The spacer layer in the margin region is broken through at a selected location and at least part of the spacer layer is removed in the active region using a common process. The location is selected such that at least part of the semiconductor mesa structure is exposed and the spacer layer in the margin region is broken through to the conductive layer and not to the semiconductor substrate. | 2013-09-26 |
20130252424 | WAFER HOLDER WITH TAPERED REGION - An apparatus, a system and a method are disclosed. An exemplary apparatus includes a wafer holder including a first portion and a second portion. The first and second portions are formed of the same continuous material. The first portion includes a first upper surface and a first lower surface, and the second portion including a second upper surface and a second lower surface. The apparatus further includes an interface between the first and second portions. The interface provides for a transition such that the first upper surface of the first portion tends toward the second upper surface of the second portion. The apparatus further includes a tapered region formed in the first portion. The tapered region starts at a radial distance from a center line of the wafer holder and terminates at the interface. The tapered region has an initial thickness that gradually decreases to a final thickness. | 2013-09-26 |
20130252425 | METHOD OF FORMING A SEMICONDUCTOR DEVICE - A method includes providing a first mask pattern over a substrate, forming first spacers adjoining sidewalls of the first mask pattern, removing the first mask pattern, forming second spacers adjoining sidewalls of the first spacers, forming a filling layer over the substrate and between the second spacers, and forming a second mask pattern over the substrate. | 2013-09-26 |
20130252426 | POLISHING AGENT AND METHOD FOR POLISHING SUBSTRATE USING THE POLISHING AGENT - Disclosed is a polishing agent comprising: water; tetravalent metal hydroxide particles; and an additive, wherein the additive contains at least one of a cationic polymer and a cationic polysaccharide. The present invention can provide a polishing agent which is capable of polishing an insulating film at a high speed with less polishing flaws, and having a high polishing rate ratio of a silicon oxide film and a stopper film, in the CMP technology of flattening insulating film. The present invention can also provide a polishing agent set for storing the polishing agent, and a method for polishing a substrate using this polishing agent. | 2013-09-26 |
20130252427 | METHOD FOR CLEANING TEXTURED SILICON WAFERS - Substrates for solar cells are prepared by the reverse of the standard RCA clean. The substrates are first cleaned in RCA-2 solution and then in RCA-1 solution. A pyramids rounding step using HF/HNO | 2013-09-26 |
20130252428 | Photo-etching and Exposing System - A method of photo-etching is proposed. The method includes steps as follows. Expose a photoresist layer with a stack of at least two masks. Each mask defines a corresponding pattern, and a new pattern is formed when the at least two masks are stacked. Process the exposed photoresist layer to derive a hollow-out structure that complements the new pattern. A mask system is also proposed. The adoption of the abovementioned method can lower the possibility of manufacturing new masks and reduce production costs. | 2013-09-26 |
20130252429 | MASK AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A photo mask for exposing according to an embodiment includes a mark pattern arranged in a mark region that is different from an effective region to form a semiconductor device; and a regular pattern arranged in the mark region and around the mark pattern and smaller than the mark pattern in size and pitch. | 2013-09-26 |
20130252430 | METHOD FOR REDUCING DAMAGE TO LOW-K GATE SPACER DURING ETCHING - A method for performing a spacer etch process is described. The method includes providing a gate structure on a substrate having a low-k spacer material conformally applied over the gate structure, and performing a spacer etch process sequence to partially remove the spacer material from the gate structure and the substrate, while retaining a sidewall spacer positioned along a sidewall of the gate structure. The spacer etch process sequence may include depositing a spacer protection layer on an exposed surface of said spacer material, and performing one or more etching processes to selectively and anisotropically remove the spacer protection layer and the spacer material to leave behind the sidewall spacer on the sidewall of the gate structure, wherein, while being partly or fully consumed by the one or more etching processes, the spacer protection layer exhibits a reduced variation in composition and/or dielectric constant. | 2013-09-26 |
20130252431 | Method of Forming Trench in Semiconductor Substrate - The present invention provides a method of forming a trench in a semiconductor substrate. First, a first patterned mask layer is formed on a semiconductor substrate. The first patterned mask layer has a first trench. Then, a material layer is formed along the first trench. Then, a second patterned mask layer is formed on the material layer to completely fill the first trench. A part of the material layer is removed when the portion of the material layer between the second patterned mask layer and the semiconductor substrate is maintained so as to form a second trench. Lastly, an etching process is performed by using the first patterned mask layer and the second patterned mask layer as a mask. | 2013-09-26 |
20130252432 | PATTERNING METHOD - Provided is a patterning method that can greatly reduce process costs and environmental load. The patterning method includes: a film forming step of forming a functional film ( | 2013-09-26 |
20130252433 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD, SUBSTRATE PROCESSING APPARATUS, AND NON-TRANSITORY RECORDING MEDIUM - A method of manufacturing a semiconductor device includes: accommodating a substrate having an oxide film formed thereon into a processing chamber; supplying a process gas to the substrate; performing a preprocessing step in which the process gas is excited in a state that a pressure within the processing chamber is kept at a first pressure and an electric potential of the substrate is kept at a first electric potential; and performing a main processing step by which the process gas is excited in a state that the pressure within the processing chamber is kept at a second pressure and the electric potential of the substrate is kept at a second electric potential, wherein the first pressure is lower than the second pressure and the first electric potential is lower than the second electric potential. | 2013-09-26 |
20130252434 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, METHOD OF PROCESSING SUBSTRATE, SUBSTRATE PROCESSING APPARATUS, AND RECORDING MEDIUM - A method of manufacturing a semiconductor device includes carrying a substrate into a process container, forming a thin film on the substrate by supplying a source gas into the process container with the substrate accommodated therein, performing a first modification treatment to a byproduct adhered to an inside of the process container by supplying an oxygen-containing gas and a hydrogen-containing gas into the heated process container under a pressure less than an atmospheric pressure, while accommodating the thin film-formed substrate in the process container, carrying the thin film-formed substrate out of the process container, and performing a second modification treatment to the byproduct adhered to the inside of the process container after the first modification treatment by supplying an oxygen-containing gas and a hydrogen-containing gas into the heated process container under the pressure less than the atmospheric pressure, while not accommodating the substrate in the process container. | 2013-09-26 |
20130252435 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, METHOD OF PROCESSING SUBSTRATE, SUBSTRATE PROCESSING APPARATUS AND NON-TRANSITORY COMPUTER-READABLE RECORDING MEDIUM - An object of the present invention is to form a good thin film while suppressing generation of foreign substances in a low temperature region. Provided is a method of manufacturing a semiconductor device, including: (a) forming a thin film containing at least a predetermined element and carbon on a substrate by performing a cycle a predetermined number of times, the cycle including: supplying a source gas containing the predetermined element and a halogen element to the substrate in a process container; and supplying an amine-based gas to the substrate in the process container; and (b) modifying byproducts adhered to an inside of the process container by supplying a nitriding gas into the process container after forming the thin film | 2013-09-26 |
20130252436 | DIELECTRIC THIN FILM, METHOD OF MANUFACTURING SAME, AND APPLICATIONS THEREOF - A dielectric thin film and a method of manufacturing the same, wherein the manufacture of a dielectric thin film having a composition represented by Ba | 2013-09-26 |
20130252437 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, METHOD OF PROCESSING SUBSTRATE, SUBSTRATE PROCESSING APPARATUS, AND RECORDING MEDIUM - A method of manufacturing a semiconductor device includes forming a thin film on a substrate by performing a cycle a predetermined number of times. The cycle includes supplying a source gas to the substrate, and supplying excited species from each of a plurality of excitation units provided at a side of the substrate to the substrate. Each of the plurality of excitation units generates the excited species by plasma-exciting a reaction gas. In supplying the excited species from each of the plurality of excitation units, an in-plane distribution of the excited species supplied from at least one of the plurality of excitation units in the substrate differs from an in-plane distribution of the excited species supplied from another excitation unit, other than the at least one excitation unit, among the plurality of excitation units, in the substrate. | 2013-09-26 |
20130252438 | METHOD FOR THE DEPOSITION OF A RUTHENIUM-CONTAINING FILM - The invention concerns the use of the ruthenium-containing precursor having the formula | 2013-09-26 |
20130252439 | Method of Manufacturing Semiconductor Device, Substrate Processing Apparatus and Non-Transitory Computer-Readable Recording Medium - A method includes: forming a thin film on a substrate by performing a cycle a predetermined number of times, the cycle including: (a) supplying a source gas to the substrate in a process chamber; and (b) supplying a reactive gas to the substrate in the process chamber, wherein at least one of (a) and (b) includes: (c) supplying the source gas or the reactive gas at a first flow rate with exhaust of an inside of the process chamber being suspended until an inner pressure of the process chamber reaches a predetermined pressure; and (d) supplying the source gas or the reactive gas at a second flow rate less than the first flow rate with exhaust of the inside of the process chamber being performed while maintaining the inner pressure of the process chamber at the predetermined pressure after the inner pressure of the process chamber reaches the predetermined pressure. | 2013-09-26 |
20130252440 | PRETREATMENT AND IMPROVED DIELECTRIC COVERAGE - Methods of conformally depositing silicon oxide layers on patterned substrates are described. The patterned substrates are plasma treated such that subsequently deposited silicon oxide layers may deposit uniformly on walls of deep closed trenches. The technique is particularly useful for through-substrate vias (TSVs) which require especially deep trenches. The trenches may be closed at the bottom and deep to enable through-substrate vias (TSVs) by later removing a portion of the backside substrate (near to the closed end of the trench). The conformal silicon oxide layer thickness on the sidewalls near the bottom of a trench is greater than or about 70% of the conformal silicon oxide layer thickness near the top of the trench in embodiments of the invention. The improved uniformity of the silicon oxide layer enables a subsequently deposited conducting plug to be thicker and offer less electrical resistance. | 2013-09-26 |
20130252441 | ROTATABLE CONNECTOR DEVICE - A rotatable connector device includes a rotator and a stator which are fit to each other so as to be rotatable with respect to each other. The rotator and the stator form an accommodation space. In a bottom part of the accommodation space, a retainer for axially supporting a plurality of rotatable rollers and a flat cable are accommodated. A guide unit for allowing a reversed part to be pressed thereon is fit and fixed to the retainer. In a vertical cross-section vertical to a planar surface of the retainer, a guide surface of the guide unit which faces the reversed part has a vertical cross-sectional shape which does not contact a prescribed range of the flat cable in a width direction of the flat cable. | 2013-09-26 |
20130252442 | ROTATABLE CONNECTOR DEVICE - A fixed-side ring plate rotation regulation section is provided at an outer circumferential edge of a fixed-side ring plate, and an outer cylinder rotation regulation section is provided at an outer circumferential edge of an outer cylinder at a position corresponding to the fixed-side ring plate rotation regulation section. The fixed-side ring plate and the outer cylinder formed of different members from each other are fit to each other such that the fixed-side ring plate rotation regulation section and the outer cylinder rotation regulation section are in contact with each other so as not to rotate about a rotation axis thereof. | 2013-09-26 |
20130252443 | STRUCTURE HAVING CIRCUIT BOARDS CONNECTED THEREIN AND METHOD FOR CONNECTING CIRCUIT BOARDS - An anisotropic conductive member is connected to a rigid circuit board having a first electrode and a flexible circuit board having a second electrode as a land. A plurality of conductive paths penetrate an insulating base material of the anisotropic conductive member. Each conductive path has a first protrusion and a second protrusion on respective first and second surfaces of the insulating base. The height of the second protrusion is equal to or less than double the thickness of the land. The first protrusion contacts a part of the first electrode. The second protrusion contacts part of the land. The base of the anisotropic conductive member is pressed such that the insulating material is not in direct contact with the flexible circuit board. When attaching the boards, a pressure of 300 MPa to 1,000 MPa is applied to the surfaces of the lands to reduce circuit board breakage. | 2013-09-26 |
20130252444 | MODULAR WIRING SYSTEM - A modular wiring system includes a junction box having a plurality of ports and a programmable wiring board carrying electrically conductive elements. A plurality of cable receiving connectors are each insertable into a corresponding one of the plurality of ports of the junction box and each provides electrical coupling between wires of a cable and the electrically conductive elements of the programmable wiring board. At least one electrical device receiving connector is coupled to the programmable wiring board. The at least one electrical device receiving connector releasably receives an electrical device and provides electrical coupling between the electrical device and the electrically conductive elements of the programmable wiring board. | 2013-09-26 |
20130252445 | Electrical Connectors Including Electromagnetic Interference (EMI) Absorbing Material - Examples of electrical connectors that incorporate electromagnetic interference (EMI) absorbing materials are described. In one example, an electrical connector includes a first pair of conductors, a second pair of conductors, and electromagnetic interference (EMI) absorbing material at least partially separating the first pair of conductors from the second pair of conductors. Each of the first and second pairs of conductors defines one of a differential pair or a signal conductor/ground pair. The EMI absorbing material may be configured to attenuate, primarily by absorption, an electromagnetic field generated due to transmission of electrical signals via one of the first pair and second pair of conductors to reduce the electromagnetic inference from the electromagnetic field on the other of the first pair and second pair of conductors. | 2013-09-26 |
20130252446 | ELECTRICAL CONNECTOR - An electrical plug-in connector with a casing, with a lever rotatably mounted on the casing. The lever has a guideway provided for guiding a guide element of a second casing, with the guide element being guided in the guideway upon rotation of the lever and the second casing being pulled from a pre-assembly position with regard to the casing into an end position. The casing has a flexible blocking element, an insertion space for introducing the guide element into the guideway being provided, the blocking element having an actuating surface, the actuating surface in a rest position of the blocking element projecting into the insertion space. The lever has a blocking surface, the blocking element having a second blocking surface, with, in a rest position of the lever and in a rest position of the blocking element, the second blocking surface of the blocking element being associated with the blocking surface of the lever and blocking a movement of the lever from the rest position into an end position. | 2013-09-26 |
20130252447 | PLUGGING DEVICE - A plugging device includes a supporting frame having two opposite side plates disposed between front and rear ends thereof, at least one slide member adapted to be connected to one side of an electronic component and connected slidably to an inner surface of one of the side plates, and an operating member having at least one lever that includes a fulcrum portion connected pivotally to one of the side plates. When the operating member is pivoted rearwardly about the fulcrum portion, the slide member together with the electronic component is driven to slide relative to the supporting frame in a forward direction for plugging a plug electrical connector of the electronic component into a socket electrical connector. | 2013-09-26 |
20130252448 | CHARGE CORD LOCK FOR ELECTRIC VEHICLE - A charge cord assembly for a vehicle having a charging receptacle for engaging the charge cord during battery recharging. The charge cord assembly includes an electric cord extending between a source of electric current and the charging receptacle; a cord end connector engaging the electric cord and having a electrical socket engaging the charging receptacle, a latch hook that selectively secures the cord end connector to the charging receptacle, a release handle, a release linkage assembly engaged between the release handle and the latch hook to release the latch hook from the charging receptacle when the release handle is actuated; and a lock assembly having a locked position that prevents the release linkage assembly from releasing the latch hook from the charging receptacle and an unlocked position that allows the release linkage assembly to release the latch hook from the charging receptacle when the release handle is actuated. | 2013-09-26 |
20130252449 | CARD EDGE CONNECTOR - A card edge connector ( | 2013-09-26 |
20130252450 | BURN-IN SOCKET - A burn-in socket for an IC package includes a base loaded with several terminals, a sliding plate, an actuator and a pair of locking elements. The sliding plate is assembled on the base and defines an upper surface. The actuator is mounted on the base and defines a receiving opening facing the upper surface. The locking elements is assembled on the actuator under a condition that the locking elements rotate inwards to press against the IC package and outwards to release the IC package when the actuator is push downwards in a vertical direction. Each locking element includes a rotating element and a pressing element. The rotating elements rotate in relative to the actuator and the pressing element rotates in relative to the rotating element. The pressing element defines a sliding slot and the rotating element defines a sliding post slidably receiving in the sliding slot. | 2013-09-26 |
20130252451 | LATCH ASSEMBLY FOR A PLUGGABLE ELECTRONIC MODULE - A latch assembly is provided for latching a pluggable electronic module to a receptacle assembly. The latch assembly includes a yoke assembly having an actuation end that is movable between a latched position and an unlatched position. A lever is operatively connected to the yoke assembly to move the actuation end of the yoke assembly between the latched and unlatched positions. A latch element is operatively connected to the actuation end of the yoke assembly. The latch element is movable along a latch axis between an extended position and a retracted position as the actuation end is moved between the latched and unlatched positions, respectively. The actuation end of the yoke assembly is configured to float along the latch axis relative to the latch element. | 2013-09-26 |
20130252452 | CONNECTOR ASSEMBLY - A connector assembly includes a connector affixed to a printed circuit board and a covering with an integrated holding frame slidably mounted onto the connector. The covering has an opening in which the holding frame is integrated as an inner frame with a compensation gap to the surface of the opening. The covering includes a flexible connection between the surface of the opening and the holding frame to align the holding frame within the opening during insertion of the covering onto the connector. | 2013-09-26 |
20130252453 | Multi-Position Quick Release Plug Cassette Assmbly - A cassette assembly which holds at least two electrical plugs which typically are connected to digital signal carrying cables. In one example, six of these plugs are positioned within a cassette, and are arranged in two rows of three plugs each for ease in connecting the plugs simultaneously to similarly arranged switch port jacks. A lever pivotally connected to the housing, when rotated, causes the release latch of the plugs held within the cassette to move from a locked to an unlocked position to simultaneously remove all of the plugs from the jacks to which they are connected. | 2013-09-26 |
20130252454 | Coupling Socket For Connecting Medical Instruments - A medical-engineering coupling mechanism for connecting two medical instruments having a coupling plug and a coupling socket for inserting the coupling plug, so that the coupling socket and the coupling plug can be secured to one another by at least one spring-loaded notching connection. To produce a medical-engineering coupling mechanism that is easy to manipulate and ensures a secure notching connection of the components that are to be connected to one another, it is proposed with the invention that the notching connection consists of at least two notching hooks that are positioned on one of the components and are in active engagement with at least one spring element configured as a spring washer, and at least one notching recess positioned on the other component for insertion of the at least two notching hooks. | 2013-09-26 |
20130252455 | CONNECTOR ASSEMBLY - A connector assembly comprising a connector housing, a secondary locking member and a safety spring bar, whereby the secondary locking member and the safety spring bar are assigned to the connector housing. The secondary locking member is movable between a first and a second position, whereby the safety spring bar is adapted to lock the secondary locking member in its second position. The secondary locking member comprises a deflection surface adapted to engage the safety spring bar when the secondary locking member is moved in an insertion direction. Thereby, upon movement of the secondary locking member, the safety spring bar is deflected essentially in the insertion direction, urging the secondary locking member towards its first position. When the secondary locking member is placed in the second position, the safety spring bar is adapted to snap into a safety position, to lock the secondary locking member in its second position | 2013-09-26 |
20130252456 | Securing a Field Replaceable Unit - An assembly may have first and second components. The first component may include a first electrical connector and a guide member. The second component may include a second electrical connector to couple with the first electrical connector, and a receptacle to receive the guide member in a mated position. An adhesive may be provided between the guide member and the receptacle to form a bond between the guide member and the receptacle. The bond may be reversed when the adhesive is heated above a threshold temperature. A heating element to heat the adhesive may be provided. | 2013-09-26 |
20130252457 | ELECTRICAL CONNECTOR HAVING POSITION FIXER FOR CONDUCTIVE TERMINALS - An electrical connector ( | 2013-09-26 |
20130252458 | ELECTRICAL COMPONENT - An electrical component ( | 2013-09-26 |
20130252459 | CONNECTION STRUCTURE OF ELECTRIC WIRE AND TERMINAL, AND MANUFACTURING METHOD THEREOF - A connection structure of an electric wire and a terminal includes the electric wire, the terminal, and a seal part. The electric wire has an insulating coated part in which a conductor part is covered with an insulating material, and a conductor exposed part in which the insulating material of an end of the electric wire is removed. The terminal includes a first crimp part crimped to the insulating coated part, and a second crimp part crimped to the conductor exposed part. The seal part is made of thermoplastic elastomer and covers a surface including the first crimp part and the insulating coated part of a side extending from said first crimp part toward a direction opposite to the end of the electric wire and a surface of the second crimp part in an extension direction of the electric wire. | 2013-09-26 |
20130252460 | RETAINING CLIP FOR ELECTRICAL CONNECTORS - A retaining clip that provides a method for securing electrical connections between a male and female electrical connectors is disclosed. Current locking mechanisms are on both the electrical plug and the connector. These locking mechanisms often break when disconnecting the plug. Some embodiments of the present invention eliminate the need for the locking mechanisms. Furthermore, in cases where the mechanisms have been broken, some embodiments provide a method for reusing the electrical plug and/or the connector. | 2013-09-26 |
20130252461 | Plug and Socket Connector Part For a Medical Device or Instrument - A plug and socket connector system in accordance with the invention for use, in particular, in medical technology comprises a plug | 2013-09-26 |
20130252462 | GROUND MAINTAINING AUTO SEIZING COAXIAL CABLE CONNECTOR - A coaxial cable female connector for inclusion in a port of a device or outer shell of a cable connector, includes a centrally located female pin within a pin carrier, the pin has an upper portion with two opposing resilient arms configured for receiving the central pin of a mating male connector. A non-electrically conductive cap is partially covered with an electrically conductive coating, and configured for seating upon said pin carrier, and for maintaining a ground or electrical connection between a shell of a male connector mated to a shell of the female connector, even if the male connector mating to the female connector loosens. | 2013-09-26 |
20130252463 | FRICTION WELD COAXIAL CONNECTOR INTERCONNECTION SUPPORT - A coaxial connector for interconnection with a coaxial cable with a solid outer conductor by friction welding is provided with a monolithic connector body with a bore dimensioned for an interference fit with an outer diameter of the outer conductor. A friction groove may be formed around the leading end of the outer conductor by application of a friction weld support against the inner diameter and leading end of the outer conductor. The friction groove may include a material chamber formed between a radial friction protrusion of the bore and a bottom of the friction groove. The friction weld support may be provided with ceramic surfaces contacting the outer conductor, a stop shoulder dimensioned to abut a cable end of the bore and/or an elastic insert seated within an inner conductor bore. | 2013-09-26 |
20130252464 | RF MODULE - An RF module includes a contact insert having a separable shielding body retaining an RF contact. The RF contact includes an RF mating tip connected to a signal tail. The mating tip and the signal tail extend out of shielding body. The shielding body includes first and second body members. The RF contact is positioned within the first body member and the second body member is removably secured to the second body member so that at least a portion of the RF contact is contained between the first and second body members. The RF module may also include a grounding block. The contact insert may be removably secured within the grounding block. | 2013-09-26 |
20130252465 | PCB-MOUNT ELECTRICAL CONNECTOR WITH SHIELDING FOR INHIBITING CROSSTALK - A board-mount electrical connector includes an electrically conductive rear shell interposed between a contact-retaining front body and an insulator member that holds a plurality of board-mount contacts. The rear shell includes at least one electrically conductive shielding divider that extends through the insulator member and is positioned between two or more of the board-mount contacts. Also disclosed is a rear shell elbow for an electrical connector that is assembled from a pair of slidably interlocking members that form an X-shaped divider within the rear shell when assembled. | 2013-09-26 |
20130252466 | ELECTRICAL CONNECTOR WITH SPECIALLY DESIGNED METAL CONTACT TERMINALS TO AVOID SOLDER-OFF - An electrical connector includes an electrically insulative holder member, a signal module formed of a circuit board with longitudinal terminal holes, circuit lines, electrical contacts and via-holes, metal contact terminals and metal mounting terminals, and a metal shield. The metal contact terminals have rear soldering end portions thereof soldered to respective circuit lines, an extension arm forwardly extended from the rear soldering end portion along one longitudinal terminal hole, a turn portion extended from the extension arm and curved into the associating longitudinal terminal hole to enhance vertical deformation stroke of the respective metal contact terminal, a front contact portion suspending below the associating longitudinal terminal hole, and an oblique spring arm connected between the turn portion and the front contact portion to flexibly support the front contact portion. | 2013-09-26 |
20130252467 | ELECTRICAL CONNECTOR - An electrical connector includes an electrically insulative holder member, a signal module formed of a circuit board with longitudinal terminal holes, circuit lines, electrical contacts and via-holes, metal contact terminals and metal mounting terminals, and a metal shield. The metal contact terminals have rear soldering end portions thereof respectively soldered to respective circuit lines, front contact portions thereof positioned in front ends of the longitudinal terminal holes of the circuit board and middle suspension arms thereof connected between the rear soldering end portions and the front contact portions and suspending below the longitudinal terminal holes. The electrical contacts of the circuit board are positioned in respective bottom contact holes of the tongue plate. The circuit lines electrically connect the electrical contacts and the metal contact terminals to the via-holes. The surface area of each circuit line may be modified to adjust impedance, reducing interference. | 2013-09-26 |
20130252468 | ELECTRICAL CONNECTOR - An electrical connector for mounting onto a printed circuit board includes an insulating housing and a plurality of power contacts. The insulating housing has a number of dividing walls and a number of receiving passageways defined between the dividing walls. The plurality of power contacts is received in the corresponding receiving passageways, respectively. One of the dividing walls defines a heat dissipation cutout thereon for heat dissipation purpose. | 2013-09-26 |
20130252469 | CONNECTION STRUCTURE AND CONNECTION UNIT OF ELETRONIC COMPONENT - A connection structure includes: a box-shaped housing having a bottom wall and side walls which extend from the bottom wall; an electronic component which is accommodated inside the housing; and a pair of terminals, being the same in shape, which are inserted into the housing vertically along planes of two side walls and placed on a placement surface of the bottom wall to be fixed inside the housing. Each terminal includes: a component-connection portion which is formed at a first end of the terminal to be electrically connected to the electronic component; and a press-contact terminal portion which is formed at a second end opposite to the first end and which has a notch to which an electric wire is to be press-fitted and electrically connected, wherein a surface in which the notch is formed extends in parallel to the placement surface of the bottom wall of the housing. | 2013-09-26 |
20130252470 | CARD HOLDER - A card holder adapted for converting a micro SIM card into a standard SIM card in size and shape includes an insulating housing of a flat board shape which is in accordance with the standard SIM card in size and shape, and defines a card groove in accordance with the micro SIM card in size and shape and in accordance with the standard SIM card in contact position for receiving the micro SIM card in place. At least one groove sidewall of the card groove defines an open slot spaced from the card groove for accordingly forming at least one elastic arm between the open slot and the card groove, wherein the elastic arm further projects into the card groove for resisting against the micro SIM card. A metal part is molded in the insulating housing and exposed in the card groove for supporting the micro SIM card thereon. | 2013-09-26 |
20130252471 | CABLE ASSEMBLY - A cable assembly comprises an insulative housing, a plurality of terminals disposed in the insulative housing; printed circuit board assembled to a rear end of the insulative housing and electrically connected to the plurality of terminals; a wire management assembled to a rear end of the printed circuit board and defining a curved top surface. The wire management defines a plurality of spaced slots formed on the curved top surface, arranged along a transversal direction and extending along a longitudinal direction. And, a cable comprises a plurality of conductive wires respectively passing through the plurality of slots and electrically connected to the rear end of the printed circuit board. The lengths of the plurality of slots are gradually decreased from higher section of the curved top surface to lower section of the curved top surface. | 2013-09-26 |
20130252472 | RELAY CONNECTOR, MODULE, MODULE DEVICE, AND LUMINAIRE - According to one embodiment, a relay connector connects two input connectors respectively mounted on mounting surfaces of two substrates, ends of which are arranged to be opposed to each other. The relay connector includes a relay connector main body and relay terminals. The relay connector main body includes a substrate regulating section interposed between the ends of the two substrates and set in contact with the ends of the two substrates to form a space between the ends of the two substrates. The relay terminals project from both ends of the relay connector main body to be connected to the input connectors. | 2013-09-26 |
20130252473 | GANGABLE POWER SUPPLY CHANNELS - An interface module includes a first side having a plurality of input connectors of a same cross-sectional area corresponding to a same amperage rating, a second side having a plurality of output connectors of different cross-sectional areas from each other corresponding to different amperage ratings from each other, and wiring in the interface module configured to connect a first number of input connectors to a first one of the output connectors having a first amperage rating, and configured to connect a second number of input connectors to a second one of the output connectors having a second amperage rating different from the first amperage rating. | 2013-09-26 |
20130252474 | ELECTRICAL CONNECTION SYSTEM - An electrical connection assembly includes a first connector which includes a first electrical contact surrounded by a first connector wall defining a first connector cavity. The first connector wall includes a plurality of ribs extending into the first connector cavity. A second connector is matable with the first connector along a mating axis and includes a second electrical contact in electrical communication with the first electrical contact when the first connector is mated with the second connector. The second connector includes a second connector body surrounding the second electrical contact. | 2013-09-26 |
20130252475 | CONNECTING STRUCTURE FOR ELECTRONIC DEVICES - In a connecting structure for electronic devices, a housing is configured to be inserted into a cover, and a terminal is accommodated in the housing to hold an electronic device inserted therein. A terminal accommodating chamber in the housing accommodates the terminal. An opening part is formed in a forward end surface of the housing in a first direction in which the housing is inserted into the cover, and communicates with the terminal accommodating chamber so that the electronic device is inserted therethrough. A positioning part is provided in the terminal accommodating chamber, and is configured to come in contact with a forward end of the electronic device in a insertion direction of the electronic device, so as to position the electronic device in the second direction. | 2013-09-26 |
20130252476 | CONNECTING STRUCTURE FOR ELECTRONIC DEVICE - A connecting structure includes a housing which is inserted into a cover, and a terminal which is accommodated in the housing and holds an electronic device. The housing allows the electronic device to be inserted from an outside of the housing into the housing in a state where the terminal is accommodated in the housing. The cover comes in contact with the electronic device in a state where a part of the electronic device is inserted to the terminal. The cover allows the housing to be inserted into the cover in a state where whole part of the electronic device is inserted into the housing to be held at a normal position by the terminal. The cover has an abutting face preventing the electronic device from slipping out from the housing in a state where the housing is inserted into the cover. | 2013-09-26 |
20130252477 | ELECTRICAL MODULE HOUSING - An assembly is configured to retain a plurality of electrical modules and mate with a shroud having a plurality of connecting interfaces configured to mate with the plurality of electrical modules. The assembly includes a frame having at least one shroud-securing bracket and at least one bay configured to retain at least one of the plurality of electrical modules, and at least one keying insert retained within at least one insert passage of the at least one shroud-securing bracket. The at least one keying insert includes at least one adjustable keying feature that is configured to be adjusted to different positions in order to accommodate a reciprocal alignment post of the shroud. | 2013-09-26 |
20130252478 | Integrated AISG Connector Assembly - A connector assembly is provided. In one example, the connector assembly includes a connector plate, a connector bracket, and a wiring set. The connector plate has a male connector shell and a female connector shell. The connector bracket has a male connector core and a female connector core. The connector bracket is dimensioned to be mounted on the connector plate with the male connector core disposed within the male connector shell and the female connector core disposed within the female connector shell. The wiring set is coupled to the male connector core and to the female connector core, and is further provides a pigtail connection. | 2013-09-26 |