39th week of 2015 patent applcation highlights part 54 |
Patent application number | Title | Published |
20150270163 | METHOD OF ETCHING A POROUS DIELECTRIC MATERIAL - A method for producing interconnection lines including etching a layer of porous dielectric material forming a trench and filling the trench is provided. The etching is carried out in a plasma so as to grow, all along the etching, a protective layer on flanks of the layer of porous dielectric material. The plasma is formed from a gas formed from a first component and a second component, or a gas formed from a first component, a second component and a third component. The first component is a hydrocarbon of the CXHY type, where X is the proportion of carbon in the gas and Y the proportion of hydrogen in the gas; the second component is taken from nitrogen or dioxygen or a mixture of nitrogen and dioxygen; the third component is taken from argon or helium; and the protective layer is based on hydrocarbon. | 2015-09-24 |
20150270164 | CONTACT WINDOW STRUCTURE, PIXEL STRUCTURE AND METHOD FOR MANUFACTURING THEREOF - The present disclosure provides a contact window structure. In the contact window structure, a first insulating layer, having a first opening, is positioned on a first metal layer, wherein the first opening exposes a part of the first metal layer. A second metal layer covers the first opening and contacts with the first metal layer via the first opening. A second insulating layer, having a second opening, is positioned on the first insulating layer, wherein the second opening exposes a part of the second layer and the first insulating layer. The projection area of the second opening on the first metal layer covers the projection area of the first opening on the first metal layer. A pixel structure containing the contact window structure and a manufacturing method thereof are also provided herein. | 2015-09-24 |
20150270165 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes conductive patterns and interlayer insulating patterns having a stair structure and being alternately stacked, pad patterns connected to end portions of upper surfaces of the conductive patterns exposed through the stair structure, and a channel film penetrating the conductive patterns and the interlayer insulating patterns. | 2015-09-24 |
20150270166 | Method of Fabricating Semiconductor Device Including A Substrate Having Copper Interconnects - A method of fabricating a semiconductor device including a substrate having a copper interconnect exposed on a surface of an insulation film, wherein a layer of an anti-corrosion agent composed of organic material is formed on the surface of the copper interconnect. The method includes removing the layer of the anti-corrosion agent by heating the substrate; and forming a thin layer including manganese oxide on the surface of the copper interconnect by supplying a gas containing an organic compound of manganese to the substrate. | 2015-09-24 |
20150270167 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device and a method of fabricating the same. The semiconductor device includes a semiconductor substrate having a P-type region, on at least one main surface of which integrated circuits are formed; one or more via electrodes inserted into the P-type region of the semiconductor substrate; a dielectric layer formed between the semiconductor substrate and the via electrodes; an N-type region, which is formed in the semiconductor substrate to contact a portion of the dielectric layer and to expose other portion of the dielectric layer; and a power circuit, which is electrically connected to the N-type region and apply a bias voltage or a ground voltage thereto, such that electric signals flowing in the via electrodes form an inversion layer on a surface of the semiconductor substrate facing the exposed portion of the dielectric layer. | 2015-09-24 |
20150270168 | SEMICONDUCTOR CONTACT WITH DIFFUSION-CONTROLLED IN SITU INSULATOR FORMATION - A contact is created by forming a layer of dielectric material on a silicon-containing region of a semiconductor substrate. An opening is created through the layer of dielectric material, the opening having a bottom and exposing the silicon-containing region. An oxygen-containing layer is formed on type of the semiconductor substrate. A metal stack is formed within the opening and includes a first metal film with a first type of metal and a second type of metal and a second metal film. The metal stack, the oxygen-containing layer and the silicon-containing region of the semiconductor substrate are annealed to form a metallic oxide layer and a metal silicide layer. A first liner is formed within the opening. A fill metal is deposited in the opening. | 2015-09-24 |
20150270169 | METHODS OF CONNECTING A FIRST ELECTRONIC PACKAGE TO A SECOND ELECTRONIC PACKAGE - A method of fabricating an electronic package. The method includes filling a mold with an electric conductor to form a number of electrical interconnects within the mold. The mold includes openings that are filled with several electric conductors to form a number of electrical interconnects. The method of fabricating an electronic package further includes attaching the mold to a substrate such that the electrical interconnects engage electrical contacts on the substrate. The method of fabricating an electronic package may further include forming conductive pads on the electrical insulator that engage the electrical interconnects and attaching a die to the substrate such that the die is electrically connected to at least some of the electrical interconnects. | 2015-09-24 |
20150270170 | Method of Semiconductor Integrated Circuit Fabrication - A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate and depositing a conductive layer on the substrate. A patterned hard mask and a catalyst layer are formed on the conductive layer. The method further includes growing a plurality of carbon nanotubes (CNTs) from the catalyst layer and etching the conductive layer by using the CNTs and the patterned hard mask as an etching mask to form metal features. | 2015-09-24 |
20150270171 | DIELECTRIC LINER FOR A SELF-ALIGNED CONTACT VIA STRUCTURE - At least one dielectric material layer having a top surface above the topmost surface of the gate electrode of a field effect transistor is formed. Active region contact via structures are formed through the at least one dielectric material layer to the source region and the drain region. A self-aligned gate contact cavity is formed over the gate electrode such that at least one sidewall of the gate contact cavity is a sidewall of the active region contact via structures. A dielectric spacer is formed at the periphery of the gate contact cavity by deposition of a dielectric liner and an anisotropic etch. A conductive material is deposited in the gate contact cavity and planarized to form a self-aligned gate contact via structure that is electrically isolated from the active region contact via structures by the dielectric spacer. | 2015-09-24 |
20150270172 | Novel 3D Integration Method using SOI Substrates and Structures Produced Thereby - A process and resultant article of manufacture made by such process comprises forming through vias needed to connect a bottom device layer in a bottom silicon wafer to the one in the top device layer in a top silicon wafer comprising a silicon-on-insulator (SOI) wafer. Through vias are disposed in such a way that they extend from the middle of the line (MOL) interconnect of the top wafer to the buried oxide (BOX) layer of the SOI wafer with appropriate insulation provided to isolate them from the SOI device layer. | 2015-09-24 |
20150270173 | ELECTRONIC DIE SINGULATION METHOD - In one embodiment, die are singulated from a wafer having a back layer by placing the wafer onto a carrier substrate with the back layer adjacent the carrier substrate, forming singulation lines through the wafer to expose the back layer within the singulation lines, and applying a pressure substantially uniformly along the second major surface to batch separate the layer of material in the singulation lines. In one embodiment, a fluid filled vessel can be used to apply the pressure. | 2015-09-24 |
20150270174 | INTEGRATED CIRCUIT AND METHOD OF FORMING THE INTEGRATED CIRCUIT WITH IMPROVED LOGIC TRANSISTOR PERFORMANCE AND SRAM TRANSISTOR YIELD - In an integrated circuit that includes an NMOS logic transistor, an NMOS SRAM transistor, and a resistor, the gate of the SRAM transistor is doped at the same time that the resistor is doped, thereby allowing the gate of the logic transistor to be separately doped without requiring any additional masking steps. | 2015-09-24 |
20150270175 | PARTIALLY CRYSTALLIZED FIN HARD MASK FOR FIN FIELD-EFFECT-TRANSISTOR (FINFET) DEVICE - Provided herein are approaches for forming a fin field-effect-transistor (FinFET) device using a partially crystallized fin hard mask. Specifically, a hard mask is patterned over a substrate, and the FinFET device is annealed to form a set of crystallized hard mask elements adjacent a set of non-crystallized hard mask elements. A masking structure is provided over a first section of the patterned hard mask to prevent the set of non-crystallized hard mask elements from being crystallized during the anneal. During a subsequent fin cut process, the non-crystallized mask elements are removed, while crystallized mask elements remain. A set of fins is then formed in the FinFET device according to the location(s) of the crystallized mask elements. | 2015-09-24 |
20150270176 | METHODS OF FORMING REDUCED RESISTANCE LOCAL INTERCONNECT STRUCTURES AND THE RESULTING DEVICES - A method includes forming a layer of insulating material above first and second transistors, within the layer of insulating material, forming a set of initial device-level contacts for each of the first and second transistors, wherein each set of initial device-level contacts comprises a plurality of source/drain contacts and a gate contact, forming an initial local interconnect structure that is conductively coupled to one of the initial device-level contacts in each of the first and second transistors, and removing the initial local interconnect structure and portions, but not all, of the initial device-level contacts for each the first and second transistors. The method also includes forming a copper local interconnect structure and copper caps above the recessed device-level contacts. | 2015-09-24 |
20150270177 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - Provided is a method for fabricating a semiconductor device. The method includes forming an interlayer insulating layer on a substrate, the interlayer insulating layer including a first trench; forming a high-k dielectric layer in the first trench; successively forming a diffusion layer and a blocking layer on the high-k dielectric layer; subsequently performing annealing; after the annealing, successively removing the blocking layer and the diffusion layer; forming a first barrier layer on the high-k dielectric layer; successively forming a work function adjustment layer and a gate conductor on the first barrier layer; and forming a capping layer on the gate conductor. | 2015-09-24 |
20150270178 | DIFFUSION-CONTROLLED SEMICONDUCTOR CONTACT CREATION - A contact can be formed by forming a layer of dielectric material on a silicon-containing region of a semiconductor substrate. An opening is created through the layer of dielectric material that exposes the silicon-containing region. A metal stack is formed within the opening. The metal stack includes at least a first metal film having a first and second type of metal and a second metal film. The metal stack and the silicon-containing region of the semiconductor substrate are annealed to form a silicide that includes the first and second types of metal and that is in contact with the semiconductor substrate. A first liner is formed within the opening and a fill metal is deposited in the opening. | 2015-09-24 |
20150270179 | DIFFUSION-CONTROLLED OXYGEN DEPLETION OF SEMICONDUCTOR CONTACT INTERFACE - A device is created by forming a layer of dielectric material on a silicon-containing region of a semiconductor substrate. An opening is created through the layer of dielectric material, the opening having a bottom and exposing the silicon-containing region. A metal stack is formed within the opening. The metal stack includes at least a first metal film on the silicon-containing region and a second gettering metal film on the first metal film. The metal stack is annealed to cause oxygen to migrate from the substrate to the gettering metal film. A first liner is formed within the opening. A fill metal is deposited in the opening. | 2015-09-24 |
20150270180 | METHOD AND STRUCTURE OF THREE DIMENSIONAL CMOS TRANSISTORS WITH HYBRID CRYSTAL ORIENTATIONS - A method for fabricating a three-dimensional integrated circuit device includes providing a first substrate having a first crystal orientation, forming at least one or more PMOS devices overlying the first substrate, and forming a first dielectric layer overlying the one or more PMOS devices. The method also includes providing a second substrate having a second crystal orientation, forming at least one or more NMOS devices overlying the second substrate, and forming a second dielectric layer overlying the one or more NMOS devices. The method further includes coupling the first dielectric layer to the second dielectric layer to form a hybrid structure including the first substrate overlying the second substrate. | 2015-09-24 |
20150270181 | OPPORTUNISTIC PLACEMENT OF IC TEST STRUCUTRES AND/OR E-BEAM TARGET PADS IN AREAS OTHERWISE USED FOR FILLER CELLS, TAP CELLS, DECAP CELLS, SCRIBE LINES, AND/OR DUMMY FILL, AS WELL AS PRODUCT IC CHIPS CONTAINING SAME - Product ICs/wafers include additional diagnostic, test, or monitoring structures opportunistically placed in filler cell positions, within tap cells, within decap cells, within scribe line areas, and/or within dummy fill regions. Improved fabrication processes utilize data from such structure(s) in wafer disposition decisions, rework decisions, process control, yield learning, or fault diagnosis. | 2015-09-24 |
20150270182 | SEMICONDUCTOR INSPECTING APPARATUS AND METHOD OF INSPECTING AND MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME - A method of manufacturing a semiconductor device includes: preparing a semiconductor device comprising a first substrate, a second substrate disposed on the first substrate, inner terminals disposed between the first and second substrates, and a filling material disposed between the first and second substrates and between the inner terminals; loading the semiconductor device on a stage; irradiating an electromagnetic wave to the filling material in a direction parallel to a top surface of the first substrate by an electromagnetic wave generating unit; and scanning the filling material as the electromagnetic wave generating unit is moved in relation to the stage in a direction along a first side of the semiconductor device while maintaining the irradiating direction of the electromagnetic wave. | 2015-09-24 |
20150270183 | SUBSTRATE PROCESSING METHOD, PROGRAM, CONTROL DEVICE, SUBSTRATE PROCESSING APPARATUS, AND SUBSTRATE PROCESSING SYSTEM - Disclosed is a substrate processing method. The substrate processing method includes: a first acquisition step of acquiring a first processing condition in a first processing performed using a first number of monitor substrates and a first processing result related to the monitor substrates; a second acquisition step of acquiring a second processing condition in a second processing performed using a second number of monitor substrates and a second processing result related to the monitor substrates; a first calculation step of calculating a processing condition difference between the first processing condition and the second processing condition; and a second calculation step of calculating a processing result of substrates at slot positions where no monitor substrate is placed in the first processing, based on the first processing result, the second processing result, the processing condition difference, and a process model representing a relationship between a processing condition and a processing result. | 2015-09-24 |
20150270184 | Location-Shifted Probe Pads For Pre-Bond Testing - An arrangement for performing pre-bond testing of a wafer of semiconductor devices utilizes probe pads that are location-shifted into wafer regions adjacent to the devices such that when the pre-bond testing is completed and the wafer is separated into individual elements, the electrical connection between the pre-bond probe pad and tested device is broken. The adjacent wafer regions may be “vacant” areas or another device region. When separated into individual components, a given pre-bond probe pad and its associated device will be physically separated and electrically isolated from one another. Thus, a large probe pad is electrically connected to an associated device only while the wafer is intact, facilitating probe placement during pre-bond testing. Once the devices are separated, the probe pad is disconnected from its associated active element portion, eliminating the capacitance associated with maintaining an electrical connection between a co-located probe and active region. | 2015-09-24 |
20150270185 | TSV TESTING METHOD AND APPARATUS - An integrated circuit die includes a substrate of semiconductor material having a top surface, a bottom surface, and an opening through the substrate between the top surface and the bottom surface. A through silicon via (TSV) has a conductive body in the opening, has a top contact point coupled to the body at the top surface, and has a bottom contact point coupled to the body at the bottom surface. A scan cell has a serial input, a serial output, control inputs, a voltage reference input, a response input coupled to one of the contact points, and a stimulus output coupled to the other one of the contact points. | 2015-09-24 |
20150270186 | SEMICONDUCTOR DEVICE - An electrode includes an extending portion extending such that both ends thereof get into a first recessed portion and a second recessed portion provided in a first inner wall and a second inner wall, respectively, facing each other in a lateral direction of a case. The extent to which both the ends of the extending portion get into is set such that positions of both the ends thereof in a case where both the ends are narrowed toward a midpoint therebetween to reduce a length of the extending portion to 70% of the length of the extending portion exist between positions of the first and second inner walls in a case where the first and second inner walls are each narrowed toward a midpoint therebetween by 10% of the distance between the first and second inner walls. | 2015-09-24 |
20150270187 | FLEXIBLE, STRETCHABLE ELECTRONIC DEVICES - Fabrication methods are disclosed that facilitate the production of electronic structures that are both flexible and stretchable to conform to non-planar (e.g. curved) surfaces without suffering functional damage due to excessive strain. Electronic structures including CMOS devices are provided that can be stretched or squeezed within acceptable limits without failing or breaking. The methods disclosed herein further facilitate the production of flexible, stretchable electronic structures having multiple levels of intra-chip connectors. Such connectors are formed through deposition and photolithographic patterning (back end of the line processing) and can be released following transfer of the electronic structures to flexible substrates. | 2015-09-24 |
20150270188 | Under-Fill Material and Method for Producing Semiconductor Device - The present invention provides an under-fill material with which a semiconductor device having a high connection reliability can be provided while securing a usable material by reducing a difference in thermal-responsive behavior between a semiconductor element and an adherend, and a method for producing a semiconductor device using the under-fill material. In the under-fill material of the present invention, a storage elastic modulus E′ [MPa] and a thermal expansion coefficient α [ppm/K] after carrying out a heat-curing treatment at 175° C. for an hour satisfy the following formula (1) at 25° C.: | 2015-09-24 |
20150270189 | Low-K Dielectric Layer and Porogen - A system and method for a low-k dielectric layer are provided. A preferred embodiment comprises forming a matrix and forming a porogen within the matrix. The porogen comprises an organic ring structure with fewer than fifteen carbons and a large percentage of single bonds. Additionally, the porogen may have a viscosity greater than 1.3 and a Reynolds numbers less than 0.5. | 2015-09-24 |
20150270190 | SEMICONDUCTOR PACKAGE - A semiconductor package is provided. The semiconductor package includes a substrate, a semiconductor chip mounted on an upper surface of the substrate, an encapsulant formed to cover sides of the semiconductor chip on the upper surface of the substrate, a heat transfer layer formed on the upper surface of the semiconductor chip and an upper surface of the encapsulant, and a heat slug including a plurality of metal plates disposed to be spaced apart from each other on an upper surface of the heat transfer layer. | 2015-09-24 |
20150270191 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device provided herewith includes a semiconductor substrate; a brazing material bonded to the semiconductor substrate; a heat sink connected to the semiconductor substrate via the brazing material and a resin. The heat sink includes a protruding portion formed outside of a range in which the heatsink is connected to the semiconductor substrate via the brazing material. The protruding portion is making contact with the brazing material. The resin seals the semiconductor substrate, the brazing material and the protruding portion. | 2015-09-24 |
20150270192 | INTEGRATED CIRCUIT CHIP ASSEMBLED ON AN INTERPOSER - A device includes a chip assembled on an interposer. An electrically-insulating layer coats an upper surface of the interposer around the chip. First metal lines run on the upper surface of the interposer and are arranged between conductive elements of connection to the chip. An end of each first metal line is arranged to extend beyond a projection of the chip on the interposer. A thermally-conductive via connects the end of the first metal line to a heat sink supported at an upper surface of the device. | 2015-09-24 |
20150270193 | METHOD AND STRUCTURES FOR VIA SUBSTRATE REPAIR AND ASSEMBLY - A component can include a substrate having an opening extending between first and second surfaces thereof, and an electrically conductive via having first and second portions. The first portion can include a first layer structure extending within the opening and at least partially along an inner wall of the opening, and a first principal conductor extending within the opening and at least partially overlying the first layer structure. The first portion can be exposed at the first surface and can have a lower surface located between the first and second surfaces. The second portion can include a second layer structure extending within the opening and at least partially along the lower surface of the first portion, and a second principal conductor extending within the opening and at least partially overlying the second layer structure. The second portion can be exposed at the second surface. | 2015-09-24 |
20150270194 | ELECTRONIC COMPONENT AND LEADFRAME - In an embodiment an electronic component includes a semiconductor die having a first surface, the first surface including a first current electrode and a control electrode. The electronic component further includes a die pad having a first surface, a plurality of leads and a gull-wing shaped conductive element coupled to a first lead of the plurality of leads. The first current electrode is mounted on the die pad and the gull-wing shaped conductive element is coupled between the control electrode and the first lead. | 2015-09-24 |
20150270195 | LEAD FRAME WITH MOLD LOCK STRUCTURE - A lead frame for a semiconductor device includes a die paddle and leads situated on a perimeter of the lead frame. The die paddle has a metal frame and a number of substantially linear metal connecting bars within the frame. The connecting bars interconnect different locations of the frame to form a multiple triangles, where a triangular-shaped cavity is formed within each triangle. An overall area of the cavities is greater than an overall area of the connecting bars. | 2015-09-24 |
20150270196 | SEMICONDUCTOR DEVICES AND METHODS OF MAKING THE SAME - In one embodiment, methods for making semiconductor devices are disclosed. | 2015-09-24 |
20150270197 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a semiconductor device using a lead frame, in which an outer lead (5) is electrically connected to an inner lead suspension lead (3) via an inner lead, and hence a plated film is also formed on an outer lead cut surface (11) so that a solder layer is easily formed on all of surfaces of the outer lead extending from an encapsulating resin (10). Further, the inner lead suspension lead (3) includes a first narrowed portion (12 | 2015-09-24 |
20150270198 | INTEGRATED CIRCUIT ARRANGEMENT - An integrated circuit arrangement comprising a substrate and a flange disposed on top of the substrate. The flange comprises a cantilever portion configured to project over the substrate. A die disposed on top of the flange. A first output terminal disposed on the substrate. A first lead configured to provide for an electrical connection between the die and the first output terminal. A first electrically conducting member configured to provide at least part of a current return path between the substrate and the die and arranged to bridge a gap between the cantilever portion and the substrate. The first electrically conducting member is disposed between the die and the first output terminal and is configured to enable electrical current to flow from the substrate to the cantilever portion of the flange. | 2015-09-24 |
20150270199 | Semiconductor Module - A semiconductor module is provided for shortening a manufacturing tact time, reducing manufacturing costs and for ensuring reliability of a bonding portion. The semiconductor module includes a substrate formed of a metal, an insulating layer formed on the substrate, a plurality of wiring patterns formed on the insulating layer, a bare-chip transistor mounted on one wiring pattern via a solder, and copper connectors that connect electrodes formed on the bear-chip transistor and other wiring patterns via a solder. The copper connectors have a bridge shape, have a width-reduced portion formed in the vicinity of the bonding face to the electrodes, and have a stress-reducing portion formed on the bonding face bonded to the electrode. | 2015-09-24 |
20150270200 | SYSTEM-IN-PACKAGE MODULE AND METHOD FOR FORMING THE SAME - A system-in-package (SiP) module is disclosed. The SiP module includes a substrate and a dam on the substrate. The dam defines a cavity. At least one chip is on the substrate inside the cavity. A printed circuit board (PCB) is bonded to the dam and covers the cavity. A thermal conductive sheet is in the cavity and is disposed between the chip and the PCB. The chip is in thermal contact with the PCB through the thermal conductive sheet. The disclosure also provides a method for manufacturing the SiP module. | 2015-09-24 |
20150270201 | SEMICONDUCTOR MODULE PACKAGE AND METHOD OF MANUFACTURING THE SAME - There is provided a semiconductor module package including: a base substrate formed by mounting one or more first semiconductor devices thereon; a lead frame formed to have an end portion of one side connected to the base substrate and an end portion of the other side protruded to the outside; a supporting frame formed on a top surface of the first semiconductor device and having a first adjusting member formed to protrude to a lower portion thereof; and a mold part sealing the base substrate, the lead frame, and a portion of the supporting frame, wherein one or more of the first semiconductor devices are formed to have different steps from each other. | 2015-09-24 |
20150270202 | Semiconductor Package with Integrated Die Paddles for Power Stage - In one implementation, a semiconductor package includes a first conductive carrier including a first die paddle of the semiconductor package, and a control transistor having a drain attached to the first die paddle. The semiconductor package also includes a second conductive carrier attached to the first conductive carrier and including a second die paddle of the semiconductor package, and a sync transistor having a drain attached to the second die paddle. The second die paddle couples a source of the control transistor to the drain of the sync transistor. | 2015-09-24 |
20150270203 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - According to one embodiment, a first semiconductor element has a first electrode connected to the first conductor, a second electrode connected to the second conductor, and a control electrode connected to a first signal terminal. A second semiconductor element has a first electrode connected to the first conductor, and a second electrode connected to the second conductor. A third semiconductor element has a first electrode connected to the third conductor, a second electrode connected to the fourth conductor, and a control electrode connected to a second signal terminal. A fourth semiconductor element has a first electrode connected to the third conductor, and a second electrode connected to the fourth conductor. | 2015-09-24 |
20150270204 | LEAD FRAME WITH RADIATOR PLATE, METHOD FOR MANUFACTURING LEAD FRAME WITH RADIATOR PLATE, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A lead frame with a radiator plate on which a semiconductor chip | 2015-09-24 |
20150270205 | LEADLESS CHIP CARRIER - A leadless chip carrier comprises a thermal pad for attaching to a printed circuit board (PCB) and an integrated circuit electrically connected to a plurality of electrical lead frame pads for connection to a plurality of corresponding pads on the PCB. The leadless chip carrier further comprises a non-collapsible conductive shim bonded to a first surface of the thermal pad and each of the plurality of electrical lead frame pads is attached to a volume of solder. The conductive shim provides a stand-off between the thermal pad and the PCB and improves the integrity of a joint between the thermal pad and the PCB. | 2015-09-24 |
20150270206 | PRESSURE SENSOR DEVICE WITH THROUGH SILICON VIA - A semiconductor pressure sensor device having a pressure-sensing die electrically connected to a microcontrol unit (MCU) using either through silicon vias (TSVs) or flip-chip bumps. An active surface of the pressure-sensing die is in facing relationship with the MCU. These embodiments avoid the need to used bonds to electrically connect the pressure-sensing die to the MCU, thereby saving time, reducing size, and reducing cost. | 2015-09-24 |
20150270207 | SEMICONDUCTOR MODULE PACKAGE AND METHOD OF MANUFACTURING THE SAME - There is provided a semiconductor module package including: a base substrate formed by mounting one or more first semiconductor devices thereon; a lead frame formed on a top surface of the first semiconductor device and having an inlet formed to inject a solder paste; and spaces inserted between the first semiconductor device and the lead frame to form a separation space, wherein the solder paste is filled in the separation space. | 2015-09-24 |
20150270208 | POWER SEMICONDUCTOR DEVICE - A power semiconductor device is provided. The power semiconductor device includes a leadframe, which includes a first chip carrier part and at least one second chip carrier part, which are fitted at a distance from one another and are in each case electrically conductive, at least one first power semiconductor component applied on the first chip carrier part, at least one second power semiconductor component applied on the second chip carrier part, external contacts in the form of external leads, and a capacitor. The capacitor is mounted on two adjacent external leads. | 2015-09-24 |
20150270209 | STACKED DIE INTEGRATED CIRCUIT - An apparatus relates generally to an integrated circuit package. In such an apparatus, a package substrate has a first plurality of via structures extending from a lower surface of the package substrate to an upper surface of the package substrate. An die has a second plurality of via structures extending to a lower surface of the die. The lower surface of the die faces the upper surface of the package substrate in the integrated circuit package. The package substrate does not include a redistribution layer. The die and the package substrate are coupled to one another. | 2015-09-24 |
20150270210 | Semiconductor Device - A semiconductor device includes a first semiconductor and second semiconductor chips mounted over a package substrate. The first semiconductor chip includes a plurality of first bonding pads which are arranged along one side of the first semiconductor chip. The second semiconductor chip includes a plurality of second bonding pads and at least one third bonding pad. The second bonding pads are arranged along one side of the second semiconductor chip and for coupling respectively to the first bonding pads by wire-bonding coupling. The at least one third bonding pad is for enabling relay coupling of a corresponding second bonding pad to at least one predetermined first bonding pad which is arranged along the second bonding pads and included in the first bonding pads without crossing another wire in the wire-bonding coupling. | 2015-09-24 |
20150270211 | SCALABLE INTERCONNECT STRUCTURES WITH SELECTIVE VIA POSTS - Interconnect structures including a selective via post disposed on a top surface of a lower level interconnect feature, and fabrication techniques to selectively form such a post. Following embodiments herein, a minimum interconnect line spacing may be maintained independent of registration error in a via opening. In embodiments, a selective via post has a bottom lateral dimension smaller than that of a via opening within which the post is disposed. Formation of a conductive via post may be preferential to a top surface of the lower interconnect feature exposed by the via opening. A subsequently deposited dielectric material backfills portions of a via opening extending beyond the interconnect feature where no conductive via post was formed. An upper level interconnect feature is landed on the selective via post to electrically interconnect with the lower level feature. | 2015-09-24 |
20150270212 | SEMICONDUCTOR DEVICE, FABRICATION METHOD FOR A SEMICONDUCTOR DEVICE AND ELECTRONIC APPARATUS - Disclosed herein is a semiconductor device, including: a first substrate including a first electrode, and a first insulating film configured from a diffusion preventing material for the first electrode and covering a periphery of the first electrode, the first electrode and the first insulating film cooperating with each other to configure a bonding face; and a second substrate bonded to and provided on the first substrate and including a second electrode joined to the first electrode, and a second insulating film configured from a diffusion preventing material for the second electrode and covering a periphery of the second electrode, the second electrode and the second insulating film cooperating with each other to configure a bonding face to the first substrate. | 2015-09-24 |
20150270213 | METHOD FOR FORMING VOIDS AND STRUCTURE WITH VOIDS FORMED USING THE SAME - A method for forming voids corresponding to pads of SMT components is provided. The method comprises following steps: One or more condition parameters are inputted into a searching unit. The searching unit searches all of the pads with reference to the condition parameters to obtain a pre-selected group of pads. A judgment unit is provided to determine whether each pad of the pre-selected group of pads meets a pre-determined processing requirement to generate a to-be-processed group of pads. An execution unit executes a void formation step with reference to corner coordinates of each of the to-be-processed group of pads, so as to form at least a void at the portion of a contact surface corresponding to a corner of the pad. In an embodiment, four voids which are related to respective corners of each pad of the to-be-processed group are formed at the contact surface accordingly. | 2015-09-24 |
20150270214 | METHOD FOR LAYOUT DESIGN AND STRUCTURE WITH INTER-LAYER VIAS - A computer implemented layout method for an integrated circuit (IC) structure and IC structure are provided. The layout method can include placing a circuit cell and an inter-layer via together in a first device layer of the IC structure, and placing a metal pattern in a second device layer of the IC structure. The inter-layer via and the metal pattern may be configured to form a direct connection channel for the circuit cell and the metal pattern. | 2015-09-24 |
20150270215 | VIA PRE-FILL ON BACK-END-OF-THE-LINE INTERCONNECT LAYER - The present disclosure relates to a metal interconnect layer formed using a pre-fill process to reduce voids, and an associated method. In some embodiments, the metal interconnect layer has a dielectric layer disposed over a substrate. An opening with an upper portion above a horizontal plane and a lower portion below the horizontal plane extends downwardly through the dielectric layer. A first conductive layer fills the lower portion of the opening. An upper barrier layer is disposed over the first conductive layer covering bottom and sidewall surfaces of the upper portion of the opening. A second conductive layer is disposed over the upper barrier layer filling the upper portion of the opening. | 2015-09-24 |
20150270216 | SELF-ALIGNED CONTACTS - A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations. | 2015-09-24 |
20150270217 | POWER MODULE PACKAGE - There is provided a power module package. The power module package includes: a base substrate provided with a pattern; a heat spreader formed by being stacked on an upper surface of the base substrate; and at least one first semiconductor device mounted on an upper surface of the heat spreader, wherein an outer circumferential surface of the heat spreader is provided with a coil. | 2015-09-24 |
20150270218 | Semiconductor Chip Including Integrated Circuit Including Four Transistors of First Transistor Type and Four Transistors of Second Transistor Type with Electrical Connections Between Various Transistors and Methods for Manufacturing the Same - A semiconductor chip region includes a first conductive structure (CS) that forms a gate electrode (GE) of a first transistor of a first transistor type (TT) and a GE of a first transistor of a second TT, a second CS that forms a GE of a second transistor of the first TT, a third CS that forms a GE of a second transistor of the second TT, a fourth CS that forms a GE of a third transistor of the first TT, a fifth CS that forms a GE of a third transistor of the second TT, another CS that forms a GE of a fourth transistor of the first TT, and another CS that forms a GE of a fourth transistor of the second TT. The second and third transistors of the first and second TT's have a common diffusion terminal electrical connection and specified gate electrode electrical connections. | 2015-09-24 |
20150270219 | INTERCONNECT STRUCTURE AND METHOD FOR FABRICATING ON-CHIP INTERCONNECT STRUCTURES BY IMAGE REVERSAL - An interconnect structure includes a patterned and cured dielectric layer located directly on a surface of a patterned permanent antireflective coating. The patterned and cured dielectric layer and the permanent antireflective coating form shaped openings. The shaped openings include an inverse profile which narrows towards a top of the shaped openings. A conductive structure fills the shaped openings wherein the patterned and cured dielectric layer and the permanent antireflective coating each have a conductively filled region. | 2015-09-24 |
20150270220 | SEMICONDUCTOR DEVICES HAVING THROUGH ELECTRODES AND METHODS OF MANUFACTURING THE SAME - Semiconductor devices are provided. The semiconductor device includes a semiconductor layer having a first surface and a second surface that are opposite each other, a through electrode penetrating the semiconductor layer and having a protrusion that protrudes over the second surface of the semiconductor layer, a front-side bump disposed over the first surface of the semiconductor layer and electrically coupled to the through electrode, a polymer pattern disposed over the second surface of the semiconductor layer to enclose a part of the protrusion of the through electrode, and a back-side bump covering an upper surface and a sidewall of a remaining part of the protrusion of the through electrode and extending over a portion of the polymer pattern. | 2015-09-24 |
20150270221 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - Semiconductor devices, and methods of fabricating a semiconductor device, include forming a via hole through a first surface of a substrate, the via hole being spaced apart from a second surface facing the first surface, forming a first conductive pattern in the via hole, forming an insulating pad layer on the first surface of the substrate, the insulating pad having an opening exposing the first conductive pattern, performing a thermal treatment on the first conductive pattern to form a protrusion protruding from a top surface of the first conductive pattern toward the opening, and then, forming a second conductive pattern in the opening. | 2015-09-24 |
20150270222 | OXIDE MEDIATED EPITAXIAL NICKEL DISILICIDE ALLOY CONTACT FORMATION - Contact openings are formed into a dielectric material exposing a surface portion of a semiconductor substrate. An interfacial oxide layer is then formed in each contact opening and on an exposed surface portion of the interfacial oxide layer. A NiPt alloy layer is formed within each opening and on the exposed surface portion of each interfacial oxide layer. An anneal is then performed that forms a contact structure of, from bottom to top, a nickel disilicide alloy body having an inverted pyramidal shape, a Pt rich silicide cap region and an oxygen rich region. A metal contact is then formed within each contact opening and atop the oxygen rich region of each contact structure. | 2015-09-24 |
20150270223 | METHOD FOR APPLYING A FINAL METAL LAYER FOR WAFER LEVEL PACKAGING AND ASSOCIATED DEVICE - A wafer level semiconductor device and manufacturing method including providing a semiconductor device wafer substitute having a backside, applying to the backside a conductive metallization layer, and applying to the backside over the conductive metallization layer a protective metal layer of titanium, titanium alloys, nickel, nickel alloys, chromium, chromium alloys, cobalt, cobalt alloys, palladium, and palladium alloys. | 2015-09-24 |
20150270224 | METHODS AND APPARATUSES TO FORM SELF-ALIGNED CAPS - At least one conductive line in a dielectric layer over a substrate is recessed to form a channel. The channel is self-aligned to the conductive line. The channel can be formed by etching the conductive line to a predetermined depth using a chemistry comprising an inhibitor to provide uniformity of etching independent of a crystallographic orientation. A capping layer to prevent electromigration is deposited on the recessed conductive line in the channel. The channel is configured to contain the capping layer within the width of the conductive line. | 2015-09-24 |
20150270225 | INTERCONNECT STRUCTURE AND MANUFACTURING METHOD THEREOF - The present disclosure provides an interconnect structure, including a substrate, a first conductive feature over the substrate, a second conductive feature over the first conductive feature, and a dielectric layer surrounding the first conductive feature and the second conductive feature. A width of the first conductive feature and a width of the second conductive feature are between 10 nm and 50 nm. The present disclosure also provides a method for manufacturing an interconnect structure, including (1) forming a via opening and a line trench in a dielectric layer, (2) forming a 1-dimensional conductive feature in the via opening, (3) forming a conformal catalyst layer over a sidewall of the line trench, a bottom of the line trench, and a top of the 1-dimensional conductive feature, and (4) removing the conformal catalyst layer from the bottom of the line trench and the top of the 1-dimensional conductive feature. | 2015-09-24 |
20150270226 | GRAPHENE WIRING AND SEMICONDUCTOR DEVICE - A graphene wiring of an embodiment includes graphene, first conductive layers, second conductive layers, and a third conductive layer. The first conductive layers are connected to first sides of the graphene opposite to each other in a longitudinal direction of the wiring. The second conductive layers are connected to second sides of the graphene opposite to each other in a widthwise direction of the wiring. The third conductive layer is connected to a top surface of the graphene. The first and second conductive layers are connected to each other. | 2015-09-24 |
20150270227 | Edge Coated Ceramic Substrates for Electronic Device Components - An electrical component may be mounted on a substrate such as a ceramic substrate. Contacts may be formed on upper and lower surfaces of the substrate. The electrical component may be soldered to the contacts on the upper surface. The contacts on the lower surface may be used to solder the substrate to a printed circuit. During manufacturing, it may be desirable to use metal traces on a ceramic panel to make connections to contacts on the substrate. Following singulation of the ceramic panel to form the ceramic substrate, some of the metal traces may run to the edge of the ceramic substrate. A folded tab of the printed circuit may form a shield that covers these exposed traces. A divided metal-coated groove or a row of divided metal-coated vias running along each edge of the substrate may also provide shielding. | 2015-09-24 |
20150270228 | CRACK-STOPPING STRUCTURE AND METHOD FOR FORMING THE SAME - A crack-stopping structure includes a semiconductor wafer comprising a plurality of dies defined by a plurality of scribe line regions, a plurality of metal patterns formed in the scribe line regions, and a plurality of groups of through silicon holes (TSHs) formed in the scribe line regions. The wafer further includes a front side and a back side, and the TSHs respectively include at least a bottom opening formed in the bottom side of the wafer. The groups of TSHs are formed between the metal patterns and the dies. | 2015-09-24 |
20150270229 | SEMICONDUCTOR CHIP AND SEMICONDUCTOR PACKAGE HAVING THE SAME - A semiconductor chip includes a semiconductor substrate having a front surface, a circuit unit formed within the semiconductor substrate and extending from the front surface into the semiconductor substrate, and a rear surface opposite the front surface, and a girder beam disposed outside of the circuit unit and within the semiconductor substrate. | 2015-09-24 |
20150270230 | Through Silicon Via Keep Out Zone Formation Method and System - Keep out zones (KOZ) are formed for a through silicon via (TSV). A device can be placed outside a first KOZ of a TSV determined by a first performance threshold so that a stress impact caused by the TSV to the device is less than a first performance threshold while the first KOZ contains only those points at which a stress impact caused by the TSV is larger than or equal to the first performance threshold. A second KOZ for the TSV can be similarly formed by a second performance threshold. A plurality of TSVs can be placed in a direction that the KOZ of the TSV has smallest radius to a center of the TSV, which may be in a crystal orientation [010] or [100]. A plurality of TSV stress plug can be formed at the boundary of the overall KOZ of the plurality of TSVs. | 2015-09-24 |
20150270231 | PACKAGE OF ENVIRONMENTAL SENSITIVE ELEMENT - A package of an environmental sensitive element including a flexible substrate, an environmental sensitive element, at least one flexible sacrificial layer and a packaging structure is provided. The environmental sensitive element is disposed on the flexible substrate. The flexible sacrificial layer is disposed on the environmental sensitive element, wherein the environmental sensitive element includes a plurality of first thin films and the flexible sacrificial layer includes a plurality of second thin films. The bonding strength between two adjacent second thin films is equal to or lower than the bonding strength between two adjacent first thin films. Further, the packaging structure covers the environmental sensitive element and the flexible sacrificial layer. | 2015-09-24 |
20150270232 | SEMICONDUCTOR PACKAGES AND METHODS OF FORMING THE SAME - Embodiments of the present disclosure include semiconductor packages and methods of forming the same. An embodiment is a semiconductor package including a first package including one or more dies, and a redistribution layer coupled to the one or more dies at a first side of the first package with a first set of bonding joints. The redistribution layer including more than one metal layer disposed in more than one passivation layer, the first set of bonding joints being directly coupled to at least one of the one or more metal layers, and a first set of connectors coupled to a second side of the redistribution layer, the second side being opposite the first side. | 2015-09-24 |
20150270233 | WAFER LEVEL PACKAGES AND METHODS FOR PRODUCING WAFER LEVEL PACKAGES HAVING DELAMINATION-RESISTANT REDISTRIBUTION LAYERS - Wafer level packages and methods for producing wafer level packages having delamination-resistant redistribution layers are provided. In one embodiment, the method includes building inner redistribution layers over a semiconductor die. Inner redistribution layers include a body of dielectric material containing metal routing features. A routing-free dielectric block is formed in the body of dielectric material and is uninterrupted by the metal routing features. An outer redistribution layer is produced over the inner redistribution layers and contains a metal plane, which is patterned to include one or more outgassing openings overlying the routing-free dielectric block. The routing-free dielectric block has a minimum width, length, and depth each at least twice the thickness of the outer redistribution layer. | 2015-09-24 |
20150270234 | PAD STRUCTURE FOR SEMICONDUCTOR DEVICE CONNECTION - A pad structure may include a conductive pad that includes an exposed portion. The pad structure may further include a first conductive set that includes a first conductive part and a second conductive part. The first conductive part may overlap the exposed portion in a direction perpendicular to the conductive pad. The first conductive part may be spaced from the second conductive part in a direction parallel to the conductive pad and may overlap the second conductive part in the direction parallel to the conductive pad. The pad structure may further include a conductive layer that contacts the conductive pad and is positioned between the conductive pad and the first conductive set in the direction perpendicular to the conductive pad. The pad structure may further include a first via member, which may electrically connect the first conductive part to the conductive layer. | 2015-09-24 |
20150270235 | DRY-REMOVABLE PROTECTIVE COATINGS - Techniques are disclosed for protecting a surface using a dry-removable protective coating that does not require chemical solutions to be removed. In an embodiment, a protective layer is disposed on a surface. The protective layer is composed of one layer that adheres to the surface. The surface is then processed while the protective coating is on the surface. Thereafter, the protective layer is removed from the surface by separating the protective layer away from the surface without the use of chemical solutions. | 2015-09-24 |
20150270236 | CHIP PACKAGE AND METHOD THEREOF - The present invention provides a chip package that includes a semiconductor chip, at least one recess, a plurality of first redistribution metal lines, and at least one protrusion. The semiconductor chip has a plurality of conductive pads disposed on an upper surface of the semiconductor chip. The recess extends from the upper surface to a lower surface of the semiconductor chip, and is arranged on the side of the semiconductor chip. The first redistribution metal lines are disposed on the upper surface, electrically connected to the conductive pad individually, and extended into the recesses separately. The protrusion is disposed in the recess and located between the adjacent first redistribution metal lines. | 2015-09-24 |
20150270237 | Semiconductor Device and Method of Forming 3D Dual Side Die Embedded Build-Up Semiconductor Package - A semiconductor device has a plurality of semiconductor die. A substrate is provided with bumps disposed over the substrate. A first prefabricated insulating film is disposed between the semiconductor die and substrate. An interconnect structure is formed over the semiconductor die and first prefabricated insulating film. The bumps include a copper core encapsulated within copper plating. The first prefabricated insulating film includes glass cloth, glass fiber, or glass fillers. The substrate includes a conductive layer formed in the substrate and coupled to the bumps. The semiconductor die is disposed between the bumps of the substrate. The bumps and the semiconductor die are embedded within the first prefabricated insulating film. A portion of the first prefabricated insulating film is removed to expose the bumps. The bumps electrically connect the substrate to the interconnect structure. | 2015-09-24 |
20150270238 | JOINTED STRUCTURE AND METHOD OF MANUFACTURING SAME - The jointed structure of the present invention is configured such that a first metal layer and a second metal layer are jointed together. More specifically, the jointed structure of the present invention includes: the first metal layer which receives heat from a heat generating body; and the second metal layer which is jointed to the first metal layer and receives heat from the first metal layer, for example. The first metal layer and the second metal layer according to the present invention are jointed together by solid-phase joining via a joining interface microstructure that has a thickness of 50 nm or less. Since the first metal surface and the second metal surface are jointed together without via a brazing material, adhesive or other material, the jointed structure of the present invention exhibits high conductivity and heat resistance property. Such a jointed structure is suitable for power modules. | 2015-09-24 |
20150270239 | Semiconductor Device Package and Method of the Same - The invention proposes a semiconductor device package structure, comprising a substrate, an adhesive layer and a die. The substrate has electrical through-holes to inter-connect a first and second wiring circuit on a top surface and a bottom surface of the substrate respectively, wherein a contact conductive bump is formed on the first wiring circuit. The under-fill adhesive layer is formed on the top surface and the first wiring circuit of the substrate except the area of the die. The die has a bump structure on the bonding pads of the die, wherein the bump structure of the die is electrically connected to the contact conductive bump of the first wiring circuit of the substrate. | 2015-09-24 |
20150270240 | POWER SEMICONDUCTOR DEVICE - A power semiconductor element includes an electrode layer made of a conductor. A first wiring portion is made of a conductor and is apart from the power semiconductor element. At least one main bonding wire has one end on the electrode layer and the other end on the first wiring portion. At least one sub-bonding wire supports the main bonding wire and has both ends on one of the electrode layer and the first wiring portion. | 2015-09-24 |
20150270241 | FLIP CHIP INTERCONNECTION WITH REDUCED CURRENT DENSITY - A method and system for electrically connect a semiconductor device with a flip-chip form factor to a printed circuit board. An exemplary embodiment of the method comprises: aligning solder contacts on the device with a first copper contact and a second copper contact of the external circuitry, and, applying a supply current only directly to a buried layer of the first copper and not directly to the layer which is nearest the device, such that no current is sourced to the device through the layer nearest the device. | 2015-09-24 |
20150270242 | SEMICONDUCTOR PACKAGES AND METHODS OF FABRICATING THE SAME - A semiconductor package includes a wiring board, a semiconductor chip mounted on the wiring board, and a mounting connection terminal electrically connecting a bonding pad of the semiconductor chip to a first connection pad of the wiring board. The mounting connection terminal includes a core portion and a connecting shell solder portion substantially surrounding the core portion. The core portion of the mounting connection terminal is not in contact with the bonding pad of the semiconductor chip. | 2015-09-24 |
20150270243 | Semiconductor Device Package and Method of the Same - The invention proposes a semiconductor device package structure, comprising a substrate, an adhesive layer and a die. The substrate has electrical through-holes to inter-connect a first and second wiring circuit on a top surface and a bottom surface of the substrate respectively, wherein a contact conductive bump is formed on the first wiring circuit. The under-fill adhesive layer is formed on the top surface and the first wiring circuit of the substrate except the area of the die. The die has a bump structure on the bonding pads of the die, wherein the bump structure of the die is electrically connected to the contact conductive bump of the first wiring circuit of the substrate. | 2015-09-24 |
20150270244 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device, includes providing a multi-chip interconnection substrate having an upper surface and a lower surface, providing a semiconductor chip having a main surface and a back surface, making the back surface of the semiconductor chip and the upper surface of the multi-chip interconnection substrate face each other and mounting the semiconductor chips in the chip mounting areas of the multi-chip interconnection substrate through a bonding adhesive, coupling the electrode pads formed on the main surface of each of the semiconductor chips with the bonding pads formed on the upper surface of the multi-chip interconnection substrate by the conductive wires respectively, forming a resin sealing body by resin-sealing the semiconductor chips, the conductive wires, and the upper surface of the multi-chip interconnection substrate, and forming a plurality of solder balls to be coupled to a plurality of bump lands formed on the lower surface of the multi-chip interconnection substrate. | 2015-09-24 |
20150270245 | SEMICONDUCTOR DEVICE AND ELECTRONIC CIRCUIT DEVICE - A semiconductor device according to an embodiment includes a first semiconductor unit including a plurality of first semiconductor chips, an organic resin provided between the first semiconductor chips, a wiring layer provided above the first semiconductor chips to electrically connect the first semiconductor chips to each other, and a plurality of connecting terminals provided on an upper portion of the wiring layer and a second semiconductor unit fixed to a wiring layer side of the first semiconductor unit, the second semiconductor unit fixed to a region sandwiched between the connecting terminals, the second semiconductor unit having a second semiconductor chip, the second semiconductor unit electrically connected to the first semiconductor unit. | 2015-09-24 |
20150270246 | VOLUMETRIC INTEGRATED CIRCUIT AND VOLUMETRIC INTEGRATED CIRCUIT MANUFACTURING METHOD - A volumetric integrated circuit manufacturing method is provided. The method includes assembling a slab element of elongate chips, exposing a wiring layer between adjacent elongate chips of the slab element, metallizing a surface of the slab element at and around the exposed wiring layer to form a metallized surface electrically coupled to the wiring layer and passivating the metallized surface to hermetically seal the metallized surface. | 2015-09-24 |
20150270247 | Semiconductor Packages and Methods of Forming the Same - Embodiments of the present disclosure include semiconductor packages and methods of forming the same. An embodiment is a semiconductor package including a first package including one or more dies, and a redistribution layer coupled to the one or more dies at a first side of the first package with a first set of bonding joints. The redistribution layer including more than one metal layer disposed in more than one passivation layer, the first set of bonding joints being directly coupled to at least one of the one or more metal layers, and a first set of connectors coupled to a second side of the redistribution layer, the second side being opposite the first side. | 2015-09-24 |
20150270248 | SEMICONDUCTOR PACKAGE AND GUARD UNITS - A semiconductor package may include: a plurality of slave chips stacked over a master chip through a through silicon via (TSV); a first guard unit disposed around each of the slave chips; and a second guard unit formed at a first distance from the first guard unit and disposed at the master chip. | 2015-09-24 |
20150270249 | Semiconductor Package with Via-Coupled Power Transistors - In one implementation, a semiconductor package includes a carrier including first and second conductive segments, and first and second transistors attached respectively to the first and second conductive segments. The semiconductor package also includes a dielectric material formed in exposed portions of the first and second conductive segments, a first via extending through the dielectric material to the first conductive segment, and a second via extending through the dielectric material to the second conductive segment. A solder material fills each of the vias, the solder material protruding beyond the dielectric material and configured to electrically, thermally, and mechanically connect the carrier to a mounting surface for the semiconductor package. | 2015-09-24 |
20150270250 | SEMICONDUCTOR DEVICE - [Problem] To match operating conditions during normal operations in which a bump electrode is used and operating conditions during test operations when a test pad is used. | 2015-09-24 |
20150270251 | DISPLAY DEVICE - In a display device connected with an IC driver, particularly the reliability of connection between an IC terminal located on the outermost side and the IC driver is improved. IC terminals and flexible wiring board terminals are formed on a terminal region of a TFT substrate. A plurality of the IC terminals are formed at a predetermined pitch. The reliability of an outermost IC terminal is degraded as compared with the reliability of the other IC terminals caused by the loading effect in etching a protection insulating film. In order to prevent this degradation, a dummy terminal is formed on the outer side of the outermost IC terminal, and the loading effect on the outermost IC terminal is made equal to the loading effect on the other IC terminals. Accordingly, degradation in the reliability of the outermost IC terminal is prevented. | 2015-09-24 |
20150270252 | STACK PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A stack package includes a cover film, a first package having a first semiconductor chip which is attached to the cover film, a first adhesive member which is formed to seal the first semiconductor chip and a surface of the cover film, and a first circuit pattern which is disposed over the first adhesive member and electrically connected with the first semiconductor chip; a second package disposed over the first package, having a second semiconductor chip which is electrically connected with the first circuit pattern, a second adhesive member which is formed to seal the second semiconductor chip, and a second circuit pattern which is formed over the second adhesive member, and a via formed to pass through the second circuit pattern and the second adhesive member and to be electrically connected with the first circuit pattern and the second circuit pattern. | 2015-09-24 |
20150270253 | PROGRAMMABLE ESD PROTECTION CIRCUIT - An electrostatic discharge (ESD) protection circuit (FIG. | 2015-09-24 |
20150270254 | HEMT TEMPERATURE SENSOR - An integrated structure ( | 2015-09-24 |
20150270255 | SEMICONDUCTOR DEVICE - A semiconductor device according to the embodiments includes: a first normally-off transistor including a first source terminal, a first drain terminal, and a first gate terminal; a normally-on transistor including a second source terminal connected to the first drain terminal, a second drain terminal, and a second gate terminal connected to the first source terminal; a protection element provided between the first gate terminal and the second drain terminal, and having breakdown voltage lower than breakdown voltage of the normally-on transistor; and a first diode including a first anode connected to the second drain terminal and a first cathode connected to the protection element. | 2015-09-24 |
20150270256 | SEGMENTED NPN VERTICAL BIPOLAR TRANSISTOR - A segmented bipolar transistor includes a p-base in a semiconductor surface including at least one p-base finger having a base metal/silicide stack including a base metal line that contacts a silicide layer on the semiconductor surface of the p-base finger. An n+ buried layer is under the p-base. A collector includes an n+ sinker extending from the semiconductor surface to the n+ buried layer including a collector finger having a collector metal/silicide stack including a collector metal line that contacts a silicide layer on the semiconductor surface of the collector finger. An n+ emitter has at least one emitter finger including an emitter metal/silicide stack that contacts the silicide layer on the semiconductor surface of the emitter finger. The emitter metal/silicide stack and/or collector metal/silicide stack include segmentation with a gap which cuts a metal line and/or the silicide layer of the stack. | 2015-09-24 |
20150270257 | SERIES CONNECTED ESD PROTECTION CIRCUIT - An electrostatic discharge (ESD) protection circuit (FIG. | 2015-09-24 |
20150270258 | Optimized ESD Clamp Circuitry - ESD protection circuitry is disclosed. In one embodiment, an integrated circuit includes first and second sensor circuits. The first sensor circuit has a first resistive-capacitive (RC) time constant, while the second sensor circuit has a second RC time constant. The RC time constant of the first sensor circuit is at least one order of magnitude greater than that of the second sensor circuit. A first clamp transistor is coupled to and configured to be activated by the first sensor circuit responsive to the latter detecting an ESD event. A second clamp transistor is coupled to and configured to be activated by the second sensor circuit responsive to the latter detecting the ESD event. | 2015-09-24 |
20150270259 | INTEGRATED CIRCUIT, INTEGRATED CIRCUIT PACKAGE AND METHOD OF PROVIDING PROTECTION AGAINST AN ELECTROSTATIC DISCHARGE EVENT - An integrated circuit comprising a power supply node, a ground node and a gated domain coupled between the power node and the ground node. A Charged Device Model electrostatic discharge protection module is provided for shunting electrical energy of a CDM ESD event away from the gated domain. A gating switch makes an electrical connection in a connected state between the gated domain and at least one of the power node and the ground node. ESD gating control circuitry is coupled to the CDM ESD protection module and controls shunting of energy away from the gated domain by the CDM ESD protection module, thereby avoiding the energy flowing through the gated domain. The ESD gating control circuitry inhibits actuation of the CDM ESD protection module to prevent response to CDM ESD events when the gating domain is powered-up. | 2015-09-24 |
20150270260 | ESD PROTECTION CIRCUIT CELL - A protection cell for a cell library. The protection cell defines a protection circuit for an IC having a driving device with a first supply voltage Vdd | 2015-09-24 |
20150270261 | SEMICONDUCTOR PROCESS - A semiconductor structure includes a metal gate, a second dielectric layer and a contact plug. The metal gate is located on a substrate and in a first dielectric layer, wherein the metal gate includes a work function metal layer having a U-shaped cross-sectional profile and a low resistivity material located on the work function metal layer. The second dielectric layer is located on the metal gate and the first dielectric layer. The contact plug is located on the second dielectric layer and in a third dielectric layer, thereby a capacitor is formed. Moreover, the present invention also provides a semiconductor process forming said semiconductor structure. | 2015-09-24 |
20150270262 | GATE STRUCTURES WITH PROTECTED END SURFACES TO ELIMINATE OR REDUCE UNWANTED EPI MATERIAL GROWTH - One method disclosed herein includes, among other things, forming a line-end protection layer in an opening on an entirety of each opposing, spaced-apart first and second end face surfaces of first and second spaced-apart gate electrode structures, respectively, and forming a sidewall spacer adjacent opposing sidewall surfaces of each of the gate electrode structures but not adjacent the opposing first and second end face surfaces having the line-end protection layer positioned thereon. | 2015-09-24 |