39th week of 2009 patent applcation highlights part 40 |
Patent application number | Title | Published |
20090239324 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE USING SEPARABLE SUPPORT BODY - In a method for manufacturing a semiconductor device, a first conductivity type semiconductor layer and a second conductivity type semiconductor layer are sequentially grown on a growth substrate. Then, an electrode layer is formed on the second conductivity type semiconductor layer. Then, a support body is adhered to the electrode layer by providing at least one adhesive layer therebetween. Finally, at least a part of the growth substrate is removed. In this case, the adhesive layer is removable from the electrode layer. | 2009-09-24 |
20090239325 | METHOD OF FABRICATING A INTEGRATED PRESSURE SENSOR - A method of fabricating a pressure sensor ( | 2009-09-24 |
20090239326 | METHOD FOR MANUFACTURING MICROCRYSTALLINE SILICON SOLAR CELL - A method for manufacturing a microcrystalline silicon solar cell comprises forming a zinc oxide transparent electrode with a textured surface on an insulation substrate by chemical vapor deposition, etching the zinc oxide transparent electrode with acid water solution and depositing a microcrystalline silicon thin film on the zinc oxide transparent electrode with the textured surface. | 2009-09-24 |
20090239327 | CMOS IMAGE SENSOR AND METHOD OF FABRICATING THE SAME - In a CMOS image sensor and method of fabricating the same, the CMOS image sensor is comprised of a pixel array generating image signals and a peripheral circuit processing the image signals. In the method, a substrate is provided having a pixel region and a peripheral circuit region. A photo-receiving element and at least one transistor are formed on the pixel region of the substrate and a transistor is formed on the peripheral circuit region of the substrate. A silicide barrier pattern is formed to cover a region where the photo-receiving element is formed. A silicide layer is formed on a predetermined region of the substrate. An interlevel insulation film is formed on the silicide barrier layer. At least one contact hole penetrating the interlevel insulation film is formed, the at least one contact hole exposing a predetermined region of the silicide layer. This is effective to prevent a problem such as an excessive etching due to disagreement of the etch target films between the pixel array and the peripheral circuit. | 2009-09-24 |
20090239328 | PHOTO-DETECTOR FOR DETECTING IMAGE SIGNAL OF INFRARED LASER RADAR AND METHOD OF MANUFACTURING THE SAME - A photo-detector, in which metal wiring for connecting electrodes is arranged on a planarized surface and thus the metal wiring arrangement is simplified, and a method of manufacturing the same are provided. The photo-detector includes a multi-layer compound semiconductor layer formed on a compound semiconductor substrate. A number of p-n junction diodes are arranged in a regular order in a selected region of the compound semiconductor layer, and an isolation region for individually isolating the p-n junction diodes is formed by implanting impurity ions in the multi-layer compound semiconductor layer. The isolation region and the surface of the compound semiconductor layer are positioned on the same level. The isolation region may be a Fe-impurity region. | 2009-09-24 |
20090239329 | METHOD FOR MANUFACTURING PACKAGE STRUCTURE OF OPTICAL DEVICE - A package structure of optical devices has a chip, a sealant, a cover, a substrate, a plurality of bonding wires, and a transparent encapsulant. The chip has at least an optical device and a plurality of chip connection pads. The sealant is disposed around the optical elements. The cover is disposed on the sealant. The substrate supports the chip and has a plurality of connection pads. The bonding wires are used for electrically connecting the chip connection pads of the chip to the connection pads of the substrate. The transparent encapsulant is formed over the substrate and the cover, and encapsulates the bonding wires. | 2009-09-24 |
20090239330 | METHODS FOR FORMING COMPOSITE NANOPARTICLE-METAL METALLIZATION CONTACTS ON A SUBSTRATE - A method for forming a contact to a substrate is disclosed. The method includes providing a substrate, the substrate being doped with a first dopant; and diffusing a second dopant into at least a first side of the substrate to form a second dopant region, the first side further including a first side surface area. The method also includes forming a dielectric layer on the first side of the substrate. The method further includes forming a set of composite layer regions on the dielectric layer, wherein each composite layer region of the set of composite layer regions further includes a set of Group IV semiconductor nanoparticles and a set of metal particles. The method also includes heating the set of composite layer regions to a first temperature, wherein at least some composite layer regions of the set of composite layer regions etch through the dielectric layer and form a set of contacts with the second dopant region. | 2009-09-24 |
20090239331 | METHODS FOR FORMING MULTIPLE-LAYER ELECTRODE STRUCTURES FOR SILICON PHOTOVOLTAIC CELLS - Methods for forming a photovoltaic cell electrode structure, wherein the photovoltaic cell includes a semiconductor substrate having a passivation layer thereon, includes providing a plurality of contact openings through the passivation layer to the semiconductor substrate, selectively plating a contact metal into the plurality of contact openings to deposit the contact metal, depositing a metal containing material on the deposited contact metal, and firing the deposited contact metal and the deposited metal containing material. The metal containing material may include a paste containing a silver or silver alloy along with a glass frit and is substantially free to completely free of lead. The methods may also use light activation of the passivation layer or use seed layers to assist in the plating. | 2009-09-24 |
20090239332 | Bifacial Cell With Extruded Gridline Metallization - Provided is a bifacial photovoltaic arrangement comprising a bifacial cell which included a semiconductor layer having a first surface and a second surface, a first passivation layer formed on the first surface of the semiconductor layer and a second passivation layer formed on the second surface of the semiconductor layer, and a plurality of metallizations formed on the first and second passivation layers and selectively connected to the semiconductor layer. At least some of the metallizations on the bifacial photovoltaic arrangement comprising an elongated metal structure having a relatively small width and a relatively large height extending upward from the first and second passivation layers. | 2009-09-24 |
20090239333 | Organic semiconductor device and method of manufacturing the same - A low-cost and efficient process producing improved organic electronic devices such as transistors that may be used in a variety of applications is described. The applications may include radio frequency identification (RFID) devices, displays and the like. In one embodiment, the improved process is implemented by flash annealing a substrate with an energy having wavelengths ranging from about 250 nm to about 1100 nm or higher. In this flash annealing process energy having wavelengths from about 250 nm to about 350 nm or higher is substantially prevented from irradiating the substrate. | 2009-09-24 |
20090239334 | ELECTRODE FORMED IN APERTURE DEFINED BY A COPOLYMER MASK - A method of manufacturing a memory device is provided that in one embodiment includes providing an interlevel dielectric layer including a first via containing a memory material; forming at least one insulating layer on an upper surface of the memory material and the interlevel dielectric layer; forming an cavity through a portion of a thickness of the at least one insulating layer; forming a copolymer mask in at least the cavity, the copolymer mask including at least one opening that provides an exposed surface of a remaining portion of the at least one insulating layer that overlies the memory material; etching the exposed surface of the remaining portion of the at least one insulating layer to provide a second via to the memory material; and forming a conductive material within the second via in electrical contact with the memory material. | 2009-09-24 |
20090239335 | Semiconductor Device and Manufacturing Method Thereof - An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region. | 2009-09-24 |
20090239336 | Semiconductor packages and methods of fabricating the same - A semiconductor package and module, and methods of fabricating the same are provided. A method of fabricating a semiconductor package may include bonding rear surfaces of first and second semiconductor chips to each other, each of the semiconductor chips having chip pads exposed on front surfaces. The method may also include forming an encapsulation portion configured to encapsulate side surfaces of the bonded semiconductor chips, forming via plugs configured to pass through the encapsulation portion, forming an insulating layer configured to expose surfaces of the chip pads and the via plugs on the exposed surfaces of the two semiconductor chips and surfaces of the encapsulation portion, and forming package pads on the exposed surfaces of the chip pads and the surfaces of the via plugs. | 2009-09-24 |
20090239337 | MICROELECTRONIC DEVICES, STACKED MICROELECTRONIC DEVICES, AND METHODS FOR MANUFACTURING MICROELECTRONIC DEVICES - Microelectronic devices, stacked microelectronic devices, and methods for manufacturing microelectronic devices are described herein. In one embodiment, a set of stacked microelectronic devices includes (a) a first microelectronic die having a first side and a second side opposite the first side, (b) a first substrate attached to the first side of the first microelectronic die and electrically coupled to the first microelectronic die, (c) a second substrate attached to the second side of the first microelectronic die, (d) a plurality of electrical couplers attached to the second substrate, (e) a third substrate coupled to the electrical couplers, and (f) a second microelectronic die attached to the third substrate. The electrical couplers are positioned such that at least some of the electrical couplers are inboard the first microelectronic die. | 2009-09-24 |
20090239338 | Method of Forming an Interconnect on a Semiconductor Substrate - The present invention relates to a method of forming a wire bond-free conductive interconnect area on a semiconductor substrate. A semiconductor substrate with an electrically conductive protrusion, defining a bond pad, is provided as well as a plurality of carbon nanotubes. The plurality of carbon nanotubes is immobilized on the bond pad by allowing at least one random portion along the length of the carbon nanotubes to attach to the surface of the bond pad. Thus an aggregate of loops of carbon nanotubes is formed on the surface of the bond pad. Thereby a conductive interconnect area is formed on the electrically conductive protrusion without heat treatment. | 2009-09-24 |
20090239339 | METHOD OF STACKING DIES FOR DIE STACK PACKAGE - A method of manufacturing a die stack package includes the steps of providing a wafer having a first surface and a second surface, said first surface having a plurality of cut ways thereon, the second surface being coated with adhesive of a predetermined thickness at a predetermined position thereof, removing parts of the adhesive by photo-lithography, each of the parts of the adhesive corresponds to the cut way and is wider than the cut way; cutting the wafer along the cut ways to make a plurality of dies, each of the dies having a part of the adhesive thereon; and stacking each of the dies, whose surface having the adhesive faces a lower-layer die, on the lower-layer die. Therefore, the method facilitates the stacking operation and saves the production cost. | 2009-09-24 |
20090239340 | METHODS FOR A MULTIPLE DIE INTEGRATED CIRCUIT PACKAGE - Methods for a multiple die package for integrated circuits are disclosed. An insulator layer is provided and one or more vias are formed within it. The insulator may be provided without vias, and vias formed later. At least one integrated circuit is provided and electrically coupled to at least one lead of a first leadframe overlying one surface of the insulator. At least one second integrated circuit is provided and electrically coupled to a second leadframe overlying a second surface of the insulator. Electrical connections between the two leadframes and the first and second integrated circuits are made through the insulator at selected locations, by coupling at least one lead of the first and second leadframes one to another. The leads of the first and second leadframe may be physically coupled by a welding process within vias in the insulator. A method for a removable storage card is also described. | 2009-09-24 |
20090239341 | IC PACKAGING PROCESS - An IC packaging process includes the steps of preparing a substrate having a chip-receiving place formed on a front side thereof; creating a dam layer on the front side of the substrate; coating an ultraviolet adhesive layer on the dam layer; removing a part of the ultraviolet adhesive layer that corresponds to the chip-receiving place; removing a part of the dam layer that corresponds to the chip-receiving place; mounting a chip to the chip-receiving place in the open chamber and bonding wires between the substrate and the chip for electrical connection of the chip and the substrate; and mounting a cover layer on the ultraviolet adhesive layer and then heating the ultraviolet adhesive layer to adhesively fasten the cover layer on the dam layer. Accordingly, the IC packaging process effectively reduces the adhesive squeeze-out to prevent it from damage to the chip. | 2009-09-24 |
20090239342 | Thin Film Transistor Substrate of Horizontal Electric Field Type Liquid Crystal Display Device and Fabricating Method Thereof - A thin film transistor substrate of horizontal electric field type includes: a gate line and a first common line formed on a substrate to be in parallel to each other; a data line crossing the gate line and the first common line with a gate insulating film therebetween to define a pixel area; a second common line crossing the first common line having the gate insulating film therebetween; a thin film transistor connected to the gate line and the data line; a common electrode extending from the second common line in said pixel area; a pixel electrode that is parallel to the common electrode and the second common line; a protective film for covering the thin film transistor; a gate pad having a lower gate pad electrode connected to an upper gate pad electrode through a first contact hole; a common pad having a lower common pad electrode connected to an upper common pad electrode through a second contact hole; and a data pad having a lower data pad electrode connected to an upper data pad electrode provided within a third contact hole. | 2009-09-24 |
20090239343 | Methods Of Forming Lines Of Capacitorless One Transistor DRAM Cells, Methods Of Patterning Substrates, And Methods Of Forming Two Conductive Lines - This invention includes a capacitorless one transistor DRAM cell that includes a pair of spaced source/drain regions received within semiconductive material. An electrically floating body region is disposed between the source/drain regions within the semiconductive material. A first gate spaced is apart from and capacitively coupled to the body region between the source/drain regions. A pair of opposing conductively interconnected second gates are spaced from and received laterally outward of the first gate. The second gates are spaced from and capacitively coupled to the body region laterally outward of the first gate and between the pair of source/drain regions. Methods of forming lines of capacitorless one transistor DRAM cells are disclosed. | 2009-09-24 |
20090239344 | Methods of Forming Field Effect Transistors Having Silicided Source/Drain Contacts with Low Contact Resistance - Methods of forming integrated circuit devices according to embodiments of the present invention include forming a PMOS transistor having P-type source and drain regions, in a semiconductor substrate, and then forming a diffusion barrier layer on the source and drain regions. A silicon nitride layer is deposited on at least portions of the diffusion barrier layer that extend opposite the source and drain regions. Hydrogen is removed from the deposited silicon nitride layer by exposing the silicon nitride layer to ultraviolet (UV) radiation. This removal of hydrogen may operate to increase a tensile stress in a channel region of the field effect transistor. This UV radiation step may be followed by patterning the first and second silicon nitride layers to expose the source and drain regions and then forming silicide contact layers directly on the exposed source and drain regions. | 2009-09-24 |
20090239345 | Methods of Fabricating Nonvolatile Semiconductor Memory Devices - A nonvolatile semiconductor memory device includes a plurality of pillars protruding upward from a semiconductor substrate and having respective top surfaces and opposing sidewalls, a bit line on the top surfaces of the pillars and connecting a row of the pillars along a first direction, a pair of word lines on the opposing sidewalls of one of the plurality of pillars and crossing beneath the bit line, and a pair of memory layers interposed between respective ones of the pair of word lines and the one of the plurality of pillars. Methods of fabricating a nonvolatile semiconductor memory device include selectively etching a semiconductor substrate to form pluralities of stripes having opposing sidewalls and being arranged along a direction, forming memory layers and word lines along the sidewalls of the stripes selectively etching the stripes to form a plurality of pillars, and forming a bit line connecting the pillars and crossing above the word lines. | 2009-09-24 |
20090239346 | SEMICONDUCTOR DEVICE WITH FINFET AND METHOD OF FABRICATING THE SAME - A FinFET semiconductor device has an active region formed of a semiconductor substrate and projecting from a surface of the substrate. A fin having a first projection and a second projection composed of the active region are arranged in parallel and at each side of a central trench formed in a central portion of the active region. Upper surfaces and side surfaces of the first projection and the second projection comprise a channel region. A channel ion implantation layer is provided at a bottom of the central trench and at a lower portion of the fin. A gate oxide layer is provided on the fin. A gate electrode is provided on the gate oxide layer. A source region and a drain region are provided in the active region at sides of the gate electrode. A method of forming such a device is also provided. | 2009-09-24 |
20090239347 | METHOD OF FORMING MOS DEVICE - The present invention provides a method for forming a metal-oxide-semiconductor (MOS) device. The method includes at least the steps of forming a silicon germanium layer by the selective epitaxy growth process and forming a cap layer on the silicon germanium layer by the selective growth process. Hence, the undesirable effects caused by ion implantation can be mitigated. | 2009-09-24 |
20090239348 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device formed on a strained silicon layer and a method of manufacturing such a semiconductor device are disclosed. In accordance with this invention, a first silicon germanium layer is formed on a single crystalline silicon substrate; a second silicon germanium layer is formed on the first silicon germanium layer, the second silicon germanium layer having a concentration of germanium in a range of about 1 percent by weight to about 15 percent by weight based on the total weight of the second silicon germanium layer; a strained silicon layer is formed on the second silicon germanium layer; an isolation layer is formed at a first portion of the strained silicon layer; a gate structure is formed on the strained silicon layer; and, source/drain regions are formed at second portions of the strained silicon layer adjacent to the gate structure to form a transistor. | 2009-09-24 |
20090239349 | NONVOLATILE MEMORY DEVICES AND METHODS OF FORMING THE SAME - In a nonvolatile memory device and a method of fabricating the same, a device isolation layer is formed defining an active region in a semiconductor substrate. A gate insulation layer and a first conductive layer are formed on the semiconductor substrate. A pair of stack patterns are formed, each having a intergate dielectric layer pattern and a second conductive layer pattern on the first conductive layer. A mask pattern is formed on the first conductive layer pattern between the stack patterns, the mask pattern being spaced apart from each of the stack patterns. The first conductive layer is patterned using the stack patterns and the mask patterns as an etching mask. Impurity ions are implanted into the active region to form a pair of nonvolatile memory transistors and a select transistor. The resulting nonvolatile memory device includes a memory cell unit that includes the pair of nonvolatile memory transistors and the select transistor. | 2009-09-24 |
20090239350 | HIGH PERFORMANCE TAPERED VARACTOR - Disclosed is a semiconductor structure, which includes a non-planar varactor having a geometrically designed depletion zone with a taper, as to provide improved Cmax/Cmin with low series resistance. Because of the taper, the narrowest portion of the depletion zone can be designed to be fully depleted, while the remainder of the depletion zone is only partially depleted. The fabrication of semiconductor structure may follow that of standard FinFET process, with a few additional or different steps. These additional or different steps may include formation of a doped trapezoidal (or triangular) shaped silicon mesa, growing/depositing a gate dielectric, forming a gate electrode over a portion of the mesa, and forming a highly doped contact region in the mesa where it is not covered by the gate electrode. | 2009-09-24 |
20090239351 | Method For Fabricating Capacitor Structures Using The First Contact Metal - A capacitor structure is fabricated with only slight modifications to a conventional single-poly CMOS process. After front-end processing is completed, grooves are etched through the pre-metal dielectric layer to expose polysilicon structures, which may be salicided or non-salicided. A dielectric layer is formed over the exposed polysilicon structures. A conventional contact process module is then used to form contact openings through the pre-metal dielectric layer. The mask used to form the contact openings is then removed, and conventional contact metal deposition steps are performed, thereby simultaneously filling the contact openings and the grooves with the contact (electrode) metal stack. A planarization step removes the upper portion of the metal stack, thereby leaving metal contacts in the contact openings, and metal electrodes in the grooves. The metal electrodes may form, for example, transistor gates, EEPROM control gates or capacitor plates. | 2009-09-24 |
20090239352 | METHOD FOR PRODUCING SILICON OXIDE FILM, CONTROL PROGRAM THEREOF, RECORDING MEDIUM AND PLASMA PROCESSING APPARATUS - A silicon oxide film formation method includes generating plasma inside a process chamber of a plasma processing apparatus, by use of a process gas having an oxygen ratio of 1% or more, and a process pressure of 133.3 Pa or less; and oxidizing by the plasma a silicon surface exposed inside a recessed part formed in a silicon layer on a target object, thereby forming a silicon oxide film. | 2009-09-24 |
20090239353 | Methods For Forming Multi-layer Three-Dimensional Structures - The embodiments of the present invention are directed to the formation of multi-layer three-dimensional structures by forming and attaching a plurality of individual layers where each of the layers comprises one or more materials forming a desired pattern. In one embodiment, a multi-layer three-dimensional structure is formed by forming a plurality of individual layers and attaching at least them together. In another embodiment, a multi-layer three-dimensional structure is formed by 1) forming one or more individual layers, 2) attaching the one or more formed layers onto a substrate, 3) if desired, forming new structures on the attached one or more layers. In still another embodiment, a multi-layer three-dimensional structure is formed by 1) attaching a layer of a material onto a substrate; 2) processing the attached layer to form a desired pattern; 3) attaching another layer of a material onto the previously formed layer; 4) processing the new attached layer to form a desired pattern, and 5) if desired, repeating the steps of 3) and 4) one or more times. | 2009-09-24 |
20090239354 | METHOD FOR MANUFACTURING SOI SUBSTRATE - Forming an insulating film on a surface of the single crystal semiconductor substrate, forming a fragile region in the single crystal semiconductor substrate by irradiating the single crystal semiconductor substrate with an ion beam through the insulating film, forming a bonding layer over the insulating film, bonding a supporting substrate to the single crystal semiconductor substrate by interposing the bonding layer between the supporting substrate and the single crystal semiconductor substrate, dividing the single crystal semiconductor substrate at the fragile region to separate the single crystal semiconductor substrate into a single crystal semiconductor layer attached to the supporting substrate, performing first dry etching treatment on a part of the fragile region remaining on the single crystal semiconductor layer, performing second dry etching treatment on a surface of the single crystal semiconductor layer subjected to the first etching treatment, and irradiating the single crystal semiconductor layer with laser light. | 2009-09-24 |
20090239355 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes spraying fluid onto a surface of a treatment target substrate including a semiconductor substrate; forming a protection layer on the surface of the treatment target substrate after spraying the fluid; selectively removing the protection layer and a part of the treatment target substrate by an energy beam; and conducting removal processing on an area of the treatment target substrate from which the protection layer and the part of the treatment target substrate are selectively removed. | 2009-09-24 |
20090239356 | DEVICE MANUFACTURING METHOD - A device manufacturing method includes a buffer layer forming step of forming a buffer layer on an underlying substrate, a mask pattern forming step of forming, on the buffer layer, a mask pattern which partially covers the buffer layer, a growth step of growing a group III nitride crystal from regions exposed by the mask pattern on the surface of the buffer layer, thereby forming a structure in which a plurality of crystal members are arranged with gaps therebetween so as to partially cover the buffer layer and the mask pattern, a channel forming step of forming a channel, to supply a second etchant for the buffer layer to the buffer layer, by selectively etching the mask pattern using a first etchant for the mask pattern, and a separation step of separating the plurality of crystal members from the underlying substrate and separating the plurality of crystal members from each other by supplying the second etchant to the buffer layer through the gaps and the channel and selectively etching the buffer layer. | 2009-09-24 |
20090239357 | AlGaN SUBSTRATE AND PRODUCTION METHOD THEREOF - A substrate is formed of Al | 2009-09-24 |
20090239358 | Memory Device Manufacturing Method - A method for making a memory device includes providing a dielectric material, having first and second upwardly and inwardly tapering surfaces and a surface segment connecting the first and second surfaces. First and second electrodes are formed over the first and second surfaces. A memory element is formed over the surface segment to electrically connect the first and second electrodes. | 2009-09-24 |
20090239359 | INTEGRATED PROCESS SYSTEM AND PROCESS SEQUENCE FOR PRODUCTION OF THIN FILM TRANSISTOR ARRAYS USING DOPED OR COMPOUNDED METAL OXIDE SEMICONDUCTOR - The present invention generally relates to an integrated processing system and process sequence that may be used for thin film transistor (TFT) fabrication. In fabricating TFTs, numerous processes may be performed on a substrate to ultimately produce the desired TFT. These processes may be performed in numerous processing chambers that may be coupled to a common transfer chamber. The arrangement of the processing chambers and the sequence in which the substrate may pass through the processing chambers may affect the device performance. By placing specific processing chambers around a common transfer chamber, multiple processes may be performed without undue exposure of the TFT to atmosphere. Alternatively, by passing the substrate sequentially through specific processing chambers, multiple processes may be performed without undue exposure of the TFT to atmosphere. | 2009-09-24 |
20090239360 | SEMICONDUCTOR DEVICE MANUFACTURING APPARATUS AND METHOD - A sealing member | 2009-09-24 |
20090239361 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - An aspect of the invention provides a method of manufacturing a method of manufacturing a semiconductor element comprises the steps of: growing epitaxially a semiconductor layer on top of a semiconductor substrate; forming a patterned portion of the grown semiconductor layer by forming a pattern by a patterning process on top of the grown semiconductor layer; removing a portion of the semiconductor layer other than the patterned portion by a first etching method with a first etchant; and immersing a resultant from the first etching method in a second etchant that etches only the semiconductor substrate by a second etching method thereby removing the substrate from the semiconductor layer. | 2009-09-24 |
20090239362 | APPARATUS FOR MANUFACTURING SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - An apparatus for manufacturing a semiconductor device, including in a reaction chamber: a rotor provided with a holding member holding a wafer thereon and a heater heating the wafer therein; a rotation drive mechanism; a gas supply mechanism; a gas exhaust mechanism; and a rectifying plate for rectifying the supplied process gas to supply the rectified gas, and including: an annular rectifying fin mounted on a lower portion of the plate, having a larger lower end inside diameter than an upper end inside diameter thereof and downward rectifying gas exhausted in an outer circumferential direction from above the wafer; and a distance control mechanism controlling a vertical distance between the plate and the wafer and a vertical distance between the fin and the rotor top face to be predetermined distances, respectively, thereby providing higher film formation efficiency. | 2009-09-24 |
20090239363 | METHODS FOR FORMING DOPED REGIONS IN SEMICONDUCTOR SUBSTRATES USING NON-CONTACT PRINTING PROCESSES AND DOPANT-COMPRISING INKS FOR FORMING SUCH DOPED REGIONS USING NON-CONTACT PRINTING PROCESSES - Methods for forming doped regions in semiconductor substrates using non-contact printing processes and dopant-comprising inks for forming such doped regions using non-contact printing processes are provided. In an exemplary embodiment, a method for forming doped regions in a semiconductor substrate is provided. The method comprises providing an ink comprising a conductivity-determining type dopant, applying the ink to the semiconductor substrate using a non-contact printing process, and subjecting the semiconductor substrate to a thermal treatment such that the conductivity-determining type dopant diffuses into the semiconductor substrate. | 2009-09-24 |
20090239364 | METHOD FOR FORMING INSULATING FILM AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - Disclosed is a method for forming a gate insulating film comprising an oxidation step wherein a silicon oxide film is formed by having an oxygen-containing plasma act on silicon in the surface of an object to be processed in a processing chamber of a plasma processing apparatus. The processing temperature in the oxidation step is more than 600° C. and not more than 1000° C., and the oxygen-containing plasma is formed by introducing an oxygen-containing processing gas containing at least a rare gas and an oxygen gas into the process chamber while introducing a high frequency wave or microwave into the process chamber through an antenna. | 2009-09-24 |
20090239365 | NONVOLATILE SEMICONDUCTOR MEMORY AND FABRICATION METHOD FOR THE SAME - A nonvolatile semiconductor memory that allows simultaneous implementation of high performance transistors in a low-voltage circuit region and transistors with high withstand voltages in a high-voltage circuit region. The nonvolatile semiconductor memory includes a cell array region that comprises aligned memory cell transistors, each including a control gate electrode, which includes a metal silicide film, an inter-gate insulating film below the control gate electrode, a floating gate electrode below the inter-gate insulating film, and a tunnel insulating film under the floating gate electrode; a high-voltage circuit region arranged in a periphery of the cell array region and including a high voltage transistor, which includes a first gate insulating film thicker than the tunnel insulating film; and a low-voltage circuit region that is arranged in a different position than the high-voltage circuit region arranged in the periphery of the cell array region and that includes a low-voltage transistor, which includes a gate electrode and a second gate insulating film thinner than the first gate insulating film below the gate electrode. | 2009-09-24 |
20090239366 | Method Of Forming A Transistor Gate Of A Recessed Access Device, Method Of Forming A Recessed Transistor Gate And A Non-Recessed Transistor Gate, And Method Of Fabricating An Integrated Circuit - Methods and structures are provided for full silicidation of recessed silicon. Silicon is provided within a trench. A mixture of metals is provided over the silicon in which one of the metals diffuses more readily in silicon than silicon does in the metal, and another of the metals diffuses less readily in silicon than silicon does in the metal. An exemplary mixture includes 80% nickel and 20% cobalt. The silicon within the trench is allowed to fully silicide without void formation, despite a relatively high aspect ratio for the trench. Among other devices, recessed access devices (RADs) can be formed by the method for memory arrays. | 2009-09-24 |
20090239367 | Nonvolatile memory device and method of fabricating the same - A method of fabricating a nonvolatile memory device includes forming a tunnel insulating layer on a semiconductor substrate, forming a charge storage layer on the tunnel insulating layer, forming a dielectric layer on the charge storage layer, the dielectric layer including a first aluminum oxide layer, a silicon oxide layer, and a second aluminum oxide layer sequentially stacked on the charge storage layer, and forming a gate electrode on the dielectric layer, the gate electrode directly contacting the second aluminum oxide layer of the dielectric layer. | 2009-09-24 |
20090239368 | Methods of Forming an Oxide Layer and Methods of Forming a Gate Using the Same - An oxide layer is selectively formed on a layer including silicon by a plasma process using hydrogen gas and a gas including oxygen. The hydrogen gas is controlled to have a flow rate less than about 50 percent of an overall flow rate by adding helium gas to the plasma process. | 2009-09-24 |
20090239369 | Method of Forming Electrical Interconnects within Insulating Layers that Form Consecutive Sidewalls - Methods of forming integrated circuit device having electrical interconnects include forming an electrically insulating layer on a substrate and forming a hard mask on the electrically insulating layer. The hard mask and the electrically insulating layer are selectively etched in sequence using a mask to define an opening therein. This opening, which may be a via hole, exposes inner sidewalls of the hard mask and the electrically insulating layer. The inner sidewall of the hard mask is then recessed relative to the inner sidewall of the electrically insulating layer and a sacrificial reaction layer is formed on the inner sidewall of the electrically insulating layer. This reaction layer operates to recess the inner sidewall of the electrically insulating layer. The reaction layer is then removed to define a wider opening having relatively uniform sidewalls. This wider opening is then filled with an electrical interconnect. | 2009-09-24 |
20090239370 | Methods Of Forming An Antifuse And A Conductive Interconnect, And Methods Of Forming DRAM Circuitry - A first via opening is formed to a first conductor and a second via opening is formed to a second conductor. The first and second via openings are formed through insulative material. Then, the first conductor is masked from being exposed through the first via opening and to leave the second conductor outwardly exposed through the second via opening. An antifuse dielectric is formed within the second via opening over the exposed second conductor while the first conductor is masked. Then, the first conductor is unmasked to expose it through the first via opening. Then, conductive material is deposited to within the first via opening in conductive connection with the first conductor to form a conductive interconnect within the first via opening to the first conductor and to within the second via opening over the antifuse dielectric to form an antifuse comprising the second conductor, the antifuse dielectric within the second via opening and the conductive material deposited to within the second via opening. Other aspects are contemplated. | 2009-09-24 |
20090239371 | Method For Applying Selectively A Layer To A Structured Substrate By The Usage Of A Temperature Gradient In The Substrate - A semiconductor wafer ( | 2009-09-24 |
20090239372 | Seed Layers for Electroplated Interconnects - One embodiment of the present invention is a method for depositing two or more seed layers for electroplating metallic interconnects over a substrate, the substrate having a patterned insulating layer which includes at least one opening and a field surrounding the at least one opening, the at least one opening having top corners, sidewalls, and bottom, the field and the at least one opening being ready for depositing one or more seed layers, and the method includes: (a) depositing a continuous seed layer over the sidewalls and bottom of the at least one opening using a first set of deposition parameters; and (b) depositing a second seed layer over the continuous seed layer using a second set of deposition parameters, wherein (i) the second set of deposition parameters includes at least one deposition parameter which is different from any of the parameters in the first set of deposition parameters, or the second set of deposition parameters includes at least one deposition parameter whose value is different in the two sets of deposition parameters, (ii) the continuous and second seed layers being sufficiently thick over the field to enable uniform electroplating across the substrate, and (iii) after depositing the seed layers, there is sufficient room for electroplating inside the at least one opening. | 2009-09-24 |
20090239373 | CHEMICAL MECHANICAL POLISHING METHOD AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A chemical mechanical polishing method comprises polishing an organic film using a slurry including polymer particles having a surface functional group and a water-soluble polymer. | 2009-09-24 |
20090239374 | Methods of Forming Metal Interconnect Structures on Semiconductor Substrates Using Oxygen-Removing Plasmas and Interconnect Structures Formed Thereby - Methods of forming devices include forming a first electrically insulating layer having a metal interconnection therein, on a substrate and then forming a first electrically insulating barrier layer on an upper surface of the metal interconnection and on the first electrically insulating layer. The first electrically insulating barrier layer is exposed to a plasma that penetrates the first electrically insulating barrier and removes oxygen from an upper surface of the metal interconnection. The barrier layer may have a thickness in a range from about 5 Å to about 50 Å and the plasma may be a hydrogen-containing plasma that converts oxygen on the upper surface of the metal interconnection to water. | 2009-09-24 |
20090239375 | Dual Damascene Process - Structures and methods of forming metallization layers on a semiconductor component are disclosed. The method includes etching a metal line trench using a metal line mask, and etching a via trench using a via mask after etching the metal line trench. The via trench is etched only in regions common to both the metal line mask and the via mask. | 2009-09-24 |
20090239376 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH INTERFACE BARRIER - A method for fabricating a semiconductor memory device includes forming a first layer, injecting a tungsten source gas and a silicon source gas simultaneously to form a tungsten silicide layer over the first layer, forming a tungsten nitride layer over the tungsten silicide layer without a post purge process of additionally supplying the silicon source gas, and forming a second layer over the tungsten nitride layer. | 2009-09-24 |
20090239377 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate, a copper-containing metal interconnect over the semiconductor substrate, and a copper-containing connection plug, and the metal interconnect includes metal elements other than copper, and a concentration of different metal elements in a connection portion between the metal interconnect and the connection plug is higher than a concentration of the different metal elements in a center portion of the metal interconnect, and higher than a concentration of different elements in upper face portion of the metal interconnect other than the connection portion. | 2009-09-24 |
20090239378 | METHODS FOR FORMING A TITANIUM NITRIDE LAYER - Methods for forming titanium nitride layers are provided herein. In some embodiments, a method of forming a titanium nitride layer on a substrate may include providing a substrate into a processing chamber having a target comprising titanium disposed therein; supplying a nitrogen-containing gas into the processing chamber; sputtering a titanium source material from the target in the presence of a plasma formed from the nitrogen-containing gas to deposit a titanium nitride layer on the substrate; and upon depositing the titanium nitride layer to a desired thickness, forming a magnetic field that biases ions in the processing chamber away from the substrate. | 2009-09-24 |
20090239379 | Methods of Planarization and Electro-Chemical Mechanical Polishing Processes - A method of removing a material from a surface includes providing a substrate comprising a material having a surface, contacting the surface with a polishing medium, applying a voltage to the substrate to remove material from the surface, and changing the voltage during the removing material from the surface. An electrochemical mechanical polishing method includes providing a substrate having a surface, applying a platen to the surface, applying a first voltage to the substrate, rotating the platen and surface relative to each other at a first rotational speed, increasing to a second voltage, and decreasing to a second rotational speed. | 2009-09-24 |
20090239380 | POLISHING LIQUID FOR METAL AND POLISHING METHOD USING THE SAME - A liquid for polishing a metal is provided that is used for chemically and mechanically polishing a conductor film including copper or a copper alloy in production of a semiconductor device, and a polishing method using the metal-polishing liquid is also provided. The liquid includes: (a) colloidal silica particles having an average primary particle size of from 10 nm to 25 nm and an average secondary particle size of from 50 nm to 70 nm; (b) a metal anticorrosive agent; (c) at least one compound selected from the group consisting of a surfactant and a water-soluble polymer compound; (d) an oxidizing agent; and (e) an organic acid. | 2009-09-24 |
20090239381 | POROUS FILM - A porous film which is formed using a block copolymer composed of a water-soluble polymer and a water-insoluble polymer, has nanometer-size pores, and in which a desired functional polymer is present on the pore inner walls is provided. The porous film includes a microphase-separated morphology including a continuous phase which is composed primarily of a water-insoluble polymer A, and a plurality of cylindrical microdomains which are composed primarily of a water-soluble polymer B incompatible with the water-insoluble polymer A, distributed within the continuous phase and oriented perpendicular to a surface of the film. The cylindrical microdomains contain therein pores having a cylindrical shape and an average diameter of between 1 and 200 nm. | 2009-09-24 |
20090239382 | METHOD FOR SELECTIVELY MODIFYING SPACING BETWEEN PITCH MULTIPLIED STRUCTURES - Methods for circuit material processing are provided. In at least one such method, a substrate is provided with a plurality of overlying spacers. The spacers have substantially straight inner sidewalls and curved outer sidewalls. An augmentation material is formed on the plurality of spacers such that the inner or the outer sidewalls of the spacers are selectively expanded. The augmentation material can bridge the upper portions of pairs of neighboring inner sidewalls to limit deposition between the inner sidewalls. The augmentation material is selectively etched to form a pattern of augmented spacers having a desired augmentation of the inner or outer sidewalls. The pattern of augmented spacers can then be transferred to the substrate through a series of selective etches such that features formed in the substrate achieve a desired pitch. | 2009-09-24 |
20090239383 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - Provided is a semiconductor device manufacturing method by which plasma processing can be performed uniformly on a substrate. A plasma processing apparatus according to one embodiment of the present invention includes an auxiliary electrode provided annularly along a periphery of the lower electrode on a lateral side of the lower electrode. When plasma processing is performed on a substrate S, a potential of the lower electrode is set lower than the potential of the upper electrode while a potential of the auxiliary electrode is set lower than a potential of the upper electrode. | 2009-09-24 |
20090239384 | SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING METHOD - A discharge hole of a lower nozzle is directed at an angle of 5 degrees to 40 degrees slanting inward with respect to a normal to the upper surface of a bottom plate. Thus, the flow pressure of a processing solution discharged through the discharge hole is not excessively reduced. Further, a circulation area of the processing solution does not expand widely in an inner bath. As a result, the processing solution in the inner bath is effectively displaced while the processing solution smoothly flows into gaps between substrates. | 2009-09-24 |
20090239385 | SUBSTRATE-SUPPORTING DEVICE HAVING CONTINUOUS CONCAVITY - A substrate-supporting device has a top surface for placing a substrate thereon composed of a plurality of surfaces separated from each other and defined by a continuous concavity being in gas communication with at least one through-hole passing through the substrate-supporting device in its thickness direction. The continuous concavity is adapted to allow gas to flow in the continuous concavity and through the through-hole under a substrate placed on the top surface. | 2009-09-24 |
20090239386 | PRODUCING METHOD OF SEMICONDUCTOR DEVICE AND SUBSTRATE PROCESSING APPARATUS - Disclosed is a producing method of a semiconductor device, comprising: loading a substrate into a reaction furnace; forming a film on the substrate in the reaction furnace; unloading the substrate from the reaction furnace after the film has been formed; and forcibly cooling an interior of the reaction furnace in a state where the substrate does not exist in the reaction furnace after the substrate has been unloaded. | 2009-09-24 |
20090239387 | PRODUCING METHOD OF SEMICONDUCTOR DEVICE AND SUBSTRATE PROCESSING APPARATUS - Disclosed is a producing method of a semiconductor device produced by transferring a plurality of substrates into a processing chamber, supplying oxygen-containing gas and hydrogen-containing gas into the processing chamber which is in a heated state to process the plurality of substrates by oxidation, and transferring the plurality of the oxidation-processed substrates out from the processing chamber, wherein the hydrogen-containing gas is supplied from a plurality of locations of a region corresponding to a substrate arrangement region in which the plurality of substrates are arranged in the processing chamber. | 2009-09-24 |
20090239388 | Semiconductor device and method for manufacturing the same - The present invention provides a semiconductor device having a coating film of a predetermined thickness provided along the circumference of a semiconductor light emitting element, and provide a method for easily manufacturing the semiconductor device. | 2009-09-24 |
20090239389 | Method of Forming a Layer of Material Using an Atomic Layer Deposition Process - Disclosed is a method of forming a layer of material using an atomic layer deposition (ALD) process in a process chamber of a process tool. In one illustrative embodiment, the method includes identifying a target characteristic for the layer of material, determining a precursor pulse time for introducing a precursor gas into the process chamber during the ALD process to produce the target characteristic in the layer of material, and performing the ALD process that comprises a plurality of steps wherein the precursor gas is introduced into the chamber for the determined precursor pulse time to thereby form the layer of material. | 2009-09-24 |
20090239390 | METHODS FOR PRODUCING LOW STRESS POROUS AND CDO LOW-K DIELECTRIC MATERIALS USING PRECURSORS WITH ORGANIC FUNCTIONAL GROUPS - Methods of preparing a carbon doped oxide (CDO) layers having a low dielectric constant are provided. The methods involve, for instance, providing a substrate to a deposition chamber and exposing it to one or multiple carbon-doped oxide precursors having molecules with at least one carbon-carbon triple bond, or carbon-carbon double bond, or a combination of these groups and depositing the carbon doped oxide dielectric layer under conditions in which the resulting dielectric layer has a dielectric constant of not greater than about 2.7. Methods of preparing a low stress porous low-k dielectric material on a substrate are provided. The methods involve the use of a structure former precursor and/or porogen precursor with one or more organic functional groups. In some cases, the structure former precursor has carbon-carbon double or triple bonds. In other cases, one or both of the structure former precursor and porogen precursor has one or more bulky organic groups. In other cases, the structure former precursor has carbon-carbon double or triple bonds and one or both of the structure former precursor and porogen precursor has one or more bulky organic groups. Once the precursor film is formed, the porogen is removed, leaving a porous low-k dielectric matrix with high mechanical strength. Different types of structure former precursors and porogen precursors are described. The resulting low stress low-k porous film may be used as a low-k dielectric film in integrated circuit manufacturing applications. | 2009-09-24 |
20090239391 | ROTARY CONTACT CONNECTOR FOR ELECTRICAL CABLES - A rotary contact-connection assembly for electric cables contains an electrically non-conducting support crossed by a borehole. A first bearing is configured in the borehole and a second bearing is configured radially outside the borehole around the support. The bearings are configured axially relative to each other and to the borehole. Both bearings are radially continuously electrically conducting. An electrically conducting plug is pluggable into an axial bearing passage aperture of the first bearing. A first electrical conductor of a first cable is fixable to an outer race of the first bearing. A second electrical conductor of the first cable is connectable to a hookup muff situated within the second bearing. A first electrical conductor of a second cable is passable through the borehole of the support and is connectable to the plug. A second electrical conductor of the second cable is connectable to an outer race of the second bearing. | 2009-09-24 |
20090239392 | Electronic Apparatus - According to one embodiment, An electronic apparatus includes: a receptacle that is not compatible with a plug having a support magnet around a plug terminal; a magnet that is disposed so that one pole of the magnet is opposed to a certain pole of the support magnet when the plug is inserted in the receptacle, the certain pole having the same polarity as the one pole. | 2009-09-24 |
20090239393 | Conductive Magnetic Coupling System - Technologies are described herein for a conductive magnetic coupling system. The system includes a signal supply component that provides electrical and/or data signals to a signal consumption component that utilizes the signal to provide an output. The two components are magnetically coupled together such that the magnetic coupling mechanisms not only provide the bonding mechanism for securing the components to one another, but also provide the electrical and communicative continuity that allows for the transfer of electrical and/or data signals between the two components. Aspects provide for the repositioning of the signal consumption component along any section of a signal supply component configured as a magnetic track system. Aspects further provide for a flexible, fluid impermeable signal supply component in which a signal consumption component is repositionable along its length. | 2009-09-24 |
20090239394 | ELECTRONIC COMPONENT CONNECTING APPARATUS, ELECTRONIC UNIT AND ELECTRONIC APPARATUS - An electronic component connecting apparatus includes an electronic component connecting section connected to an electronic component having terminals, a circuit board connecting section which is connected to a circuit board and which is electrically connects at least one of the terminals and the circuit board with each other, and a conduction section which electrically connects outside other than the circuit board and at least one of the terminals with each other. A current path between the electronic component and the external apparatus is shortened, and a heating value is suppressed. It is possible to prevent the apparatus from being damaged, and to increase the number of signal lines while preventing the circuit from becoming complicated. | 2009-09-24 |
20090239395 | ELECTRICAL CONNECTOR LEAD FRAME - An electrical interconnection system with high speed, high density electrical connectors. The connector is assembled from wafers containing columns of conductive elements, held in an insulative housing. The conductive elements may each have a plurality of beams of different lengths such that the mating contact surfaces of the first beam are offset, in a direction perpendicular with the columns, from the mating contact surfaces of the second beam. The mating contact surface of the shorter beam of each conductive element may be behind the mating contact of the longer beam such that the width of the conductive element is reduced while still protecting the shorter beam from stubbing upon connector mating. The multi-beam conductive elements may be used as signal or ground conductors. | 2009-09-24 |
20090239396 | Compression Connector - A compression connector, a terminal for a compression connector and an assembly including a compression connector and a PCB. The compression connector including a housing; one or more terminals disposed in the housing; each terminal including a substantially U-shaped contact portion protruding above a surface level of the housing with a close end of the substantially U-shaped contact portion facing away from the housing, the substantially U shaped contact portion including a first leg connected to a main body of said each terminal and a second leg having a free end, the free end being disposed substantially at or below the surface level of the housing; wherein the first and second legs are angled with respect to each other in a quiescent state and such that the first and second legs are substantially parallel to each other in a contact state where the substantially U-shaped contact portion resiliently engages a contact through-hole of a PCB. | 2009-09-24 |
20090239397 | Socket contact - A low-profile socket contact is provided that is mountable on a print substrate and has a high contact pressure. The socket contact includes a base portion provided on a print substrate, and a contact connecting portion connecting to the tab-shaped contact provided on a central portion of the base portion. The base portion has an opening in which the tab-shaped contact passes through, and a plurality of lead portions solderable to the print substrate. The contact connecting portion has a pair of first bending fragments, a pair of first inverted arms, a pair of second bending fragments, and a pair of second inverted arms. A contact point in contact with the tab-shaped contact is provided on each front ends of the pair of first inverted arms, and a guiding face in which the tab-shaped contact slides is provided on the pair of second inverted arms. | 2009-09-24 |
20090239398 | PRESS FIT (COMPLIANT) TERMINAL AND OTHER CONNECTORS WITH TIN-SILVER COMPOUND - A tin-silver press-fit interconnect which includes a press-fit terminal having a coating or finish of a tin-silver compound for use with a terminal receiving device. The tin-silver compound serves to prevent the formation of tin whiskers which appear most frequently in pure tin coated electrical components under mechanical stress and which make the electronic device susceptible to short circuits. The tin-silver compound may include between 85 and 99.5% weight of tin and between 0.5 and 15% weight of silver and is applied at a thickness range between 0.4 and 5 microns using a technique such as electroplating, hot dip or immersion. | 2009-09-24 |
20090239399 | ADAPTER DEVICE FOR A LOW VOLTAGE SWITCHING DEVICE - The present invention relates to an adapter device for connection of a low voltage switching device to a distribution bus bar system. The adapter device comprises a body provided with a front wall, which can be connected to the switching device, and a back wall, opposite the front wall. The device comprises first electrical terminals susceptible to electrically contact one of the distribution bus bars and second electrical terminals. The device also comprises first electrical connections electrically connected to first electrical terminals and which can be coupled with corresponding third electrical connections of the switching device. The adapter device is also provided with second electrical connection means connected to corresponding second electrical terminals and which can be coupled with corresponding fourth electrical connections of the switching device. The adapter device also comprises a plurality of coupling terminals, at least partly emerging from the back wall of the body, to removably connect the adapter device to the distribution bus bar system. In particular, each of the first electrical terminals electrically contacts one of the distribution bars following the action of one of said coupling terminals. | 2009-09-24 |
20090239400 | SAFETY RECEPTACLE WITH TAMPER RESISTANT SHUTTER - The disclosed embodiments are directed to a apparatus that includes a frame and a shutter device located within the frame, the shutter device being configured to simultaneously block openings for at least a hot connector element and a neutral connector element of an electrical receptacle when forces are unequally applied to the shutter device through openings corresponding to the at least hot and neutral connector elements. | 2009-09-24 |
20090239401 | Conductor Track Carrier - A conductor track carrier is intended to contact-connect electrical components. The carrier has a flexible base film, a conductor track on the base film, and a contact-connection eye arranged in a contact-connection section of the conductor track carrier and electrically coupled to the conductor track. The conductor track carrier has a respective recess on two opposite sides of the contact-connection section, and web elements formed between the recesses in such a manner that the contact-connection section is pivotably mounted. | 2009-09-24 |
20090239402 | MODULAR ELECTRICAL SYSTEM INCLUDING BACK-TO-BACK RECEPTACLE CONFIGURATIONS AND CAPABLE OF PROVIDING FOUR WIRE CIRCUITRY - A modular electrical system ( | 2009-09-24 |
20090239403 | Modular electrical system utilizing four wire circuitry - A four wire system ( | 2009-09-24 |
20090239404 | Fixture - The present invention relates to a fixture capable of fixing a USB connector on a housing. The fixture comprises a housing connection surface, a top surface, a first lateral surface, and a second lateral surface, wherein the housing connection surface is capable of being fixed on the housing; the top surface is connected to the housing connection surface where both surfaces are substantially perpendicular to each other, and the top surface comprises a first constraining unit capable of contacting a protection part of the USB connector to constrain movement of the USB connector along a first direction; the first lateral surface is connected to the top surface to constrain movement of the USB connector; and the second lateral surface is connected to the top surface to constrain movement of the USB connector. | 2009-09-24 |
20090239405 | RELEASABLY ENGAGING HIGH DEFINITION MULTIMEDIA INTERFACE PLUG - A releasably engaging high definition multimedia plug comprises a plug body and an actuator operable with the plug body to move a locking tab of the plug and facilitate releasable engagement of the plug with a standard high definition multimedia receptacle. | 2009-09-24 |
20090239406 | RELEASABLY ENGAGING HIGH DEFINITION MULTIMEDIA INTERFACE PLUG - A releasably engaging high definition multimedia plug comprises a plug body and an actuator operable with the plug body to move a locking tab of the plug and facilitate releasable engagement of the plug with a standard high definition multimedia receptacle. A corresponding method of releasably securing a high definition multimedia interface plug into standard high definition multimedia interface receptacle is also provided. | 2009-09-24 |
20090239407 | Lamp Socket and Light Appliance Thereof - Disclosed are a lamp socket and a light appliance having the same. The lamp socket includes connection terminal bodies including connection terminals provided in sides of the lamp socket to contact the connection pins of the lamp and connection terminal recesses into which the connection terminals are inserted, and connection caps to slide to press and fix the connection pins when the connection pins contact the connection terminals. Pressure against the lamp is eliminated when the lamp is installed or separated so that the lamp is prevented from being broken. The installation of the lamp can be improved. | 2009-09-24 |
20090239408 | ELECTRICAL CONNECTION DEVICE AND CONNECTOR - The disclosure relates to a connection device, in particular a heavy-duty plug-type connection, with a first connector and a second connector, which each have a contact-making element in order to produce an electrical connection in the connected state of the connectors; the connectors bearing against one another at a connection region in the connected state; at least one of the connectors comprising a coolant line with one or more access points for the supply and discharge, respectively, of a coolant; the coolant line being provided at the contact-making element in order to dissipate heat from a contact point between the contact-making elements; all of the access points of the coolant line being arranged outside of the connection region. | 2009-09-24 |
20090239409 | INSULATION DISPLACEMENT CONNECTOR (IDC) - An electrical insulation displacement connector includes a body having at least one channel with an open top side configured for receipt of an insulated conductive core wire therein. A contact element is fixed in the body with a first insulation displacement end defined by opposed blades oriented across the channel, and a second end extending from a bottom surface of the body and configured for electrical contact with a PCB. The body includes retaining structure extending into the channel at a location relative to a depth of the blades within the channel such that the insulation portion of a wire inserted into the channel and pressed down into the first end of the contact element is pushed below the retaining structure, thereby preventing the wire from being inadvertently pulled out from the first end of the contact. | 2009-09-24 |
20090239410 | CONNECTION MODULE - A connection module for housing a contact element used to electrically connect wires within the module, the module being formed of first and second parts arranged to interfit so as to define a first set of openings, each being shaped to receive an end section of one of said wires for electric connection to the contact element, which pass into the module from a first end face toward an opposite second end face, the first part having first and second slots in opposed side walls, and the second part having a first protrusion which is received in a first one of the slots to at least partially fill an open end of said first one of said slots to thereby define an aperture to allow a test probe to access the contact element. | 2009-09-24 |
20090239411 | CRIMP CONTACT FOR AN ALUMINUM STRANDED WIRE, AND CABLE END STRUCTURE OF AN ALUMINUM STRANDED WIRE HAVING THE CRIMP CONTACT CONNECTED THERETO - The present invention is directed to a crimp contact for an aluminum stranded wire having a serration provided in an inner face of a crimping portion of the crimp contact, wherein a ratio d/e is 0.33 or more, in which d represents a depth of a groove constituting the serration and e represents a diameter of an aluminum wire constituting the aluminum stranded wire. The number of grooves in the crimp contact is 3 or more. The present invention is also directed to a cable end structure of an aluminum stranded wire, wherein a ratio between a sectional area of the aluminum stranded wire after crimping and a sectional area thereof before crimping is from 0.7 to 0.95. | 2009-09-24 |
20090239412 | TERMINAL COVER - A terminal cover has first and second pieces ( | 2009-09-24 |
20090239413 | REINFORCED PATCH PANEL FRAME WITH REAR MOUNTED MODULES - There is provided a patch panel for mounting thereto a plurality of keystone style modular jacks each comprising a forward portion having a plug receiving opening moulded therein. The patch panel comprises a flat frame comprising a first plurality of like rectangular openings, each one of the first plurality of openings adapted to receive one of the plurality of jacks; and a flat panel arranged behind the frame substantially co-planar therewith and comprising a second plurality of like rectangular openings, each one of the second plurality of openings aligned with and of dimensions greater than a respective one of the first plurality of openings. The panel is spaced from the frame by a distance for accommodating the forward portion of the plurality of jacks when the plurality of jacks are received in aligned pairs of the first and the second plurality of openings. Also, when one of the plurality of jacks is positioned within one of the second plurality of openings, the plug receiving opening is accessible via one of the first plurality of openings. | 2009-09-24 |
20090239414 | CONNECTOR FOR SUBSTRATE - A connector ( | 2009-09-24 |
20090239415 | ATTACHMENT DEVICE FOR A CONNECTOR - An attachment device ( | 2009-09-24 |
20090239416 | Apparatus for Mechanical and Electrical Connection - An apparatus is proposed for detachable mechanical and electrical and/or optical connection of a recording appliance to an imaging apparatus. The apparatus comprises a mounting board and an insert board, which is pushed into the mounting board. In this case, the mounting board has guides on opposite sides, which hold the insert board in an interlocking manner in the pushed-in state. Electrical and/or optical contacts on the mounting board and on the insert board are connected to one another when the insert board has been pushed essentially completely into the guides on the mounting board. In one embodiment, a locking lever is provided, which converts a rotary movement of the locking lever to a linear movement of the insert board in the insertion direction. A latching position is provided in an end position of the locking lever. | 2009-09-24 |
20090239417 | CONNECTOR ARRANGEMENT OF MULTIPLE INDEPENDENTLY OPERABLE ELECTRICAL CONNECTORS - A connector arrangement including a connector body; a first electrical connector coupled with the connector body; a jacket surrounding the first electrical connector and coupled with the connector body; and a second electrical connector arranged around the first electrical connector is provided; in which the first and second electrical connectors are independently operable, and the second electrical connector includes connecting elements at least partially arranged within a body of the jacket. | 2009-09-24 |
20090239418 | SCREEN | 2009-09-24 |
20090239419 | Connector header with wire wrap pins - A connector header ( | 2009-09-24 |
20090239420 | CONNECTOR FOR CONNECTING ELECTRONIC COMPONENT - Provided is a connector for connecting an electronic component, which reduces noise radiation when the electronic component is connected to a substrate through the connector and driven. In a connector ( | 2009-09-24 |
20090239421 | ELECTRICAL CONNECTOR - An electrical connector consists of a plug connector and a receptacle connector to be fitted. An insulator is supported only by plug contacts each having an elastic portion between second and third fixed portions so as to be floating in a housing. The elastic portion is so positioned that its upper curved portion is at the same height as a second contact portion and its lower curved portion is at the same height as the lower end of the insulator. The distal end of a first contact portion of a receptacle contact is folded back toward a first connection portion to provide a third contact to contact the elastic portion so that the first contact portion and the third contact portion of the receptacle contact and the second contact portion and the elastic portion of the plug contact are caused to contact each other in line contacts at two locations. The electrical connector thus constructed is superior in resistance to vibration, and achieves space-saving and a reduced overall height less than 5 mm and further the floating of the insulator. | 2009-09-24 |
20090239422 | ELECTRICAL CONNECTOR - An electrical connector consists of a plug connector and a receptacle connector to be fitted. An insulator is supported only by plug contacts each provided between second and third fixed portions with an elastic portion having at least one snaked portion so as to be floating in a housing. The shape of the second contact portion of each of the plug contacts is substantially in the form of a plate-shaped piece so that the second contact portion of the plug contact and the first contact portion of a receptacle contact are caused to contact each other in line contact at one location, and the elastic portion is arranged within a range from a position below the second contact portion to a position below the insulator. The electrical connector thus constructed is superior in resistance to vibration, and achieves space-saving and floating of the insulator. | 2009-09-24 |
20090239423 | DEVICES FOR CONNECTING CONDUCTORS OF TWISTED PAIR CABLE TO INSULATION DISPLACEMENT CONTACTS - A termination device to facilitate interconnection of a twisted pair communications cable to IDCs includes: a housing having an aperture and a pair of first and second IDCs extending within the aperture; a twisted pair communications cable having a twisted pair of first and second conductors; and a termination device. The termination device comprises: a body having an outer surface; a channel in the outer surface of the body, the channel being sized and configured to receive a twist of the first and second conductors and to maintain the twist in position; and IDC guide structure configured to guide the first IDC into engagement with the first conductor at a first engagement location and the second IDC into engagement with the second conductor at a second engagement location, the first and second engagement locations being positioned within the channel and within the twist of the first and second conductors. A splitting structure is positioned in the channel that separates at least a portion of the first and second conductors as they reside in the channel. | 2009-09-24 |