38th week of 2013 patent applcation highlights part 76 |
Patent application number | Title | Published |
20130246793 | METHOD AND APPARATUS FOR ENCRYPTION AND PASS-THROUGH HANDLING OF CONFIDENTIAL INFORMATION IN SOFTWARE APPLICATIONS - Methods and apparatus for securely transmitting sensitive information to a remote device at the request of an application program are provided. The application program generates a request to a secure channel provider to make a transmission to a remote device. A first message is passed from the from the application program to the secure channel provider containing insertion point codes indicating locations within the first message where the sensitive information should be inserted. Sensitive information is obtained from a source outside of the application program and the sensitive information is inserted into the first message at the locations in the first message indicated by the insertion point codes to form a second message containing the sensitive information. The second message is encrypted and this encrypted message is transmitted to the remote device. The sensitive information is unaccessed by the application program during the execution of the method. | 2013-09-19 |
20130246794 | SYSTEMS, DEVICES, AND METHODS FOR SECURELY TRANSMITTING A SECURITY PARAMETER TO A COMPUTING DEVICE - Embodiments of the systems, devices, and methods described herein generally facilitate the secure transmittal of security parameters. In accordance with at least one embodiment, a representation of first data comprising a password is generated at the first computing device as an audio signal. The audio signal is transmitted from the first computing device to the second computing device. The password is determined from the audio signal at the second computing device. A key exchange is performed between the first computing device and the second computing device wherein a key is derived at each of the first and second computing devices. In at least one embodiment, one or more security parameters (e.g. one or more public keys) are exchanged between the first and second computing devices, and techniques for securing the exchange of security parameters or authenticating exchanged security parameters are generally disclosed herein. | 2013-09-19 |
20130246795 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR ALLOWING CONTENT TRANSFER BASED ON A SIGNATURE AND A CONTEXT THEREOF - A system, method, and computer program product are provided for conditionally allowing a transfer of content, based on a signature and a context. In operation, a signature for content is identified. In addition, a context of an attempt to transfer the content is identified. Furthermore, the transfer is conditionally allowed, based on the signature and the context. | 2013-09-19 |
20130246796 | SYSTEM AND METHOD FOR SECURING DATABASE ACTIVITY - A method is provided in one example embodiment that includes detecting database activity associated with a statement having a signature, validating the signature; and evaluating the statement as a signed statement if the signature is valid. In more particular embodiments, the signature may include a unique script identifier and a hash function of a shared key. In yet other embodiments, validating the signature may include checking a session variable and comparing the statement to a list of signed statements. | 2013-09-19 |
20130246797 | APPARATUS AND METHOD FOR ELECTRONIC SIGNATURE VERIFICATION - An apparatus for electronic signature verification, including a grouping unit to group, into at least one group, a plurality of kernels included in an application to which electronic signature verification is to be performed, and an electronic signature verification unit to perform electronic signature verification with respect to the at least one group. | 2013-09-19 |
20130246798 | METHOD FOR SECURING MESSAGES - There is provided a method for secure communications. The method comprises receiving a transmission comprising a signature of a broadcast message at a communication device, and verifying the signature using a certificate. | 2013-09-19 |
20130246799 | Providing Differential Access to a Digital Document - In a method for providing differential access to a digital document among workflow participants, in which at least one of the workflow participants is outside of a common secure environment ( | 2013-09-19 |
20130246800 | Enhancing Security of Sensor Data for a System Via an Embedded Controller - System and method for securing sensor data in a computer system that includes a host processor and memory that stores an operating system, and an embedded controller coupled to the host processor. The embedded processor receives sensor data for a user from at least one sensor, and encrypts and/or digitally signs the sensor data, thereby generating protected sensor data, or performs pattern recognition on the sensor data, thereby generating user identification data. The embedded processor then sends the protected sensor data or the user identification data to the operating system or another process coupled to the computer system. The protected sensor data or the user identification data are used for secure transmission of the sensor data. | 2013-09-19 |
20130246801 | DATA TRANSMITTING DEVICE, DATA RECEIVING DEVICE, AND COMPUTER-READABLE STORAGE MEDIUM - According to one embodiment, the data transmitting device includes a storing unit, an authenticator generating unit, and a communication unit. The storing unit stores accuracy information based on an accuracy of synchronization between a first clock and a second clock. The first clock indicates a current time of the data transmitting device. The second clock indicates a current time of other device to be a destination of a data packet. The authenticator generating unit calculates a first time by adding a predetermined time to the current time of the data transmitting device, calculates a second time by adjusting the first time using the accuracy information, and generates an authenticator using the second time, the data packet, and a predetermined secret key. The communication unit transmits, to the other device, the data packet with the authenticator at a third time obtained by adding the second time to a predetermined time. | 2013-09-19 |
20130246802 | Collusion-Resistant Outsourcing of Private Set Intersection - Implementations of the present disclosure include methods, systems, and computer-readable storage mediums for receiving an encrypted first data set from a first entity, storing the encrypted first data set in computer-readable memory, receiving an encrypted second data set from a second entity, storing the encrypted second data set in computer-readable memory, receiving public encryption information associated with the encrypted first data set and the encrypted second data set, storing the public encryption information in computer-readable memory, and processing, using the one or more processors, the encrypted first data set and the encrypted second data set to provide the set intersection, wherein an advantage of a first adversary in guessing data elements of the encrypted first data set is negligible in a security parameter. | 2013-09-19 |
20130246803 | ENABLING DELIVERY OF PROTECTED CONTENT USING UNPROTECTED DELIVERY SERVICES - Disclosed are an apparatus and method configured to perform media file encryption. One example method may include retrieving a media file stored in a memory during a play time operation, executing the media file and receiving additional portions of the media file during the play time operation. The method may also include processing the media file and the additional portions of the media file to generate an output media and displaying the output media on a display of a user device. | 2013-09-19 |
20130246804 | DELIVERY POINT VALIDATION SYSTEM - A computer-implemented method represents a list of informational items using a bit array. The method converts an informational item to a cryptographic value using a cryptographic algorithm and extracts a plurality of n-bit samples from the cryptographic value. The n-bit samples includes at least a first field and a second field. The first field identifies a group of bits of the bit array and the second field identifies one or more individual bits within the group of bits. The individual bits are set to a pre-determined value according to the first field identifying the group of bits and the second field identifying the individual bits within the group of bits. | 2013-09-19 |
20130246805 | SECURE INTERFACE FOR VERSATILE KEY DERIVATION FUNCTION SUPPORT - Improper re-use of a static Diffie-Hellman (DH) private key may leak information about the key. The leakage is prevented by a key derivation function (KDF), but standards do not agree on key derivation functions. The module for performing a DH private key operation must somehow support multiple different KDF standards. The present invention provides an intermediate approach that neither attempts to implement all possible KDF operations, nor provide unprotected access to the raw DH private key operation. Instead, the module performs parts of the KDF operation, as indicated by the application using the module. This saves the module from implementing the entire KDF for each KDF needed. Instead, the module implements only re-usable parts that are common to most KDFs. Furthermore, when new KDFs are required, the module may be able to support them if they built on the parts that the module has implemented. | 2013-09-19 |
20130246806 | INFORMATION PROCESSING APPARATUS, FILE ENCRYPTION DETERMINATION METHOD AND AUTHORITY DETERMINATION METHOD - An information processing apparatus includes an application operation file information holding unit | 2013-09-19 |
20130246807 | SYSTEMS AND METHODS FOR SECURING DATA IN MOTION - The systems and methods of the present invention provide a solution that makes data provably secure and accessible—addressing data security at the bit level—thereby eliminating the need for multiple perimeter hardware and software technologies. Data security is incorporated or weaved directly into the data at the bit level. The systems and methods of the present invention enable enterprise communities of interest to leverage a common enterprise infrastructure. Because security is already woven into the data, this common infrastructure can be used without compromising data security and access control. In some applications, data is authenticated, encrypted, and parsed or split into multiple shares prior to being sent to multiple locations, e.g., a private or public cloud. The data is hidden while in transit to the storage location, and is inaccessible to users who do not have the correct credentials for access. | 2013-09-19 |
20130246808 | SYSTEMS AND METHODS FOR SECURING DATA IN MOTION - The systems and methods of the present invention provide a solution that makes data provably secure and accessible—addressing data security at the bit level—thereby eliminating the need for multiple perimeter hardware and software technologies. Data security is incorporated or weaved directly into the data at the bit level. The systems and methods of the present invention enable enterprise communities of interest to leverage a common enterprise infrastructure. Because security is already woven into the data, this common infrastructure can be used without compromising data security and access control. In some applications, data is authenticated, encrypted, and parsed or split into multiple shares prior to being sent to multiple locations, e.g., a private or public cloud. The data is hidden while in transit to the storage location, and is inaccessible to users who do not have the correct credentials for access. | 2013-09-19 |
20130246809 | DIFFERENTIAL UNCLONEABLE VARIABILITY-BASED CRYPTOGRAPHY - Differential uncloneable variability-based cryptography techniques are provided. The differential cryptography includes a hardware based public physically uncloneable function (PPUF) to perform the cryptography. The PPUF includes a first physically uncloneable function (PUF) and a second physically uncloneable function. An arbiter determines the output of the circuit using the outputs of the first and second PUFs. Cryptography can be performed by simulating the PPUF with selected input. The output of the simulation, along with timing information about a set of inputs from where the corresponding input is randomly selected for simulation, is used by the communicating party that has the integrated circuit with the PPUF to search for an input that produces the output. The input can be configured to be the secret key or a part of the secret key. | 2013-09-19 |
20130246810 | SYSTEMS AND METHODS FOR SECURING DATA IN MOTION - The systems and methods of the present invention provide a solution that makes data provably secure and accessible—addressing data security at the bit level—thereby eliminating the need for multiple perimeter hardware and software technologies. Data security is incorporated or weaved directly into the data at the bit level. The systems and methods of the present invention enable enterprise communities of interest to leverage a common enterprise infrastructure. Because security is already woven into the data, this common infrastructure can be used without compromising data security and access control. In some applications, data is authenticated, encrypted, and parsed or split into multiple shares prior to being sent to multiple locations, e.g., a private or public cloud. The data is hidden while in transit to the storage location, and is inaccessible to users who do not have the correct credentials for access. | 2013-09-19 |
20130246811 | STORAGE METHOD, SYSTEM AND APPARATUS - The present invention discloses a storage method, system and apparatus. The method comprises: encrypting data with a storage key to obtain encrypted data; encrypting the storage key with two different encryption methods to generate a personal key and a data key, respectively, wherein the personal key can be decrypted with a key from the user who owns the data to obtain the storage key, and the data key can be decrypted with the unencrypted data to obtain the storage key; saving the encrypted data, personal key and data key in a server. The technical scheme of the present invention can prevent saving duplicate files while ensuring that the unencrypted data cannot be accessed by any other users and storage service providers. | 2013-09-19 |
20130246812 | SECURE STORAGE OF SECRET DATA IN A DISPERSED STORAGE NETWORK - A method for secure storage of secret data begins with an originating device transforming the secret data to produce a plurality of secret data shares and encrypting the plurality of secret data shares using unique encryption values of trusted agent modules of a dispersed storage network (DSN) to produce a plurality of encrypted secret data shares for storage in storage nodes of the DSN. Retrieval of the secret data begins with the originating device sending a secret data retrieval request to the trusted agent modules and recovering, by the trusted agent modules, the plurality of encrypted secret data shares from the storage nodes. The method continues with the trusted agent modules decrypting the plurality of encrypted secret data shares using a decryption function corresponding to the unique encryption values and sending the plurality of secret data shares to the originating device. | 2013-09-19 |
20130246813 | DATABASE ENCRYPTION SYSTEM, METHOD, AND PROGRAM - A user apparatus connected to database apparatus via network comprises: unit that manages key information in order to encrypt and decrypt; storage unit that stores security configuration information of data and/or metadata; application response unit that determines whether or not encryption is necessary for database operation command, and if encryption is necessary, selects encryption algorithm corresponding to data and/or metadata, performs encryption, and transmits result to database control unit to cause database control unit to execute database operation, if encryption is not necessary, transmits database operation command to database control unit to cause database control unit to execute database operation, and receives processing result transmitted by database control unit, and if decryption or conversion of data and/or metadata of processing result is necessary, performs necessary decryption or conversion, and returns response to database operation command; and security configuration unit that configures security information of data stored in database. | 2013-09-19 |
20130246814 | UNINTERRUPTIBLE POWER SUPPLY AND METHOD FOR CONTROLLING POWER DISTRIBUTION UNIT BY THE SAME - A method for controlling power distribution unit (PDU) by an uninterruptible power supply (UPS) has steps of allowing logging in the UPS through a network, providing a web-based user interface and allowing adding an identification of at least one PDU to use sockets on the added PDU to simulate additional sockets on the UPS, performing a handshaking task with the added PDU, receiving information from the added PDU during performing of the handshaking task, displaying the received information of the added PDU on the web-based user interface and allowing either operating the UPS or controlling the added PDU. The method allows the UPS to be capable of communicating with all connected PDUs so the user can merely login the UPS to control and manage all PDUs connected to the UPS. | 2013-09-19 |
20130246815 | BACKUP POWER SUPPLY DEVICE, POWER SUPPLY SYSTEM, COMPUTER SYSTEM, METHOD FOR CONTROLLING POWER SUPPLY OF COMPUTER SYSTEM, AND RECORDING MEDIUM - A backup power supply device that is used as a backup for a normal power supply device that includes a first converter configured to convert a first alternating-current voltage into a first direct-current voltage and a second converter configured to convert the first direct-current voltage into a second direct-current voltage includes a first detector that is coupled to an output of the first converter and outputs a first detection signal when the first direct-current voltage is lower than a first predetermined value; a third converter that converts a second alternating-current voltage into a third direct-current voltage; a battery that is charged by the third direct-current voltage; and a first switch that connects an output of the battery or an output of the third converter to an input of the second converter based on the output of the first detection signal. | 2013-09-19 |
20130246816 | POWER DISTRIBUTION UNIT AND METHOD USING A SINGLE INTERNET PROTOCOL ADDRESS TO CONTROL MULTIPLE POWER DISTRIBUTION UNITS - A power distribution unit (PDU) performs a method using a single IP address to control multiple PDUs and has a controller and at least one network port connected to the controller. The controller provides an html-based user interface for users to set up virtual outlets therethrough. When multiple foregoing PDUs are connected through a network, one of the PDUs can be logged in with an internet protocol (IP) address, and the outlets of other PDUs are virtualized as added outlets of the login PDU. Outlet information associated with the original and added outlets of the login PDU can be simultaneously displayed on the user interface of the login PDU. Accordingly, users can employ a single IP address to control the outlets of all the PDUs. | 2013-09-19 |
20130246817 | BATTERY REPLACING SYSTEM AND METHOD THEREOF - A battery replacing system for replacing a battery of an electronic device, includes a power storage unit and a switch circuit. The power storage unit can be charged by the battery when the battery is mounted to the electronic device. The switch circuit alternatively connects one of the power storage unit or the battery to an operating system of the electronic device. The switch connects the power storage unit to the operating system to have the power storage unit provide power to the operating system when the battery is detached from the electronic device, and connect the battery to the operating system to have the battery provide power to the operating system when the battery is mounted to the electronic device. | 2013-09-19 |
20130246818 | CACHE DEVICE, CACHE SYSTEM AND CONTROL METHOD - According to an embodiment, a cache device includes a cache memory, an access controller, and a power controller. The cache memory includes a plurality of memory areas associated with a plurality of ways, respectively. The access controller controls access to the memory areas. The power controller controls power supplied to each of the memory areas individually such that power supplied to a memory area that has not been accessed for a predetermined time is standby power that is lower than operating power that enables the memory area to operate. The power controller controls power supplied to a memory area such that standby power for a memory area that is highly likely to be accessed has a value closer to the operating power than a value of standby power for a memory area that is less likely to be accessed. | 2013-09-19 |
20130246819 | FOOTER-LESS NP DOMINO LOGIC CIRCUIT AND RELATED APPARATUS - A domino logic circuit includes a pre-charge circuit pre-charging a first dynamic node in response to a clock signal, a first logic network determining a logic level of the first dynamic node in response to first data signals, an inverter receiving the clock signal, a discharge circuit discharging a second dynamic node in response to an output signal of the inverter, and a second logic network determining a logic level of the second dynamic node in response to at least one second data signal and an output signal of the first dynamic node. | 2013-09-19 |
20130246820 | METHOD FOR ADAPTIVE PERFORMANCE OPTIMIZATION OF THE SOC - An apparatus and method for dynamically adjusting power limits for processing nodes and other components, such as peripheral interfaces, is disclosed. The apparatus includes multiple processing nodes and other components, and further includes a power management unit configured to set a first frequency limit for at least one of the processing nodes responsive to receiving an indication of a first detected temperature greater than a first temperature threshold. Initial power limits are set below guard-band power limits for components that do not have reliable reporting of power consumption or for cost or power saving reasons. The amount of throttling of processing nodes is used to adjust the power limits for the processing nodes and these components. | 2013-09-19 |
20130246821 | Serial Interface Transmitting method and Peripheral Device Chip - The present invention discloses a serial interface transmitting method utilized in a serial interface for connecting between a master controller and a peripheral device. The serial interface transmitting method comprises receiving a saving power signal from the master controller, a peripheral clock source and a serial interface clock source for generating a clock source selection result, switching an operational mode of the peripheral device according to the clock source selection result, and transmitting a datum to a peripheral-device register or a serial interface register according to the saving power signal and the operational mode. | 2013-09-19 |
20130246822 | ELECTRONIC DEVICE WITH STANDBY MODE - An electronic device with standby state includes a MCU, a voltage conversion unit, a screen lock circuit, and a power-saving trigger circuit. The voltage conversion unit is connected to the MCU and is used to convert a power supply voltage to a suitable voltage to power the MCU. The screen lock circuit includes a switch, therein, the screen lock circuit is connected to the MCU and is used to lock or unlock the electronic device in response to an operation on the switch when the electronic device is in a work state. The power-saving trigger circuit is connected to the MCU, the voltage conversion unit, and the screen lock circuit, and is used to disable or enable the voltage conversion unit in response to the operation on the switch when the electronic device is in the standby state. | 2013-09-19 |
20130246823 | IMAGE PROCESSING APPARATUS AND METHOD OF IMAGE PROCESSING - An image processing apparatus included in a system including another image processing apparatus, and configured to transition to a first and a second electric power saving mode when functioning as a main apparatus and a slave apparatus, respectively, in the system where the second electric power saving mode is lower than that of the first electric power saving mode, includes a function determining unit which determines whether the image processing apparatus is to function as the main apparatus or the slave apparatus based on a status of the other image processing apparatus which is obtained when the image processing apparatus is performing a job; and an instruction sending unit which sends an instruction to have the other image processing apparatus function as the slave apparatus or the main apparatus when the image processing apparatus is determined to function as the main apparatus or the slave apparatus, respectively. | 2013-09-19 |
20130246824 | Instruction For Enabling A Processor Wait State - In one embodiment, the present invention includes a processor having a core with decode logic to decode an instruction prescribing an identification of a location to be monitored and a timer value, and a timer coupled to the decode logic to perform a count with respect to the timer value. The processor may further include a power management unit coupled to the core to determine a type of a low power state based at least in part on the timer value and cause the processor to enter the low power state responsive to the determination. Other embodiments are described and claimed. | 2013-09-19 |
20130246825 | METHOD AND SYSTEM FOR DYNAMICALLY POWER SCALING A CACHE MEMORY OF A MULTI-CORE PROCESSING SYSTEM - A system and method of power scaling cache memory ( | 2013-09-19 |
20130246826 | METHOD AND SYSTEM FOR CONTROLLING POWER - A method and system for controlling power is provided. The system is configured to selectively control a plurality of power control domains. The system may be configured to process audio data in at least one of the domains. The system may be configured to output audio data, while one or more of the power control domains is suspended. | 2013-09-19 |
20130246827 | Method and system for predicting the power consumption of a mobile terminal - A method of and device for predicting the power consumption of a battery-powered mobile terminal ( | 2013-09-19 |
20130246828 | AT LEAST ONE MESSAGE TO ANNOUNCE ENTRY INTO RELATIVELY LOWER POWER STATE - An embodiment may include circuitry that may be capable of performing operations that may include generating, at least in part, at least one message to announce that at least one network node (1) is requesting, at least in part, that one or more transmissions to the at least one network node be postponed, at least in part, and/or (2) is entering, at least in part after issuance of the at least one message, a relatively lower power state relative to a relatively higher power state. Additionally or alternatively, the operations may include, in response, at least in part, to the at least one message, postponing, at least in part, at least one intermediate node at least one transmission (received by the at least one intermediate node) to the at least one network node. Many alternatives, variations, and/or modifications are possible without departing from this embodiment. | 2013-09-19 |
20130246829 | GENERATING A POWER MODEL FOR AN ELECTRONIC DEVICE - A method of fabricating a semiconductor device generates a power model for an electronic device. The method includes receiving a data file including design information corresponding to the semiconductor device. The method further includes fabricating the semiconductor device according to the design information, where the semiconductor device includes a processor configured to identify a subset of operating parameters of the electronic device that contribute most to power consumption of the electronic device by reducing training data. The processor is further configured to generate a power model for the electronic device based on the reduced training data. The power model is operable to predict, responsive to a set of operating parameter values corresponding to operation of the electronic device, a power consumption value corresponding to the electronic device. | 2013-09-19 |
20130246830 | SYNCHRONIZING A DEVICE THAT HAS BEEN POWER CYCLED TO AN ALREADY OPERATIONAL SYSTEM - A method comprises a system comprising a host device coupled to a first remote device actively operating according to a state diagram that the host device and all remote devices follow during operation of the system. The method further comprises powering up a second remote device while the host device and first remote device are actively operating according to the state diagram. The second remote device waits for a synchronization point sequence. Upon detecting the synchronization point sequence, the second remote device implements a predetermined feature set and synchronizes itself to the state diagram at a common point as the host device and first remote device. | 2013-09-19 |
20130246831 | SELECTION DEVICE, SELECTION METHOD AND INFORMATION PROCESSING DEVICE - A selection device includes an interface connected to at least a clock signal line and a chip select signal line among output lines of a first device, a plurality of interfaces respectively connected to chip select signal lines of a plurality of second devices each operated in synchronization with a clock signal of the first device, a measuring unit that measures a clock frequency of the first device, and a selecting unit that, according to the clock frequency of the first device measured by the measuring unit, selects a chip select signal line connected to one of the plurality of second devices, and outputs a chip select signal from the first device to the selected chip select signal line. | 2013-09-19 |
20130246832 | INFORMATION PROCESSING DEVICE, COMPUTER-READABLE RECORDING MEDIUM HAVING STORED THEREIN PROGRAM FOR SETTING TIME OF INFORMATION PROCESSING DEVICE, MONITOR, AND METHOD FOR SETTING TIME OF INFORMATION PROCESSING DEVICE - An information processing device includes a monitoring object device, a monitor that monitors the monitoring object device, a controller including a first time source, a base monitor including a second time source, and a console. The controller sets times of the first time source and the monitoring object device on the basis of an instruction of time setting from the console and then transmits notification of time setting completion to the console. When an exclusive relationship that the base monitor is not allowed to set a time in the second time source under a state where the controller is running is established, the console stops the controller, causes the base monitor to set a time in the second time source after the reception of the notification of time setting completion. After time setting in the second time source is completed, the console restarts the controller and the base monitor. | 2013-09-19 |
20130246833 | CLOCK GENERATOR AND INFORMATION PROCESSING APPARATUS - A clock generator includes a first clock generating unit configured to generate a first clock signal based on a system clock signal, a second clock generating unit configured to generate a second clock signal with a frequency higher than the frequency of the first clock signal based on the system clock signal, a counting unit configured to count the number of clock pulses of the second clock signal in a cycle of the first clock signal, and an adjusting unit configured to adjust a falling edge or a rising edge of the second clock signal to synchronize with a falling edge or a rising edge of the first clock signal based on an assert signal that is output when the number of clock pulses of the second clock signal counted by the counting unit reaches a predetermined value. | 2013-09-19 |
20130246834 | PSEUDO-STATIC DOMINO LOGIC CIRCUIT AND APPARATUSES INCLUDING SAME - A domino logic circuit includes a plurality of domino logic stages connected in series between a latch and a flip-flop and a clock signal generator generating a clock signal having a first duty cycle and a flip-flop clock signal having a second duty cycle. The latch and the domino logic stages respectively operate in response to a domino clock signals derived from the first clock signal. The flip-flop operates in response to the flip-flop clock signal. | 2013-09-19 |
20130246835 | SLEEP CLOCK SLEW COMPENSATION - A method for compensating for sleep clock slew is disclosed. The method may conserve battery power. The method includes operating in a discontinuous receive mode. A measured sleep clock slew is determined. Discontinuous receive mode parameters are adjusted based on the measured sleep clock slew. Discontinuous receive mode wake-up procedures are performed. The discontinuous receive mode parameters may include a sleep time and a search time. Other aspects, embodiments, and features are also claimed and described. | 2013-09-19 |
20130246836 | COMMAND DECODING METHOD AND CIRCUIT OF THE SAME - A decoding circuit includes a pre-trigger signal generating unit, a comparing unit, and a starting signal generating unit. The pre-trigger signal generating unit receives the former encoded data and generates a pre-trigger signal when the former encoded data of the received command matches the corresponding former encoded data of a predetermined command. The comparing unit generates a match signal when the latter encoded data of the received command is the same with the latter encoded data of the predetermined command. The starting signal generating unit outputs a starting signal according to the pre-trigger signal and the match signal. The starting signal starts a corresponding operation of the predetermined command. | 2013-09-19 |
20130246837 | SYSTEM AND METHOD FOR MITIGATING REPEATED CRASHES OF AN APPLICATION RESULTING FROM SUPPLEMENTAL CODE - Provided is a method for mitigating the effects of an application which crashes as the result of supplemental code (e.g., plug-in), particularly a plug-in from a source other than the source of the operating system of the device or the source of the application that crashes. The method includes executing the application. As the application is running, it may be monitored to determine if normal execution of instructions ceases. When that occurs, the system will make a determination if code from a supplemental code module was the cause of the crash, and will make an evaluation if that supplemental code module is from a source other than the source(s) of the operating system and application in question. In some implementations, remedial steps may be provided, such as providing information on subsequent executions of the application. | 2013-09-19 |
20130246838 | DISCOVERING BOOT ORDER SEQUENCE OF SERVERS BELONGING TO AN APPLICATION - A survey tool for use in a Recover to Cloud (R2C) replication service environment that determines configuration information automatically (such as through SNMP messaging or custom APIs) and stores it in a survey database. A Virtual Data Center (VDC) representation is then instantiated from the survey database, with the VDC being a virtual replica of the production environment including dormant Virtual Machine (VM) definition files, applications, storage requirements, VLANs firewalls, and the like. The survey tool determines the order in which the replicas are brought on line to ensure orderly recovery, determining the order in which each machine makes requests for connections to other machines. | 2013-09-19 |
20130246839 | DYNAMIC HIGHER-LEVEL REDUNDANCY MODE MANAGEMENT WITH INDEPENDENT SILICON ELEMENTS - A Solid-State Disk (SSD) controller enables dynamic higher-level redundancy mode management with independent silicon elements to provide graceful degradation as non-volatile (e.g. flash) memory elements fail during operation of an SSD implemented by the controller. Higher-level error correction provides correction of lower-level uncorrectable errors. If a failure of one of the non-volatile memory elements is detected, then the higher-level error correction is dynamically transitioned from operating in a current mode to operating in a new mode. The transition includes one or more of reducing free space available on the SSD, rearranging data storage of the SSD, recovering/storing failed user data (if possible), and determining/storing revised higher-level error correction information. Operation then continues in the new mode. If another failure of the non-volatile memory elements is detected, then another transition is made to another new mode. | 2013-09-19 |
20130246840 | NODE APPARATUS OF MULTI-NODE STORAGE SYSTEM AND METHOD FOR MANAGING PROCESSING SPEED - A storage management apparatus manages a plurality of storage apparatuses in a storage system that disperses and stores data that is made redundant so as to have a predetermined redundancy level. The storage management apparatus includes: a patrol process unit that performs, at a patrol speed, a patrol process of confirming that the plurality of storage apparatuses are being operated normally; a relocating process unit that performs, at a relocating process speed, a relocating process of moving the data between the plurality of storage apparatuses; a recovery process unit that performs, at a recovery process speed, a recovery process of recovering the redundancy level of the data when a fault occurs in the plurality of storage apparatuses; and a processing speed control unit that controls the recovery process speed or a sum of the patrol process speed and the relocating process speed to have a predetermined value. | 2013-09-19 |
20130246841 | METHOD, APPARATUS, AND SYSTEM FOR A REDUNDANT AND FAULT TOLERANT SOLID STATE DISK - A solid state drive includes a first solid state disc controller (SSDC), a second SSDC and a flash array. The flash array includes a first flash port and a second flash port. The first SSDC is configured to connect to the flash array through the first flash port and the second flash array is configured to connect to the flash array through the second flash port. | 2013-09-19 |
20130246842 | INFORMATION PROCESSING APPARATUS, PROGRAM, AND DATA ALLOCATION METHOD - In an information processing apparatus, a first selecting unit selects, as a source stripe, a stripe in which at least one of blocks stores a data item and another one of the blocks stores an error-correcting code for the data item, among a plurality of stripes each including a group of storage areas of a plurality of blocks that are located one on each of a plurality of storage devices. A second selecting unit selects, as a destination stripe, a stripe in which at least one of blocks stores a data item and in which the number of available blocks is equal to or greater than the number of blocks of the source stripe which store data items, among the stripes other than the source stripe. A moving unit moves the data item stored in the source stripe to the available block of the destination stripe. | 2013-09-19 |
20130246843 | METHOD AND SYSTEM FOR PROVIDING HIGH AVAILABILITY TO DISTRIBUTED COMPUTER APPLICATIONS - Method, system, apparatus and/or computer program for achieving transparent integration of high-availability services for distributed application programs. Loss-less migration of sub-programs from their respective primary nodes to backup nodes is performed transparently to a client which is connected to the primary node. Migration is performed by high-availability services which are configured for injecting registration codes, registering distributed applications, detecting execution failures, executing from backup nodes in response to failure, and other services. High-availability application services can be utilized by distributed applications having any desired number of sub-programs without the need of modifying or recompiling the application program and without the need of a custom loader. In one example embodiment, a transport driver is responsible for receiving messages, halting and flushing of messages, and for issuing messages directing sub-programs to continue after checkpointing. | 2013-09-19 |
20130246844 | CONTROLLER AND CONTROL METHOD FOR A CONTROLLER - A controller and a control method for a controller can simplify application development and can improve the performance of device control processes. When a request is received from an application | 2013-09-19 |
20130246845 | SYSTEMS AND METHODS FOR SUPPORTING TRANSACTION RECOVERY BASED ON A STRICT ORDERING OF TWO-PHASE COMMIT CALLS - Systems and methods are provided for supporting transaction recovery based on a strict ordering of two-phase commit calls. At least one resource manager in a mid-tier transactional environment can be designated as the “determiner resource,” in order to support eliminating mid-tier transaction logs (TLOG) in processing a two-phase transaction. A transaction manager can prepare all other resource managers in the mid-tier transactional system before the determiner resource. Furthermore, the transaction manager can rely on the list of outstanding transactions to be committed that is provided by the determiner resource for recovering the transaction. The transaction manager can commit an in-doubt transaction returned from a resource manager that matches the list of in-doubt transactions returned from the determiner resource. Otherwise, the transaction manager can roll back the in-doubt transaction. | 2013-09-19 |
20130246846 | IP MULTIMEDIA SUBSYSTEM AND METHOD FOR MBMS FILE REPAIR USING HTTP SERVERS - Disclosed in some examples is a method of media repair in an IMS based network, the method includes communicating with an IMS network using SIP to setup a download session with a BMSC over a MBMS bearer; responsive to determining that one or more received encoding symbols of media downloaded using the established MBMS bearer cannot be decoded: requesting a file repair procedure from the IMS network component using a SIP re-invite request, the SIP re-invite request including an address of an HTTP repair server indicated by the IMS network component during the MBMS bearer setup; responsive to receiving a SIP acknowledgement indicating that the request was successful, requesting an HTTP connection with the HTTP server to re-download the one or more encoding symbols of the media that could not be decoded; and receiving the one or more encoding symbols from the HTTP server. | 2013-09-19 |
20130246847 | METHOD OF DETECTING ERROR IN WRITE DATA AND DATA PROCESSING SYSTEM TO PERFORM THE METHOD - A method of detecting an error in write data includes generating first error detection data based on first write data to be written to a buffer memory, generating second error detection data based on second write data related with the first write data, comparing the first error detection data with the second error detection data, and generating an error detection signal according to a comparison result. | 2013-09-19 |
20130246848 | METHOD AND SYSTEM PROVIDNG A SELF-TEST ON ONE OR MORE SENSORS COUPLED TO A DEVICE - A method and system for providing a self-test configuration in a device is disclosed. The method and system comprise providing a self-test mechanism in a kernel space of a memory and enabling a hook in a user space of the memory, wherein the hook is in communication with the self-test mechanism. The method and system also include running the self-test driver and utilizing the results. | 2013-09-19 |
20130246849 | Distributed Testing Of A Software Platform - A system includes a platform server with a software platform on which platform targeting applications (PTAs) execute. An update server may be coupled to the platform server to provide an update to this software platform. Responsive to notification to independent software vendors of the PTAs, results of regression testing performed on at least some of the PTAs can be received in a test server, which may enable commitment of the update based on at least some of the results. | 2013-09-19 |
20130246850 | SYSTEM FOR REMOTE INSTALLED SOUND COMPLIANCE TESTING - A network communication system includes a central control system that may transmit a request packet over a network to an apparatus that is configured to operate in an alarm system. The alarm system may be configured in accordance with a standard or protocol. The request packet may include instructions that instruct the apparatus to perform one or more tests that determine whether the apparatus is compliant with the standard or protocol. The apparatus may be configured to receive the packet from over the network and perform the tests in accordance with the instructions. The apparatus may report test results of the tests to the central control system by sending a reply packet that includes the test results over the network to the central control system. | 2013-09-19 |
20130246851 | INFORMATION PROCESSING APPARATUS, A SENDER APPARATUS AND A CONTROL METHOD OF THE INFORMATION PROCESSING APPARATUS - An information processing apparatus may include a sender apparatus and a receiver apparatus connected to the sender apparatus. The sender apparatus includes a processor configured to output a plurality of output signals, a counter configured to send a report indicating that a predetermined time has been counted, and a pseudofault generator configured to change a value of any one of the output signals output by the processor based on the report sent from the counter. The receiver apparatus includes an error detector configured to detect an error with respect to the changed value of the one of the output signals output by the processor. | 2013-09-19 |
20130246852 | TEST METHOD, TEST APPARATUS, AND RECORDING MEDIUM - A test method which tests a processing device includes: obtaining a maximum number of processing units with which the processing device as a test target can simultaneously parallel process a plurality of threads; specifying a number of threads, causing the processing device as the test target to parallel process the threads, and obtaining a processing time corresponding to the number of threads; and outputting information indicating that the processing device as the test target is normal when the number of threads for which the processing time is more than or equal to a threshold matches the maximum number of processing units which can simultaneously parallel process, or outputting information indicating that the processing device as the test target is abnormal when the number of threads does not match. | 2013-09-19 |
20130246853 | SYSTEM AND METHODS FOR AUTOMATED TESTING OF FUNCTIONALLY COMPLEX SYSTEMS - A system for automated testing of functionally complex systems, comprising a test manager module operating on a server computer, a test data storage subsystem coupled to the test manager module and adapted to store at least test results, a test execution module operating on a server computer, and a test analysis module operating on a server computer and adapted to receive test data from the test data storage subsystem. The test manager module causes tests to be executed by the test execution engine, and on detection of an anomalous test result, the test manager module at least causes additional testing to be performed and causes the test analysis module to analyze the results of at least some of the additional testing in order to isolate at least one component exhibiting anomalous behavior. | 2013-09-19 |
20130246854 | WIRELESS COMMUNICATION CHECK SYSTEM AND METHOD - A wireless communication check method using a monitoring device. The monitoring device sends commands to a wireless check device embeded in into a check system, and invokes a wireless check device to check firmware embeded in into components of the check system. The monitoring device receives a check report from the wireless check device, and analyzes the check report to determine if the firmware embeded in into the components of the check system includes error. The monitoring device sends check data to the check system and notifies the wireless check device to update the firmware having error using the check data. | 2013-09-19 |
20130246855 | Error Location Specification Method, Error Location Specification Apparatus and Computer-Readable Recording Medium in Which Error Location Specification Program is Recorded - A method for specifying an error location by an information processing apparatus that includes a plurality of devices connected to each other through a transmission path includes deciding, when an interrupt is generated, whether the interrupt is a periodic interrupt or an error interrupt, and storing, where the generated interrupt is a periodic interrupt, history information of errors of each of the devices, but analyzing, where the generated interrupt is an error interrupt, the stored history information of errors of the devices to specify a suspect location of the error. | 2013-09-19 |
20130246856 | VERIFICATION SUPPORTING APPARATUS AND VERIFICATION SUPPORTING METHOD OF RECONFIGURABLE PROCESSOR - A verification supporting apparatus and a verification supporting method of a reconfigurable processor is provided. The verification supporting apparatus includes an invalid operation determiner configured to detect an invalid operation from a result of scheduling on a source code, and a masking hint generator configured to generate a masking hint for the detected invalid operation. | 2013-09-19 |
20130246857 | CONTROLLER, STORAGE APPARATUS, METHOD OF TESTING STORAGE APPARATUS, AND TANGIBLE COMPUTER-READABLE STORAGE MEDIUM - A controller includes an address generator that sets a plurality of different paths, each connecting an information processing apparatus connected to a storage apparatus via a network, first and second storage mediums, and the controller, and generates a second address that is different from a first address used for a communication with the information processing apparatus via the network; an access monitor that determines that no access has been issued for a certain time duration from the information processing apparatus to the first or second storage medium; an access issuing unit that issues a test access to the first and second storage mediums on one of the paths, using the second address; and an access decoder that converts the test access to an access including the first address, receives a result of the access including the first address from the first or second storage mediums, and checks for an error. | 2013-09-19 |
20130246858 | METHODS AND APPARATUS FOR MONITORING OPERATION OF A SYSTEM ASSET - A device for use in monitoring operation of a plurality of system assets includes a storage device configured to store a model of a plurality of system assets and a processor coupled to the storage device. The processor is configured to receive data representative of a status of the system assets, and display, in a first display state, a plurality of asset images representative of the system assets using the model. The processor is also configured to display, in a second display state, a first asset image of the asset images within the display upon a determination that the system asset represented by first asset image is in an alarm state, and display, in a third display state, the remaining asset images within the display upon a determination that the system assets represented by the remaining asset images are not in an alarm state. | 2013-09-19 |
20130246859 | INTEGRATED CIRCUIT AND METHOD FOR MONITORING BUS STATUS IN INTEGRATED CIRCUIT - Embodiments of the present invention disclose an integrated circuit and a method for monitoring a bus status in the integrated circuit. Multiple status detectors and a top layer monitor are disposed in the integrated circuit. Each status detector in the multiple status detectors is used to read status data on a branch bus that is coupled to each status detector in the multiple status detectors, and then the top layer monitor collects the status data from each status detector, and outputs the status data through an interface. | 2013-09-19 |
20130246860 | SYSTEM MONITORING - A method of monitoring a system is disclosed, in particular to identify the cause of conditions outside expected operating conditions. The output of one or more sensors associated with a system is monitored and data from the one or more sensors is arranged as a plurality of modes with each mode being defined by a different condition in which the system may operate. Faulty conditions are identified by monitored data being outside one of the plurality of modes. The use of a plurality of modes enables operation of the system to be defined and tracked more precisely and false alarms may be reduced. At least one of the modes may be established to indicate a particular failure of the system. This failure mode may have a likely cause of the failure associated with it such that diagnosis and repair may be facilitated quickly and easily. | 2013-09-19 |
20130246861 | METHOD, APPARATUS AND COMPUTER PROGRAM PRODUCT FOR USER INPUT INTERPRETATION AND INPUT ERROR MITIGATION - Provided herein are a method, apparatus and computer program product for interpreting user input and mitigating erroneous inputs on a device. In particular, methods may include receiving an indication of a first touch event, determining, by a touch mediation function, if the first touch event is an erroneous touch event, causing the first touch event to be sent to an application in response to the touch mediation function determining that the touch event is not erroneous; and causing the first touch event to not be sent to the application in response to the touch mediation function determining that the first touch event is erroneous. The first touch event may occur proximate a first capture area for the user interface and the method may further include causing the first capture area for the user interface to be adjusted in response to the first touch event. | 2013-09-19 |
20130246862 | INFORMATION PROCESSING APPARATUS AND MAINTENANCE METHOD OF AN INFORMATION PROCESSING APPARATUS - An information processing apparatus includes: processing units to perform information processing, the processing units being capable of continuing the information processing even if a processing unit in the processing units stops its operation; and a control unit to perform a potential failure detection process of restarting the processing units one by one and outputting information requesting replacement or repair of a processing unit that is not restarted up. | 2013-09-19 |
20130246863 | CHANGE MESSAGE BROADCAST ERROR DETECTION - A hardware device detects change messages broadcast within a system. The system includes the hardware device, one or more controller devices, one or more expander devices, and one or more target devices interconnected among one another. The hardware device determines whether the change messages were broadcast within the system every first period of time or less for at least a second period of time, the first period of time less than the second period of time. In response to determining that the change messages were broadcast within the system every first period of time or less for at least the second period of time, the hardware devices signals that an error has been detected. | 2013-09-19 |
20130246864 | METHOD FOR NATIVE PROGRAM TO INHERIT SAME TRANSACTION CONTEXT WHEN INVOKED BY PRIMARY PROGRAM RUNNING IN SEPARATE ENVIRONMENT - Native applications inherit transaction contexts when invoked by primary applications running in separate hosting environments, by: receiving, by an interface of a native application server in a first hosting environment, a unique transaction context identifier for an invocation of the native application at the native application server by the primary application at a primary application server in a second hosting environment; receiving a SQL statement from the native application by the interface of the native application server; sending the SQL statement and the unique transaction context identifier to the primary application server for execution by the interface of the native application server; receiving a result of the execution of the SQL statement and the unique transaction context identifier from the primary application server by the interface of the native application server; and sending the result to the native application by the interface of the native application server. | 2013-09-19 |
20130246865 | IDENTIFYING A STORAGE ERROR OF A DATA SLICE - A method begins by a processing module obtaining common storage name information regarding data that is stored in storage units of a distributed storage network (DSN) as a set of data slices. Each data slice of the set of data slices has a unique storage name, where each of the unique storage names for the set of data slices has common naming information regarding the data. The method continues where the processing module interprets the common storage name information to determine whether a difference exists between the common naming information of a data slice of the set of data slices and the common naming information of other data slices of the set of data slices. When the difference exists, the method continues where the processing module indicates a potential storage error of the data slice and implements a storage error process regarding the potential storage error of the data slice. | 2013-09-19 |
20130246866 | SYSTEM AND METHOD FOR VERIFYING THE INTEGRITY OF A SAFETY-CRITICAL VEHICLE CONTROL SYSTEM - A control system according to the principles of the present disclosure includes an operation control module, a fault detection module, a remedial action module, and a reset module. The operation control module controls operation of a vehicle system. The fault detection module detects a fault in the operation control module when the operation control module fails an integrity test. The remedial action module takes a remedial action when the fault is detected. The reset module resets the operation control module when the fault is detected and the remedial action is not taken. | 2013-09-19 |
20130246867 | TEST CIRCUIT, MEMORY SYSTEM, AND TEST METHOD OF MEMORY SYSTEM - This technology relates to smoothly performing a test on a memory circuit having a high memory capacity while reducing the size of a test circuit. A test circuit according to the present invention includes a test execution unit configured to perform a test on a target test memory circuit, an internal storage unit configured to store data for the test execution unit, and a conversion setting unit configured to set a part of or the entire storage space of the target test memory circuit as an external storage unit for storing the data for the test execution unit. | 2013-09-19 |
20130246868 | ARITHMETIC PROCESSING APPARATUS AND METHOD OF CONTROLLING ARITHMETIC PROCESSING APPARATUS - An arithmetic processing apparatus includes a cache memory to store data in cache lines, an error detecting unit to detect an error occurring in one of the cache lines, a way comparing unit to compare way identification information of a cache line to be accessed with error-way identification information, a word comparing unit to compare a word address of the cache line to be accessed with an error word address, a column comparing unit to compare a column address of the cache line to be accessed with an error column address, and a control unit to disable all cache lines sharing a failed word line in response to results of comparisons made by the way comparing unit, the word comparing unit, and the column comparing unit when the error detecting unit detects a second error occurring in any one of the cache lines after the occurrence of the first error. | 2013-09-19 |
20130246869 | ENHANCED DIAGNOSIS WITH LIMITED FAILURE CYCLES - Chain or logic diagnosis resolution can be enhanced in the presence of limited failure cycles using embodiments of the various methods, systems, and apparatus described herein. For example, pattern sets can be ordered according to a diagnosis coverage figure, which can be used to measure chain or logic diagnosability of the pattern set. Per-pin based diagnosis techniques can also be used to analyze limited failure data. | 2013-09-19 |
20130246870 | DOUBLE DATA RATE TEST INTERFACE AND ARCHITECTURE - A device test architecture and a reduced device test interface are provided to enable efficient testing of embedded cores and other circuits within devices. The reduced device test interface is achieved using a double data rate (DDR) signaling technique between the tester and the device. The DDR test interface allows the tester to interface to test circuits within the device, such as IEEE 1500 and/or IEEE 1149.1 test circuits, to provide high test data bandwidth to the test circuits using a minimum of test interface signals. The test architecture includes compare circuits that allow for comparison of test response data to be performed within the device. The test architecture further includes a memory for storing the results of the test response comparisons. The test architecture includes a programmable test controller to allow for various test control operations by simply inputting an instruction to the programmable test controller from the external tester. Additional features and embodiments of the device test architecture and reduced test interface are also disclosed. | 2013-09-19 |
20130246871 | ADAPTING SCAN-BIST ARCHITECTURES FOR LOW POWER OPERATION - A Scan-BIST architecture is adapted into a low power Scan-BIST architecture. A generator | 2013-09-19 |
20130246872 | LOCK STATE MACHINE OPERATIONS UPON STP DATA CAPTURES AND SHIFTS - A process of selecting alternative test circuitry within an integrated circuit enables a test access port. Scan test instruction data is loaded into an instruction register of a test access port TAP, the instruction data including information for selecting the alternative test circuitry. An Update-IR instruction update operation is performed at the end of the loading to output scan test control signals from the instruction register. A lockout signal is changed to an active state to disable the test access port and enable scan test circuits. | 2013-09-19 |
20130246873 | SELECTIVELY ACCESSING TEST ACCESS PORTS IN A MULTIPLE TEST ACCESS PORT ENVIRONMENT - A TAP linking module ( | 2013-09-19 |
20130246874 | POSITION INDEPENDENT TESTING OF CIRCUITS - Scan distributor, collector, and controller circuitry connect to the functional inputs and outputs of core circuitry on integrated circuits to provide testing through those functional inputs and outputs. Multiplexer and demultiplexer circuits select between the scan circuitry and the functional inputs and outputs. The core circuitry can also be provided with built-in scan distributor, collector, and controller circuitry to avoid having to add it external of the core circuitry. With appropriately placed built-in scan distributor and collector circuits, connecting together the functional inputs and outputs of the core circuitry also connects together the scan distributor and collector circuitry in each core. This can provide a hierarchy of scan circuitry and reduce the need for separate test interconnects and multiplexers. | 2013-09-19 |
20130246875 | Multi-Modal Signal Processing with Linearization - A system for signal processing includes: a plurality of signal processing units associated with corresponding channels; a feedback channel for receiving a selected feedback signal through a selector of an output associated with each of the signal processing units; and a correlator connected to the feedback channel and having a receiving unit to receive the selected feedback signal, an error calculating unit to calculate an error based at least in part on the selected feedback signal, and a correction calculation unit to generate a correcting information based at least in part on the error. In some cases, the association between the signal processing units and the signal channels is configured based on a mode. | 2013-09-19 |
20130246876 | Method and Arrangement for Retransmission Control - A method and arrangement for retransmission control. A method in a sending system entity for controlling retransmissions of data to a sending system entity is provided. Initial data encoded with a first forward error correction code is sent | 2013-09-19 |
20130246877 | Systems and Methods for Compression Driven Variable Rate Decoding in a Data Processing System - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for variable rate encoding and/or decoding in a data processing system. | 2013-09-19 |
20130246878 | STATISTICAL DISTRIBUTION BASED VARIABLE-BIT ERROR CORRECTION CODING - A method may be performed at a data storage device that includes a memory and a controller. The method includes providing user data to a variable-bit error correction coding (ECC) encoder. The ECC encoder generates a first set of parity bits. A first number of parity bits in the first set of parity bits is determined based on stored counts of read errors. The method also includes storing the user data and the first set of parity bits to a memory of the data storage device. | 2013-09-19 |
20130246879 | ITERATIVE DECODER SYSTEMS AND METHODS - Systems and methods are provided for improved designs and performance for iterative decoder systems. In some embodiments, the iterative decoder may be decoupled from FIR samples through an FIR RAM, thus resulting in a less complex design and shorter processing times. In some embodiments, an intermediate memory may be used when passing information between the SOVA and LDPC of the iterative decoder. In some embodiments, the SOVA-required information may be continuously serialized from information received from the LDPC during each LDPC iteration. In some embodiments, the 1/(1+D | 2013-09-19 |
20130246880 | LDPC SELECTIVE DECODING SCHEDULING USING A COST FUNCTION - A cost function is obtained. For each of a plurality of groups of nodes, the cost function is evaluated by obtaining, for a given group of nodes, one or more reliability values associated with the given group of nodes; the one or more reliability values include sign and magnitude. For a given group of nodes, a reliability value with a smallest magnitude is selected where the evaluated cost function for the given group of nodes is set to the smallest magnitude. One of the plurality of groups of nodes is selected based at least in part on the evaluated cost functions. Error correction decoding related processing is performed on the selected group of nodes. | 2013-09-19 |
20130246881 | Apparatus and Method for Reconstructing a Bit Sequence with Preliminary Correction - A method for reconstructing a physically uncloneable function (PUF) A for use in an electronic device is provided. The method includes generating a potentially erroneous PUF A | 2013-09-19 |
20130246882 | DECODING APPARATUS AND DECODING METHOD FOR DECODING LDPC-ENCODED DATA - A min-sum processing unit executes a min-sum algorithm on input data so as to alternately execute check node processing in which an extrinsic value ratio is updated based on prior value ratios and variable node processing in which a prior value ratio is updated based on the extrinsic value ratios. Here, an initializing unit calculates the total product of the signs of the prior value ratios associated with the row to be processed. A deriving unit derives the sign for an extrinsic value ratio associated with the row to be processed, based on the sign of the prior value ratio that is unused in the updating of the extrinsic value ratio and the total product of the signs thus calculated. An updating unit updates an extrinsic value ratio associated with the row to be processed, using the sign thus derived. | 2013-09-19 |
20130246883 | DATA PROCESSING DEVICE AND DATA PROCESSING METHOD - A data processing device and a data processing method that can readily process control data having its PAPR improved. In a transmission device, a padder pads control data necessary for demodulation with zeros as dummy data, and a scrambler scrambles the padded control data (post-padding control data). A replacement unit replaces scrambled dummy data in the scrambled post-padding control data with the dummy data, and a BCH encoder and an LDPC encoder perform BCH encoding and LDPC encoding as error correction encoding on the replacement data obtained through the replacement. A shortening unit performs shortening by deleting the dummy data contained in the LDPC code and puncturing the parity bits of the LDPC code. The device can be applied in cases where control data is subjected to error correction encoding and is then transmitted, for example. | 2013-09-19 |
20130246884 | METHOD AND APPARATUS FOR WIRELESS DATA TRANSMISSION SUBJECT TO PERIODIC SIGNAL BLOCKAGES - A system and method for data transmissions in a wireless communications system, which accommodates for a periodic blockage of the transmission signal, is provided. A data stream is segmented into packets of a predetermined fixed-size for a burst-mode transmission over a channel of the communications system, wherein the transmission is subject to a periodic blockage. A forward error correction outer code is then applied to the packets of the data stream for recovery of packets subjected to the periodic blockage, and a unique word is added to each packet for acquisition of frequency, carrier phase and symbol timing of the respective packet. The packets of the data stream are interleaved based on an interleaver of a depth based at least in part on a ratio of a blockage free duration between two consecutive blockages of the periodic blockage to a duration of each blockage of the periodic blockage. | 2013-09-19 |
20130246885 | Method and Apparatus for Decoding Low-Density Parity-Check Codes - A method and an apparatus for decoding low-density parity-check codes are provided. A first decoding unit performs decoding computation on a first code word from a second time period to an O | 2013-09-19 |
20130246886 | STORAGE CONTROL APPARATUS, STORAGE SYSTEM, AND STORAGE CONTROL METHOD - A storage control apparatus writes n pieces of data (here, n is an integer greater than 1) in a first memory apparatus, and reads the n pieces of written data from the first memory apparatus. A parity calculation unit calculates parity based on divided data extracted from each of the n pieces of data for each certain size, and stores the calculated parity in a second memory apparatus. A read control unit restores, in reading the n pieces of data from the first memory apparatus, at least one of the n pieces of data instead of reading it from the first memory apparatus but using other data having been read from the first memory apparatus among the n pieces of data and the parity stored in the second memory apparatus. | 2013-09-19 |
20130246887 | MEMORY CONTROLLER - According to an embodiment, a memory controller includes: a coding unit that performs an error correction coding process for user data to generate first to n-th parities and performs the error correction coding process for each of the first to n-th parities to generate first to n-th external parities; and a decoding unit that performs an error correction decoding process using the user data, the first to n-th parities, and the first to n-th external parities. A generator polynomial used to generate an i-th parity is selected on the basis of a generator polynomial used to generate the first to (i−1)-th parities. | 2013-09-19 |
20130246888 | Systems and Methods for Out of Order Processing in a Data Retry - Various embodiments of the present invention provide systems and methods for data processing that includes selectively reporting results out of order or in order. | 2013-09-19 |
20130246889 | LOW OVERHEAD AND TIMING IMPROVED ARCHITECTURE FOR PERFORMING ERROR CHECKING AND CORRECTION FOR MEMORIES AND BUSES IN SYSTEM-ON-CHIPS, AND OTHER CIRCUITS, SYSTEMS AND PROCESSES - An electronic circuit ( | 2013-09-19 |
20130246890 | ARCHITECTURE TO ALLOW EFFICIENT STORAGE OF DATA ON NAND FLASH MEMORY - Systems, methods, apparatus, and techniques are provided for writing data to a storage medium. A stripe of the storage medium is interfaced via one or more data transfer channels, where the stripe comprises a plurality of pages of the storage medium. A data stream is received and the data stream is portioned into a plurality of allocation units (AUs), where each AU in the plurality of AUs has a pre-determined byte length. A first portion of a selected AU from the plurality of AUs is written to a first page of the plurality of pages and a second portion of the selected AU is written to a second page of the plurality of pages by consecutively writing bytes of the selected AU from a starting byte on the first page to an ending byte on the second page. | 2013-09-19 |
20130246891 | PHYSICAL PAGE, LOGICAL PAGE, AND CODEWORD CORRESPONDENCE - The present disclosure includes apparatuses and methods for physical page, logical page, and codeword correspondence. A number of methods include error coding a number of logical pages of data as a number of codewords and writing the number of codewords to a number of physical pages of memory. The number of logical pages of data can be different than the number of physical pages of memory. | 2013-09-19 |
20130246892 | ARCHITECTURE FOR STORAGE OF DATA ON NAND FLASH MEMORY - Systems, methods, apparatus, and techniques are provided for processing data from a storage medium. A stripe of data stored on the storage medium is read, where the stripe comprises a plurality of data allocation units (AUs) and a parity AU. Error correction decoding is applied to each of the plurality of data AUs to produce a plurality of decoded data AUs. It is determined whether a value of the parity AU is satisfied by values of bytes in the plurality of decoded data AUs. The plurality of decoded data AUs are output in response to a determination that the value of the parity AU is satisfied by the values of bytes in the plurality of decoded data AUs. | 2013-09-19 |