38th week of 2013 patent applcation highlights part 52 |
Patent application number | Title | Published |
20130244387 | METHODS FOR FABRICATING INTEGRATED CIRCUITS - Methods are provided for forming semiconductor devices. One method includes forming a first layer overlying a bulk semiconductor substrate. A second layer is formed overlying the first layer. A plurality of trenches is etched into the first and second layers. Portions of the second layer that are disposed between the plurality of trenches define a plurality of fins. A gate structure is formed overlying the plurality of fins. The first layer is etched to form gap spaces between the bulk semiconductor substrate and the plurality of fins. The plurality of fins is at least partially supported in position adjacent to the gap spaces by the gate structure. The gap spaces are filled with an insulating material. | 2013-09-19 |
20130244388 | METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH REDUCED ELECTRICAL PARAMETER VARIATION - Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a gate stack on a semiconductor substrate. In the method, a first halo implantation is performed on the semiconductor substrate with a first dose of dopant ions to form first halo regions therein. A second halo spacer is formed around the gate stack. Then a second halo implantation is performed on the semiconductor substrate with a second dose of dopant ions to form second halo regions therein. | 2013-09-19 |
20130244389 | STRAINED SEMICONDUCTOR DEVICE WITH FACETS - A method for fabricating a semiconductor device, the method includes forming a gate stack over a major surface of a substrate. The method further includes recessing the substrate to form source and drain recess cavities adjacent to the gate stack in the substrate. The method further includes selectively growing a strained material in the source and drain recess cavities in the substrate using an LPCVD process, wherein the LPCVD process is performed at a temperature of about 660 to 700° C. and under a pressure of about 13 to 50 Torr, using SiH | 2013-09-19 |
20130244390 | EXTENDED DRAIN LATERAL DMOS TRANSISTOR WITH REDUCED GATE CHARGE AND SELF-ALIGNED EXTENDED DRAIN - A method to form a LDMOS transistor includes forming a gate/source/body opening and a drain opening in a field oxide on a substrate structure, forming a gate oxide in the gate/source/body opening, and forming a polysilicon layer over the substrate structure. The polysilicon layer is anisotropically etched to form polysilicon spacer gates separated by a space in the gate/source/body opening and a polysilicon drain contact in the drain opening. A body region is formed self-aligned about outer edges of the polysilicon spacer gates, a source region is formed self-aligned about inner edges of the polysilicon spacer gates, and a drain region is formed under the polysilicon drain contact and self-aligned with respect to the polysilicon spacer gates. A drift region forms in the substrate structure between the body region and the drain region, and a channel region forms in the body region between the source region and the drift region. | 2013-09-19 |
20130244391 | SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREOF - An object of the present invention is to provide a semiconductor device having a nonvolatile memory cell of a high operation speed and a high rewrite cycle and a nonvolatile memory cell of high reliability. In a split gate type nonvolatile memory in which memory gate electrodes are formed in the shape of sidewalls of control gate electrodes, it is possible to produce a memory chip having a memory of a high operation speed and a high rewrite cycle and a memory of high reliability at a low cost by jointly loading memory cells having different memory gate lengths in an identical chip. | 2013-09-19 |
20130244392 | METHOD OF FABRICATING FIN-FIELD EFFECT TRANSISTORS (FINFETS) HAVING DIFFERENT FIN WIDTHS - Provided are methods of forming field effect transistors. The method includes preparing a substrate with a first region and a second region, forming fin portions on the first and second regions, each of the fin portions protruding from the substrate and having a first width, forming a first mask pattern to expose the fin portions on the first region and cover the fin portions on the second region, and changing widths of the fin portions provided on the first region. | 2013-09-19 |
20130244393 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device is provided, in which after forming a gate stack and a first spacer thereof, a second spacer and a third spacer are formed; and then an opening is formed between the first spacer and the third spacer by removing the second spacer. The range of the formation for the raised active area | 2013-09-19 |
20130244394 | METHOD FOR FABRICATING CAPACITOR WITH HIGH ASPECT RATIO - A method for fabricating a capacitor includes: forming a first silicon layer over a semiconductor substrate, where the first silicon layer is doped with a dopant; forming an undoped second silicon layer over the first silicon layer; forming an opening by etching the second silicon layer and the first silicon layer; forming a storage node in the opening; and removing the first silicon layer and the second silicon layer. | 2013-09-19 |
20130244395 | METHODS FOR PROTECTING PATTERNED FEATURES DURING TRENCH ETCH - A method is provided for forming a monolithic three dimensional memory array. The method includes forming a first memory level above a substrate, and monolithically forming a second memory level above the first memory level. The first memory level is formed by forming first substantially parallel conductors extending in a first direction, forming first pillars above the first conductors, each first pillar including a first conductive layer or layerstack above a vertically oriented diode, the first pillars formed in a single photolithography step, depositing a first dielectric layer above the first pillars, etching first trenches in the first dielectric layer, the first trenches extending in a second direction. After etching, a lowest point in the trenches is above a lowest point of the first conductive layer or layerstack, and the first conductive layer or layerstack does not include a resistivity-switching metal oxide or nitride. Numerous other aspects are provided. | 2013-09-19 |
20130244396 | FIELD EFFECT TRANSISTORS HAVING AN EPITAXIAL LAYER ON A FIN AND METHODS OF FABRICATING THE SAME - A method of fabricating a fin field effect transistor may include forming a fin portion protruding from a substrate, forming a device isolation layer to cover a lower sidewall of the fin portion, forming a semiconductor layer using an epitaxial method to cover an upper sidewall and a top surface of the fin portion, selectively etching an upper portion of the device isolation layer to form a gap region between a top surface of the device isolation layer and a bottom surface of the semiconductor layer, and forming a gate electrode pattern on the semiconductor layer to fill the gap region. Related devices are also described. | 2013-09-19 |
20130244397 | MULTI-DRAIN SEMICONDUCTOR POWER DEVICE AND EDGE-TERMINATION STRUCTURE THEREOF - An embodiment of a semiconductor power device provided with: a structural body made of semiconductor material with a first conductivity, having an active area housing one or more elementary electronic components and an edge area delimiting externally the active area; and charge-balance structures, constituted by regions doped with a second conductivity opposite to the first conductivity, extending through the structural body both in the active area and in the edge area in order to create a substantial charge balance. The charge-balance structures are columnar walls extending in strips parallel to one another, without any mutual intersections, in the active area and in the edge area. | 2013-09-19 |
20130244398 | METHOD OF MANUFACTURING SEMICONDUCTOR MEMORY DEVICE - The present disclosure relates to a method of manufacturing a semiconductor memory device, the method including: forming isolation layers in trenches dividing active regions of a substrate; depositing a tunnel insulating layer and a charge storing layer on an entire structure including the isolation layers; forming mask patterns on the charge storing layer to cover the active regions and to expose the isolation layers; and etching the charge storing layer by using the mask patterns as an etch barrier, thereby forming charge storing layer patterns on the active regions. | 2013-09-19 |
20130244399 | METHOD OF FORMING A LAMINATED SEMICONDUCTOR FILM - According to some embodiments of the present disclosures, a method of forming a laminated semiconductor film is constituted by alternately laminating first and second semiconductor films on an underlying film of each of a plurality of substrates to be processed. The method includes performing a first operation of forming the first semiconductor film and a second operation of forming the second semiconductor film until a predetermined number of laminated films are obtained. In the method, a film forming temperature in the first operation and a film forming temperature in the second operation are set to be equal to each other, and temperatures between the first and second operations are set to be constant. | 2013-09-19 |
20130244400 | METHOD AND APPARATUS FOR TEMPORARY BONDING OF ULTRA THIN WAFERS - A method for temporary bonding first and second wafers includes, applying a first adhesive layer upon a first surface of a first wafer and then curing the first adhesive layer. Next, applying a second adhesive layer upon a first surface of a second wafer. Next, inserting the first wafer into a bonder module and holding the first wafer by an upper chuck assembly so that its first surface with the cured first adhesive layer faces down. Next, inserting the second wafer into the bonder module and placing the second wafer upon a lower chuck assembly so that the second adhesive layer faces up and is opposite to the first adhesive layer. Next, moving the lower chuck assembly upwards and bringing the second adhesive layer in contact with the cured first adhesive layer, and then curing the second adhesive layer. | 2013-09-19 |
20130244401 | Adhesive Composition, An Adhesive Sheet and a Production Method of a Semiconductor Device - An adhesive composition includes an acrylic polymer (A), a heat curable resin (B) having unsaturated hydrocarbon group, and a coupling agent (C) having reactive a double bond group. | 2013-09-19 |
20130244402 | Adhesive Composition, An Adhesive Sheet and a Production Method of a Semiconductor Device - An adhesive composition includes an acrylic polymer (A), a heat curable resin (B) having unsaturated hydrocarbon group, and a filler (C) having reactive double bond on a surface. | 2013-09-19 |
20130244403 | METHOD AND DEVICE FOR CUTTING SEMICONDUCTOR WAFERS - A method for cutting a semiconductor wafer into semiconductor chips that reduces defects at the semiconductor chip corners. The method includes a pre-cutting processing step of trimming the semiconductor chip corners so that mechanical stress is reduced at the corners. The method includes dicing channels on a semiconductor wafer thereby defining the geometrical shape of one of the semiconductor chips, modifying the corners of the one of the semiconductor chips, and cutting the semiconductor wafer to separate the one of the semiconductor chips from other semiconductor chips. | 2013-09-19 |
20130244404 | METHOD OF SINGULATING A THIN SEMICONDUCTOR WAFER - A method of singulating a semiconductor wafer having two surfaces separated by a thickness T<200 μm includes partitioning it along a network of scribelines on one side. The other side is secured to an elastic foil, which is clamped to a wafer table. A radiative scribing tool is used to produce at least one laser beam having a pulse duration P≦75 ps, and causing the laser beam to scan along each of the scribelines so as to create a scribe with a depth D2013-09-19 | |
20130244405 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device disclosed herein includes: mounting a substrate on an electrostatic chuck placed inside a chamber, the electrostatic chuck having a first temperature and the substrate being retained in advance in an atmosphere having a second temperature lower than the first temperature; fixing the substrate onto the electrostatic chuck by applying a voltage to the electrostatic chuck; heating the electrostatic chuck to a third temperature higher than the first temperature and the second temperature after mounting the substrate; and processing the substrate after the heating. | 2013-09-19 |
20130244406 | FABRICATION METHOD AND FABRICATION APPARATUS OF GROUP III NITRIDE CRYSTAL SUBSTANCE - A fabrication method of a group III nitride crystal substance includes the steps of cleaning the interior of a reaction chamber by introducing HCl gas into the reaction chamber, and vapor deposition of a group III nitride crystal substance in the cleaned reaction chamber. A fabrication apparatus of a group III nitride crystal substance includes a configuration to introduce HCl gas into the reaction chamber, and a configuration to grow a group III nitride crystal substance by HVPE. Thus, a fabrication method of a group III nitride crystal substance including the method of effectively cleaning deposits adhering inside the reaction chamber during crystal growth, and a fabrication apparatus employed in the fabrication method are provided. | 2013-09-19 |
20130244407 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A problem in the conventional technique is that metal contamination on a silicon carbide surface is not sufficiently removed in a manufacturing method of a semiconductor device using a monocrystalline silicon carbide substrate. Accordingly, there is a high possibility that the initial characteristics of a manufactured silicon carbide semiconductor device are deteriorated and the yield rate is decreased. Further, it is conceivable that the metal contamination has an adverse affect even on the long-term reliability of a semiconductor device. In a manufacturing method of a semiconductor device using a monocrystalline silicon carbide substrate, there is applied a metal contamination removal process, on a silicon carbide surface, including a step of oxidizing the silicon carbide surface and a step of removing a film primarily including silicon dioxide formed on the silicon carbide surface by the step. | 2013-09-19 |
20130244408 | Systems And Methods For Growing A Non-Phase Separated Group-III Nitride Semiconductor Alloy - Systems and methods for MBE growing of group-III Nitride alloys, comprising establishing an average reaction temperature range from about 250 C to about 850 C; introducing a nitrogen flux at a nitrogen flow rate; introducing a first metal flux at a first metal flow rate; and periodically stopping and restarting the first metal flux according to a first flow duty cycle. According to another embodiment, the system comprises a nitrogen source that provides nitrogen at a nitrogen flow rate, and, a first metal source comprising a first metal effusion cell that provides a first metal at a first metal flow rate, and a first metal shutter that periodically opens and closes according to a first flow duty cycle to abate and recommence the flow of the first metal from the first metal source. Produced alloys include AlN, InN, GaN, InGaN, and AlInGaN. | 2013-09-19 |
20130244409 | SCHOTTKY BARRIER DIODE AND METHOD FOR MAKING THE SAME - A schottky diode includes a SiC substrate which has a first surface and a second surface facing away from the first surface, a semiconductor layer which is formed on the first surface of the SiC substrate, a schottky electrode which is in contact with the semiconductor layer, and an ohmic electrode which is in contact with the second surface of the SiC substrate. The first surface of the SiC substrate is a (000-1) C surface, upon which the semiconductor layer is formed. | 2013-09-19 |
20130244410 | METHODS OF FORMING BULK III-NITRIDE MATERIALS ON METAL-NITRIDE GROWTH TEMPLATE LAYERS, AND STRUCTURES FORMED BY SUCH METHODS - Bulk III-nitride semiconductor materials are deposited in an HPVE process using a metal trichloride precursor on a metal nitride template layer of a growth substrate. Deposition of the bulk III-nitride semiconductor material may be performed without ex situ formation of the template layer using a MOCVD process. In some embodiments, a nucleation template layer is formed ex situ using a non-MOCVD process prior to depositing bulk III-nitride semiconductor material on the template layer using an HVPE process. In additional embodiments, a nucleation template layer is formed in situ using an MOCVD process prior to depositing bulk III-nitride semiconductor material on the template layer using an HVPE process. In further embodiments, a nucleation template layer is formed in situ using an HVPE process prior to depositing bulk III-nitride semiconductor material on the template layer using an HVPE process. | 2013-09-19 |
20130244411 | DIODES WITH A DOG BONE OR CAP-SHAPED JUNCTION PROFILE TO ENHANCE ESD PERFORMANCE, AND OTHER SUBSTRUCTURES, INTEGRATED CIRCUITS AND PROCESSES OF MANUFACTURE AND TESTING - An integrated circuit structure includes a semiconductor doped area (NWell) having a first conductivity type, and a layer (PSD) that overlies a portion of said doped area (NWell) and has a doping of an opposite second type of conductivity that is opposite from the first conductivity type of said doped area (NWell), and said layer (PSD) having a corner in cross-section, and the doping of said doped area (NWell) forming a junction beneath said layer (PSD) with the doping of said doped area (NWell) diluted in a vicinity below the corner of said layer (PSD). Other integrated circuits, substructures, devices, processes of manufacturing, and processes of testing are also disclosed. | 2013-09-19 |
20130244412 | REPLACEMENT METAL GATE TRANSISTORS WITH REDUCED GATE OXIDE LEAKAGE - A method of fabricating a semiconductor device having a transistor with a metal gate electrode and a gate dielectric layer includes forming a protective layer on the gate dielectric layer and forming a metal gate electrode over the protective layer. The protective layer has a graded composition between the gate dielectric layer and the metal gate electrode. | 2013-09-19 |
20130244413 | Method for Fabricating a Semiconductor Device Having a Saddle Fin Transistor - A method for fabricating a semiconductor device includes forming a pad nitride layer that exposes an isolation region over a cell region of a semiconductor substrate; forming a trench in the isolation region of the semiconductor substrate; forming an isolation layer within the trench; etching an active region of the semiconductor substrate by a certain depth to form a recessed isolation region; etching the isolation layer by a certain depth to form a recessed isolation region; depositing a gate metal layer in the recessed active region and the recessed isolation region to form a gate of a cell transistor; forming an insulation layer over an upper portion of the gate; removing the pad nitride layer to expose a region of the semiconductor substrate to be formed with a contact plug; and depositing a conductive layer in the region of the semiconductor substrate to form a contact plug. | 2013-09-19 |
20130244414 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE HAVING DUAL GATE DIELECTRIC LAYER - Methods for manufacturing a semiconductor device having a dual gate dielectric layer may include providing a substrate including first and second regions, forming a first gate dielectric layer having a first thickness on the substrate, forming an interlayer insulating layer including first and second trenches exposing the first gate dielectric layer in the first and second regions, forming a sacrificial layer on the interlayer insulating layer and bottoms of the first and second trenches, forming a sacrificial pattern exposing the first gate dielectric layer of the bottom of the first trench, removing the first gate dielectric layer of the bottom of the first trench, forming a second gate dielectric layer having a second thickness on the bottom of the first trench, removing the sacrificial pattern, and forming a gate electrode on each of the first and second gate dielectric layers. | 2013-09-19 |
20130244415 | FLOATING GATE FLASH CELL DEVICE AND METHOD FOR PARTIALLY ETCHING SILICON GATE TO FORM THE SAME - A method for forming a split gate flash cell memory device provides for establishing a floating gate region then using spacers or other hard mask materials that cover opposed edges of a gate electrode material in the gate region, to serve as hard masks during an etching operation that partially etches the gate electrode material which may be polysilicon. The gate electrode so produced serves as a floating gate electrode and includes a recessed central portion flanked by a pair of opposed upwardly extending fins which may terminate upwardly at an apex. A floating gate oxide is then formed by thermal oxidation and/or oxide deposition techniques. | 2013-09-19 |
20130244416 | SPACER STRUCTURE OF A FIELD EFFECT TRANSISTOR WITH AN OXYGEN-CONTAINING LAYER BETWEEN TWO OXYGEN-SEALING LAYERS - A method of fabricating a spacer structure which includes forming a dummy gate structure comprising a top surface and sidewall surfaces over a substrate and forming a spacer structure over the sidewall surfaces. Forming the spacer structure includes depositing a first oxygen-sealing layer on the dummy gate structure and removing a portion of the first oxygen-sealing layer on the top surface of the dummy gate structure, whereby the first oxygen-sealing layer remains on the sidewall surfaces. Forming the spacer structure further includes depositing an oxygen-containing layer on the first oxygen-sealing layer and the top surface of the dummy gate structure. Forming the spacer structure further includes depositing a second oxygen-sealing layer on the oxygen-containing layer and removing a portion of the second oxygen-sealing layer over the top surface of the dummy gate structure. Forming the spacer structure further includes thinning the second oxygen-sealing layer. | 2013-09-19 |
20130244417 | Template Wafer Fabrication Process for Small Pitch Flip-Chip Interconnect Hybridization - A template wafer fabrication process is disclosed for high density indium bumping of microchips by using an innovative template wafer upon which the bumps are initially fabricated. Once fabricated, these bumps are transferred to the microchip, after which can be hybridized to another microchip. Such a template wafer is reusable, and thus provides an economical way to fabricate indium bumps. Reusability also eliminates nonuniformities in bump shape and size in serial processing of separate microchips, which is not the case for other indium bump fabrication processes. Such a fabrication process provides a way to form relatively tall indium bumps and accomplishes this without the standard thick photoresist liftoff process. The described process can be suitable for bump pitches under 10 microns, and is only limited by the resolution of the photolithography equipment used. | 2013-09-19 |
20130244418 | METHOD OF MANUFACTURING A SEMICONDUCTOR COMPONENT - A method for manufacturing a semiconductor component that includes the use of multiple layers of photoresist. A first layer of electrically conductive material is formed over a substrate and a first layer of photoresist is formed over the first layer of electrically conductive material. A portion of the first layer of photoresist is removed leaving photoresist having sidewalls separated by a gap. A second layer of electrically conductive material having first and second sidewalls is formed in the gap. A second layer of photoresist is formed over the first layer of photoresist and over the second layer of electrically conductive material. Portions of the second layer of photoresist and the first layer of photoresist are removed to uncover the first and second edges of the second layer of electrically conductive material. A protective structure is formed over the first and second edges of the second electrically conductive material. | 2013-09-19 |
20130244419 | INTER CONNECTION STRUCTURE INCLUDING COPPER PAD AND PAD BARRIER LAYER, SEMICONDUCTOR DEVICE AND ELECTRONIC APPARATUS INCLUDING THE SAME - A semiconductor device including an interconnection structure including a copper pad, a pad barrier layer and a metal redistribution layer, an interconnection structure thereof and methods of fabricating the same are provided. The semiconductor device includes a copper pad disposed on a first layer, a pad barrier layer including titanium disposed on the copper pad, an inorganic insulating layer disposed on the pad barrier layer, a buffer layer disposed on the inorganic insulating layer, wherein the inorganic insulating layer and the buffer layer expose a portion of the pad barrier layer, a seed metal layer disposed on the exposed buffer layer, a metal redistribution layer disposed on the seed metal layer, and a first protective layer disposed on the metal redistribution layer. | 2013-09-19 |
20130244420 | OPTIMIZED ANNULAR COPPER TSV - The present disclosure provides a thermo-mechanically reliable copper TSV and a technique to form such TSV during BEOL processing. The TSV constitutes an annular trench which extends through the semiconductor substrate. The substrate defines the inner and outer sidewalls of the trench, which sidewalls are separated by a distance within the range of 5 to 10 microns. A conductive path comprising copper or a copper alloy extends within said trench from an upper surface of said first dielectric layer through said substrate. The substrate thickness can be 60 microns or less. A dielectric layer having interconnect metallization conductively connected to the conductive path is formed directly over said annular trench. | 2013-09-19 |
20130244421 | METHODS OF FORMING COPPER-BASED CONDUCTIVE STRUCTURES ON AN INTEGRATED CIRCUIT DEVICE - Disclosed herein are various methods of forming copper-based conductive structures on integrated circuit devices. In one example, the method includes the steps of forming a trench/via in a layer of insulating material, forming a copper-based seed layer above the layer of insulating material and in the trench/via, performing a heating process on the copper-based seed layer to increase an amount of the copper-based seed layer positioned proximate a bottom of the trench/via, performing an etching process on said copper-based seed layer and performing an electroless copper deposition process to fill the trench/via with a copper-based material. | 2013-09-19 |
20130244422 | METHODS OF FORMING COPPER-BASED CONDUCTIVE STRUCTURES ON SEMICONDUCTOR DEVICES - Disclosed herein are various methods of forming copper-based conductive structures on semiconductor devices, such as transistors. In one example, the method involves performing a first etching process through a patterned metal hard mask layer to define an opening in a layer of insulating material, performing a second etching process through the opening in the layer of insulating material that exposes a portion of an underlying copper-containing structure, performing a wet etching process to remove the patterned metal hard mask layer, performing a selective metal deposition process through the opening in the layer of insulating material to selectively form a metal region on the copper-containing structure and, after forming the metal region, forming a copper-containing structure in the opening above the metal region. | 2013-09-19 |
20130244423 | ELECTROLESS GAP FILL - A method for providing copper filled features is provided. Features are provided in a layer on a substrate. A simultaneous electroless copper plating and anneal is provided. The electroless copper plating is chemical-mechanical polished, where there is no annealing before the chemical-mechanical polishing and after the simultaneous electroless copper plating and anneal. | 2013-09-19 |
20130244424 | INTERCONNECT STRUCTURES AND METHODS OF MANUFACTURING OF INTERCONNECT STRUCTURES - Interconnect structures and methods of manufacturing the same are disclosed herein. The method includes forming a barrier layer within a structure and forming an alloy metal on the barrier layer. The method further includes forming a pure metal on the alloy metal, and reflowing the pure metal such that the pure metal migrates to a bottom of the structure, while the alloy metal prevents exposure of the barrier layer. The method further includes completely filling in the structure with additional metal. | 2013-09-19 |
20130244425 | Formation of a Masking Layer on a Dielectric Region to Facilitate Formation of a Capping Layer on Electrically Conductive Regions Separated by the Dielectric Region - A masking layer is formed on a dielectric region of an electronic device so that, during subsequent formation of a capping layer on electrically conductive regions of the electronic device that are separated by the dielectric region, the masking layer inhibits formation of capping layer material on or in the dielectric region. The capping layer can be formed selectively on the electrically conductive regions or non-selectively; in either case, capping layer material formed over the dielectric region can subsequently be removed, thus ensuring that capping layer material is formed only on the electrically conductive regions. Silane-based materials, can be used to form the masking layer. The capping layer can be formed of an conductive material, a semiconductor material, or an insulative material, and can be formed using any appropriate process, including conventional deposition processes such as electroless deposition, chemical vapor deposition, physical vapor deposition or atomic layer deposition. | 2013-09-19 |
20130244426 | METHOD FOR OBTAINING EXTREME SELECTIVITY OF METAL NITRIDES AND METAL OXIDES - Methods for etching metal nitrides and metal oxides include using ultradilute HF solutions and buffered, low-pH HF solutions containing a minimal amount of the hydrofluoric acid species H | 2013-09-19 |
20130244427 | METHODS OF MAKING JOGGED LAYOUT ROUTINGS DOUBLE PATTERNING COMPLIANT - One illustrative method disclosed herein involves creating an overall target pattern that includes an odd-jogged feature with a crossover region that connects first and second line portions, wherein the crossover region has a first dimension in a first direction that is greater than a second dimension that is transverse to the first direction, decomposing the overall target pattern into a first sub-target pattern and a second sub-target pattern, wherein each of the sub-target patterns comprise a line portion and a first portion of the crossover region, and generating first and second sets of mask data corresponding to the first and second sub-target patterns, respectively. | 2013-09-19 |
20130244428 | METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - In a method for manufacturing a silicon carbide semiconductor device, a conductive layer is formed on a silicon carbide layer. The silicon carbide layer and the conductive layer react with each other thus forming an alloy layer formed of a reaction layer in contact with the silicon carbide layer and a silicide layer on the reaction layer. A carbon component is removed from the silicide layer. A portion of the silicide layer is removed using an acid thus exposing at least a portion of the reaction layer. An electrode layer is formed on an upper side of the exposed reaction layer. | 2013-09-19 |
20130244429 | SHOT BLASTING MATERIAL USED FOR SILICON SUBSTRATE SURFACE TREATMENT AND METHOD FOR PREPARING SILICON SUBSTRATE - A shot blasting material used for silicon substrate surface treatment and a method for preparing a silicon substrate. The shot blasting material includes silicon carbide particles, and the median particle diameter of the silicon carbide particles is 1 μm to 30 μm. Surface treatment can be performed on at least one surface of a silicon substrate in a bombarding manner through the shot blasting material. The particle diameter of the silicon carbide particles used for bombarding is small, and only a mechanical damage layer with a small thickness is formed on a first surface of the silicon substrate, so in the subsequent chemical treatment procedure, it is not required to add concentrated sulfuric acid to a chemical corrosive liquid, and a corrosion step and a cleaning step may be combined into one step, thereby reducing the process flow time, and decreasing the process cost; meanwhile, the method is environment friendly. | 2013-09-19 |
20130244430 | Double Patterning Method for Semiconductor Devices - A method of fabricating a semiconductor device is disclosed. The exemplary method includes providing a substrate including a device layer and a sacrificial layer formed over the device layer and patterning the sacrificial layer thereby defining a cut pattern. The cut pattern of the sacrificial layer having an initial width. The method further includes depositing a mask layer over the device layer and over the cut pattern of the sacrificial layer. The method further includes patterning the mask layer thereby defining a line pattern including first and second portions separated by the cut pattern of the sacrificial layer and selectively removing the cut pattern of the sacrificial layer thereby forming a gap that separates the first and second portions of the line pattern of the mask layer. The method further includes patterning the device layer using the first and second portions of the line pattern of the mask layer. | 2013-09-19 |
20130244431 | SLURRY, POLISHING LIQUID SET, POLISHING LIQUID, METHOD FOR POLISHING SUBSTRATE, AND SUBSTRATE - The polishing liquid according to the embodiment comprises abrasive grains, an additive and water, wherein the abrasive grains satisfy either or both of the following conditions (a) and (b).
| 2013-09-19 |
20130244432 | CMP COMPOSITIONS SELECTIVE FOR OXIDE AND NITRIDE WITH HIGH REMOVAL RATE AND LOW DEFECTIVITY - The invention relates to a chemical-mechanical polishing composition comprising a ceria abrasive, cations of one or more lanthanide metals, one or more nonionic polymers, water, and optionally one or more additives. The invention further relates to a method of chemically-mechanically polishing a substrate with the inventive chemical-mechanical polishing composition. Typically, the substrate comprises one or more of silicon oxide, silicon nitride, and polysilicon. | 2013-09-19 |
20130244433 | CMP COMPOSITIONS SELECTIVE FOR OXIDE AND NITRIDE WITH HIGH REMOVAL RATE AND LOW DEFECTIVITY - The invention provides a chemical-mechanical polishing composition containing a ceria abrasive, one or more nonionic polymers, optionally one or more phosphonic acids, optionally one or more nitrogen-containing zwitterionic compounds, optionally one or more sulfonic acid copolymers, optionally one or more anionic copolymers, optionally one or more polymers comprising quaternary amines, optionally one or more compounds that adjust the pH of the polishing compositions, water, and optionally one or more additives. The invention further provides a method of chemically-mechanically polishing a substrate with the inventive chemical-mechanical polishing composition. Typically, the substrate contains silicon oxide, silicon nitride, and/or polysilicon. | 2013-09-19 |
20130244434 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE - The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a plurality of circuit devices over a substrate. The method includes forming an organic layer over the substrate. The organic layer is formed over the plurality of circuit devices. The method includes polishing the organic layer to planarize a surface of the organic layer. The organic layer is free of being thermally treated prior to the polishing. The organic material is un-cross-linked during the polishing. The method includes depositing a LT-film over the planarized surface of the organic layer. The depositing is performed at a temperature less than about 150 degrees Celsius. The depositing is also performed without using a spin coating process. The method includes forming a patterned photoresist layer over the LT-film. | 2013-09-19 |
20130244435 | SEMICONDUCTOR DEVICE HAVING AN N-CHANNEL MOS TRANSISTOR, A P-CHANNEL MOS TRANSISTOR AND A CONTRACTING FILM - In a second direction, in a plan view, an n-channel MOS transistor and an expanding film are adjacent. Therefore, the n-channel MOS transistor receives a positive stress in the direction in which a channel length is extended from the expanding film. As a result, a positive tensile strain in an electron moving direction is generated in a channel of the n-channel MOS transistor. On the other hand, in the second direction, in a plan view, a p-channel MOS transistor and the expanding film are shifted from each other. Therefore, the p-channel MOS transistor receives a positive stress in the direction in which a channel length is narrowed from the expanding film. As a result, a positive compressive strain in a hole moving direction is generated in a channel of the p-channel MOS transistor. Thus, both on-currents of the n-channel MOS transistor and the p-channel MOS transistor can be improved. | 2013-09-19 |
20130244436 | MASKING TECHNIQUES AND CONTACT IMPRINT RETICLES FOR DENSE SEMICONDUCTOR FABRICATION - A reticle comprising isolated pillars is configured for use in imprint lithography. In some embodiments, on a first substrate a pattern of pillars pitch-multiplied in two dimensions is formed in an imprint reticle. The imprint reticle is brought in contact with a transfer layer overlying a series of mask layers, which in turn overlie a second substrate. The pattern in the reticle is transferred to the transfer layer, forming an imprinted pattern. The imprinted pattern is transferred to the second substrate to form densely-spaced holes in the substrate. In other embodiments, a reticle is patterned by e-beam lithography and spacer formations. The resultant pattern of closely-spaced pillars is used to form containers in an active integrated circuit substrate. | 2013-09-19 |
20130244437 | METHODS OF FORMING FEATURES ON AN INTEGRATED CIRCUIT PRODUCT USING A NOVEL COMPOUND SIDEWALL IMAGE TRANSFER TECHNIQUE - One illustrative method disclosed herein includes forming a sacrificial mandrel above a structure, forming a plurality of first sidewall spacers on opposite sides of the sacrificial mandrel, removing the sacrificial mandrel, forming a plurality of second sidewall spacers on opposite sides of each of the first sidewall spacers, and removing the first sidewall spacers to thereby define a patterned spacer mask layer comprised of the plurality of second sidewall spacers. | 2013-09-19 |
20130244438 | PHOTOLITHOGRAPHIC METHODS - Provided are photoresist overcoat compositions, substrates coated with the overcoat compositions and methods of forming electronic devices by a negative tone development process. The compositions, coated substrates and methods find particular applicability in the manufacture of semiconductor devices. | 2013-09-19 |
20130244439 | REMOVABLE TEMPLATES FOR DIRECTED SELF ASSEMBLY - A sacrificial-post templating method is presented for directing block copolymer (BCP) self-assembly to form nanostructures of monolayers and bilayers of microdomains. The topographical post template can be removed after directing self-assembly and, therefore, is not incorporated into the final microdomain pattern. The sacrificial posts can be a material removable using a selective etchant that will not remove the material of the final pattern block(s). The sacrificial posts may be removable, at least in part, using a same etchant as for removing one of the blocks of the BCP, for example, a negative tone polymethylmethacrylate (PMMA) when a non-final pattern block of polystyrene is removed and polydimethylsiloxane (PDMS) remains on the substrate. | 2013-09-19 |
20130244440 | CHAMBER FILLER KIT FOR PLASMA ETCH CHAMBER USEFUL FOR FAST GAS SWITCHING - A chamber filler kit for an inductively coupled plasma processing chamber in which semiconductor substrates are processed by inductively coupling RF energy through a window facing a substrate supported on a cantilever chuck. The kit includes at least one chamber filler which reduces the lower chamber volume in the chamber below the chuck. The fillers of the kit can be mounted in a standard chamber having a chamber volume of over 60 liters and by using different sized chamber fillers it is possible to reduce the chamber volume to provide desired gas flow conductance and accommodate changes in vacuum pressure during processing of the substrate. The chamber filler kit can be used to modify a standard chamber to accommodate different processing regimes such as rapid alternating processes wherein wide pressure changes are needed without varying a gap between the substrate and the window. | 2013-09-19 |
20130244441 | COMPOSITE SHOWERHEAD ELECTRODE ASSEMBLY FOR A PLASMA PROCESSING APPARATUS - A method of forming an elastomeric sheet adhesive bond between mating surfaces of an electrode and a backing member to accommodate stresses generated during temperature cycling due to mismatch in coefficients of thermal expansion. The elastomeric sheet comprises a thermally conductive silicone adhesive able to withstand a high shear strain of ≧300% in a temperature range of room temperature to 300° C. such as heat curable high molecular weight dimethyl silicone with fillers. Installation can be manually, manually with installation tooling, or with automated machinery. | 2013-09-19 |
20130244442 | ULTRA HIGH-SPEED WET ETCHING APPARATUS - There is provided with an etching method using an etching apparatus. Four arms can be positioned in a direction substantially from a center of the stage toward a peripheral portion with an angle difference of about 90°. Etchant is supplied to a first position nearest to the center of the object which is rotating, from a first etchant supply nozzle placed on a first arm. Etchant is further supplied to a second position second nearest to the center of the object, from a second etchant supply nozzle placed on a second arm. The second arm is substantially symmetrically positioned with respect to the first arm and the second arm has an angle difference of about 180° with respect to the first arm. | 2013-09-19 |
20130244443 | METHOD OF PRODUCING A SEMICONDUCTOR SUBSTRATE PRODUCT AND ETCHING LIQUID - A method for manufacturing a semiconductor substrate product having: providing an etching liquid containing water, a hydrofluoric acid compound and an organic solvent, and applying the etching liquid to a semiconductor substrate, the semiconductor substrate having a silicon layer and a silicon oxide layer, the silicon layer containing an impurity, and thereby selectively etching the silicon oxide layer. | 2013-09-19 |
20130244444 | METHOD OF PRODUCING A SEMICONDUCTOR SUBSTRATE PRODUCT AND ETCHING LIQUID - A method of producing a semiconductor substrate product, having the steps of: providing an etching liquid containing water, a hydrofluoric acid compound, and a water-soluble polymer; and applying the etching liquid to a semiconductor substrate, the semiconductor substrate having a silicon layer and a silicon oxide layer, the silicon layer containing an impurity, and thereby selectively etching the silicon oxide layer. | 2013-09-19 |
20130244445 | Method of Fabricating Semiconductor Device - Methods of fabricating a semiconductor device include forming a deposited film on a semiconductor substrate in a process chamber by repeatedly forming unit layers on the semiconductor substrate. The unit layer is formed by forming a preliminary unit layer on the semiconductor substrate by supplying a process material including a precursor material and film-control material into the process chamber, purging the process chamber, forming a unit layer from the preliminary unit layer, and again purging the process chamber. The precursor material includes a central atom and a ligand bonded to the central atom, and the film-control material includes a hydride of the ligand. | 2013-09-19 |
20130244446 | Method for Forming Si-Containing Film Using Two Precursors by ALD - A method for forming a silicon-containing dielectric film on a substrate by atomic layer deposition (ALD) includes: providing two precursors, one precursor containing a halogen in its molecule, another precursor containing a silicon but no halogen in its molecule, adsorbing a first precursor, which is one of the two precursors onto a substrate to deposit a monolayer of the first precursor; adsorbing a second precursor, which is the other of the two precursors onto the monolayer of the first precursor to deposit a monolayer of the second precursor; and exposing the monolayer of the second precursor to radicals of a reactant to cause surface reaction with the radicals to form a compound monolayer of a silicon-containing film. | 2013-09-19 |
20130244447 | OXIDATION OF METALLIC FILMS - Methods for the aqueous oxidation of metallic films are described. For example, a film of hafnium metal on a silicon substrate can be oxidized to hafnium dioxide using hot deionized water. Methods for fabricating electrical components such as capacitors and field effect transistors using the oxidized metallic films are also described. For example, capacitors having a hafnium dioxide dielectric layer can be fabricated. | 2013-09-19 |
20130244448 | Precursors for CVD Silicon Carbo-Nitride Films - Classes of liquid aminosilanes have been found which allow for the production of silicon carbo-nitride films of the general formula Si | 2013-09-19 |
20130244449 | Methods and Apparatus For Patterning Photovoltaic Devices and Materials For Use With Such Devices - A picosecond laser beam shaping assembly is disclosed for shaping a picosecond laser beam for use in patterning (e.g., scribing) semiconductor devices. The assembly comprises a pulsed fibre laser source of picosecond laser pulses, a harmonic conversion element for converting laser pulses at a first laser wavelength having a first spectral bandwidth to laser pulses at a second laser wavelength having a second spectral bandwidth, and a beam shaping apparatus for shaping the laser beam at the second laser wavelength, the beam shaping apparatus having a spectral bandwidth that substantially corresponds to the second spectral bandwidth so as to produce a laser beam having a substantially rectangular cross-sectional profile. | 2013-09-19 |
20130244450 | BRUSH LEAD GUIDE FOR A BRUSH HOLDER ASSEMBLY - A brush lead guide for a brush holder assembly configured to retain the leads extending from a brush in a desired position/orientation to ensure the leads do not interfere with movement of the brush within the brush holder. In some instances, the lead guide includes a first guide rail including a channel for receiving a first lead of the brush and a second guide rail including a channel for receiving a second lead from the brush. The lead guide maintains the leads in a position such that the leads are held within the width of the opening of the brush holder to ensure the leads do not interfere with movement of the brush within the brush holder during use of the brush holder assembly. | 2013-09-19 |
20130244451 | BRUSH HOLDER MARKING SYSTEM AND ASSOCIATED MAINTENANCE - A marking system for knowing precisely at which location on an electrical device a used brush and associated brush holder assembly were positioned to evaluate whether abnormal brush wear, abnormal operation or other anomaly is occurring and performing maintenance and/or replacement of components as needed. | 2013-09-19 |
20130244452 | ELECTRICAL CONNECTOR ASSEMBLY AND AN ELECTRONIC DEVICE INCORPORATING THE SAME - An electrical connector assembly to be connected to a first control circuit includes a first connector including a switch unit, a second control circuit, and a first contact unit, and a second connector including a detecting circuit and a second contact unit. When connecting the first and second connectors, the connector assembly is disposed sequentially in first and second states. In the second state, where contact pads of the first and second contact units are in respective electrical contacts such that a loop is formed for a trigger signal to be transmitted to the detecting circuit for the latter to generate a detecting signal to the second control circuit, when the first control circuit generates a control signal, the second control circuit controls the switch unit to switch to a conducting state to transmit an electrical power signal to the first control circuit. | 2013-09-19 |
20130244453 | CABLE CONNECTOR AND ENDOSCOPE APPARATUS - A cable connector includes a circuit board, having a predetermined width in a manner passable through an elongated tube of an endoscope apparatus, disposed to extend in an axial direction. A terminal group is formed on the circuit board, for electrically contacting a socket connector. First and second land patterns are formed on the circuit board, arranged in the axial direction so that the terminal group is disposed therebetween, wherein a front end of a first electric line group having lines among electric lines of a cable structure is electrically coupled to the first land pattern, and a front end of a second electric line group having lines among the electric lines is coupled to the second land pattern. A wiring pattern is formed on the circuit board, for electrically coupling the first land pattern to the terminal group and coupling the second land pattern to the terminal group. | 2013-09-19 |
20130244454 | DAUGHTER CARD ASSEMBLY HAVING A LATCHING SUB-ASSEMBLY WITH A COUPLING ARM EXTENDING IN AN INSERTION DIRECTION - A daughter card assembly including a printed circuit board that defines a board plane and has a mating edge, a trailing edge, and a side edge that extends between the mating and trailing edges. The mating edge extends lengthwise along a longitudinal axis and has electrical contacts positioned therealong. The mating edge is configured to engage a card connector when the mating edge is moved in an insertion direction that is substantially perpendicular to the longitudinal axis. The daughter card assembly also includes a latching sub-assembly that is coupled to the circuit board and extends along the side edge. The latching sub-assembly includes a coupling arm that extends in the insertion direction and has a latch end that is proximate to the mating edge. The latch end is configured to removably couple to the card connector. | 2013-09-19 |
20130244455 | PROCESSING DEVICE AND PROCESSING SYSTEM - A processing device includes: a first connecter including a first pin and a second pin which is able to be coupled to one of a first external apparatus and a second external apparatus; and a controller to set a signal of the second pin as an input signal, detect coupling of the first connecter with the first external apparatus or the second external apparatus, set the signal of the second pin as an output signal based on detection of the coupling of the first connecter with the second external apparatus, and outputs a first signal to the second pin. | 2013-09-19 |
20130244456 | CABLE CONNECTOR FOR ENDOSCOPE APPARATUS AND METHOD OF PRODUCING ENDOSCOPE APPARATUS - An endoscope apparatus includes an elongated tube, a imaging unit in the elongated tube, and a cable structure, including plural signal lines, having first and second ends, the first end being connected to the imaging unit. A cable connector is connected with the second end, and couplable with a socket connector connectively. The cable connector includes a circuit board having a width in a manner passable through the elongated tube in an axial direction. A conductive land is formed on the circuit board, and coupled to the second end. A terminal pattern is formed on the circuit board, for connective coupling by reception in the socket connector. An advancing tip is formed on a front side of the circuit board in the axial direction, for initially advancing upon entry of the circuit board in the elongated tube, to enable the conductive land and the terminal pattern to pass safely. | 2013-09-19 |
20130244457 | THREE-POLE ADAPTER SET WITH A PLUG PART AND A SOCKET PART WHICH MAY BE PLUGGED IN THE PLUG PART - The invention relates to an adapter set. The adapter set is made up of a plug part and a socket part. The plug part is provided with at least one three-pole plug contact of a particular country standard at one end and a three pole safety plug socket at the other end of the adapter set. The socket part is provided with a three-pole safety plug and a three-pole multi-way plug socket. The adapter set comprises one single safety plug, namely the plug formed on the socket part. It is provided that the polarity of the multi-way plug socket matches the polarity of the plug contacts. | 2013-09-19 |
20130244458 | Electrical Connection Between Two BusBars Made of Flat Conductors and of an Insulating Layer Disposed Between the Conductors - The disclosure relates to an electrical connection between two busbars made of flat conductors and an insulating layer disposed between the conductors at the opposite longitudinal edges of the two busbars. The two conductors of each busbar run parallel to each other at a distance on the longitudinal edge thereof, wherein a molded part made of electrically insulating material bridges the distances between the conductors of the two busbars. Electrically conductive contact elements, forced against each other but electrically insulated from each other, each contact one of the conductors of each busbar by means of structured contact surfaces and clamp the same between the element and the molded part, wherein the contact surfaces for the conductors of the two busbars including clamping protrusions running parallel to the longitudinal edges. | 2013-09-19 |
20130244459 | PROTECTION MODULE FOR DATA TRANSMISSION CONNECTOR - A protection module includes a protective cover having a first main body and an elastic arm, and a cover removing tool having a second main body, at least one elastic engaging pin and a release pin. The first main body has at least one engaging slot and a retaining slot; the elastic arm has a free front end with at least one beveled slot. The release pin is longer than the elastic engaging pin and has a thickness larger than a height of two raised portions in a socket of the data transmission connector, and has an acute-angled beveled free end. The elastic engaging pin has a cross-sectional shape corresponding to the engaging slot and has a free end with a retaining block. The protective cover is plugged into the data transmission connector for protecting the same against damages caused by maliciously applied force or improper use of it. | 2013-09-19 |
20130244460 | Apparatus Comprising a User Input Device - According to embodiments of the disclosure there is provided an apparatus including a user input device; and a mechanism configured to enable the user input device to be moved between a first position and a second position wherein when the user input device is in the first position a socket is accessible by a user of the apparatus and when the user input device is in the second position the socket is not accessible by the user of the apparatus. | 2013-09-19 |
20130244461 | CONTROL APPARATUS - A control apparatus includes a port, an openable and closable door, and a holding mechanism. A connector of the USB device is insertable into and removable from the port so as to connect and disconnect the USB device to and from the control apparatus. The openable and closable door is disposed adjacent the port, and configured to open so as to expose the port and configured to close so as to shield the port. The holding mechanism is disposed at the openable and closable door and configured to hold a housing of the USB device when the openable and closable door is open. | 2013-09-19 |
20130244462 | POWER SOCKET AND ELECTRICAL CONNECTOR ASSEMBLY - An exemplary electrical connector assembly includes a power plug and a power socket. The power plug includes a magnet. The power socket includes a pop-up mechanism. The pop-up mechanism includes a sliding assembly which can be switched from a first position to a second position. When the sliding assembly is switched from the first position to the second position, the pop-up mechanism generates a magnetic field which repels the magnet of the power plug, and the power plug moves away from the power socket. | 2013-09-19 |
20130244463 | MODULAR CONNECTOR FOR BICYCLE COMPONENTS - A bicycle including a frame, an electrical circuit including a power source, and an electrical connector. The electrical connector includes a first port defined by a first terminal that has a first configuration, and a second port defined by a second terminal that has a second configuration complementary to the first configuration. The electrical connector further includes a third port that is distinct from the first and second ports, a plurality of passthrough conductors extending from the first port to the second port to connect the electrical connector to the electrical circuit, and at least one lateral conductor providing an electrical connection from the first port to the third port. | 2013-09-19 |
20130244464 | ELECTRICAL CONNECTOR FOR FPC - An electrical connector includes an insulative housing, a plurality of contacts and an actuator. The insulative housing defines a front opening and a back receiving space. The receiving space defines a horizontal plane and a vertical plane connecting each other. The contacts include retaining portions, contacting portions and pressing portions. Each contacting portion and corresponding pressing portion extends oppositely from the retained portion. The actuator includes a base portion and several separate costal parts extending from the base portion. Adjacent costal parts are connected by a shaft and the pressing portions are against to the shaft. The actuator rotates around the shaft and defines a cambered surface at the costal parts, the cambered surface slides between the horizontal plane and the vertical plane. | 2013-09-19 |
20130244465 | RECEPTACLE CONNECTOR - A receptacle connector includes an insulative body, conductive terminals mounted therein, and a seal covering a central portion of the body. The receptacle connector mates with at least one mating electrical connector. The seal prevents the intrusion of dust into the joint between the receptacle connector and the mating electrical connector(s). The seal and the body have locking features provided thereon to secure the seal to the housing. | 2013-09-19 |
20130244466 | Anti-Vibration Connector Coupling with Disengagement Feature - A connector coupling that comprises a connector body, a first collar that receives the connector body, and second collar that surrounds the first collar. A movable ratchet ring is supported by the connector body and includes at least one locking member. The movable ratchet ring is axially movable with respect to the first collar between engaged and disengaged positions. A stationary ratchet ring is coupled to the first collar and includes at least one locking member. When the movable ratchet ring is in the engaged position, the locking members of the rings are engaged, and rotating the second collar from the first position to the second position with respect to the first collar moves the movable ratchet ring to the disengaged position away from the stationary ratchet ring such that the locking members are disengaged, thereby allowing rotation of the first collar with respect to the connector body. | 2013-09-19 |
20130244467 | SMP ELECTRICAL CONNECTOR AND CONNECTOR SYSTEM - A push-on connector system includes a male push-on bore including a center conductor pin, and a female push-on core including a socket. The male push-on bore receives the female push-on core. A second bore is configured forwardly of the male push-on bore, and a latch track is positioned in the second bore and forms a plurality of inclined latch surfaces. A movable collar is mounted rearwardly of the female push-on core with a plurality of bayonet pins as is configured for engaging the second bore. The bayonet pins slide along the inclined latch surfaces to axially drive the movable collar into the second bore and secure the female push-on core into the male push-on bore. A resilient member is coupled between the movable collar and female push-on core to bias the female push-on core into the male push-on bore. | 2013-09-19 |
20130244468 | SAFETY SOCKET - A safety socket of the present invention has a lock mechanism which is utilized for engaging a tubular hexagonal shell of a plug when the plug inserts into the safety socket. Thus, the components of the safety socket can be arranged loose within easier spacing. Therefore, safety purpose is fulfilled with simplified structure. Manufacturing of the safety socket is facilitated. | 2013-09-19 |
20130244469 | CAM-ACTUATED INDEPENDENT SECONDARY LOCK - A connector assembly according to the present disclosure includes a connector body, a lock reinforcement, and a secondary lock. The connector body has a plurality of terminal cavities and a plurality of lock projections configured to engage a plurality of terminals to retain the terminals in the terminal cavities. The lock reinforcement is slidable relative to the connector body for engagement with a subset of the lock projections to maintain the lock projections engaged with a first subset of the terminals. The secondary lock is slidable relative to the connector body for engagement with a second subset of the terminals to retain the terminals in the terminal cavities independent from the lock projections. The secondary lock is coupled to the lock reinforcement such that moving one of the lock reinforcement and the secondary lock moves the other one of the lock reinforcement and the secondary lock. | 2013-09-19 |
20130244470 | LOCKING MECHANISM FOR CONNECTOR - A locking mechanism is used to lock a connector to an information handling device. The locking mechanism includes a supporting bracket, a locking member, and an attachment member sleeved on a cable extending from the connector and slidably coupled to the supporting bracket. The supporting bracket is cantilevered from the information handling device. The locking member is rotatably mounted to the supporting bracket, adjacent to a distal end of the supporting bracket. The locking member engages with the attachment member by rotating the locking member in a first direction, thereby locking the connector to the information handling device. The locking member disengages from the holding member by rotating the locking member in a second direction opposite to the first direction, thereby the attachment member is capable of moving away from the information handling device to release the connector from the information handling device. | 2013-09-19 |
20130244471 | COUPLING APPARATUS FOR HIGH POWER ELECTRICAL CONNECTORS - A coupler for mating high power electrical connectors as may be used in mining environments includes a frame | 2013-09-19 |
20130244472 | RETENTION MECHANISM DEVICE - A retention latch mechanism having corresponding retention features and stress reducing members is provided herein. In an exemplary embodiment, the retention latch mechanism comprises a pair of spring arm retention features of a receptacle engageable with a corresponding pair of recessed retention features of an insertable tab and one or more backup spring members for reducing stress within the spring arms during insertion of the tab into the receptacle. The backup spring may be positioned adjacent an outward facing surface such that outward lateral deflection of the spring arms deflects the backup spring thereby reducing force within the spring arm. The backup spring may include any or all of a bent portion of an associated bracket or arm member, a wire, a loop, a complementary spring arm, dual backup springs, elastomeric members and self-lubricating members. Methods of providing retention of a tab within a receptacle are also provided herein. | 2013-09-19 |
20130244473 | ELECTRICAL CONNECTOR EQUIPPED WITH DETECTION SWITCH - An electrical connector includes an insulative housing with a plurality of conductive terminals mounted thereon. A metallic shell surrounds the insulative housing thereby defining a mating cavity therein for receiving a mating plug. A spring plate is formed on one side wall of the metallic shell and projects into the mating cavity. A terminal module is attached to said side wall of the metallic shell and separated from the insulative housing by said side wall. The terminal module has a body section and a conductive terminal. The spring plate together with the conductive terminal form a detection switch which can detect whether a mating plug is inserted or not. | 2013-09-19 |
20130244474 | VISUAL MATING DETECTOR FOR ELECTRICAL CONNECTOR - The present disclosure describes a system for connecting two connectors to each other. The system includes a first connector having a first connector surface, and the first connector surface includes a transparent shape. Further, a second connector, having a second connector surface, includes a portion that includes a second connector color. Particularly, the second connector is configured to be inserted into the first connector, enabling a superimposition and alignment of the transparent shape with the portion of the second connector surface, thereby visually indicating a valid connection between the two connectors. | 2013-09-19 |
20130244475 | WALL OUTLET WITH RETRACTABLE USB CHARGING CABLE CONNECTED TO A USB PORT WITHIN A WALL - The present invention relates to a system, method, and apparatus for charging electronics with a universal serial bus (USB) charging cable connected to a USB port. The USB port is located entirely behind a wall having a wall outlet. The USB charging cable and its connectors can easily be retracted into the wall for storage or extended outside the wall to a USB powered device. A plurality of USB charging cables can be installed in one wall outlet, such as one USB charging cable having a Micro-USB plug and one USB charging cable having an Apple 30 pin connector. The wall outlet can also have an AC outlet as well, such that the wall outlet can charge most electronic devices sold in the market today. The wall outlet allows the user to charge USB powered devices even when the user does not have his USB cord with him. | 2013-09-19 |
20130244476 | SELF-MANAGING CORD - The invention is a self-managing cord or cable and method for managing a self-managing cord that includes one or more permanently formed spiral coils within one section of a cord and one or more non-coiled sections. The one or more non-coiled sections of the cord are inserted into the coiled section(s) in order to wrap, bind, manage, or otherwise organize the cord as a whole. To use the self-managing cord, the user wraps or winds the coiled portion(s) of the cord around the non-coiled portion(s) to form an organized and self-secured bundle. | 2013-09-19 |
20130244477 | Apparatus And Method Of Zeroing A Test Instrument - An apparatus and method for shorting together a plurality of electrical leads. The apparatus includes an electrical conductor that extends between first and second ends and a first surface and a second surface facing away from the first surface. The electrical conductor includes a central bight that is disposed between the first and second ends and has a concave contour that defines a portion of the first surface. The electrical conductor also includes first and second bights that have convex contours that define portions of the first surface. The first bight is disposed between the central bight and the first end and the second bight is disposed between the central bight and the second end. The electrical conductor also includes a first and second contact segments that are respectively disposed between the first and second bights and the first and second ends. | 2013-09-19 |
20130244478 | SAFETY ELECTRICAL OUTLET AND SWITCH SYSTEM - An electrical box is mounted on a wall stud, and a wiring panel is installed within the electrical box so as to partition the interior of the electrical box into a user inaccessible wiring compartment and a user accessible module compartment. A protective cover is attached to the wiring panel so as to protect the wiring panel during a makeup phase of wall panel installation and painting. After the makeup phase, the protective cover is removed from the wiring panel and a module having a user operable electrical function is mounted to the wiring panel within the user accessible module compartment. | 2013-09-19 |
20130244479 | High Density Jack - The present disclosure provides for electrical connectors or jack assemblies/housings for use in voice/data communication systems. More particularly, the present disclosure provides for modular jack assemblies that include a movable locking member. The present disclosure provides for improved systems/designs for jack assemblies/housings that are easily secured and/or unsecured to or from a jack panel or jack faceplate. In exemplary embodiments, the present disclosure provides for convenient, low-cost and effective systems and methods for easily securing and/or unsecuring jack assemblies/housings to or from a jack panel/faceplate (e.g., in the field) by utilizing advantageous modular jack assemblies that include a movable locking member, and related assemblies. | 2013-09-19 |
20130244480 | ELECTRONIC DEVICE WITH CONNECTOR MODULE - An electronic device includes a chassis including a bottom wall, a bracket fixed to the bottom wall, a data storage assembly received in the bracket, and a connector assembly. The connector assembly includes a main body and two mounting members. The mounting members are fixed to the chassis and the bracket. The main body is slidably arranged between the mounting members. The main body includes a first side surface and a second side surface, a first signal connector and a power connector are set on the first side surface, the first signal connector is to electrically connect with a motherboard of the electronic device, the power connector is to connect with a power supply, a plurality of second signal connectors are set on the second side surface, to electrically connect with the data storage assembly. | 2013-09-19 |
20130244481 | INGRESS REDUCTION COAXIAL CABLE CONNECTOR - A coaxial connector including a selectively engageable radio frequency interference shield. | 2013-09-19 |
20130244482 | CONTACT, CONNECTOR AND METHOD FOR MANUFACTURING CONNECTOR - A contact includes: a cable connection portion that is connected to a signal line in an exterior cable; a fixed portion that is extended toward a front edge of the contact from the cable connection portion, and fixed to an exterior connector cover; and a connector connection portion that is extended toward the front edge of the contact from the fixed portion, and connected to a conductor of an exterior connector. | 2013-09-19 |
20130244483 | COAXIAL CABLE CONNECTOR HAVING A COLLAPSIBLE CONNECTOR BODY - A connector body comprising a body portion having one or more weakened portions disposed across the body portion to structurally weaken the body portion along a discontinuous revolution around the body portion, wherein upon axial compression of the connector body, the one or more weakened portions of the body portion buckle inward towards a coaxial cable to securely fasten the coaxial cable connector to the coaxial cable is provided. Furthermore, an associated method is also provided. | 2013-09-19 |
20130244484 | CONNECTOR ASSEMBLY FOR CORRUGATED COAXIAL CABLE - A connector comprising a connector body comprising a first end, a second end, and an inner bore defined between the first and second ends of the body, a compression member comprising a first end, a second end, and an inner bore defined between the first and second ends of the cap, the first end of the compression member being structured to engage the second end of the connector body, a clamp comprising a first end, a second end, an inner bore defined between the first and second ends of the clamp, wherein the clamp facilitates threadable insertion of a coaxial cable, and a compression surface disposed within the connector body, wherein axial advancement of the compression member facilitates the clamp being axially advanced into proximity with the compression surface such that the clamp and the compression surface transmit force between one another is provided. An associated method is also provided. | 2013-09-19 |
20130244485 | SERIAL ELECTRICAL CONNECTOR - A serial electrical connector includes a connector plug and a connector jack. The connector plug includes an audio plug with a hollow cylindrical space formed in the center thereof; a coaxial cable being inserted into and filling the space; and an engagement element being disposed at a tip of the audio plug and configured to electrically connect the audio plug to the connector jack. | 2013-09-19 |
20130244486 | COAXIAL ELECTRICAL CONNECTOR AND COAXIAL ELECTRICAL CONNECTOR DEVICE - A guiding function of an annular contact upon mating/removal with/from an opposing connector can be maintained well with a simple configuration. An annular contact is formed with an unruptured annular member having no ruptured part in a circumferential direction and continued in the circumferential direction. As a result, compared with a conventional annular contact having ruptured parts in the circumferential direction, rigidity is increased while maintaining necessary elasticity; and, for example even when an opposing connector is mated or removed in a direction inclined in an axial direction with respect to the axial direction of the annular shape, conventional twisting deformation is suppressed in the annular contact, and the opposing connector is stably guided along the axial direction of the annular shape, thereby well maintaining a mating guiding function of the annular contact. | 2013-09-19 |