38th week of 2014 patent applcation highlights part 72 |
Patent application number | Title | Published |
20140266364 | SEMICONDUCTOR CIRCUIT AND METHOD OF OPERATING THE SAME - Provided are a semiconductor circuit and a method of operating the same. The semiconductor circuit includes a first pulse generating circuit enabled to a rising edge of a clock signal and configured to generate a first read pulse, a second pulse generating circuit enabled to a rising edge of the clock signal and configured to generate a second read pulse independent of the first read pulse, a dynamic pull-down stage configured to develop a voltage level of a first dynamic node based at least on data values of an input signal and the first and second read pulses, and a dynamic pull-up stage configured to develop a voltage level of a second dynamic node based at least on data values of the input signal and the first and second read pulses. | 2014-09-18 |
20140266365 | LATENCY/AREA/POWER FLIP-FLOPS FOR HIGH-SPEED CPU APPLICATIONS - A circuit for a low latency, low area, and low power flip-flop may include a pass-gate multiplexer that can selectively allow one of input or test data to enter a master cell when a clock signal is low. The master cell may include a first inverter cross-coupled to a second inverter, and may receive the input or test data and may latch and provide at an input node of the slave cell, an inverted input data or the test data, upon a transition of the clock signal to a high state. The slave cell may include a second clock pass-gate and a third inverter that is cross-coupled to a fourth inverter, and may receive the inverted input data or the test data and may latch and provide at an output node, the input data or the test data, upon the transition of the clock signal to a high state. | 2014-09-18 |
20140266366 | COMPENSATED HYSTERESIS CIRCUIT - A compensated hysteresis circuit comprises a hysteresis circuit including an output node and a first control transistor. The first control transistor provides feedback to the hysteresis circuit. A temperature and voltage compensation circuit includes a self-biasing threshold control circuit including an input coupled to the output node of the hysteresis circuit, and a first trim transistor coupled between the first control transistor of the hysteresis circuit and the self-biasing threshold control circuit. | 2014-09-18 |
20140266367 | SEMICONDUCTOR DEVICE - To provide a semiconductor device which can perform a scan test and includes a logic circuit capable of reducing signal delay. The semiconductor device includes a combinational circuit, sequential circuits each holding first data supplied to the combinational circuit or second data output from the combinational circuit, first memory circuits each holding first data supplied to the corresponding sequential circuit and holding second data output from the corresponding sequential circuit, and second memory circuits electrically connecting the first memory circuits in series by supplying the first data or second data supplied from one of the first memory circuits to another one of the first memory circuits. The second memory circuit includes a first switch controlling supply of the first data or second data to the node, a capacitor electrically connected to the node, and a second switch controlling output of the first data or second data from the node. | 2014-09-18 |
20140266368 | LIGHT RECEIVING CIRCUIT - The light receiving circuit includes: a photoelectric conversion element for causing a current corresponding to an amount of incident light to flow; a MOS transistor including a source connected to the photoelectric conversion element and a drain connected to a node, for causing the current of the photoelectric conversion element to flow to the node while maintaining a voltage of the source to a first voltage; a reset circuit for causing a current to flow from the node to a GND terminal so that a voltage of the node becomes a second voltage lower than the first voltage; a control circuit for outputting a reset signal to the reset circuit; and a voltage increase detection circuit for detecting a fluctuation in the voltage of the node and outputting a detection result. | 2014-09-18 |
20140266369 | LOW POWER ARCHITECTURES - Systems and methods for operating transistors near or in the sub-threshold region to reduce power consumption are described herein. In one embodiment, a method for low power operation comprises sending a clock signal to a flop via a clock path comprising a plurality of transistors, wherein the clock signal has a high state corresponding to a high voltage that is above threshold voltages of the transistors in the clock path. The method also comprises sending a data signal to the flop via a data path comprising a plurality of transistors, wherein the data signal has a high state corresponding to a low voltage that is below threshold voltages of the transistors in the data path. The method further comprises latching the data signal at the flop using the clock signal. | 2014-09-18 |
20140266370 | Multi-Stage Delay-Locked Loop Phase Detector - A phase detector includes a phase propagator circuit including a plurality of flip-flops. Each flip-flop includes a clock input configured to receive a clock signal having a different phase relative to phases of the clock signal received by other flip-flops in the plurality of flip-flops. The phase detector further includes a phase controller coupled to the clock input of each flip-flop in the plurality of flip-flops. The phase controller is configured to provide the different phases of the clock signal to the plurality of flip-flops such that the different phases are scaled exponentially relative to one another. | 2014-09-18 |
20140266371 | MULTI-PHASE GENERATOR - A multi-phase generator includes an oscillator unit including a plurality of first buffer units forming a single closed loop and a delay unit including a plurality of second buffer units respectively connected to a plurality of nodes, wherein each of the plurality of nodes is connected between two adjacent buffer units of the first buffer units. A phase of an output signal of a second buffer unit, among the second buffer units, lags behind a phase of an output signal of a first buffer unit, among the first buffer units. | 2014-09-18 |
20140266372 | APPARATUS, METHOD AND SYSTEM FOR IMPLEMENTING A HARDWARE INTERFACE PINOUT - Techniques and mechanisms for operating an integrated circuit to communicate via a hardware interface for the integrated circuit, wherein a pinout with the hardware interface is based on the configuration. In an embodiment, the integrated circuit receives a first plurality of signals via the hardware interface, and sequentially latches a second plurality of signals based on the first plurality of signals. In another embodiment, some or all of the second plurality of signals are variously latched by the integrated circuit in an order which is based on the first configuration. | 2014-09-18 |
20140266373 | INTEGRATED DELAYED CLOCK FOR HIGH SPEED ISOLATED SPI COMMUNICATION - A system may include a plurality of isolators to transfer data signals across an isolation barrier, one of the signals including a clock signal. A delay circuit may be included to receive the clock signal and provide a delayed clock signal that lags the clock signal by an amount representing a delay across the isolation barrier. The delayed clock signal may be delayed by a round trip propagation delay over the isolation barrier. The delayed clock signal may be used as a reference to read data sent over the isolation barrier. | 2014-09-18 |
20140266374 | Fractional Order Capacitor - Disclosed is a fractional order capacitor comprising a dielectric nanocomposite layer of thickness t, comprising a first side, and a second side opposite the first side, a first electrode layer coupled to the first side of the dielectric nanocomposite layer, a second electrode layer coupled to the second side of the dielectric nanocomposite layer, a complex impedance phase angle dependent on at least a material weight percentage of filler material in a dielectric nanocomposite layer. | 2014-09-18 |
20140266375 | Integrated Circuitry for Generating a Clock Signal in an Implantable Medical Device - Timer circuitry completely formable in an integrated circuit (IC) for generating a clock signal in an implantable medical device is disclosed. The timer circuitry can be formed on the same Application Specific Integrated Circuit typically used in the implant, and requires no external components. The timer circuitry comprises modification to a traditional astable timer circuit. A resistance in the disclosed timer circuit can be trimmed to adjust the frequency of the clock signal produced, thus allowing that frequency to be set to a precise value during manufacturing. Precision components are not needed in the RC circuit, which instead are used to set the rough value of the frequency of the clock signal. A regulator produces a power supply for the timer circuitry from a main power supply (Vcc), producing a clock signal with a frequency that is generally independent of temperature and Vcc fluctuations. | 2014-09-18 |
20140266376 | ACTIVE CLOCK TREE FOR DATA CONVERTERS - A multi-stage clock distribution circuit for an integrated circuit is provided. The clock distribution circuit may route a common clock signal to a plurality of clock receiver circuits. Each stage in the distribution circuit may include a plurality of buffers. Outputs of at least some, perhaps all, of the buffers may be connected to each other by an interconnect. The interconnect may align clock signals that are output by the interconnected buffers and thereby encourage synchronization of those clock signals. Other stages of the clock distribution signal may be connected as well. | 2014-09-18 |
20140266377 | HYBRID ANALOG/DIGITAL POINT-OF-LOAD CONTROLLER - In one example, there is disclosed a hybrid analog-digital point-of-load controller (ADPOL) for use in a power supply. The ADPOL is configured to respond to transient current loads. In the presence of moderate current transients, power is clocked by a digital power core, which may be programmatically configured to adjust pulse width in response to the transient. In the presence of larger current transients, control may be passed to an analog transient compensator, which includes high-speed circuitry selecting between a very high-duty-cycle clock and a very low-duty-cycle clock, which will drive the transient back to the digital control domain. | 2014-09-18 |
20140266378 | METHOD FOR SETTING OFFSET GAIN OF ANALOG OUTPUT MODULE - A method for setting an offset gain of analog output module configured to convert a digital signal outputted from an MPU (Micro Processing Unit) to an analog signal and to output the converted analog signal is proposed, the method including outputting, by the MPU, a digital signal value to the analog output module, calculating an offset gain by measuring, by the analog output module, an analog signal value outputted by receipt and conversion of the digital signal value, and entering the measured analog signal value to an offset gain inverse function preset by the MPU, and setting the offset gain of the analog output module as the calculated offset gain. | 2014-09-18 |
20140266379 | SEMICONDUCTOR DEVICE - A sample-and-hold circuit including a transistor and a capacitor is connected to the differential circuit. The sample-and-hold circuit acquires voltage for correcting the offset voltage of the differential circuit by charging or discharging the capacitor through sampling operation. Then, it holds the potential of the capacitor through holding operation. In normal operation of the differential circuit, the output potential of the differential circuit is corrected by the potential held by the capacitor. The transistor in the sample-and-hold circuit is preferably a transistor whose channel is formed using an oxide semiconductor. An oxide semiconductor transistor has extremely low leakage current; thus, a change in the potential held in the capacitor of the sample-and-hold circuit can be minimized. | 2014-09-18 |
20140266380 | INTERFACE AND RELATED METHOD FOR CONNECTING SENSOR EQUIPMENT AND A PHYSIOLOGICAL MONITOR - An interface to connect sensor equipment and a physiological monitor includes a first connector to receive power from a first channel of the monitor and a second connector to receive power from a second channel of the monitor. The power from each of the first and second channels of the monitor is combined within the interface. The interface further includes a third connector to provide the combined power to the sensor equipment; a voltage converter to rescale the voltage of the combined power that is provided to the sensor equipment; and a scaling circuit to reduce the voltage of a signal representing a measured physiological parameter. The signal representing the measured physiological parameter is sent from the sensor equipment to the monitor. The interface is advantageous to allow sensor equipment to be sufficiently powered by a monitor that would not typically provide enough power. | 2014-09-18 |
20140266381 | BIAS CIRCUIT FOR A SWITCHED CAPACITOR LEVEL SHIFTER - A noise resistant switch control circuit is provided. The circuit includes a low pass filter configured to couple to a first terminal of a switch and a first voltage clamp coupled to the low pass filter. The first voltage clamp is configured to couple to a control terminal of the switch and limit a voltage of the control terminal relative to the first terminal to within a first clamping range. The circuit includes a second voltage clamp coupled to an input terminal of the switch control circuit. The second voltage clamp is configured to couple to the control terminal of the switch. The second voltage clamp is further configured to reduce a level of a control voltage coupled to the second voltage clamp. The circuit includes a bias device configured to couple to the control terminal of the switch and to impress a biasing voltage to the control terminal. | 2014-09-18 |
20140266382 | LOW-POWER INTERFACE AND METHOD OF OPERATION - In a particular embodiment, a method includes modifying an output impedance associated with the input receiver. In response to modifying the output impedance, the method restricts an output voltage at an output node of the input receiver. Particular embodiments of an input receiver circuit are also disclosed. | 2014-09-18 |
20140266383 | Self-Activating Adjustable Power Limiter - A fast response time, self-activating, adjustable threshold limiter including a limiting element LE, a first coupling element CE | 2014-09-18 |
20140266384 | SYSTEMS AND METHOD FOR LEVEL SHIFTERS - A level shifter system includes an inverting portion, a non-inverting portion and a cross latch output component. The inverting portion is configured to receive an inverting input, a supply voltage and to generate an intermediary inverting output. The non-inverting portion is configured to receive a non-inverting input, the supply voltage and to generate an intermediary non-inverting output. The cross latch output component is configured to drive the intermediary inverting and non-inverting outputs to inverting and non-inverting outputs, respectively. The inverting and non-inverting outputs are at selected upper and lower levels according to the inverting input and non-inverting inputs, respectively. | 2014-09-18 |
20140266385 | DUAL SUPPLY LEVEL SHIFTER CIRCUITS - A dual supply level shifter circuit includes a switching circuit and a set of level shifter circuits coupled to the switching circuit. The switching circuit includes a first set of coupled transistors, wherein the supply switching circuit is coupled to a first supply source that is configured to provide a first power supply voltage and is coupled to a second supply source that is configured to provide a second power supply voltage. The set of level shifter circuits includes a second set of coupled transistors, wherein the set of level shifter circuits is configured to receive a voltage input signal at an input node from a first circuit and to supply to an output node of the dual supply level shifter circuit an output signal having a value that is a highest voltage value between the first power supply voltage and the second power supply voltage. | 2014-09-18 |
20140266386 | LEVEL SHIFTER FOR HIGH DENSITY INTEGRATED CIRCUITS - A level shifter for converting between voltages of a core voltage range to voltages within a larger I/O voltage range. The level shifter has interconnected transistors implemented as core devices operable within the core voltage range. The level shifter is connected to first and second power connections at the I/O voltage range. A voltage clamping element implemented as a core device has a threshold voltage greater than or equal to the difference between the I/O voltage range and the core voltage range and configured to prevent overstressing the transistors with voltages beyond the core voltage range. The input to the level shifter is within the core voltage range. The level shifter output signal has a high level at the high voltage of the I/O voltage range and a low level at approximately one threshold voltage above the low voltage level of the core voltage range. | 2014-09-18 |
20140266387 | INPUT/OUTPUT INTERFACE - One or more systems and techniques for communicating a signal between a first chip and a second chip using one or more circuits are provided. If the signal corresponds to a first voltage, one or more voltages are provided to one or more locations and a capacitive load is charged using a pull-up driver that is connected to a power supply. If the signal corresponds to a second voltage, one or more voltages are provided to one or more locations and the capacitive load is discharged using a pull-down driver that is connected to ground. When the first chip is powered off, a fail-safe mode is provided by configuring a cross control circuit to generate a bias to control one or more transistors. | 2014-09-18 |
20140266388 | VOLTAGE LEVEL SHIFTER - The voltage level shifter includes a first voltage shift circuit, a second voltage shift circuit, a first switch circuit, a second switch circuit, a third switch circuit and a fourth switch circuit. The first voltage shift circuit receives a first input voltage, and the second voltage shift circuit receives a second voltage shift circuit. When the first voltage is high level voltage, a second output voltage and a first voltage are transformed to a ground voltage so as to open the second switch circuit and the fourth switch circuit, and then the first output voltage is transited to a system voltage. When the second voltage is high level voltage, a first output voltage and a second voltage are transited to a ground voltage so as to open the first switch circuit and the third switch circuit, and then the second output voltage is transited to the system voltage. | 2014-09-18 |
20140266389 | Powerline Control Interface - A powerline control interface includes a powerline connection, a level shifter connected to the powerline connection, the level shifter having a zero crossing detector signal output, a capacitor connected to the powerline connection, an inductor connected to the powerline connection, and a receive signal inductively coupled to the inductor. | 2014-09-18 |
20140266390 | TRANSCONDUCTANCE CIRCUIT AND FREQUENCY MIXER - The present invention provides a transconductance circuit and a frequency mixer. The transconductance circuit includes: a first transistor, a second transistor, a first impedor, a second impedor, a first input network, and a second input network, where a gate of the first transistor is connected to a source of the second transistor through the first input network and the first impedor; and a gate of the second transistor is connected to a source of the first transistor through the second input network and the second impedor. The present invention can enable a current that passes through a transconductance circuit to be reused between a first transistor and a second transistor, thereby improving the gain efficiency of the transconductance circuit and improving performance of the transconductance circuit. | 2014-09-18 |
20140266391 | CONTROLLING THE CONDUCTIVITY OF AN OXIDE BY APPLYING VOLTAGE PULSES TO AN IONIC LIQUID - Electrolyte gating with ionic liquids is a powerful tool for inducing conducting phases in correlated insulators. An archetypal correlated material is VO | 2014-09-18 |
20140266392 | BOOTSTRAPPED SWITCHING CIRCUIT WITH FAST TURN-ON - An apparatus and method for implementing a bootstrapped switching circuit having improved (i.e. faster) turn-on time is provided. In an embodiment, an inner switching loop is implemented in a bootstrapped switching circuit where the inner switching loop is configured to turn on an input switch in the bootstrapped drive circuit independent of the drive circuit output. The embodiment decouples the inner switching loop circuitry from the output drive circuit of the bootstrapped switching circuit, which typically has a larger load capacitance than the inner switching loop. This allows the inner switching loop to turn on the input switch in the bootstrapped switching circuit faster and decreases the turn-on time of the bootstrapped switching circuit. | 2014-09-18 |
20140266393 | BIPOLAR TRANSISTOR WITH LOWERED 1/F NOISE - In a bipolar transistor, a thin gate oxide, preferably less than 600 Å, is formed over the base surface region between the emitter and collector. A conductive gate, such as doped polysilicon, is then formed over the gate oxide and biased at the emitter voltage. In the example of a PNP transistor, when the emitter is forward biased with respect to the base to turn the transistor on, the gate is at a positive potential relative to the base. This causes the holes in the base conducting the emitter-collector current to be repelled away from the surface, and the electrons in the base to be attracted to the surface, so that more of the emitter-collector current flows deeper into the base. Thus, the effect of defects at the base surface is mitigated, and 1/f noise is reduced. The invention is equally applicable to PNP and NPN transistors. Other benefits result. | 2014-09-18 |
20140266394 | HIGH-SPEED SWITCH WITH SIGNAL-FOLLOWER CONTROL OFFSETTING EFFECTIVE VISIBLE-IMPEDANCE LOADING - A data link circuit switches high-speed signals through FET-based circuitry between channels. A FET responds to control signals at the gate terminal to operate in either a signal-passing mode or another (blocking) mode. In the passing mode, an AC (high-speed) signal is passed between the S-D terminals by coupling a first signal portion (of the AC signal) and with another signal portion diverted by the inherent capacitances associated with the FET. For offsetting the loading caused by the inherent capacitances associated with the FET-based switch, a biasing circuit is configured and arranged to bias the back-gate terminal of the FET transistor with a follower signal. | 2014-09-18 |
20140266395 | AC COUPLING CIRCUIT WITH HYBRID SWITCHES - A coupling apparatus having a first branch and a second branch is disclosed. The first branch generally comprises (A) a first switch group configured to connect an input signal to an output node through a first capacitor, and (B) second switch group configured to connect either (i) a second signal, or (ii) a ground voltage, to the output node through a second capacitor. The second branch generally comprises (A) a third switch group configured to connect the input signal to the output node through a third capacitor, and (B) a fourth switch group configured to connect either (i) the second signal, or (ii) the ground voltage, to the output node through a fourth capacitor. | 2014-09-18 |
20140266396 | INTEGRATED CLOCK GATER (ICG) USING CLOCK CASCODE COMPLIMENTARY SWITCH LOGIC - Inventive aspects include an integrated clock gater (ICG) circuit having clocked complimentary voltage switched logic (CICG) that delivers high performance while maintaining low power consumption characteristics. The CICG circuit provides a small enable setup time and a small clock-to-enabled-clock delay. A significant reduction in clock power consumption is achieved in both enabled and disabled modes, but particularly in the disabled mode. Complimentary latches work in tandem to latch different voltage levels at different nodes depending on the voltage level of the received clock signal and whether or not an enable signal is asserted. An inverter takes the voltage level from one of the nodes, inverts it, and outputs a gated clock signal. The gated clock signal may be active or quiescent depending on the various voltage levels. Time is “borrowed” from an evaluation window and added to a setup time to provide greater tolerances for receiving the enable signal. | 2014-09-18 |
20140266397 | DIGITAL SOFT START WITH CONTINUOUS RAMP-UP - A soft-start generation system is configured to generate a soft-start voltage. The soft-start generation system includes sawtooth circuitry configured to generate current having a sawtooth waveform and staircase circuitry configured to generate current having an ascending staircase waveform. A ramp-up current may be generated that is a combination of the sawtooth current and the staircase current. The ramp-up current may continuously ramp up to a predetermined current level. The soft-start voltage may be generated based on the ramp-up current. | 2014-09-18 |
20140266398 | METHOD AND SEMICONDUCTOR APPARATUS FOR REDUCING POWER WHEN TRANSMITTING DATA BETWEEN DEVICES IN THE SEMICONDUCTOR APPARATUS - A semiconductor apparatus is provided herein for reducing power when transmitting data between a first device and a second device in the semiconductor apparatus. Additional circuitry is added to the semiconductor apparatus to create a communication system that decreases a number of state changes for each signal line of a data bus between the first device and the second device for all communications. The additional circuitry includes a decoder coupled to receive and convert a value from the first device for transmission over the data bus to an encoder that provides a recovered (i.e., re-encoded) version of the value to the second device. One or more multiplexers may also be included in the additional circuitry to support any number of devices. | 2014-09-18 |
20140266399 | ACTIVE LUMPED ELEMENT CIRCULATOR - An integrated circuit can comprise: a first port, a second port, and a third port; and a plurality of microwave operational amplifiers coupled to each other and the first port, the second port, and the third port. The plurality of microwave operational amplifiers can be arranged to substantially pass a signal provided to the first port to the second port while substantially isolating the signal provided to the first port from the third port; the plurality of microwave operational amplifiers can be arranged to substantially pass a signal provided to the second port to the third port while substantially isolating the signal provided to the second port from the first port; and the plurality of microwave operational amplifiers can be arranged to substantially pass a signal provided to the third port to the first port while substantially isolating the signal provided to the third port from the second port. | 2014-09-18 |
20140266400 | METHOD OF REDUCING CURRENT COLLAPSE OF POWER DEVICE - According to example embodiments, a method of operating a power device includes applying a control voltage to a control electrode of the power device, where the control electrode is electrically separated from a source electrode, a drain electrode, and a gate electrode of the power device. The control voltage is separately applied to the control electrode. The method may include applying a negative control voltage to the control electrode prior to applying a gate voltage to the gate electrode. | 2014-09-18 |
20140266401 | DATA-RETAINED POWER-GATING CIRCUIT AND DEVICES INCLUDING THE SAME - A power-gating circuit and devices including the same are provided. The power-gating circuit includes a flip-flop configured to receive a first power supply voltage and a gated clock signal to operate and a switch circuit connected between a first power supply voltage source configured to supply the first power supply voltage and a second power supply voltage source configured to supply a second power supply voltage. The switch circuit includes a first switch configured to be connected between the first power supply voltage source and the second power supply voltage source and to operate in response to a clock enable signal and a second switch configured to be connected between the first power supply voltage source and the second power supply voltage source and to operate in response to the first power supply voltage. | 2014-09-18 |
20140266402 | TRANSISTOR INCLUDING REENTRANT PROFILE - A transistor includes a substrate, an electrically conductive material layer, and an electrically insulating material layer. At least a portion of one or more of the substrate, the electrically conductive material layer, and the electrically insulating material layer define a reentrant profile. | 2014-09-18 |
20140266403 | Low Loss Electronic Devices Having Increased Doping for Reduced Resistance and Methods of Forming the Same - An electronic device includes a drift region having a first conductivity type and a grid including a plurality of doped regions formed in the drift region and having a second conductivity type. The doped regions have a dopant concentration greater than 2.2×10 | 2014-09-18 |
20140266404 | METHOD FOR DETECTING ENVIRONMENTAL VALUE IN ELECTRONIC DEVICE AND ELECTRONIC DEVICE - A method of detecting an environment vale of an electronic device is provided. The method includes measuring a state of one or more units related to the electronic device, determining a value based at least in part on the measured state of the one or more units related to the electronic device, determining an operation state of the electronic device according to the value, and generating an approximated environment value according to the operation state. Further, other various embodiments are available. | 2014-09-18 |
20140266405 | MANAGEMENT OF EXTERIOR TEMPERATURES ENCOUNTERED BY USER OF A PORTABLE ELECTRONIC DEVICE BY REDUCING HEAT GENERATION BY A COMPONENT - Described embodiments include a portable electronic device. The device includes a shell housing components of the portable electronic device and a heat-generating component. The device includes a contact sensor configured to determine a user touch to the shell. The device includes a temperature sensor configured to determine an exterior temperature of the shell. The device includes a thermal manager configured to reduce the exterior shell temperature by regulating heat generation by the heat-generating component. The regulating heat generation is responsive to the determined user touch and the measured determined temperature of the shell. | 2014-09-18 |
20140266406 | SYMMETRIC PLACEMENT OF COMPONENTS ON A CHIP TO REDUCE CROSSTALK INDUCED BY CHIP MODES - A method and system to control crosstalk among qubits on a chip are described. The method includes placing two or more components symmetrically on the chip, the chip including the qubits, and driving two or more ports symmetrically to control the crosstalk based on controlling coupling of chip mode frequencies and qubit frequencies. | 2014-09-18 |
20140266407 | BIPOLAR JUNCTION TRANSISTOR AND OPERATING AND MANUFACTURING METHOD FOR THE SAME - A bipolar junction transistor and an operating method and a manufacturing method for the same are provided. The bipolar junction transistor comprises a first doped region, a second doped region and a third doped region. The first doped region has a first type conductivity. The second doped region comprises well regions formed in the first doped region, having a second type conductivity opposite to the first type conductivity, and separated from each other by the first doped region. The third doped region has the first type conductivity. The third doped region is formed in the well regions or in the first doped region between the well regions. | 2014-09-18 |
20140266408 | Circuit and Method for a Multi-Mode Filter - An embodiment integrated circuit includes a first capacitive element including a first metal-oxide-semiconductor (MOS) capacitor and a second capacitive element coupled in parallel with the first capacitive element, where the second capacitive element includes a second MOS capacitor. Also, the integrated circuit includes a third capacitive element coupled in parallel with the first capacitive element and the second capacitive element, where the third capacitive element includes a first metal-insulator-metal (MIM) capacitor and a fourth capacitive element coupled in parallel with the first capacitive element, the second capacitive element, and the third capacitive element, where the fourth capacitive element includes a second MIM capacitor. | 2014-09-18 |
20140266409 | SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A semiconductor structure with a high voltage area and a low voltage area includes a substrate of a first conductivity type accommodating the high voltage area and the low voltage area. A resistor is on the substrate, connecting the high voltage area and the low voltage area, and the resistor resides substantially in the high voltage area. The structure further includes a first doped region of the first conductivity type in the substrate between the high voltage area and the low voltage area, and a second doped region of a second conductivity type between the substrate and the first doped region. Moreover, an insulating layer is formed between the resistor and the first doped region. | 2014-09-18 |
20140266410 | APPARATUS AND METHOD FOR CONTROLLING CHARGE PUMP - An apparatus for controlling a charge pump includes a current sensor arranged to output a current sense signal that is linearly proportional to an output current of the charge pump, and an oscillator that provides a clock signal for the charge pump. The oscillator receives the current sense signal and uses it to vary an oscillation frequency of the clock signal. An amplitude of the clock signal also may be varied in response to the current sense signal. | 2014-09-18 |
20140266411 | SWITCHING DEVICE - The present invention provides a switching device capable of further minimizing the ON resistance of a switching element. Switching element has hole injecting unit that includes injecting electrode which is directly connected to semiconductor substrate. Injection driving unit of driving unit is connected to injecting electrode and source electrode of switching element, and applies an injection voltage Vin between injecting electrode and source electrode. Injection driving unit injects holes from hole injecting unit to a hetero-junction interface of semiconductor substrate, by applying the injection voltage Vin exceeding a threshold value to switching element.
| 2014-09-18 |
20140266412 | SYSTEMS AND METHODS FOR POWER LIMITING FOR A PROGRAMMABLE I/O DEVICE - A device includes a digital to analog converter (DAC) configured to generate a voltage output or a current output. The device also includes an integrated circuit configured to receive at least one of the voltage output or the current output and transmit the at least one of the voltage output or the current output to a load, wherein the integrated circuit is configured to measure a voltage level or a current level related to the transmission of the at least one of the voltage output or the current output. In one embodiment, a current limiter is included for voltage outputs as a form of power limiting and circuit protection. Additionally, the device includes a controller configured to receive an indication of the measurement from the integrated circuit and determine if the indication of the measurement exceeds a predetermined threshold. | 2014-09-18 |
20140266413 | BANDGAP REFERENCE CIRCUIT - A circuit for generating a temperature-stabilized reference voltage on a semiconductor chip includes a differential pair including a first and a second bipolar junction transistor. The circuit further includes a feedback circuit including an amplification stage and configured to control a current flowing through the first bipolar junction transistor and a current flowing through the second bipolar junction transistor. A first resistor is connected between an emitter of the first bipolar junction transistor and an emitter of the second bipolar junction transistor, thereby generating a PTAT voltage across the first resistor. Further, the circuit includes a current source forcing a partial current having a CTAT behavior through the first resistor. | 2014-09-18 |
20140266414 | INTERNAL VOLTAGE GENERATOR AND CONTACTLESS IC CARD INCLUDING THE SAME - A voltage generator of a contactless integrated circuit (IC) card includes a regulator configured to generate a first internal voltage based on an input voltage and a first reference voltage, the input voltage being received through an antenna of the contactless IC card. The voltage generator includes an internal voltage generator configured to generate a second internal voltage, the second internal voltage being used to operate an internal circuit of the contactless IC card. The voltage generator includes a reference voltage generator configured to generate a second reference voltage based on the first internal voltage, the second reference voltage being generated without regard to a fluctuation component of the first internal voltage. The voltage generator includes a switching unit configured to provide one of the first and second internal voltages as the first reference voltage in response to first and second switching control signals. | 2014-09-18 |
20140266415 | HARMONIC CANCELLATION CIRCUIT FOR AN RF SWITCH BRANCH - Disclosed is a harmonic cancellation circuit for an RF switch branch having a first transistor with a first gate terminal and a first body terminal, a second transistor having a second gate terminal coupled to the first body terminal, and having a second body terminal coupled to the first gate terminal. Also included is a first resistor coupled between a first coupling node and the second body terminal, and a second resistor coupled between a second coupling node and the first body terminal, wherein the first transistor and second transistor are adapted to generate an inverse phase third harmonic signal relative to a third harmonic signal generated by the RF switch branch, such that the inverse phase third harmonic signal is output through the first resistor and the second resistor to the RF switch branch to reduce the third harmonic signal. | 2014-09-18 |
20140266416 | ON-PACKAGE MULTIPROCESSOR GROUND-REFERENCED SINGLE-ENDED INTERCONNECT - A system of interconnected chips comprising a multi-chip module (MCM) includes a first processor chip, a second processor chip, and an MCM package configured to include the first processor chip, the second processor chip, and an interconnect circuit. The first processor chip is configured to include a first ground-referenced single-ended signaling (GRS) interface circuit. A first set of electrical traces fabricated within the MCM package and configured to couple the first GRS interface circuit to the interconnect circuit. The second processor chip is configured to include a second GRS interface circuit. A second set of electrical traces fabricated within the MCM package and configured to coupled the second GRS interface circuit to the interconnect circuit. | 2014-09-18 |
20140266417 | GROUND-REFERENCED SINGLE-ENDED SIGNALING CONNECTED GRAPHICS PROCESSING UNIT MULTI-CHIP MODULE - A system of interconnected chips comprising a multi-chip module (MCM) includes a first processor chip, a graphics processing cluster (GPC) chip, and an MCM package configured to include the first processor chip, the GPC chip, and an interconnect circuit. The first processor chip is configured to include a first ground-referenced single-ended signaling interface circuit. A first set of electrical traces fabricated within the MCM package and configured to couple the first single-ended signaling interface circuit to the interconnect circuit. The GPC chip is configured to include a second single-ended signaling interface circuit and to execute shader programs. A second set of electrical traces fabricated within the MCM package and configured to couple the second single-ended signaling interface circuit to the interconnect circuit. In one embodiment, each single-ended signaling interface advantageously implements ground-referenced single-ended signaling. | 2014-09-18 |
20140266418 | Stacked Chip System - A stacked chip system is provided to comprise a first chip, a second chip, a first group of through silicon vias (TSVs) connecting the first chip and second chip and comprising at least one first VSS TSV, at least one first VDD TSV, a plurality of first signal TSVs and at least one first redundant TSV and a second group of through silicon vias (TSVs) connecting the first chip and second chip and comprising at least one second VSS TSV, at least one second VDD TSV, a plurality of second signal TSVs and at least one second redundant TSV, wherein all the first group of TSVs are coupled by a first selection circuitry configured to select the at least one first redundant TSV and bypass at least one of the rest of the first group of TSVs, and wherein the at least one first redundant TSV and the at least second redundant TSV are coupled by a second selection circuitry configured to allow one of them to replace the other. | 2014-09-18 |
20140266419 | VOLTAGE CONTROLLER FOR RADIO-FREQUENCY SWITCH - One or more systems and techniques for limiting a voltage potential between an antenna and a radio-frequency switch circuit are provided. A voltage controller comprises a voltage generator, a voltage detection circuit and a switch cell. The voltage detection circuit is coupled to the voltage generator and to the switch cell, and the switch cell is coupled to a voltage source, and to a node between the radio-frequency switch circuit and the antenna. When the voltage potential exceeds a specified threshold, the voltage generator produces a voltage which the voltage detection circuit measures such that the voltage detection circuit activates the switch cell, resulting in a short circuit between the radio-frequency switch circuit and the voltage source. This serves to inhibit the voltage potential from exceeding the specified threshold, for example. | 2014-09-18 |
20140266420 | LOGARITHMIC AMPLIFIER WITH UNIVERSAL DEMODULATION CAPABILITIES - A logarithmic amplifier (LDA) is described that includes an amplifier configured to oscillate a modulated input signal, a feedback establishing a 180 degree phase shift between the amplifier input and the output and maintaining oscillation of the input signal, a parallel resonant circuit connected to the amplifier output causing the amplifier to resonate at or around a center frequency, and a controller connected to the amplifier input cyclically terminating oscillation of the input signal each time a pre-determined threshold of current is detected, the controller including a low pass filter configured to generate a second output signal having a repetition frequency. The LDA may be used for AM with or without a PLL and/or a superhetrodyne. The LDA may be implemented as a mixer and used for phase demodulation. The LDA may be used for phase demodulation. The LDA may be used in place of a low noise amplifier. | 2014-09-18 |
20140266421 | NANOSCALE ELECTROMECHANICAL PARAMETRIC AMPLIFIER - This disclosure provides systems, methods, and apparatus related to a parametric amplifier. In one aspect, a device includes an electron source electrode, a counter electrode, and a pumping electrode. The electron source electrode may include a conductive base and a flexible conductor. The flexible conductor may have a first end and a second end, with the second end of the flexible conductor being coupled to the conductive base. A cross-sectional dimension of the flexible conductor may be less than about 100 nanometers. The counter electrode may be disposed proximate the first end of the flexible conductor and spaced a first distance from the first end of the flexible conductor. The pumping electrode may be disposed proximate a length of the flexible conductor and spaced a second distance from the flexible conductor. | 2014-09-18 |
20140266422 | DC Blocker for a High Gain Complex Circuit - An amplifying circuit comprises an analog amplifying circuit having an analog input for receiving an analog input signal to be amplified and an analog output for outputting an amplified analog signal, wherein the amplifying circuit comprises an implementation of a complex transfer function. A feedback circuit has a feedback circuit input and a feedback circuit output, wherein the feedback circuit comprises an implementation of an inverse transfer function that is an estimation of an inverse of at least a DC component of the complex transfer function of the analog amplifying circuit. The feedback circuit input is arranged for receiving a signal that is based on the amplified analog signal of the analog amplifying circuit. The analog circuit is arranged for receiving a bias signal that is based on the feedback circuit output. | 2014-09-18 |
20140266423 | Envelope Tracking System with Internal Power Amplifier Characterization - An RF PA system that generates its own local characterization information. The RF PA system includes a PA to generate a RF output signal from a RF input signal, the PA powered by a supply voltage. A characterization block generates characterization information corresponding to a relationship between the supply voltage and performance (e.g., gain, power efficiency, distortion, receive band noise) of the RF PA system for a plurality of levels of one or more operating conditions (e.g., temperature, operating frequency, modulation format, antennae mismatch, etc.) of the RF PA system. An amplitude estimator block estimates an amplitude of the RF input signal. A supply control block generates a supply voltage control signal for controlling the supply voltage based on the characterization information and the amplitude of the RF input signal. | 2014-09-18 |
20140266424 | BI-DIRECTIONAL AMPLIFIER WITH A COMMON SIGNAL DETECTOR - A system of detecting signal power may include a first interface port configured to receive a first signal. The system may also include a second interface port communicatively coupled to the first interface port and configured to receive a second signal. The second interface port may be communicatively coupled to the first interface port such that the first signal propagates from the first interface port to the second interface port and such that the second signal propagates from the second interface port to the first interface port. The system may further include a common signal detector communicatively coupled between the first interface port and the second interface port such that the common signal detector is configured to receive both the first and second signals and is configured to detect a first power level of the first signal and a second power level of the second signal. | 2014-09-18 |
20140266425 | BI-DIRECTIONAL AMPLIFIER WITH A COMMON AMPLIFICATION PATH - According to some embodiments described herein, a bi-directional amplifier may include a first interface port configured to receive a first signal. The bi-directional amplifier may also include a second interface port. The second interface port may be communicatively coupled to the first interface port and may be configured to receive a second signal. The second interface port may be communicatively coupled to the first interface port such that the first signal propagates from the first interface port to the second interface port and such that the second signal propagates from the second interface port to the first interface port. The bi-directional amplifier may also include a common amplifier communicatively coupled between the first interface port and the second interface port such that the common amplifier is configured to receive and amplify both the first signal and the second signal. | 2014-09-18 |
20140266426 | SELF SETTING POWER SUPPLY USING NEGATIVE OUTPUT IMPEDANCE - A self-setting power supply monitors a supply current drawn by a power amplifier and sets a supply voltage based on the supply current to achieve efficient power operation. In order to maintain operation of the power amplifier above minimum operating conditions, the self-setting power supply sets the supply voltage to the minimum operating voltage when the supply current drops below a threshold bias current. When the supply current is above the threshold bias current, the self-setting power supply adjusts the supply voltage approximately proportionally to the supply current to maintain approximately constant gain of the power amplifier. | 2014-09-18 |
20140266427 | NOISE CONVERSION GAIN LIMITED RF POWER AMPLIFIER - A radio frequency (RF) power amplifier (PA) and an envelope tracking power supply are disclosed. The RF PA receives and amplifies an RF input signal to provide an RF transmit signal using an envelope power supply voltage. The envelope tracking power supply provides the envelope power supply voltage based on a setpoint, which has been constrained so as to limit a noise conversion gain (NCG) of the RF PA to not exceed a target NCG. | 2014-09-18 |
20140266428 | ENVELOPE TRACKING POWER SUPPLY VOLTAGE DYNAMIC RANGE REDUCTION - A radio frequency (RF) system includes an RF power amplifier (PA), which uses an envelope tracking power supply voltage to provide an RF transmit signal, which has an RF envelope; and further includes an envelope tracking power supply, which provides the envelope tracking power supply voltage based on a setpoint. RF transceiver circuitry, which includes envelope control circuitry and an RF modulator is disclosed. The envelope control circuitry provides the setpoint, such that the envelope tracking power supply voltage is clipped to form clipped regions and substantially tracks the RF envelope between the clipped regions, wherein a dynamic range of the envelope tracking power supply voltage is limited. The RF modulator provides an RF input signal to the RF PA, which receives and amplifies the RF input signal to provide the RF transmit signal. | 2014-09-18 |
20140266429 | POWER MANAGEMENT/POWER AMPLIFIER OPERATION UNDER DYNAMIC BATTERY DROPS - In one embodiment, a digital internal amplified voltage of power management circuitry is forced to an input threshold voltage upon a determination that a set of emergency conditions is satisfied, and is set to an input minimum battery voltage upon a determination that the set of emergency conditions is not satisfied. The emergency conditions may include determining that a battery voltage is less than a threshold voltage and determining that an input minimum battery voltage is less than an input threshold voltage. | 2014-09-18 |
20140266430 | Tube Amplifier Systems and Related Methods - An amplifier stage module circuit has a tube connected with an anode section, a grid section, a cathode section, and an attenuator section. The amplifier stage module circuit is configurable to provide any one of a plurality of selectable voices, each voice provided by a corresponding combination of selectively combinable voice components of the sections. | 2014-09-18 |
20140266431 | UNDER-SAMPLING DIGITAL PRE-DISTORTION ARCHITECTURE - A amplifier system may include a predistorter receiving an input signal to generate a predistortion signal, a first converter receiving the predistortion signal to generate a preamplified signal, a power amplifier receiving the preamplified signal to generate an output signal based on the preamplified signal and the input signal, and a second converter sampling the output signal to generate a feedback signal. The power amplifier may produce a distortion signal at a first frequency, the second converter may sample the output signal using a timing signal with a second frequency that is lower than the first frequency to generate the feedback signal, and the predistorter, based upon the feedback signal, may predistort the predistortion signal to reduce the distortion signal at the first frequency. | 2014-09-18 |
20140266432 | AMPLIFIER PHASE DISTORTION CORRECTION BASED ON AMPLITUDE DISTORTION MEASUREMENT - This application discloses correction circuitry for correcting a phase distortion in an amplification circuit by measuring an amplitude distortion and controlling a phase shifting component based upon the measured amplitude distortion. In one embodiment, a first amplitude distortion sensor is coupled to a first node of an amplification circuit, and a first phase shifter is coupled to a second node of the amplification circuit. Additionally, a first control circuit is coupled to the first amplitude sensor and to the first phase shifter. The first control circuit is configured to correlate a first amplitude distortion measured by the first amplitude distortion sensor to a first inferred phase distortion, and to generate a first phase correction signal based upon the first inferred phase distortion, and is configured to send the first phase correction signal towards the first phase shifter. | 2014-09-18 |
20140266433 | Systems and Methods for Optimizing Amplifier Operations - Methods and systems for optimizing amplifier operations are described. The described methods and systems particularly describe a feed-forward control circuit that may also be used as a feed-back control circuit in certain applications. The feed-forward control circuit provides a control signal that may be used to configure an amplifier in a variety of ways. | 2014-09-18 |
20140266434 | CIRCUITS FOR AND METHODS OF IMPLEMENTING A GAIN STAGE IN AN INTEGRATED CIRCUIT - A circuit for implementing a gain stage in an integrated circuit is described. The circuit comprises a first inductor formed in a first plurality of metal layers; a second inductor formed in a second plurality of metal layers, the second inductor coupled to a center tap of the first inductor; and wherein the second inductor has a diameter that is less than a diameter of the first inductor. A method of implementing a gain stage in an integrated circuit is also described. | 2014-09-18 |
20140266435 | TRANSLINEAR SLEW BOOST CIRCUIT FOR OPERATIONAL AMPLIFIER - A method of improving the slew rate of an amplifier is described where a differential pair of transistors receives a differential first control signal and second control signal. The tail current for the transistors is provided by a tail current regulator. The same control signals are applied to a slew boost controller, whose output increases as the differential between the control signals increase. The tail current regulator generates a bias signal that sets a minimum tail current. The tail current is controlled to be the minimum tail current until the slew boost output signal exceeds a threshold, whereupon the tail current increases in response to an increasing differential between the control signals. Common mode rejection is not adversely affected by the slew boost controller generating a slightly varying current under common mode conditions due to the minimum tail current. | 2014-09-18 |
20140266436 | Sense Amplifier - The present disclosure relates to a differential sense amplifier comprising first and second cross-coupled inverters with first and second complimentary storage nodes. A first current control element changes a current through the first cross-coupled inverter based upon an output of a second cross-coupled inverter, and a second current control element changes a current through the second cross-coupled inverter based upon an output of the first cross-coupled inverter. Other devices and methods are also disclosed. | 2014-09-18 |
20140266437 | ACTIVE CASCODE CIRCUIT USING BACKGATE CONTROL - An example embodiment of an active cascode circuit has a control circuit for control of the gate to source voltage (VGS) of at least one transistor in the active cascode circuit. The embodiment may be configured so that control of the VGS also controls the voltage Vin on the input. Vin may be adjusted without altering the device geometry or changing the drain current. This allows for better control and optimization of available headroom for the input voltage in low voltage designs and also results in higher active cascode circuit bandwidth and/or higher output impedance (Rout) for a given power level. | 2014-09-18 |
20140266438 | SIGNAL AMPLIFYING CIRCUIT FOR ELECTROMAGNETIC FLOW METER - In a signal amplifying circuit, a flow rate signal, inputted between flow rate signal input terminals of a connector, is inputted into one input terminal and the other input terminal of an instrumentation amplifier through resistive elements and subjected to differential amplification. The amplified output signal thereof is outputted to a sample hold circuit through a coupling capacitor. The flow rate signals, inputted between the flow rate signal input terminals, are buffered by buffer amplifiers, and output signals thereof are outputted to a fault detecting circuit. An interconnection, which connects one of the flow rate signal input terminals and a non-inverting input terminal of one of the buffer amplifiers, is guarded by a guard ring pattern. An interconnection, which connects the other one of the flow rate signal input terminals and a non-inverting input terminal of the other one of the buffer amplifiers, is guarded by another guard ring pattern. | 2014-09-18 |
20140266439 | METHODS AND SYSTEMS TO PROVIDE LOW NOISE AMPLIFICATION - An amplifier, including a voltage-to-current converter (V2I) to control an output current based on an input voltage, resistive degeneration circuitry to reduce baseband gain of the voltage-to-current converter, capacitive degeneration circuitry to increase passband gain of the voltage-to-current converter, and impedance control circuitry to compensate for negative input impedance of the capacitive degeneration circuitry. The V2I may include series-connected complimentary V2Is. The impedance control circuitry may include resistive negative feedback to provide a real part of input impedance, which may increase a frequency range for which the amplifier is linear. Capacitive degeneration and associated phase compensation may increase a frequency range for which the resistive feedback is negative. The amplifier may be configured as a single-input/single-output system and/or as a differential system. | 2014-09-18 |
20140266440 | OFFSET CANCELLATION WITH MINIMUM NOISE IMPACT AND GAIN-BANDWIDTH DEGRADATION - A system for cancelling offset includes a gain circuit. The gain circuit may include a transistor circuit connected to a pair of input nodes and configured to convert an input signal to an output signal so that the output signal has a gain compared with the input signal. The gain circuit also may include a pair of output nodes configured to receive the output signal from the transistor circuit. The gain circuit is configured to cause a voltage change at one of the output nodes relative to another output node, in response to the gain circuit receiving a feedback offset correction signal. This effectively cancels at least a portion of an offset in the output signal | 2014-09-18 |
20140266441 | THREE STAGE AMPLIFIER - A cascaded amplifier including a pre-amplifier stage having a pair of first transistors, each of the first transistors having a first gate terminal coupled to a first input voltage, a trans-conductive (gm) amplifier stage having a pair of second transistors, each of the second transistors having a second gate terminal coupled to a drain terminal of one of the first transistors, and an integrator amplifier stage having a pair of third transistors, each of the third transistors having a third gate terminal coupled to a drain node of one of the second transistors, each of the third transistors having their drain terminals coupled to an output voltage. | 2014-09-18 |
20140266442 | VOLTAGE CONTROLLED AMPLIFIER AND METHOD OF USING THE SAME - A simplified VCA circuit is presented. The VCA of the present invention uses fewer components and is less complex than prior art OTA-based VCAs. Further, the VCA of the present invention has improved total harmonic distortion (THD) and DC offset characteristics as compared to prior art VCAs. The VCA may be used to prevent clipping with the addition of clipping detection circuitry. | 2014-09-18 |
20140266443 | HIGH-FREQUENCY, BROADBAND AMPLIFIER CIRCUIT - According to one embodiment, a high-frequency, broadband amplifier circuit includes two drive elements, a matching circuit, a Balun circuit, a power supply, and a power supply circuit. The matching circuit includes two pattern circuits. The pattern circuits convey, in differential mode, the high-frequency signals supplied from the two drive elements. The Balun circuit converts the high-frequency signal to a single-end mode signal. The power supply circuit is connected one of the pattern circuits, and supplies at least the output of the power supply to the other pattern circuit. | 2014-09-18 |
20140266444 | POWER AMPLIFIER SYSTEM WITH SUPPLY MODULATION MITIGATION CIRCUITRY AND METHODS - A power amplifier system with supply modulation mitigation circuitry and methods is disclosed. The power amplifier system includes a regulator having an unregulated input and a regulated output along with a power amplifier having a supply input for receiving a supply current from the regulated output and having a signal input and a signal output that comprise a main signal path. The supply modulation mitigation circuitry is adapted to sense a supply modulation signal output from the regulator, generate a cancellation signal that is a scaled inverse of the supply modulation signal, and inject the cancellation signal into a node within the power amplifier system to sum the supply modulation signal and cancellation signal together to reduce the supply modulation signal from within the main signal path. | 2014-09-18 |
20140266445 | Low-Power Inverter-Based Differential Amplifier - A new inverter-based fully-differential amplifier is provided including one or more common-mode feedback transistors coupled to each inverter, which transistors operate in the liner region. Accordingly, due to the fully-differential nature of the new inverter-based fully-differential amplifier, the amplifier provides an improved Power Supply Rejection Ratio (PSRR), provides a reduced sensitivity to supply voltage and process or part variations, and does not require an auto-zeroing technique to be utilized, which ultimately saves power, all while utilizing the low-voltage and low-power advantages of an inverter-based design. | 2014-09-18 |
20140266446 | ACTIVE LUMPED ELEMENT CIRCULATOR - An integrated circuit can comprise: a first port, a second port, and a third port; and a plurality of microwave operational amplifiers coupled to each other and the first port, the second port, and the third port. The plurality of microwave operational amplifiers can be arranged to substantially pass a signal provided to the first port to the second port while substantially isolating the signal provided to the first port from the third port; the plurality of microwave operational amplifiers can be arranged to substantially pass a signal provided to the second port to the third port while substantially isolating the signal provided to the second port from the first port; and the plurality of microwave operational amplifiers can be arranged to substantially pass a signal provided to the third port to the first port while substantially isolating the signal provided to the third port from the second port. | 2014-09-18 |
20140266447 | VOLTAGE REGULATORS, AMPLIFIERS, MEMORY DEVICES AND METHODS - Circuits, devices and methods are provided, such as an amplifier (e.g., a voltage regulator) that includes a feedback circuit that supplies negative feedback through a feedback path. One such feedback path includes a capacitance coupled in series with a “one-way” isolation circuit through which a feedback signal is coupled. The “one-way” isolation circuit my allow the feedback signal to be coupled from a “downstream” node, such as an output node, to an “upstream” node, such as a node at which an error signal is generated to provide negative feedback. However, the “one-way” isolation circuit may substantially prevent variations in the voltage at the upstream node from being coupled to the capacitance in the isolation circuit. As a result, the voltage at the upstream node may quickly change since charging and discharging of the capacitance responsive to voltage variations at the upstream node may be avoided. | 2014-09-18 |
20140266448 | ADAPATIVE POWER AMPLIFIER - Exemplary embodiments are related to an envelope-tracking power amplifier. A device may include a first transistor of a plurality of transistors in a stacked configuration configured to receive a supply voltage varying with an envelope of a radio-frequency (RF) input signal. The device may further include a second transistor of the plurality in the stacked configuration coupled to a reference voltage and configured to receive a dynamic bias voltage varying inversely proportional to the supply voltage. | 2014-09-18 |
20140266449 | METHODS AND APPARATUSES FOR SLEW RATE ENHANCEMENT OF AMPLIFIERS - A circuit is disclosed to enhance slew rate of an amplifier. An amplifier includes an output, a first input, and a second input in a differential pair configuration. A slew rate enhancer includes a first slew rate enhancer and a second slew rate enhancer. The first slew direction enhancer is configured to detect a first slew rate condition in a first direction responsive to the first input and the second input and provide additional current for a first side of the differential pair of the amplifier during the first slew rate condition. The second slew direction enhancer is configured to detect a second slew rate condition in a second direction responsive to the first input and the second input and provide additional current for a second side of the differential pair of the amplifier during the second slew rate condition. | 2014-09-18 |
20140266450 | METHOD AND APPARATUS FOR IMPLEMENTING WIDE DATA RANGE AND WIDE COMMON-MODE RECEIVERS - Embodiments of disclosed configurations include a circuit and system for a sense amplifier having a sensing circuit changing an output voltage at an output node based on a time that is defined by the output voltage reaching a threshold voltage level. The sensing circuit changes the output voltage at the output node before the time. In addition, a regeneration circuit amplifies the changed output voltage at the time. The sense amplifier offers sufficient voltage headroom to improve operation speed and power efficiency. | 2014-09-18 |
20140266451 | POWER AMPLIFIER WITH WIDE DYNAMIC RANGE AM FEEDBACK LINEARIZATION SCHEME - Circuitry, which includes a package interface, a radio frequency (RF) amplification circuit, and a closed-loop gain linearization circuit. The package interface receives an RF signal and provides an amplified RF signal. The RF amplification circuit amplifies the RF signal in accordance with a gain of the RF amplification circuit so as to generate the amplified RF signal. In one embodiment, the closed-loop gain linearization circuit is configured to endogenously establish a target gain magnitude using the RF signal and linearize the gain of the RF amplification circuit in accordance with the target gain magnitude. By endogenously establishing the target gain magnitude using the RF signal, the closed-loop gain linearization circuit can provide linearity with greater independence from external control circuitry. | 2014-09-18 |
20140266452 | RF POWER AMPLIFIER WITH TOTAL RADIATED POWER STABILIZATION - A radio frequency (RF) amplification circuit and a closed-loop amplitude linearization circuit are disclosed. The RF amplification circuit amplifies an RF signal to generate an amplified RF signal. The RF amplification circuit and the closed-loop amplitude linearization circuit form a fast control loop and a slow control loop. The slow control loop estimates a total radiated power (TRP) from the RF amplification circuit to create a TRP estimate using a representation of the amplified RF signal, and controls a fast loop gain of the fast control loop based on the TRP estimate. The fast control loop applies a gain adjustment to the RF amplification circuit based on the fast loop gain and a difference between a target reference amplitude and a measured feedback amplitude. The gain adjustment controls amplitude distortion in the RF amplification circuit. The fast loop gain controls TRP-drift in the RF amplification circuit. | 2014-09-18 |
20140266453 | TRANSIMPEDANCE AMPLIFIER (TIA) CIRCUIT AND METHOD - A TIA circuit and method are provided that merge the automatic gain control function with the bandwidth adjustment function to allow the TIA circuit to operate over a wide dynamic range at multiple data rates. The TIA circuit has an effective resistance that is adjustable for adjusting the gain and the bandwidth of the TIA circuit. The mechanism of the TIA circuit that is used to adjust the effective resistance, and hence the gain and bandwidth of the TIA circuit, is temperature independent, and as such, the performance of the TIA circuit is not affected by temperature variations. | 2014-09-18 |
20140266454 | LNA with Linearized Gain Over Extended Dynamic Range - A low noise amplifier including a variable gain amplifier stage configured to accept an input signal and to provide a load driving signal; a tunable bandpass filter connected as a load to the variable gain amplifier stage, wherein the bandpass filter includes a cross-coupled transistor pair, and at least one cross-coupled compensation transistor pair biased in a subthreshold region configured to add a transconductance component when the load driving signal is of a magnitude large enough to decreases a transconductance of the cross-coupled transistor pair; and, a controller circuit configured to tune the bandpass filter. The filter can be tuned in respect to the frequency and the quality factor Q. | 2014-09-18 |
20140266455 | VARIABLE IMPEDANCE MATCH AND VARIABLE HARMONIC TERMINATIONS FOR DIFFERENT MODES AND FREQUENCY BANDS - An amplifier with switchable and tunable harmonic terminations and a variable impedance matching network is presented. The amplifier can adapt to different modes and different frequency bands of operation by appropriate switching and/or tuning of the harmonic terminations and/or the variable impedance matching network. | 2014-09-18 |
20140266456 | DEVICE AND METHOD FOR CONTROLLING POWER AMPLIFIER - A device for controlling operation of a power amplifier includes a detector, a reference signal generator and a controller. The detector is configured to detect a voltage level of an output signal of the power amplifier with respect to a predetermined boost threshold and to generate a corresponding detection signal and a reference signal. The controller is configured to provide a supply voltage to an output transistor of the power amplifier based on a comparison of the detection signal and the reference signal, the supply voltage being a no boost voltage, which is substantially the same as a supply voltage, when the comparison indicates that the voltage level is within the predetermined boost threshold, and the supply voltage being one of multiple boost voltages when the detection signal indicates that the voltage level is beyond the predetermined boost threshold. The controller generates the boost voltages by boosting the supply voltage. | 2014-09-18 |
20140266457 | GAIN AND PHASE CALIBRATION FOR CLOSED LOOP FEEDBACK LINEARIZED AMPLIFIERS - Embodiments of a radio frequency (RF) amplification device having an RF amplification circuit and an amplifier control circuit operably associated with the RF amplification circuit are disclosed. The RF amplification circuit is configured to amplify an RF signal in accordance with a transfer function. The amplifier control circuit includes a closed-loop linearization circuit and a calibration circuit. The closed-loop linearization circuit is configured to be activated so that the transfer function defines a closed-loop response and inactive so that the transfer function defines an open-loop response. For example, the closed-loop linearization circuit may become inactive at small-signal power levels. Accordingly, the amplifier control circuit also includes a calibration circuit configured to reduce a difference between the open-loop response and the closed-loop response of the transfer function. In this manner, the performance of the RF amplification device is maintained while the closed-loop linearization circuit is inactive. | 2014-09-18 |
20140266458 | RF REPLICATOR FOR ACCURATE MODULATED AMPLITUDE AND PHASE MEASUREMENT - The disclosure provides a communication circuit including an amplification circuit, a replicator circuit, and a correction circuit. Specifically, the amplification circuit generates an amplified signal. The replicator circuit emulates the amplification circuit and generates a replicated signal that approximates the amplified signal. The replicated signal is used by the correction circuit to generate control signals for controlling the amplification circuit. | 2014-09-18 |
20140266459 | RF POWER AMPLIFIER WITH PM FEEDBACK LINEARIZATION - Circuitry, which includes a package interface, an RF amplification circuit, and a closed-loop phase linearization circuit, is disclosed. The package interface receives an RF signal and provides an amplified RF signal. The RF amplification circuit amplifies the RF signal to generate the amplified RF signal, such that an intermediate RF signal is generated during amplification of the RF signal. The closed-loop phase linearization circuit endogenously establishes a target phase of the amplified RF signal using the RF signal. Further, the closed-loop phase linearization circuit applies a phase-shift to the intermediate RF signal based on a difference between the target phase and a measured phase, which is representative of a phase of the amplified RF signal, wherein the phase-shift reduces phase distortion in the amplified RF signal. | 2014-09-18 |
20140266460 | Scalable Periphery Tunable Matching Power Amplifier - A scalable periphery tunable matching power amplifier is presented. Varying power levels can be accommodated by selectively activating or deactivating unit cells of which the scalable periphery tunable matching power amplifier is comprised. Tunable matching allows individual unit cells to see a constant output impedance, reducing need for transforming a low impedance up to a system impedance and attendant power loss. The scalable periphery tunable matching power amplifier can also be tuned for different operating conditions such as different frequencies of operation or different modes. | 2014-09-18 |
20140266461 | SPLIT AMPLIFIERS WITH IMPROVED LINEARITY - Split amplifiers with configurable gain and linearization circuitry are disclosed. In an exemplary design, an apparatus includes first and second amplifier circuits and a linearization circuit, which may be part of an amplifier. The first and second amplifier circuits are coupled in parallel and to an amplifier input. The linearization circuit is also coupled to the amplifier input. The first and second amplifier circuits are enabled in a high-gain mode. One of the first and second amplifier circuits is enabled in a low-gain mode. The linearization circuit is enabled in the second mode and disabled in the first mode. The amplifier is split into multiple sections. Each section includes an amplifier circuit and is a fraction of the amplifier. High linearly may be obtained using one amplifier circuit and the linearization circuit in the low-gain mode. | 2014-09-18 |
20140266462 | LOW POWER CONSUMPTION ADAPTIVE POWER AMPLIFIER - An adaptive power amplifier that may be used in a wireless communication device is configured to adjust its load line or output impedance, the number of active amplifier cells in each amplification stage, the bias of the active amplifiers, and the supply voltage input capacitive load in accordance with a supply voltage modulation type provided to the power amplifier. The supply voltage modulation types include ET, APT, DC-DC, dual, multi-state or fixed voltage supply voltages. A supply voltage converter, signaled by a baseband processor, generates the selected type of supply voltage modulation for the adaptive power amplifier. The baseband processor may also provide a control interface signal to a controller within the adaptive power amplifier. The controller, based on the received control interface signal provides a configuration signal that configures the impedance, the number of active amplifier cells, the bias of the active amplifier cells, and the supply voltage capacitive load to optimize the adaptive power amplifier based on the supply voltage modulation type. | 2014-09-18 |
20140266463 | LINEAR AMPLIFIER ARRANGEMENT FOR HIGH-FREQUENCY SIGNALS - The invention relates to an amplifier arrangement for high-frequency signals. Said amplifier arrangement comprises a signal input (IN) for receiving high-frequency signals (RF | 2014-09-18 |