38th week of 2014 patent applcation highlights part 57 |
Patent application number | Title | Published |
20140264861 | SPUTTER ETCH PROCESSING FOR HEAVY METAL PATTERNING IN INTEGRATED CIRCUITS - A method for fabricating one or more conductive lines in an integrated circuit includes providing a layer of copper containing conductive metal in a multi-layer structure fabricated upon a wafer, providing a first hard mask layer over the layer of copper containing conductive metal, performing a first sputter etch of first hard mask layer using a chlorine-based plasma or a sulfur fluoride-based plasma, and performing a second sputter etch of first hard mask layer using a second plasma, wherein a portion of the layer of copper containing conductive metal residing below a portion of the first hard mask layer that remains after the second sputter etch forms the one or more conductive lines. In one embodiment, the second plasma is a fluorocarbon-based plasma. | 2014-09-18 |
20140264862 | Interconnect Structure and Method - A semiconductor device comprises a first semiconductor chip including a first substrate and a plurality of first metal lines formed over the first substrate and a second semiconductor chip bonded on the first semiconductor chip, wherein the second semiconductor chip comprises a second substrate and a plurality of second metal lines formed over the second substrate. The semiconductor device further comprises a conductive plug coupled between the first metal lines and the second metal lines, wherein the conductive plug comprises a first portion formed over a first side of a hard mask layer, wherein the first portion is of a first width and a second portion formed over a second side of the hard mask layer, wherein the second portion is of a second width greater than or equal to the first width. | 2014-09-18 |
20140264863 | Conductive Line System and Process - A system and method for providing a conductive line is provided. In an embodiment the conductive line is formed by forming two passivation layers, wherein each passivation layer is independently patterned. Once formed, a seed layer is deposited into the two passivation layers, and a conductive material is deposited to fill and overfill the patterns within the two passivation layers. A planarization process such as a chemical mechanical polish may then be utilized in order to remove excess conductive material and form the conductive lines within the two passivation layers. | 2014-09-18 |
20140264864 | INTEGRATED CIRCUIT STRUCTURE AND FORMATION - One or more integrated circuit structures and techniques for forming such integrated circuit structures are provided. The integrated circuit structures comprise a conductive structure that is formed within a trench in a dielectric layer on a substrate. The conductive structure is formed over a barrier layer formed within the trench, or the conductive structure is formed over a liner formed over the barrier layer. At least some of the dielectric layer, the barrier layer, the liner and the conductive structure are removed, for example, by chemical mechanical polishing, such that a step height exists between a top surface of the substrate and a top surface of the dielectric layer. Removing these layers in this manner removes areas where undesired interlayer peeling is likely to occur. A conductive cap is formed on the conductive structure. | 2014-09-18 |
20140264865 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device may include: a barrier layer; an adhesion layer disposed over the barrier layer; a metallization layer disposed over the adhesion layer, wherein the metallization layer is part of a final metallization level of the semiconductor device. | 2014-09-18 |
20140264866 | CHEMICAL DIRECT PATTERN PLATING INTERCONNECT METALLIZATION AND METAL STRUCTURE PRODUCED BY THE SAME - A semiconductor structure with an improved metal structure is described. The semiconductor structure can include a substrate having an upper surface, an interconnect layer over the upper surface, and an additional structure deposited over the interconnect layer. The interconnect layer can include a patterned seed layer over the substrate, at least two metal lines over the seed layer, and a dielectric material between adjacent metal lines. A barrier layer can be deposited over the at least two metal lines. Methods of making the semiconductor structures are also described. | 2014-09-18 |
20140264867 | METHOD OF FORMING HYBRID DIFFUSION BARRIER LAYER AND SEMICONDUCTOR DEVICE THEREOF - In a method of fabricating a semiconductor device, an opening is formed inside a dielectric layer above a semiconductor substrate. The opening has a wall. At least one diffusion barrier material is then formed over the wall of the opening by at least two alternating steps, which are selected from the group consisting of a process of physical vapor deposition (PVD) and a process of atomic layer deposition (ALD). A liner layer is formed over the at least one diffusion barrier material. | 2014-09-18 |
20140264868 | WAFER-LEVEL DIE ATTACH METALLIZATION - Embodiments of a semiconductor wafer having wafer-level die attach metallization on a back-side of the semiconductor wafer, resulting semiconductor dies, and methods of manufacturing the same are disclosed. In one embodiment, a semiconductor wafer includes a semiconductor structure and a front-side metallization that includes front-side metallization elements for a number of semiconductor die areas. The semiconductor wafer also includes vias that extend from a back-side of the semiconductor structure to the front-side metallization elements. A back-side metallization is on the back-side of the semiconductor structure and within the vias. For each via, one or more barrier layers are on a portion of the back-side metallization that is within the via and around a periphery of the via. The semiconductor wafer further includes wafer-level die attach metallization on the back-side metallization other than the portions of the back-side metallization that are within the vias and around the peripheries of the vias. | 2014-09-18 |
20140264869 | Semiconductor Device - A semiconductor device comprises a substrate having a first side with a first surface and a second side with a second surface, a recessed through silicon via (TSV) penetrating the substrate and forming a first step height with respect to the first surface of the first side, a first extruded backside redistribution line (RDL) filling in the first step height and engaging with the recessed through silicon via. | 2014-09-18 |
20140264870 | METHOD OF BACK-END-OF-LINE (BEOL) FABRICATION, AND DEVICES FORMED BY THE METHOD - In a method for forming a semiconductor device, an interconnect structure over a semiconductor substrate is provided. The interconnect structure includes a first dielectric layer and a conductive pattern inside a trench in the first dielectric layer. An etch stop layer (ESL) is formed over the interconnect structure. An interface layer comprising elemental silicon is deposited over the ESL. A second dielectric layer is then formed over the interface layer. | 2014-09-18 |
20140264871 | Method to Increase Interconnect Reliability - Methods to increase metal interconnect reliability are provided. Methods include forming a conformal barrier layer within an opening in a semiconductor device structure and forming a copper alloy material above the conformal barrier layer. Next, removing the copper alloy material that extends beyond the opening. Removing native oxide from a top surface of the copper alloy material. Further, annealing or applying a plasma treatment to the copper alloy material. Finally, forming a capping layer above the copper alloy material. Notably, near the top of the copper alloy material, smaller copper grain growth may be present. Furthermore, more non-copper alloy atoms are present near the top of the copper alloy material than the bulk of the copper alloy material. | 2014-09-18 |
20140264872 | Metal Capping Layer for Interconnect Applications - An integrated circuit structure includes a semiconductor substrate and a dielectric layer over the semiconductor substrate. The integrated circuit structure further includes a conductive wiring in the dielectric layer. The integrated circuit structure also includes a first metallic capping layer over the conductive wiring and a second metallic capping layer over the first metallic capping layer. The second metallic capping layer has a width substantially the same as a width of the first metallic capping layer. | 2014-09-18 |
20140264873 | Interconnection Structure And Method For Semiconductor Device - A semiconductor device is disclosed. The device includes a substrate, a first dielectric layer disposed over the substrate and a metal structure disposed in the first dielectric layer and below a surface of the first dielectric layer. The metal structure has a such shape that having an upper portion with a first width and a lower portion with a second width. The second width is substantially larger than the first width. The semiconductor device also includes a sub-structure of a second dielectric positioned between the upper portion of the metal structure and the first dielectric layer. | 2014-09-18 |
20140264874 | Electro-Migration Barrier for Cu Interconnect - Integrated circuit devices and method of forming them. The devices include a dielectric barrier layer formed over a copper-containing metal interconnect structure. The dielectric barrier layer inhibits electro-migration of Cu. The dielectric barrier layer includes a metal-containing layer that forms an interface with the interconnect structure. Incorporating metal within the interfacial layer improves adhesion of the dielectric barrier layer to copper lines and the like and provides superior electro-migration resistance over the operating lifetime of the devices. | 2014-09-18 |
20140264875 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a copper interconnect provided in a trench in an insulation film, a metal film provided on the insulation film along a boundary between the insulation film and the copper interconnect, a barrier metal provided between an inner wall of the trench and the copper interconnect and extending over the metal layer, a first metal cap to cover the copper interconnect and the barrier metal located over the metal film, and a second metal cap to continuously cover the first metal cap, the barrier metal and the metal film. | 2014-09-18 |
20140264876 | MULTI-LAYER BARRIER LAYER STACKS FOR INTERCONNECT STRUCTURES - A semiconductor device includes a recess defined in a dielectric layer and an interconnect structure defined in the recess. The interconnect structure includes a first barrier layer lining the recess, the first barrier layer including an alloy of tantalum and a first transition metal other than tantalum, wherein a first interface between the first barrier layer and the dielectric layer has a first stress level. A second barrier layer is positioned on the first barrier layer, the second barrier layer including at least one of tantalum and tantalum nitride, wherein a second interface between the second barrier layer and the first barrier layer has a second stress level that is less than the first stress level. The interconnect structure further includes a fill material substantially filling the recess. | 2014-09-18 |
20140264877 | METALLIZATION SYSTEMS OF SEMICONDUCTOR DEVICES COMPRISING A COPPER/SILICON COMPOUND AS A BARRIER MATERIAL - A semiconductor device includes a first metallization layer positioned above a substrate of the semiconductor device, the metallization layer including a dielectric material and a copper-containing metal region embedded in the dielectric material. The semiconductor device also includes a conductive barrier layer positioned along substantially an entirety of an interface between the copper-containing metal region and the dielectric material, the conductive barrier layer including a copper/silicon compound that is in direct contact with the dielectric material along substantially the entirety of the interface. | 2014-09-18 |
20140264878 | COPPER INTERCONNECT STRUCTURES AND METHODS OF MAKING SAME - A structure and method of making the structure. The structure includes a dielectric layer on a substrate; a first wire formed in a first trench in the dielectric layer, a first liner on sidewalls and a bottom of the first trench and a first copper layer filling all remaining space in the first trench; a second wire formed in a second trench in the dielectric layer, a second liner on sidewalls and a bottom of the second trench and a second copper layer filling all remaining space in the second trench; and an electromigration stop formed in a third trench in the dielectric layer, a third liner on sidewalls and a bottom of the third trench and a third copper layer filling all remaining space in the third trench, the electromigration stop between and abutting respective ends of the first and second wires. | 2014-09-18 |
20140264879 | COPPER-FILLED TRENCH CONTACT FOR TRANSISTOR PERFORMANCE IMPROVEMENT - Methods of fabricating a first contact to a semiconductor device, which fundamentally comprises providing a semiconductor device formed on a substrate. The substrate further includes a conductive surface. A dielectric layer is formed over the substrate and has an opening exposing the conductive surface. The opening extends an entire length of the semiconductor device, partway down the entire length of the device, extending from the device onto adjacent field of the device, or and a combination thereof. A barrier layer is formed within the opening. A copper containing material fills the opening to form a first contact to the semiconductor device. | 2014-09-18 |
20140264880 | INTERCONNECT STRUCTURE AND METHOD OF FORMING THE SAME - An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower conductive feature in a lower low-k (LK) dielectric layer; a first etch stop layer (ESL) over the lower conductive feature, wherein the first ESL comprises a metal compound; an upper LK dielectric layer over the first ESL; and an upper conductive feature in the upper LK dielectric layer, wherein the upper conductive feature extends through the first ESL and connected to the lower conductive feature. The interconnect structure may further include a second ESL between the upper LK dielectric layer and the first ESL, or between the first ESL and the lower conductive feature, wherein the second ESL comprises a silicon compound. | 2014-09-18 |
20140264881 | METHODS AND STRUCTURES TO FACILITATE THROUGH-SILICON VIAS - In some implementations, a metal pad for capturing or interfacing with through-silicon vias has a plurality of openings through it. Another metal pad on an upper level can also include a plurality of openings. The metal pads are vertically aligned and the placement of the openings in each metal pad is such that the openings are laterally offset and substantially do not directly overlie or underlie one another. As seen in a top-down view, the through-silicon via etch may “see” a metal etch stop that extends continuously across the width of the via, although different portions of the etch stop may be distributed on different vertical levels due to the presence of openings in the metal pads. The openings in the metal pads facilitate integrated circuit fabrication their respective levels and the aggregate structure formed by the metal pads provides an effective etch stop for the through-silicon via etch. | 2014-09-18 |
20140264882 | Forming Fence Conductors Using Spacer Etched Trenches - A spacer etching process produces ultra-narrow conductive lines in a plurality of semiconductor dice. Trenches are formed in a first dielectric then a sacrificial film is deposited onto the first dielectric and the trench surfaces formed therein. Planar sacrificial film is removed from the face of the first dielectric and bottom of the trenches, leaving only sacrificial films on the trench walls. A gap between the sacrificial films on the trench walls is filled in with a second dielectric. A portion of the second dielectric is removed to expose tops of the sacrificial films. The sacrificial films are removed leaving ultra-thin gaps that are filled in with a conductive material. The tops of the conductive material in the gaps are exposed to create “fence conductors.” Portions of the fence conductors and surrounding insulating materials are removed at appropriate locations to produce desired conductor patterns comprising isolated fence conductors. | 2014-09-18 |
20140264883 | Interconnect Structure and Method of Forming Same - A semiconductor device comprises a first chip bonded on a second chip. The first chip comprises a first substrate and first interconnection components formed in first IMD layers. The second chip comprises a second substrate and second interconnection components formed in second IMD layers. The device further comprises a first conductive plug formed within the first substrate and the first IMD layers, wherein the first conductive plug is coupled to a first interconnection component and a second conductive plug formed through the first substrate and the first IMD layers and formed partially through the second IMD layers, wherein the second conductive plug is coupled to a second interconnection component. | 2014-09-18 |
20140264884 | WLCSP Interconnect Apparatus and Method - Disclosed herein is an interconnect apparatus comprising a substrate having a land disposed thereon and a passivation layer disposed over the substrate and over a portion of the land. An insulation layer is disposed over the substrate and has an opening disposed over at least a portion of the land. A conductive layer is disposed over a portion of the passivation layer and in electrical contact with the land. The conductive layer has a portion extending over at least a portion of the insulation layer. The conductive layer comprises a contact portion disposed over at least a portion of the land. The insulation layer avoids extending between the land and the contact portion. A protective layer may be disposed over at least a portion of the conductive layer and may optionally have a thickness of at least 7 μm. | 2014-09-18 |
20140264885 | Apparatus and Method for Wafer Separation - A plurality of macro and micro alignment marks may be formed on a wafer. The macro alignment marks may be formed in pairs at opposite edges of the wafer. The micro alignment marks may be formed to align to streets on the wafer along a first and second direction. A molding compound may be formed on the wafer. The macro alignment marks may be exposed from the molding compound. A pair of the micro alignment marks may be exposed from the molding compound at opposite ends of the streets along the first and the second direction. The wafer may be aligned to a dicing tool using pairs of the macro alignment marks. The dicing tool may be aligned to the streets using pairs of the micro alignment marks. The wafer may be diced using successive pairs of micro alignment marks along the first and second direction. | 2014-09-18 |
20140264886 | Forming Fence Conductors Using Spacer Pattern Transfer - A spacer transfer process produces sub-lithographic patterns of conductive lines in a semiconductor die. A dielectric then a conductive material are deposited onto a face of a semiconductor substrate. A sacrificial dielectric is deposited on the conductive material and portions thereof are removed to form at least one trench comprising walls and a bottom exposing the conductive material. A hard mask is deposited over the sacrificial dielectric including the walls and bottom of the trench. Then the hard mask is removed therefrom except from the walls of the trench. Thereafter, the remaining sacrificial dielectric is removed leaving only the hard mask from the walls of the trench. Then all conductive material not protected by the remaining hard mask is removed. Thereafter, the hard mask is removed exposing a sub-lithographic pattern of fence conductors wherein portions thereof are removed at appropriate locations to produce desired conductor patterns comprising isolated fence conductors. | 2014-09-18 |
20140264887 | ORIENTED CRYSTAL NANOWIRE INTERCONNECTS - Interconnects for semiconductors formed of materials that exhibit crystallographic anisotropy of the resistivity size effect such that line resistivity in one crystallographic orientation becomes lower than the resistivity in the other directions and methods of fabrication and use thereof are described. A wire having a dimension that results in an increase in the electrical resistivity of the wire can be formed of a material with a conductive anisotropy due to crystallographic orientation relative to the direction of current flow that minimizes the increase in the electrical resistivity as compared to the other orientations at that dimension. | 2014-09-18 |
20140264888 | SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package structure includes a chip unit, a package unit and an electrode unit. The chip unit includes at least one semiconductor chip. The semiconductor chip has an upper surface, a lower surface, and a surrounding peripheral surface connected between the upper and the lower surfaces, and the semiconductor chip has a first conductive pad and a second conductive pad disposed on the lower surface thereof. The package unit includes a package body covering the upper surface and the surrounding peripheral surface of the semiconductor chip. The package body has a first lateral portion and a second lateral portion respectively formed on two opposite lateral sides thereof. The electrode unit includes a first electrode structure covering the first lateral portion and a second electrode structure covering the second lateral portion. The first and the second electrode structures respectively electrically contact the first and the second conductive pads. | 2014-09-18 |
20140264889 | SEMICONDUCTOR DEVICE CHANNELS - A semiconductor device and a method of manufacture are provided. The semiconductor device includes one or more layers having channels adapted to carry signals or deliver power. The semiconductor device may include at least two channels having a substantially equivalent cross-sectional area. Conductors in separate channels may have different cross-sectional areas. A spacer dielectric on a side of a channel may be included. The method of manufacture includes establishing a signal conductor layer including a first channel and a second channel having a substantially equivalent cross-sectional area, introducing a spacer dielectric on a side of the second channel, introducing a first conductor in the first channel having a first cross-sectional area, and introducing a second conductor in the second channel having a second cross-sectional area where the second cross-sectional area is smaller than the first cross-sectional area. | 2014-09-18 |
20140264890 | NOVEL PILLAR STRUCTURE FOR USE IN PACKAGING INTEGRATED CIRCUIT PRODUCTS AND METHODS OF MAKING SUCH A PILLAR STRUCTURE - One illustrative pillar disclosed herein includes a bond pad conductively coupled to an integrated circuit and a pillar comprising a base that is conductively coupled to the bond pad, wherein the base has a first lateral dimension, and an upper portion that is conductively coupled to the base, wherein the upper portion has a second lateral dimension that is less than the first lateral dimension. A method disclosed herein of forming a pillar includes forming a base such that it is conductively coupled to a bond pad on an integrated circuit product and, after forming the base, forming an upper portion such that it is conductively coupled to the base. | 2014-09-18 |
20140264891 | FORMING FENCE CONDUCTORS IN AN INTEGRATED CIRCUIT - A spacer etching process produces ultra-narrow conductive lines in a plurality of semiconductor dice. Sub-lithographic patterning of the conductive lines are compatible with existing aluminum and copper backend processing. A first dielectric is deposited onto the semiconductor dice and trenches are formed therein. A conductive film is deposited onto the first dielectric and the trench surfaces. All planar conductive film is removed from the faces of the semiconductor dice and bottoms of the trenches, leaving only conductive films on the trench walls, whereby “fence conductors” are created therefrom. Thereafter the gap between the conductive films on the trench walls are filled in with insulating material. A top portion of the insulated gap fill is thereafter removed to expose the tops of the fence conductors. Portions of the fence conductors and surrounding insulating materials are removed at appropriate locations to produce desired conductor patterns comprising isolated fence conductors. | 2014-09-18 |
20140264892 | SEMICONDUCTOR DEVICE WITH DUMMY LINES - A semiconductor device includes a first main strap, a second main strap, a plurality of first sub straps, a plurality of second sub straps, and a plurality of dummy lines. The first main strap is extended in a first direction. The second main strap is extended in the first direction. A plurality of first sub straps is branched from the first main strap. The plurality of second sub straps is branched from the second main strap. The plurality of dummy lines is positioned between the first main strap and the second main strap. Each of the plurality of dummy lines is positioned between each of the plurality of first sub straps and each of the plurality of second sub straps. Each of the dummy lines is spaced apart from the first main strap, the second main strap, each of the first sub straps and each of the second sub straps. | 2014-09-18 |
20140264893 | PITCH-HALVING INTEGRATED CIRCUIT PROCESS AND INTEGRATED CIRCUIT STRUCTURE MADE THEREBY - A pitch-halving IC process is described. Parallel base line patterns are formed over a substrate, each being connected with a hammerhead pattern at a first or second side of the base line patterns, wherein the hammerhead patterns are arranged at the first side and the second side alternately, and the hammerhead patterns at the first or second side are arranged in a staggered manner. The above patterns are trimmed. A spacer is formed on the sidewalls of each base line pattern and the corresponding hammerhead pattern, including a pair of derivative line patterns, a loop pattern around the hammerhead pattern, and a turning pattern at the other end of the base line pattern. The base line patterns and the hammerhead patterns are removed. A portion of each loop pattern and at least a portion of each turning pattern are removed to disconnect each pair of derivative line patterns. | 2014-09-18 |
20140264894 | SYSTEM AND METHOD FOR ARBITRARY METAL SPACING FOR SELF-ALIGNED DOUBLE PATTERNING - An integrated circuit includes a first conductive structure of a device configured to have a first voltage potential, a second conductive structure of the device configured to have a second voltage potential that is different than the first voltage potential, and a peacekeeper structure disposed between and separating the first conductive structure and the second conductive structure. The peacekeeper structure is separated from at least one of the first conductive structure and the second conductive structure by a fixed spacing distance for conductive lines for a self-aligned double patterning (“SADP”) process from the integrated circuit was formed. | 2014-09-18 |
20140264895 | Semiconductor Devices and Methods of Manufacture Thereof - Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes forming an etch stop layer over a workpiece. The etch stop layer has an etch selectivity to a material layer of the workpiece of greater than about 4 to about 30. The method includes forming an insulating material layer over the etch stop layer, and patterning the insulating material layer using the etch stop layer as an etch stop. | 2014-09-18 |
20140264896 | Structure and Method for a Low-K Dielectric with Pillar-Type Air-Gaps - A circuit device having an interlayer dielectric with pillar-type air gaps and a method of forming the circuit device are disclosed. In an exemplary embodiment, the method comprises receiving a substrate and depositing a first layer over the substrate. A copolymer layer that includes a first constituent polymer and a second constituent polymer is formed over the first layer. The first constituent polymer is selectively removed from the copolymer layer. A first region of the first layer corresponding to the selectively removed first constituent polymer is etched. The etching leaves a second region of the first layer underlying the second constituent polymer unetched. A metallization process is performed on the etched substrate, and the first layer is removed from the second region to form an air gap. The method may further comprise depositing a dielectric material within the etched first region. | 2014-09-18 |
20140264897 | DAMASCENE CONDUCTOR FOR A 3D DEVICE - A method of forming a conductor structure can result in vertical sidewalls. The method deposits a lining over a plurality of spaced-apart stacks of active layers. An isolation material is formed over the lining, over and in between the spaced-apart stacks. A plurality of trenches in the isolation material is arranged to cross over the plurality of spaced-apart stacks of active strips, leaving at least a residue of the lining on a bottom of the trenches between the stacks of active strips and over a sidewall of the spaced-apart stacks of active strips. The residue of the lining on the bottom of the trenches and the sidewalls of the spaced-apart stacks of active layers is selectively removed. Then the plurality of trenches is filled with conductive or semiconductor material to form the damascene structure. | 2014-09-18 |
20140264898 | 3-D IC Device with Enhanced Contact Area - A device includes a substrate with a recess, having a bottom and sides, extending into the substrate from the substrate's upper surface. The sides include first and second sides oriented transversely to one another. A stack of alternating active and insulating layers overlie the substrate's surface and the recess. At least some of the active layers have an upper and lower portions extending along upper and lower planes over and generally parallel to the upper surface and to the bottom, respectively. The active layers have first and second upward extensions positioned along the first and second sides to extend from the lower portions of their respective active layers. Conductive strips adjoin the second upward extensions of the said active layers. The conductive strips can comprise sidewall spacers on the sides of the second upward extensions, the conductive strips connected to overlying conductors by interlayer conductors. | 2014-09-18 |
20140264899 | Pattern Modification with a Preferred Position Function - A method for pattern modification for making an integrated circuit layout is disclosed. The method includes determining a feature within a pattern of the integrated circuit layout that can be rearranged; determining a range in which the feature can be repositioned; for the feature, determining a preferred position function that exhibits extreme values at preferable positions; and rearranging the position of the feature within the range to match an extreme value of the function. | 2014-09-18 |
20140264900 | ANISOTROPIC CONDUCTOR AND METHOD OF FABRICATION THEREOF - An anisotropic conductor and a method of fabrication thereof. The anisotropic conductor includes an insulating matrix and a plurality of nanoparticles disposed therein. A first portion of the plurality of nanoparticles provides a conductor when subjected to a voltage and/or current pulse. A second portion of the plurality of the nanoparticles does not form a conductor when the voltage and or current pulse is applied to the first portion. The anisotropic conductor forms a conductive path between conductors of electronic devices, components, and systems, including microelectromechanical systems (MEMS) devices, components, and systems. | 2014-09-18 |
20140264901 | SEMICONDUCTOR DEVICE AND LAYOUT DESIGN SYSTEM - In a semiconductor device including a seal ring area containing multiple seal rings are coupled to each other at equal intervals via bridge patterns, improper local relocation of bridge patterns may reduce the reliability of the semiconductor device. A semiconductor device has a first group containing a predetermined number of the bridge patterns spaced at a first interval and a second group containing a predetermined number of the bridge patterns spaced at the first interval, the second group being located at a second interval from the first group. The second interval is larger than the first interval. | 2014-09-18 |
20140264902 | Novel Patterning Approach for Improved Via Landing Profile - The present disclosure is directed to a semiconductor structure and a method of manufacturing a semiconductor structure in which a spacer element is formed adjacent to a metal body embedded in a first dielectric layer of a first interconnect layer. A via which is misaligned relative to an edge of the metal body is formed in a second dielectric material in second interconnect layer disposed over the first interconnect layer and filled with a conductive material which is electrically coupled to the metal body. The method allows for formation of an interconnect structure without encountering the various problems presented by via substructure defects in the dielectric material of the first interconnect layer, as well as eliminating conventional gap-fill metallization issues. | 2014-09-18 |
20140264903 | INTERCONNECT STRUCTURE AND METHOD OF FORMING THE SAME - An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower etch stop layer (ESL); an upper low-k (LK) dielectric layer over the lower ESL; a first conductive feature in the upper LK dielectric layer, wherein the first conductive feature has a first metal line and a dummy via contiguous with the first metal line, the dummy via extending through the lower ESL; a first gap along an interface of the first conductive feature and the upper LK dielectric layer; and an upper ESL over the upper LK dielectric layer, the first conductive feature, and the first gap. | 2014-09-18 |
20140264904 | UNIFIED PCB DESIGN FOR SSD APPLICATIONS, VARIOUS DENSITY CONFIGURATIONS, AND DIRECT NAND ACCESS - Memory systems and methods for creating the same are disclosed. The memory systems can include pairs of IC packages mounted on either side of a system substrate. Contacts formed on the IC packages can be communicatively coupled with contacts of a paired IC package using vias that extend through the system substrate. The IC packages can further communicate with a controller mounted on one side of the system substrate using the vias as well as conductive traces formed in the system substrate. | 2014-09-18 |
20140264905 | Semiconductor Device and Method of Forming WLCSP with Semiconductor Die Embedded within Interconnect Structure - A semiconductor device includes a semiconductor die. An encapsulant is deposited over the semiconductor die. An insulating layer is formed over the encapsulant and a first surface of the semiconductor die. A semiconductor component is disposed over the insulating layer and first surface of the semiconductor die. A first interconnect structure is formed over the encapsulant and first surface of the semiconductor die to embed the semiconductor component. A conductive via is formed in the semiconductor die. A heat sink is formed over the semiconductor die. A second interconnect structure is formed over a second surface of the semiconductor die opposite the first surface. A conductive layer is formed over the semiconductor component. An opening is formed in the insulating layer. | 2014-09-18 |
20140264906 | SYSTEMS AND METHODS FOR HIGH-SPEED, LOW-PROFILE MEMORY PACKAGES AND PINOUT DESIGNS - Systems and methods are provided for stacked semiconductor memory packages. Each package can include an integrated circuit (“IC”) package substrate capable of transmitting data to memory dies stacked within the package over two channels. Each channel can be located on one side of the IC package substrate, and signals from each channel can be routed to the memory dies from their respective sides. | 2014-09-18 |
20140264907 | STUBBY PADS FOR CHANNEL CROSS-TALK REDUCTION - A metal surface feature, such as a pad, terminating a vertical transition through a substrate, such as an IC package substrate, includes one or more stubs providing high edge surface area to couple with one or more complementary stubs on an adjacent metal surface feature to provide a desired amount of mutual capacitance that may at least partially cancel crosstalk for an overall channel crosstalk (e.g., FEXT) reduction. In embodiments, capacitive coupling of adjacent pads is provided for more than two pads to achieve crosstalk reduction of more than one victim-aggressor pair and/or to achieve crosstalk reduction of more than two aggressors. In embodiments, the pads have a large pitch (e.g., 1000 μm) suitable for interfacing to an interposer or PCB socket, while the gap between the stubs is small (e.g., 15 μm), as limited only by the minimum spacing allowed for metal features on the opposite side of the package employed for interfacing to the IC. | 2014-09-18 |
20140264908 | DUAL DAMASCENE GAP FILLING PROCESS - A method of forming a metallization layer in a semiconductor substrate includes forming a patterned dielectric layer on a substrate, the patterned dielectric layer having a plurality of first openings. A first conductive layer is formed in the plurality of first openings. A patterned mask layer is formed over portions of the first conductive layer outside the plurality of first openings, the patterned mask layer having a plurality of second openings, wherein at least a subset of the second openings are disposed over the first openings. A second conductive layer is filled in the plurality of second openings. The patterned mask layer is removed to leave behind the conductive layer structures on the substrate. The substrate is heated to form a self-forming barrier layer on the top and sidewalls of the conductive layer structures. | 2014-09-18 |
20140264909 | MICROELECTROMECHANICAL SYSTEM DEVICES HAVING THROUGH SUBSTRATE VIAS AND METHODS FOR THE FABRICATION THEREOF - Methods for the fabrication of a Microelectromechanical Systems (“MEMS”) devices are provided, as are MEMS devices. In one embodiment, the MEMS device fabrication method includes forming at least one via opening extending into a substrate wafer, depositing a body of electrically-conductive material over the substrate wafer and into the via opening to produce a via, bonding the substrate wafer to a transducer wafer having an electrically-conductive transducer layer, and forming an electrical connection between the via and the electrically-conductive transducer layer. The substrate wafer is thinned to reveal the via through a bottom surface of the substrate wafer, and a backside conductor is produced over a bottom surface of the substrate wafer electrically coupled to the via. | 2014-09-18 |
20140264910 | INTERCONNECT STRUCTURES WITH POLYMER CORE - Embodiments of the present disclosure are directed towards techniques and configurations of interconnect structures having a polymer core in integrated circuit (IC) package assemblies. In one embodiment, an apparatus includes a first die having a plurality of transistor devices disposed on an active side of the first die and a plurality of interconnect structures electrically coupled with the first die, wherein individual interconnect structures of the plurality of interconnect structures have a polymer core, and an electrically conductive material disposed on the polymer core, the electrically conductive material being configured to route electrical signals between the transistor devices of the first die and a second die. Other embodiments may be described and/or claimed. | 2014-09-18 |
20140264911 | THROUGH SILICON VIAS - A device and methods for forming a device are disclosed. A substrate is provided and a TSV is formed in the substrate through a top surface of the substrate. The TSV and top surface of the substrate is lined with an insulation stack having a first insulation layer, a polish stop layer and a second insulation layer. A conductive layer is formed on the substrate. The TSV is filled with conductive material of the conductive layer. The substrate is planarized to remove excess conductive material of the conductive layer. The planarizing stops on the polish stop layer to form a planar top surface. | 2014-09-18 |
20140264912 | Semiconductor Device - A semiconductor device comprises a substrate, a through-silicon via (TSV) penetrating the substrate, a plurality of first interconnect structures, right above the TSV, configured for electrically coupling the TSV to a higher-level interconnect, a second interconnect structure traversing the TSV from the top and being configured for interconnect routing of an active device and a plurality of dummy metal patterns, right above the TSV, electrically isolated from the TSV, the first interconnect structures and the second interconnect structure. | 2014-09-18 |
20140264913 | Semiconductor Device - A semiconductor device comprises a substrate, a through-silicon via (TSV) penetrating the substrate, at least one first interconnect structure traversing the TSV from the top and dividing a region right above the TSV into several sub-regions and being configured for interconnect routing of an active device and a plurality of second interconnect structures occupying the sub-regions right above the TSV and being configured for electrically coupling the TSV to a higher-level interconnect. | 2014-09-18 |
20140264914 | Chip package-in-package and method thereof - An electronic package includes an interposer, a die attached to a first side of the interposer, an embedded electronic package attached to a second side of the interposer, an encapsulation compound, a set of vias providing electrical paths from a first side of the electronic package to the interposer through the encapsulation compound, and a redistribution layer electrically redistributing the set of vias to form a set of interconnect-pads. Either the die or the embedded electronic package, or both, are electrically connected to the interposer. | 2014-09-18 |
20140264915 | Stacked Integrated Circuit System - A stacked integrated circuit system comprises a first chip with first average pattern density comprising memory cells, a second chip with second average pattern density comprising logic circuitries for the memory cells and a functioning unit and a plurality of through-silicon vias within one of the first chip and second chip to electrically connect the first chip and the second chip, wherein the memory cells of the first chip and the logic circuitries of the second chip are designed to be used collectively in order to perform complete memory functions, and wherein the first average pattern density is higher than the second average pattern density. | 2014-09-18 |
20140264916 | An Integrated Structure with a Silicon-Through Via - An integrated structure with a silicon-through via comprises a substrate, a through-silicon via penetrating the substrate, a conductive protective structure surrounding the through-silicon via and a first and a second conductive dummy patterns with different shapes disposed between the through-silicon via and the conductive protective structure. | 2014-09-18 |
20140264917 | A Semiconductor Device with a Through-Silicon Via and a Method for Making the Same - A semiconductor device with a through-silicon via comprises a substrate with a front side and a backside and a through-silicon via penetrating the substrate with a circular shape on the front side and a corner-rounded rectangular shape on the back side. | 2014-09-18 |
20140264918 | Integrated Circuit Layout - An integrated circuit layout comprises a through silicon via (TSV) configured to couple positive operational voltage VDD (VDD TSV), a through silicon via (TSV) configured to couple operational signals (signal TSV), a plurality of through silicon vias (TSVs) configured to couple operational voltage VSS (VSS TSVs) around the VDD TSV and the signal TSV and one or more backside redistribution lines (RDLs) connecting the VSS TSVs together to form a web-like heat dissipating structure at least surrounding the VDD TSV and the signal TSV. | 2014-09-18 |
20140264919 | CHIP ARRANGEMENT, WAFER ARRANGEMENT AND METHOD OF MANUFACTURING THE SAME - Various embodiments provide a chip arrangement. The chip arrangement may include a first chip having a first chip side and a second chip side opposite the first chip side and at least one contact on its second chip side; a second chip having a first chip side and a second chip side opposite the first chip side and at least one contact on its first chip side; wherein the second chip side of the first chip and the second chip side of the second chip are facing each other; a first electrically conductive structure extending from the at least one contact of the first chip from the second chip side of the first chip through the first chip to the first chip side of the first chip; and a second electrically conductive structure. | 2014-09-18 |
20140264920 | Metal Cap Apparatus and Method - Presented herein is a method for electrolessly forming a metal cap in a via opening, comprising bringing a via into contact with metal solution, the via disposed in an opening in a substrate, and forming a metal cap in the opening and in contact with the via, the metal cap formed by an electroless chemical reaction. A metal solution may be applied to the via to form the metal cap. The metal solution may comprises at least cobalt and the cap may comprise at least cobalt, and may optionally further comprise tungsten, and wherein the forming the cap comprises forming the cap to further comprise at least tungsten. The metal solution may further comprise at least hypophosphite or dimethlyaminoborane. | 2014-09-18 |
20140264921 | THROUGH-SILICON VIA WITH SIDEWALL AIR GAP - Embodiments of the present invention provide a novel process integration for air gap formation at the sidewalls for a Through Silicon Via (TSV) structure. The sidewall air gap formation scheme for the TSV structure of disclosed embodiments reduces parasitic capacitance and depletion regions in between the substrate silicon and TSV conductor, and serves to also reduce mechanical stress in silicon substrate surrounding the TSV conductor. | 2014-09-18 |
20140264922 | SEMICONDUCTOR STRUCTURE - One or more embodiments of techniques or systems for forming a semiconductor structure are provided herein. A first metal region is formed within a first dielectric region. A cap region is formed on the first metal region. A second dielectric region is formed above the cap region and the first dielectric region. A trench opening is formed within the second dielectric region. A via opening is formed through the second dielectric region, the cap region, and within some of the first metal region by over etching. A barrier region is formed within the trench opening and the via opening. A via plug is formed within the via opening and a second metal region is formed within the trench opening. The via plug electrically connects the first metal region to the second metal region and has a tapered profile. | 2014-09-18 |
20140264923 | INTERCONNECT STRUCTURE WITH KINKED PROFILE - Among other things, one or more interconnect structures and techniques for forming such interconnect structures within integrated circuits are provided. An interconnect structure comprises one or more kinked structures, such as metal structures or via structures, formed according to a kinked profile. For example, the interconnect structure comprises a first kinked structure having a first tapered portion and a second kinked structure having a second tapered portion. The first tapered portion and the second tapered portion are both situated at an interface between two layers. Current leakage at the interface is mitigated because a length of the interface corresponds to a distance between the first tapered portion and the second tapered portion that is relatively larger than if the first kinked structure and the second kinked structure were merely formed according to a non-tapered shape. | 2014-09-18 |
20140264924 | APPARATUS AND METHOD FOR MITIGATING DYNAMIC IR VOLTAGE DROP AND ELECTROMIGRATION AFFECTS - An integrated circuit structure includes a plurality of power or ground rails for an integrated circuit, the plurality of power or ground rails vertically separated on a plane, a plurality of functional cells between the plurality of power rails or between the plurality of ground rails or both, and a jumper connection between the vertically separated power rails or ground rails, the jumper connection within a vertically aligned gap among the plurality of functional cells. A method of mitigating IR drop and electromigration affects in an integrated circuit includes forming a plurality of power rails or ground rails, each of the power rails or ground rails on separate vertical levels of a plane of an integrated circuit layout and connecting with a jumper connection at least two power rails or two ground rails, the jumper connection within a vertically aligned gap among cells of the integrated circuit. | 2014-09-18 |
20140264925 | INTERLAYER CONDUCTOR AND METHOD FOR FORMING - A 3-D structure includes a stack of active layers at different depths has a plurality of contact landing areas on respective active layers within a contact area opening. A plurality of interlayer conductors, each includes a first portion within a contact area opening extending to a contact landing area, and a second portion in part outside the contact area opening above the top active layer. The first portion has a transverse dimension Y | 2014-09-18 |
20140264926 | Method and Apparatus for Back End of Line Semiconductor Device Processing - A via opening comprising an etch stop layer (ESL) opening and methods of forming the same are provided which can be used in the back end of line (BEOL) process of IC fabrication. A metal feature is provided with a first part within a dielectric layer and with a top surface. An ESL is formed with a bottom surface of the ESL above and in contact with the dielectric layer, and a top surface of the ESL above the bottom surface of the ESL. An opening at the ESL is formed exposing the top surface of the metal feature; wherein the opening at the ESL has a bottom edge of the opening above the bottom surface of the ESL, a first sidewall of the opening at a first side of the metal feature, and a second sidewall of the opening at a second side of the metal feature. | 2014-09-18 |
20140264927 | Single Mask Package Apparatus and Method - Disclosed herein is a single mask package apparatus on a device comprising a first substrate having a land disposed on a first surface, a stud disposed on the land and a protective layer disposed over the first surface of the first substrate and around the stud. The protective layer may optionally have a thickness of at least 3 μm. A PPI may be disposed over the protective layer and in electrical contact with the stud, with a first portion of the PPI extending laterally from the stud. An interconnect may be disposed on and in electrical contact with the first portion of the PPI, and a second substrate mounted on the interconnect. A molding compound may be disposed over the PPI and around the interconnect. The stud may be a substantially solid material having a cylindrical cross section and may optionally be wirebonded to the land. | 2014-09-18 |
20140264928 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A fabrication method of a semiconductor package is disclosed, which includes the steps of: disposing a plurality of first semiconductor elements on an interposer; forming a first encapsulant on the interposer for encapsulating the first semiconductor elements; disposing a plurality of second semiconductor elements on the first semiconductor elements; forming a second encapsulant on the first semiconductor elements and the first encapsulant for encapsulating the second semiconductor elements; and thinning the interposer, thereby reducing the overall stack thickness and preventing warpage of the interposer. | 2014-09-18 |
20140264929 | Interconnect Structure for Stacked Device - A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element. The first substrate includes a dielectric block in the first substrate; and a plurality of first conductive features formed in first inter-metal dielectric layers over the first substrate. The stacked IC device also includes a second semiconductor element bonded on the first semiconductor element. The second semiconductor element includes a second substrate and a plurality of second conductive features formed in second inter-metal dielectric layers over the second substrate. The stacked IC device also includes a conductive deep-interconnection-plug coupled between the first conductive features and the second conductive features. The conductive deep-interconnection-plug is isolated by dielectric block, the first inter-metal-dielectric layers and the second inter-metal-dielectric layers. | 2014-09-18 |
20140264930 | Fan-Out Interconnect Structure and Method for Forming Same - A method embodiment includes forming a sacrificial film layer over a top surface of a die, the die having a contact pad at the top surface. The die is attached to a carrier, and a molding compound is formed over the die and the sacrificial film layer. The molding compound extends along sidewalls of the die. The sacrificial film layer is exposed. The contact pad is exposed by removing at least a portion of the sacrificial film layer. A first polymer layer is formed over the die, and a redistribution layer (RDL) is formed over the die and electrically connects to the contact pad. | 2014-09-18 |
20140264931 | Stress Tuning for Reducing Wafer Warpage - An integrated circuit structure includes a substrate, a plurality of low-k dielectric layers over the substrate, a first dielectric layer over the plurality of low-k dielectric layers, and a metal line in the first dielectric layer. A stress tuning dielectric layer is over the first dielectric layer, wherein the stress tuning dielectric layer includes a first opening and a second opening. The metal line extends into the first opening. The second opening has a bottom substantially level with a top surface of the first dielectric layer. A second dielectric layer is over the first dielectric layer. | 2014-09-18 |
20140264932 | Patterning Approach to Reduce Via to Via Minimum Spacing - A method for patterning vias in a chip comprises forming a photomask layer including a gap on a patterned hardmask layer including a plurality of trenches and in contact with a uniform layer on a substrate, wherein the gap overlaps with two or more of the trenches. The method further comprises exposing a portion of the uniform layer under the gap using a photo exposure process, etching the exposed portion of the uniform layer with the photomask layer to obtain a plurality of vias extended partially through the substrate, and further etching the vias to obtain corresponding through-substrate vias. Another method comprises patterning a plurality of vias in a plurality of trenches of a hardmask layer on a substrate using a single photo exposure step and a photomask comprising a single gap that overlaps with the trenches. | 2014-09-18 |
20140264933 | Wafer Level Chip Scale Packaging Intermediate Structure Apparatus and Method - Presented herein is a WLCSP intermediate structure and method forming the same, the method comprising forming a first redistribution layer (RDL) on a carrier, the first RDL having mounting pads disposed on the first RDL, and mounting interposer dies on a second side of the first RDL. A second RDL is formed over a second side of the interposer dies, the second RDL having a first side adjacent to the interposer dies, one or more lands disposed on the second RDL, at least one of the one or more lands in electrical contact with at least one of the interposer dies or at least one of the mounting pads. A molding compound is formed around the interposer dies and over a portion of the first RDL prior to the forming the second RDL and the second RDL is formed over at least a portion of the molding compound. | 2014-09-18 |
20140264934 | INTERLAYER CONDUCTOR STRUCTURE AND METHOD - To form an interconnect conductor structure, a stack of pads, coupled to respective active layers of a circuit, is formed. Rows of interlayer conductors are formed to extend in an X direction in contact with landing areas on corresponding pads in the stack. Adjacent rows are separated from one another in a Y direction generally perpendicular to the X direction. The interlayer conductors in a row have a first pitch in the X direction. The interlayer conductors in adjacent rows are offset in the X direction by an amount less than the first pitch. Interconnect conductors are formed over and in contact with interlayer conductors. The interconnect conductors extend in the Y direction and have a second pitch less than the first pitch. | 2014-09-18 |
20140264935 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR MOUNTING SUBSTRATE - A semiconductor device manufacturing method includes: a first-process for placing, on a first-substrate on which traces and first-electrodes are formed, each of the first-electrodes being connected to one of traces, a second-substrate in which through-holes corresponding to the first-electrodes and relay-members are disposed, each of the relay-members being formed of solder, penetrating through one of the through-holes, and projecting from both ends of the one of the through-holes, so that the first-electrodes are aligned with the through-holes in a plan view; a second-process for melting the relay-members so that the relay-members are connected to the first-electrodes, after the first-process; and a third-process for placing a semiconductor substrate on which a second-electrodes corresponding to the first-electrodes are formed on a side opposite to the first-substrate across the second-substrate, after the second-process, to connect the first-electrodes and the second-electrodes to each other via the relay-members. | 2014-09-18 |
20140264936 | SEMICONDUCTOR PACKAGE - A semiconductor package including a first connection terminal group configured to receive a first signal group from the outside of the semiconductor package, a second connection terminal group configured to transmit a second signal group to the outside, a first chip connected to the first connection terminal group, and a second chip connected to the second connection terminal group and configured to receive the first and second signal groups from the first chip. Degradation of the performance of the semiconductor package, caused by the differences between signal delay times in a plurality of chips therein may be minimized. | 2014-09-18 |
20140264937 | Through-Silicon Vias and Interposers Formed by Metal-Catalyzed Wet Etching - Provided are methods for making a through-silicon via feature in a silicon substrate and related systems, such as by forming a noble metal structure on a silicon substrate support surface to generate silicon substrate contact regions that are in contact with or proximate to the noble metal structure; exposing at least a portion of the silicon substrate support surface and noble metal structure to an etchant to preferentially etch the silicon substrate contact regions compared to silicon substrate non-contact regions until the etch front reaches the silicon substrate bottom surface. | 2014-09-18 |
20140264938 | Flexible Interconnect - The described Flexible Interconnect is useful for making electrical or other contact between various combinations of semiconductor die, printed circuit boards and other components. A thin flexible material, such as a polymer, supports printed lines that connect pads which may contain vias. The flexible interconnect can be attached using conductive and non-conductive epoxies to the components that are to be interconnected. Each interconnect can be individually insulated from adjacent interconnects, so that it can be deformed and flexed without making contact with another. The described interconnects can span long distances and conform to underlying topography. Metal interconnects may be used to conduct heat or to form heat sinks. Similarly, flexible interconnects may be formed from material that is an electrical insulator but thermally conductive in order to transport heat away from the attached circuitry. Optical conductors may be supported for use as flexible photonic waveguides. | 2014-09-18 |
20140264939 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor substrate and a second semiconductor substrate laminated with an insulating layer, a first transmission line formed on the first semiconductor substrate, the first transmission line including a signal line and a ground, a second transmission line formed on the second semiconductor substrate, the second transmission line including a signal line and a ground, a first via layer for the signal lines, the first via layer for the signal lines being formed of a conductor layer formed within a via hole, a first via layer for the grounds, the first via layer for the grounds being formed of a conductor layer formed within a via hole, and a second via layer for the grounds, the second via layer for the grounds being formed of a conductor layer formed within a via hole. | 2014-09-18 |
20140264940 | SEMICONDUCTOR PACKAGE AND PACKAGE ON PACKAGE HAVING THE SAME - A semiconductor package and a package on package are provided. The semiconductor package includes a substrate; a semiconductor chip attached to a surface of the substrate; connecting conductors disposed on the surface of the substrate; a mold formed on the substrate and in which the connecting conductors and the semiconductor chip are provided; and connecting via holes extending through the mold and exposing the connecting conductors. With respect to a first connecting via hole of the connecting via holes, a planar distance between a first connecting conductor exposed by the first connecting via hole and an entrance of the first connecting via hole is not uniform. | 2014-09-18 |
20140264941 | Three-Dimensional Semiconductor Architecture - A system and method for making semiconductor die connections with through-substrate vias are disclosed. Through substrate vias are formed through the substrate to allow for signal connections as well as power and ground connections. In one embodiment the substrate has an interior region and a periphery region surrounding the interior region. A first set of through substrate vias are located within the periphery region, and a second set of through substrate vias are located within the interior region, wherein the second set of through substrate vias are part of a power matrix. The second set of through substrate vias bisect the substrate into a first part and a second part. | 2014-09-18 |
20140264942 | SEMICONDUCTOR DEVICE CHANNELS - A semiconductor device and a method of manufacture are provided. The semiconductor device includes one or more layers having channels adapted to carry signals or deliver power. The semiconductor device may include a signal channel and a power channel. The power channel may include power channel cross-sectional portions. A first conductor in the power channel may have a first cross-sectional area. A second conductor in the signal channel may have a second cross-sectional area. The second cross-sectional area may be smaller than the first cross-sectional area. The method of manufacture includes establishing a signal conductor layer including a signal channel and a power channel, introducing a first conductor in the power channel having a first cross-sectional area, and introducing a second conductor in the signal channel having a second cross-sectional area where the second cross-sectional area is smaller than the first cross-sectional area. | 2014-09-18 |
20140264943 | MULTIPLE-PATTERNED SEMICONDUCTOR DEVICE CHANNELS - A semiconductor device and method of manufacture are provided. The semiconductor device may include a multiple-patterned layer which may include multiple channels defined by multiple masks. A width of a first channel may be smaller than a width of a second channel. A conductor in the first channel may have a conductor width substantially equivalent to a conductor width of a conductor in the second channel. A spacer dielectric on a channel side may be included. The method of manufacture includes establishing a signal conductor layer including channels defined masks where a first channel may have a first width smaller than a second width of a second channel, introducing a spacer dielectric on a channel side, introducing a first conductor in the first channel having a first conductor width, and introducing a second conductor in the second channel having a second conductor width substantially equivalent to the first conductor width. | 2014-09-18 |
20140264944 | Semiconductor Package with Top-Side Insulation Layer - A semiconductor package includes a base, a die attached to the base, a lead and a connector electrically connecting the lead to the die. A mold compound encapsulates the die, the connector, at least part of the base, and part of the lead, so that the lead extends outward from the mold compound. An electrical insulation layer separate from the mold compound is attached to a surface of the mold compound over the connector. The electrical insulation layer has a fixed, defined thickness so that the package has a guaranteed minimum spacing between an apex of the connector and a surface of the electrical insulation layer facing away from the connector. | 2014-09-18 |
20140264945 | STACKED MICROELECTRONIC PACKAGES HAVING SIDEWALL CONDUCTORS AND METHODS FOR THE FABRICATION THEREOF - A stacked microelectronic package can comprise a package body having an external vertical package sidewall, a plurality of microelectronic devices embedded within the package body, and package edge conductors electrically coupled to the plurality of microelectronic devices and extending to the external vertical package sidewall. A cavity is formed on an external surface of the package body between a first one of the package edge conductors and a second one of the package edge conductors. Electrically conductive material is in the cavity and in electrical contact with a first and a second one of the package edge conductors, wherein the conductive material in the cavity is within planform dimensions of the microelectronic package. | 2014-09-18 |
20140264946 | PACKAGE-ON-PACKAGE STRUCTURE WITH REDUCED HEIGHT - To achieve a package-on-package having an advantageously reduced height, a first package substrate has a window sized to receive a second package die. The first package substrate interconnects to the second package substrate through a plurality of package-to-package interconnects such that the first and second substrates are separated by a gap. The second package die has a thickness greater than the gap such that the second package die is at least partially disposed within the first package substrate's window. | 2014-09-18 |
20140264947 | Interconnect Apparatus and Method - A method comprises bonding a first chip on a second chip, depositing a first hard mask layer over a non-bonding side of the first chip, depositing a second hard mask layer over the first hard mask layer, etching a first substrate of the first semiconductor chip using the second hard mask layer as a first etching mask and etching the IMD layers of the first chip and the second chip using the first hard mask layer as a second etching mask. | 2014-09-18 |
20140264948 | Air Trench in Packages Incorporating Hybrid Bonding - A package component includes a surface dielectric layer including a planar top surface, a metal pad in the surface dielectric layer and including a second planar top surface level with the planar top surface, and an air trench on a side of the metal pad. The sidewall of the metal pad is exposed to the air trench. | 2014-09-18 |
20140264949 | GOLD DIE BOND SHEET PREFORM - The amount of gold required for bonding a semiconductor die to an electronic package is reduced by using a sheet preform tack welded to the package prior to mounting the die. The preform, only slightly larger than a semiconductor die to be attached to the package, is placed in the die bond location and tack welded to the package at two spaced locations. | 2014-09-18 |
20140264950 | CHIP ARRANGEMENT AND A METHOD OF MANUFACTURING A CHIP ARRANGEMENT - In various embodiments, a chip arrangement is provided. The chip arrangement may include a chip carrier and a chip mounted on the chip carrier. The chip may include at least two chip contacts and an insulating adhesive between the chip and the chip carrier to adhere the chip to the chip carrier. The at least two chip contacts may be electrically coupled to the chip carrier. | 2014-09-18 |
20140264951 | LASER DIE BACKSIDE FILM REMOVAL FOR INTEGRATED CIRCUIT (IC) PACKAGING - Embodiments of the present disclosure are directed to die adhesive films for integrated circuit (IC) packaging, as well as methods for forming and removing die adhesive films and package assemblies and systems incorporating such die adhesive films. A die adhesive film may be transparent to a first wavelength of light and photoreactive to a second wavelength of light. In some embodiments, the die adhesive film may be applied to a back or “inactive” side of a die, and the die surface may be detectable through the die adhesive film. The die adhesive film may be cured and/or marked with laser energy having the second wavelength of light. The die adhesive film may include a thermochromic dye and/or nanoparticles configured to provide laser mark contrast. UV laser energy may be used to remove the die adhesive film in order to expose underlying features such as TSV pads. | 2014-09-18 |
20140264952 | SUPPLEMENTING WIRE BONDS - Systems and techniques for supplementing wire bonds. In one embodiment, a device includes a body having a first surface, a first wire bond pad disposed on the first surface, a first wire that is wire bonded to the first wire bond pad to form a contact between the first wire and the first wire bond pad, a first supplemental conductor disposed to form a supplemental conduit between the first wire and the first wire bond pad, a second wire bond pad disposed on the first surface, a second wire that is wire bonded to the second wire bond pad to form a contact between the second wire and the second wire bond pad, and a second supplemental conductor disposed to form a supplemental conduit between the second wire and the second wire bond pad. The first supplemental conductor is discrete from the second supplemental conductor. | 2014-09-18 |
20140264953 | WIRING STRUCTURES, METHODS OF MANUFACTURING THE SAME, AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES HAVING THE SAME - A method of manufacturing a wiring structure may include forming a first conductive pattern on a substrate, forming a hardmask on the first conductive pattern, forming a first spacer on sidewalls of the first conductive pattern and the hardmask, forming a first sacrificial layer pattern on a sidewall of the first spacer, forming a second spacer on a sidewall of the first sacrificial layer pattern, removing the first sacrificial layer pattern, and forming a third spacer on the second spacer, may be provided. The third spacer may contact an upper portion of the sidewall of the first spacer and define an air gap in association with the first and second spacers. The first spacer has a top surface substantially higher than a top surface of the first conductive pattern. The second spacer has a top surface substantially lower than the top surface of the first spacer. | 2014-09-18 |
20140264954 | PASSIVATION AND WARPAGE CORRECTION BY NITRIDE FILM FOR MOLDED WAFERS - Embodiments of the invention generally relate to molded wafers having reduced warpage, bowing, and outgassing, and methods for forming the same. The molded wafers include a support layer of silicon nitride disposed on a surface thereof to facilitate rigidity and reduced outgassing. The silicon nitride layer may be formed on the molded wafer, for example, by plasma-enhanced chemical vapor deposition or hot-wire chemical vapor deposition. | 2014-09-18 |
20140264955 | ELECTRONIC DEVICE WITH AN INTERLOCKING MOLD PACKAGE - An electronic device includes a mold package which encapsulates a portion of the electronic device and does not encapsulate another portion of the electronic device to enable a sensing portion of the electronic device to be exposed to a condition to be sensed. In an electronic sensing device having a sensor formed by a substrate such as silicon, a sensor area is not encapsulated, but areas surrounding the sensor area are encapsulated. The area surrounding the sensor area includes one or more trenches or interlock structures formed in the surrounding substrate which receives the mold material to provide an interlock feature. The interlock feature reduces or substantially prevents the mold from delaminating at an interface of the mold and the substrate. | 2014-09-18 |
20140264956 | SEALANT LAMINATED COMPOSITE, SEALED SEMICONDUCTOR DEVICES MOUNTING SUBSTRATE, SEALED SEMICONDUCTOR DEVICES FORMING WAFER, SEMICONDUCTOR APPARATUS, AND METHOD FOR MANUFACTURING SEMICONDUCTOR APPARATUS - Disclosed is a sealant laminated composite for collectively sealing a semiconductor devices mounting surface of a substrate on which semiconductor devices may be mounted or a semiconductor devices forming surface of a wafer on which semiconductor devices may be formed, including a support wafer that may be composed of silicon and an uncured resin layer that may be constituted of an uncured thermosetting resin formed on one side of the support wafer. | 2014-09-18 |
20140264957 | ROBUST INK FORMULATIONS FOR DURABLE MARKINGS ON MICROELECTRONIC PACKAGES AND ITS EXTENDIBILITY AS A BARRIER MATERIAL FOR THERMAL AND SEALANT MATERIALS - Methods for covalently and indelibly anchoring a polyacrylate polymer using a UV-induced polymerization process in the presence of a photoinitiator to an oxide surface are disclosed herein. The methods and compositions prepared by the methods can be used as indelible marking materials for use on microelectronic packages and as solder and sealant barriers to prevent overspreading of liquids on the oxide surfaces of microelectronic packages. | 2014-09-18 |
20140264958 | SEMICONDUCTOR PACKAGE, FABRICATION METHOD THEREOF AND MOLDING COMPOUND - A semiconductor package is disclosed, which includes: a substrate body; a semiconductor element disposed on the substrate body; and a molding compound forms on the substrate body for encapsulating the semiconductor element. The molding compound contains a metal oxide so as to have a high insulation impedance and a high heat dissipating rate and be capable of suppressing electromagnetic interference. | 2014-09-18 |
20140264959 | HARDENING RESIN COMPOSITION, SEALING MATERIAL, AND ELECTRONIC DEVICE USING THE SEALING MATERIAL - A hardening resin composition includes a base resin and a hardening agent. The base resin contains a maleimide compound having two or more maleimide groups in one molecule, and the hardening agent contains a diamine compound expressed by a general chemical formula (1), in which A is an oxygen atom or a sulfur atom, X is a hydrogen atom, an alkyl group with a carbon number of six or less, or an aryl group, and n is a natural number of 1 to 10. | 2014-09-18 |
20140264960 | ENCAPSULATION OF ADVANCED DEVICES USING NOVEL PECVD AND ALD SCHEMES - Embodiments of a multi-layer environmental barrier for a semiconductor device and methods of manufacturing the same are disclosed. In one embodiment, a semiconductor device is formed on a semiconductor die. The semiconductor die includes a semiconductor body and a passivation structure on the semiconductor body. A multi-level environmental barrier is provided on the passivation structure. The multi-layer environmental barrier is a low-defect multi-layer dielectric film that hermetically seals the semiconductor device from the environment. In one embodiment, the multi-layer environmental barrier has a defect density of less than 10 defects per square centimeter (cm | 2014-09-18 |