38th week of 2014 patent applcation highlights part 56 |
Patent application number | Title | Published |
20140264761 | SEMICONDUCTOR DEVICES AND METHODS OF MAKING THE SAME - In one embodiment, methods for making semiconductor devices are disclosed. | 2014-09-18 |
20140264762 | WAFER STACK PROTECTION SEAL - A semiconductor wafer stack and a method of forming a semiconductor device is disclosed. The method includes providing first and second wafers with top and bottom surfaces. The wafers include edge and non-edge regions, and the first wafer includes devices formed in the non-edge region. A first protection seal may be formed at the edge region of the first wafer. The first and second wafers may further be bonded to form a device stack. The protection seal in the device stack contacts the first and second wafers to form a seal, and protects the devices in subsequent processing. | 2014-09-18 |
20140264763 | ENGINEERED SUBSTRATES FOR SEMICONDUCTOR EPITAXY AND METHODS OF FABRICATING THE SAME - In a method for fabricating an engineered substrate for semiconductor epitaxy, an array of seed structures is assembled on a surface of the substrate. The seed structures in the array have substantially similar directional orientations of their crystal lattices, and are spatially separated from each other. Semiconductor materials are selectively epitaxially grown on the seed structures, such that a rate of growth of the semiconductor materials on the seed structures is substantially higher than a rate of growth of the semiconductor materials on regions of the surface. The semiconductor materials assume a lattice constant and directional orientation of crystal lattice that are substantially similar or identical to those of the seed structures. Related devices and methods are also discussed. | 2014-09-18 |
20140264764 | LAYER ARRANGEMENT - A layer arrangement in accordance with various embodiments may include: a first layer having a side; one or more nanoholes in the first layer that are open towards the side of the first layer; a second layer filling at least part of the nanoholes and covering at least part of the side of the first layer, the second layer including at least one of the following materials: a metal or metal alloy, a glass material, a polymer material, a ceramic material. | 2014-09-18 |
20140264765 | SEMICONDUCTOR WAFER AND METHOD OF PRODUCING SAME - A wafer surface of a semiconductor wafer to be used as a device active region is mirror-polished, and an outer peripheral portion of the mirror-polished wafer surface is further polished, thereby forming an edge roll-off region between the device active region of the wafer surface and a beveled portion formed at the wafer edge. The edge roll-off region has a specific roll-off shape corresponding to an edge roll-off of the oxide film to be formed in a device fabrication process. Thus, a semiconductor wafer can be provided in which reduction in the thickness of an oxide film on the outer peripheral portion of the wafer in a CMP process can be prevented while maintaining high flatness of the wafer surface. | 2014-09-18 |
20140264766 | System and Method for Film Stress Release - Disclosed herein is a method of forming a stress relieved film stack, the method comprising forming a film stack on a first side of a substrate, the film stack comprising a plurality of film layers and creating a plurality of film stack openings according to a cutting pattern and along at least a portion of a buffer region. The plurality of film stack openings extend from a top surface of the film stack to the substrate. A deflection of the substrate may be determined, and the cutting pattern selected prior to creating the film stack openings based on the deflection of the substrate. The substrate may have a deflection of less than about 2 μm after the creating the plurality of film stack openings. And at least one of the plurality of film layers may comprise one of titanium nitride, silicon carbide and silicon dioxide. | 2014-09-18 |
20140264767 | Wafer, Integrated Circuit Chip and Method for Manufacturing an Integrated Circuit Chip - A wafer has a number of IC areas and a kerf area arranged between the IC areas. The kerf area has a dicing area, a crack stop structure arranged between an IC area and a dicing area, and a trench arranged between the crack stop structure and the dicing area. The crack stop structure includes an extended layer extending beyond the crack stop structure towards the dicing area. | 2014-09-18 |
20140264768 | Die Preparation for Wafer-Level Chip Scale Package (WLCSP) - Consistent with an example embodiment, there is a method for assembling a wafer level chip scale processed (WLCSP) device from a wafer substrate, the method comprises grinding the back-side of the wafer substrate to a prescribed thickness. A plurality of trenches is sawed along a plurality of device die boundaries on a back-side surface of the wafer, the trenches having a bevel profile. The plurality of trenches is etched until the bevel profile of the plurality of trenches is rounded. | 2014-09-18 |
20140264769 | PACKAGING MECHANISMS FOR DIES WITH DIFFERENT SIZES OF CONNECTORS - Embodiments of mechanisms for forming a die package with multiple packaged dies on a package substrate use an interconnect substrate to provide electrical connections between dies and the package substrate. The usage of the interconnect substrate enables cost reduction because it is cheaper to make than an interposer with through silicon vias (TSVs). The interconnect substrate also enables dies with different sizes of bump structures to be packaged in the same die package. | 2014-09-18 |
20140264770 | METHOD OF FORMING THROUGH SUBSTRATE VIAS (TSVS) AND SINGULATING AND RELEASING DIE HAVING THE TSVS FROM A MECHANICAL SUPPORT SUBSTRATE - Accessing a workpiece object in semiconductor processing is disclosed. The workpiece object includes a mechanical support substrate, a release layer over the mechanical support substrate, and an integrated circuit substrate coupled over the release layer. The integrated circuit substrate includes a device layer having semiconductor devices. The method also includes etching through-substrate via (TSV) openings through the integrated circuit substrate that have buried ends at or within the release layer including using the release layer as an etch stop. TSVs are formed by introducing one or more conductive materials into the TSV openings. A die singulation trench is etched at least substantially through the integrated circuit substrate around a perimeter of an integrated circuit die. The integrated circuit die is at least substantially released from the mechanical support substrate. | 2014-09-18 |
20140264771 | CHIP PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - An embodiment of the present invention provides a manufacturing method of a chip package structure including: providing a first substrate having a plurality of predetermined scribe lines defined thereon, wherein the predetermined scribe lines define a plurality of device regions; bonding a second substrate to the first substrate, wherein a spacing layer is disposed therebetween and has a plurality of chip support rings located in the device regions respectively and a cutting support structure located on peripheries of the chip support rings, and the spacing layer has a gap pattern separating the cutting support structure from the chip support rings; and cutting the first substrate and the second substrate to form a plurality of chip packages. Another embodiment of the present invention provides a chip package structure. | 2014-09-18 |
20140264772 | Shielding for Through-Silicon-Via - 3D integrated circuit devices include first and second semiconductor bodies. The first semiconductor body has an active area, a through-silicon-via outside the active area, and two or more disjoint guard rings. The first guard ring encircles the via. The second guard ring encircles the active area, but not the via. The guard rings can reduce the noise coupling coefficient between the via and the active area to −60 dB or less at 3 GHz and 20 μm spacing. | 2014-09-18 |
20140264773 | SYSTEM AND METHOD FOR OPTIMIZATION OF AN IMAGED PATTERN OF A SEMICONDUCTOR DEVICE - In a method, a layout of a device having a pattern of features is provided. The method continues to include identifying a first portion of at least one feature of the plurality of features. An image criteria for the first portion may be assigned. A lithography optimization parameter is determined based on the assigned image criteria for the first portion. Finally, the first portion of the at least one feature is imaged onto a semiconductor substrate using the determined lithography optimization parameter. | 2014-09-18 |
20140264774 | WAFER AND FILM COATING METHOD OF USING THE SAME - The present disclosure provides a wafer that can be used in coating films. The wafer includes a front surface, a back surface opposite to the front surface, and a plurality of trenches. The back surface further includes a central region and a surrounding region. The trenches are disposed on the back surface. The spacing between any two adjacent trenches in surrounding region is less than the spacing between any two adjacent trenches in the central region. | 2014-09-18 |
20140264775 | METHOD AND SYSTEM FOR TRANSIENT VOLTAGE SUPPRESSION - A transient voltage suppression (TVS) device and a method of forming the device are provided. The device includes a first layer of wide band gap semiconductor material formed of a first conductivity type material, a second layer of wide band gap semiconductor material formed of a second conductivity type material over at least a portion of the first layer and comprising an ion implanted material structure between 0.1 micrometers (μm) and 22.0 μm thick, the second layer operating using punch-through physics, and a third layer of wide band gap semiconductor material formed of the first conductivity type material over at least a portion of the second layer. | 2014-09-18 |
20140264776 | Semiconductor Wafer With A LayerOf AlzGa1-zN and Process For Producing It - A semiconductor wafer contains the following layers in the given order:
| 2014-09-18 |
20140264777 | Nanocrystalline Diamond Three-Dimensional Films in Patterned Semiconductor Substrates - An array of through-silicon vias (TSVs) are formed in a silicone substrate. The vias can be tapered such that the diameter of the via at the surface of the substrate is larger than the diameter of the via at its bottom, with the diameter varying continuously along its depth. After the via is formed, it is seeded with a thin layer of nanocrystalline diamond (NCD) particles, and a NCD film is grown on the bottom and along the sidewalls of the via. The presence of the diamond-filled vias provides improved thermal management to semiconductor devices formed on the silicon substrate. | 2014-09-18 |
20140264778 | PRECURSOR COMPOSITION FOR DEPOSITION OF SILICON DIOXIDE FILM AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE USING THE SAME - A precursor composition for forming a silicon dioxide film on a substrate, the precursor composition including at least one precursor compound represented by the following chemical formulas (1), (2), and (3): | 2014-09-18 |
20140264779 | Metal Deposition on Substrates - Various techniques, methods, devices and apparatus are provided where an isolation layer is provided at a peripheral region of the substrate, and one or more metal layers are deposited onto the substrate. | 2014-09-18 |
20140264780 | ADHESION LAYER TO MINIMIZE DIELECTRIC CONSTANT INCREASE WITH GOOD ADHESION STRENGTH IN A PECVD PROCESS - Embodiments of the present invention provide a film stack and method for depositing an adhesive layer for a low dielectric constant bulk layer without the need for an initiation layer. A film stack for use in a semiconductor device comprises of a dual layer low-K dielectric deposited directly on an underlying layer. The dual low-K dielectric consists of an adhesive layer deposited without a carbon free initiation layer. | 2014-09-18 |
20140264781 | PASSIVATION LAYER FOR HARSH ENVIRONMENTS AND METHODS OF FABRICATION THEREOF - A method of fabricating a passivation layer and a passivation layer for an electronic device. The passivation layer includes at least one passivation film layer and at least one nanoparticle layer. A first film layer is formed of an insulating matrix, such as aluminum oxide (Al | 2014-09-18 |
20140264782 | FORMATION OF A HIGH ASPECT RATIO CONTACT HOLE - A small contact hole having a large aspect ratio is formed by employing a stop layer with a trench formed therein. A relatively large contact hole is formed above the trench, and the small contact hole is formed below the trench, using properties of the trench and the stop layer to limit the size of the small contact hole. | 2014-09-18 |
20140264783 | APPARATUS FOR ELECTRONIC ASSEMBLY WITH IMPROVED INTERCONNECT AND ASSOCIATED METHODS - An apparatus includes a substrate that includes electronic circuitry. The apparatus further includes a first die that includes electronic circuitry, and at least one shielded interconnect. The shielded interconnect(s) couple(s) electronic circuitry in the substrate to electronic circuitry in the first die. | 2014-09-18 |
20140264784 | Metal Shielding on Die Level - Consistent with an example embodiment, there is a semiconductor device having a front-side surface, back-side surface, and vertical surfaces. The semiconductor device comprises an active device die having electrical contacts on the front-side surface. A metal shield is plated on the back-side surface and the vertical surfaces of the active device die. Conductive links connect the plated metal shield to selected electrical contacts on the front-side surface. | 2014-09-18 |
20140264785 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and a second surface; a first recess extending from the first surface towards the second surface; a second recess extending from a bottom of the first recess towards the second surface, wherein a sidewall and the bottom of the first recess and a second sidewall and a second bottom of the second recess together form an exterior side surface of the semiconductor substrate; a wire layer disposed over the first surface and extending into the first recess and/or the second recess; an insulating layer positioned between the wire layer and the semiconductor substrate; and a metal light shielding layer disposed over the first surface and having at least one hole, wherein a shape of the at least one hole is a quadrangle. | 2014-09-18 |
20140264786 | Semiconductor Device Including RDL Along Sloped Side Surface of Semiconductor Die for Z-Direction Interconnect - A semiconductor device has a first semiconductor die with a sloped side surface. The first semiconductor die is mounted to a temporary carrier. An RDL extends from a back surface of the first semiconductor die along the sloped side surface of the first semiconductor die to the carrier. An encapsulant is deposited over the carrier and a portion of the RDL along the sloped side surface. The back surface of the first semiconductor die and a portion of the RDL is devoid of the encapsulant. The temporary carrier is removed. An interconnect structure is formed over the encapsulant and exposed active surface of the first semiconductor die. The RDL is electrically connected to the interconnect structure. A second semiconductor die is mounted over the back surface of the first semiconductor die. The second semiconductor die has bumps electrically connected to the RDL. | 2014-09-18 |
20140264787 | DIFFERENTIAL EXCITATION OF PORTS TO CONTROL CHIP-MODE MEDIATED CROSSTALK - A differential port and a method of arranging the differential port are described. The method includes arranging a first electrode to receive a drive signal, and arranging a second electrode to receive a guard signal, the guard signal having a different phase than the drive signal and the first electrode and the second electrode having a gap therebetween. The method also includes disposing a signal line from the first electrode to drive a radio frequency (RF) device. | 2014-09-18 |
20140264788 | HIGH-FREQUENCY MODULE - A high-frequency module includes a lower base member having a recess part formed in an upper face thereof, and having a base metal part formed on a lower face thereof that is to be grounded, an upper substrate disposed inside the recess part of the lower base member, a semiconductor device mounted on an upper face of the upper substrate, a first ground line connected to the semiconductor device and formed on the upper substrate, and a ground metal part connected to the base metal part and disposed in the lower base member, wherein the ground metal part is connected to the first ground line on the upper substrate. | 2014-09-18 |
20140264789 | SEMICONDUCTOR PACKAGES AND METHODS OF PACKAGING SEMICONDUCTOR DEVICES - Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a package substrate having first and second major surfaces. The package substrate includes a base substrate having a mold material and a plurality of interconnect structures including via contacts extending through the first to the second major surface of the package substrate. A die having conductive contacts on its first or second surface is provided. The conductive contacts of the die are electrically coupled to the interconnect structures. A cap is formed over the package substrate to encapsulate the die. | 2014-09-18 |
20140264790 | CHIP PACKAGE AND METHOD FOR MANUFACTURING THE SAME - Various embodiments provide a chip package. The chip package may include a metallic chip carrier; at least one chip carried by the metallic chip carrier; encapsulation material encapsulating the at least one chip and the metallic chip carrier; and a plurality of redistribution layers disposed over the at least one chip opposite the metallic chip carrier, wherein at least one redistribution layer of the plurality of redistribution layers is electrically coupled with the at least one chip. | 2014-09-18 |
20140264791 | DIRECT EXTERNAL INTERCONNECT FOR EMBEDDED INTERCONNECT BRIDGE PACKAGE - An external direct connection usable for an embedded interconnect bridge package is described. In one example, a package has a substrate, a first semiconductor die having a first bridge interconnect region, and a second semiconductor die having a second bridge interconnect region. The package has a bridge embedded in the substrate, the bridge having a first contact area to connect to the first bridge interconnect region and a second contact area to connect to the second bridge interconnect region, and an external connection rail extending between the interconnect bridge and the first and second semiconductor dies to supply external connection to the first and second bridge interconnect regions. | 2014-09-18 |
20140264792 | SEMICONDUCTOR PACKAGES AND METHODS OF PACKAGING SEMICONDUCTOR DEVICES - Semiconductor packages and methods for forming a semiconductor package are presented. The method includes providing a package substrate having first and second major surfaces. The package substrate includes at least one substrate layer having at least one cavity. Interconnect structure is formed. At least one conductive stud is formed within the cavity and a conductive trace and a connection pad are formed over the first major surface of the package substrate and are coupled to top surface of the conductive stud. A package pad is formed and is directly coupled to the conductive stud. A die having conductive contacts on its first or second surface is provided. The conductive contacts of the die are electrically coupled to the interconnect structure. A cap is formed over the package substrate to encapsulate the die. | 2014-09-18 |
20140264793 | LEAD FRAME FOR SEMICONDUCTOR PACKAGE WITH ENHANCED STRESS RELIEF - A semiconductor package includes a lead frame, a semiconductor die, bond wires providing an electrical connection between the die and the lead frame, and a mold compound that encapsulates the lead frame, the die and the bond wires. The lead frame includes spaced apart first and second frame members each having an inner peripheral edge and an opposing outer peripheral edge, spaced apart lead pads disposed between the inner peripheral edges of the first and second frame members, and conductive leads disposed proximate to the outer peripheral edge of each of the first and second frame members. The die is mounted on the lead pads. | 2014-09-18 |
20140264794 | LOW CTE INTERPOSER WITHOUT TSV STRUCTURE - A microelectronic assembly including a dielectric region, a plurality of electrically conductive elements, an encapsulant, and a microelectronic element are provided. The encapsulant may have a coefficient of thermal expansion (CTE) no greater than twice a CTE associated with at least one of the dielectric region or the microelectronic element. | 2014-09-18 |
20140264795 | NO-EXPOSED-PAD QUAD FLAT NO-LEAD (QFN) PACKAGING STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A quad flat no-lead (QFN) packaging structure. The QFN packaging structure includes a metal substrate, a first die coupled to a top surface of the metal substrate, and a plurality of I/O pads formed on the metal substrate, and extending to the proximity of the die. The no-exposed-pad QFN packaging structure also includes a first metal layer containing a plurality of inner leads corresponding to the plurality of I/O pads and extending to proximity of the die and is formed on the metal substrate by a multi-layer electrical plating process. Further, the no-exposed-pad QFN packaging structure includes metal wires connecting the die and the plurality of inner leads, and a second metal layer formed on a back surface of the plurality of I/O pads. | 2014-09-18 |
20140264796 | Insulated Bump Bonding - A semiconductor power chip, may have a semiconductor die having a power device fabricated on a substrate thereof, wherein the power device has at least one first contact element, a plurality of second contact elements and a plurality of third contact elements arranged on top of the semiconductor die; and an insulation layer disposed on top of the semiconductor die and being patterned to provide openings to access the plurality of second and third contact elements and the at least one first contact element. | 2014-09-18 |
20140264797 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The method includes the steps of: providing a lead frame, including providing a concaved part in an upper face of a joint part of a die-pad-support lead of a lead frame for setting down a die pad and a tie-bar; bonding a semiconductor chip to a first principal face of the die pad via an adhesive-member layer; then, setting the lead frame between first and second molding dies having first and second cavities respectively so that the first and second cavities are opposed to each other, and the second principal face of the die pad faces toward the second cavity; and forming first and second resin sealed bodies on the sides of the first and second principal faces of the die pad respectively by resin sealing with the first and second molding dies clamping the tie-bar and a part of the lead frame surrounding the tie-bar. | 2014-09-18 |
20140264798 | Packaged Device Comprising Non-Integer Lead Pitches and Method of Manufacturing the Same - Packaged chips comprising non-integer lead pitches, systems and methods for manufacturing packaged chips are disclosed. In one embodiment a packaged device includes a first chip, a package encapsulating the first chip and a plurality of leads protruding from the package, wherein the plurality of leads comprises differing non-integer multiple lead pitches. | 2014-09-18 |
20140264799 | POWER OVERLAY STRUCTURE AND METHOD OF MAKING SAME - A power overlay (POL) structure includes a POL sub-module. The POL sub-module includes a dielectric layer and a semiconductor device having a top surface attached to the dielectric layer. The top surface of the semiconductor device has at least one contact pad formed thereon. The POL sub-module also includes a metal interconnect structure that extends through the dielectric layer and is electrically coupled to the at least one contact pad of the semiconductor device. A conducting shim is coupled to a bottom surface of the semiconductor device and a first side of a thermal interface is coupled to the conducting shim. A heat sink is coupled to a second side of the electrically insulating thermal interface. | 2014-09-18 |
20140264800 | POWER OVERLAY STRUCTURE AND METHOD OF MAKING SAME - A semiconductor device module includes a dielectric layer, a semiconductor device having a first surface coupled to the dielectric layer, and a conducting shim having a first surface coupled to the dielectric layer. The semiconductor device also includes an electrically conductive heatspreader having a first surface coupled to a second surface of the semiconductor device and a second surface of the conducting shim. A metallization layer is coupled to the first surface of the semiconductor device and the first surface of the conducting shim. The metallization layer extends through the dielectric layer and is electrically connected to the second surface of the semiconductor device by way of the conducting shim and the heatspreader. | 2014-09-18 |
20140264801 | SEMICONDUCTOR DEVICE - A semiconductor device of the present invention comprises: an outer package; a first lead frame including a first relay lead, a first die pad with a power element mounted thereon, and a first external connection lead which has an end protruding from the outer package; and a second lead frame including a second relay lead, a second die pad with a control element mounted thereon, and a second external connection lead which has an end protruding from the outer package, wherein the first die pad and the second die pad or the first external connection lead and the second relay lead are joined to each other at a joint portion, and an end of the second relay lead extending from a joint portion with the first relay lead is located inside the outer package. | 2014-09-18 |
20140264802 | Semiconductor Device with Thick Bottom Metal and Preparation Method Thereof - A semiconductor device with thick bottom metal comprises a semiconductor chip covered with a top plastic package layer at its front surface and a back metal layer at its back surface, the top plastic package layer surrounds sidewalls of the metal bumps with a top surface of the metal bumps exposing from the top plastic package layer, a die paddle for the semiconductor chip to mount thereon and a plastic package body. | 2014-09-18 |
20140264803 | PACKAGE DEVICE INCLUDING AN OPENING IN A FLEXIBLE SUBSTRATE AND METHODS OF FORMING THE SAME - Methods and apparatus are disclosed for forming ultra-thin packages for semiconductor devices on flexible substrates. A flexible substrate may comprise a plurality of insulating layers and redistribution layers. Openings of the flexible substrate may be formed at one side of the flexible substrate, two sides of the flexible substrate, or simply cut through the flexible substrate to divide the flexible substrate into two parts. Connectors may be placed within the opening of the flexible substrate and connected to redistribution layers of the flexible substrate. Dies can be attached to the connectors and electrically connected to the connectors and to the redistribution layers of the flexible substrate. Structure supports may be placed at another side of the flexible substrate on the surface or within an opening. | 2014-09-18 |
20140264804 | STACK DIE PACKAGE - In one embodiment, a stack die package can include a lead frame and a first die including a gate and a source that are located on a first surface of the first die and a drain that is located on a second surface of the first die that is opposite the first surface. The gate and source are flip chip coupled to the lead frame. The stack die package can include a second die including a gate and a drain that are located on a first surface of the second die and a source that is located on a second surface of the second die that is opposite the first surface. The source of the second die is facing the drain of the first die. | 2014-09-18 |
20140264805 | Semiconductor Package And Fabrication Method Thereof - A method of making a semiconductor packaged device comprises mounting onto a lead frame a bottom of a molded semiconductor chip having a first plastic package body covering a top face of a semiconductor chip, encapsulating the lead frame and the semiconductor chip with a second plastic package body with top surfaces of conductive contact bodies electrically connected to electrodes on the top surface of the semiconductor chip exposed and plating conductive pads on a top surface of the assembly structure to provide external electrical connections to the electrodes through the conductive contact bodies. | 2014-09-18 |
20140264806 | SEMICONDUCTOR DEVICES AND METHODS OF MAKING THE SAME - In one embodiment, methods for making semiconductor devices are disclosed. | 2014-09-18 |
20140264807 | SEMICONDUCTOR DEVICE - Conventional semiconductor devices have a problem that it is difficult to prevent the short circuit between chips and to improve accuracy in temperature detection with the controlling semiconductor chips. In a semiconductor device of the present invention, a first mount region to which a driving semiconductor chip is fixedly attached and a second mount region to which a controlling semiconductor chip is fixedly attached are formed isolated from each other. A projecting area is formed in the first mount region, and the projecting area protrudes into the second mount region. The controlling semiconductor chip is fixedly attached to the top surfaces of the projecting area and the second mount region by use of an insulating adhesive sheet material. This structure prevents the short circuit between the two chips, and improves accuracy in temperature detection with the controlling semiconductor chip. | 2014-09-18 |
20140264808 | CHIP ARRANGEMENTS, CHIP PACKAGES, AND A METHOD FOR MANUFACTURING A CHIP ARRANGEMENT - A chip arrangement may include a semiconductor chip; an encapsulation layer at least partially encapsulating the semiconductor chip, the encapsulation layer having a receiving region configured to receive an electronic device, the receiving region comprising a cavity; and an electronic device disposed in the receiving region. | 2014-09-18 |
20140264809 | BACKPLATE INTERCONNECT WITH INTEGRATED PASSIVES - This disclosure provides systems, methods and apparatus for manufacturing display devices having electronic components mounted within a display device package. In one aspect, the electronic component connects to the exterior of the display device through pads that run below a seal that holds a substrate and a backplate of the display device together. In another aspect the electronic components also connect to an electromechanical device within the display device, as well as connecting to pads that are external to the display device. | 2014-09-18 |
20140264810 | Packages with Molding Material Forming Steps - A package includes a first package component having a top surface, a second package component bonded to the top surface of the first package component, and a plurality of electrical connectors at the top surface of the first package component. A molding material is over the first package component and molding the second package component therein. The molding material includes a first portion overlapping the second package component, wherein the first portion includes a first top surface, and a second portion encircling the first portion and molding bottom portions of the plurality of electrical connectors therein. The second portion has a second top surface lower than the first top surface. | 2014-09-18 |
20140264811 | Package-On-Package with Cavity in Interposer - A package includes an interposer, which includes a core dielectric material, a through-opening extending from a top surface to a bottom surface of the core dielectric material, a conductive pipe penetrating through the core dielectric material, and a device die in the through-opening. The device die includes electrical connectors. A top package is disposed over the interposer. A first solder region bonds the top package to the conductive pipe, wherein the first solder region extends into a region encircled by the conductive pipe. A package substrate is underlying the interposer. A second solder region bonds the package substrate to the interposer. | 2014-09-18 |
20140264812 | SEMICONDUCTOR PACKAGE ASSEMBLY - The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package. The first semiconductor package includes a first body having a first device-attach surface and a first bump-attach surface opposite to the first device-attach surface. A second semiconductor package is bonded to the first device-attach surface of the first semiconductor package. The second package includes a second body having a second device-attach surface and a second bump-attach surface opposite to the second device-attach surface. A dynamic random access memory (DRAM) device is mounted on the second device-attach surface. A decoupling capacitor is mounted on the second device-attach surface. Conductive structures are disposed on the second bump-attach surface of the second package, connecting to the first bump-attach surface of the first body of the first semiconductor package. | 2014-09-18 |
20140264813 | Semiconductor Device Package and Method - Various packages and methods of forming packages are disclosed. In an embodiment, a package includes a hybrid encapsulant encapsulating a chip attached to a substrate. The hybrid encapsulant comprises a first molding compound and a second molding compound that has a different composition than the first molding compound. In another embodiment, a package includes an encapsulant encapsulating a chip attached to a substrate. A surface of the chip is exposed through the encapsulant. The encapsulant comprises a recess in a surface of a first molding compound proximate the surface of the chip. A thermal interface material is on the surface of the chip and in the recess, and a lid is attached to the thermal interface material. | 2014-09-18 |
20140264814 | SEMICONDUCTOR CHIP, METHOD FOR MANUFACTURING A SEMICONDUCTOR CHIP, DEVICE AND METHOD FOR MANUFACTURING A DEVICE - Embodiments of the present invention relate to a semiconductor chip comprising a plurality of contact pads, which are arranged in an edge area on a surface of the semiconductor chip. In a semiconductor area of the semiconductor chip, every contact pad of the plurality of contact pads has an associated pad cell provided, which includes at least one of a driver or a receiver and is configured to drive output signals or receive input signals on its associated contact pad, if the driver or receiver is connected to the contact pad. Additionally, for a contact pad which is used as a supply contact pad, the driver or receiver of the associated pad cell is not connected to the contact pad or any other contact pad for driving output signals or receiving input signals on the same. | 2014-09-18 |
20140264815 | Semiconductor Device Package and Method - Various packages and methods are disclosed. A package according to an embodiment includes a substrate, a chip attached to a surface of the substrate with electrical connectors, a molding compound on the surface of the substrate and around the chip, an adhesive on a surface of the chip that is distal from the surface of the substrate, and a lid on the adhesive. In an embodiment, a region between the molding compound and the lid at a corner of the lid is free from the adhesive. In another embodiment, the lid has a recess in a surface of the lid facing the surface of the molding compound. | 2014-09-18 |
20140264816 | SEMICONDUCTOR PACKAGE STRUCTURE - Various embodiments relating to semiconductor package structures having reduced thickness while maintaining rigidity are provided. In one embodiment, a semiconductor package structure includes a substrate including a surface, a semiconductor die including a first interface surface connected to the surface of the substrate and a second interface surface opposing the first interface surface, a mold compound applied to the substrate surrounding the semiconductor die. The second interface surface of the semiconductor die is exposed from the mold compound. The semiconductor package structure includes a heat dissipation cover attached to the second interface surface of the semiconductor die and the mold compound. | 2014-09-18 |
20140264817 | Semiconductor Device and Method of Using Partial Wafer Singulation for Improved Wafer Level Embedded System in Package - A semiconductor device includes a semiconductor wafer including a plurality of first semiconductor die. An opening is formed partially through the semiconductor wafer. A plurality of second semiconductor die is disposed over a first surface of the semiconductor wafer. An encapsulant is disposed over the semiconductor wafer and into the opening leaving a second surface of the semiconductor wafer exposed. A portion of the second surface of the semiconductor wafer is removed to separate the first semiconductor die. An interconnect structure is formed over the second semiconductor die and encapsulant. A thermal interface material is deposited over the second surface of the first semiconductor die. A heat spreader is disposed over the thermal interface material. An insulating layer is formed over the first surface of the semiconductor wafer. A vertical interconnect structure is formed around the first semiconductor die. Conductive vias are formed through the first semiconductor die. | 2014-09-18 |
20140264818 | POLYMER THERMAL INTERFACE MATERIAL HAVING ENHANCED THERMAL CONDUCTIVITY - A polymer thermal interface material is described that has enhanced thermal conductivity. In one example, a vinyl-terminated silicone oil is combined with a silicone chain extender, and a thermally conductive filler comprising at least 85% by weight of the material, and comprising surface wetted particles with a range of shapes and sizes. The material may be used for bonding components inside a microelectronic package, for example. | 2014-09-18 |
20140264819 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a link portion that connects a second heat sink to a third heat sink via a solder. The solder is arranged on a connecting surface of a base portion of the link portion, which is orthogonal to a plate thickness direction of the base portion, in a direction perpendicular to first and second surfaces. The link portion has a rib that protrudes from the base portion in a direction orthogonal to the first and second surfaces, and a thickness of a portion where the rib is provided is equal to or less than the thickness of the corresponding heat sink. The rib is provided across an entire length of a first region that is sealed by a sealing resin body and that is between the second and the third heat sinks, in an alignment direction of a first heat sink and the third heat sink. | 2014-09-18 |
20140264820 | PASTE THERMAL INTERFACE MATERIALS - Embodiments of the present disclosure describe techniques and configurations for paste thermal interface materials (TIMs) and their use in integrated circuit (IC) packages. In some embodiments, an IC package includes an IC component, a heat spreader, and a paste TIM disposed between the die and the heat spreader. The paste TIM may include particles of a metal material distributed through a matrix material, and may have a bond line thickness, after curing, of between approximately 20 microns and approximately 100 microns. Other embodiments may be described and/or claimed. | 2014-09-18 |
20140264821 | MOLDED HEAT SPREADERS - Embodiments of the present disclosure describe techniques and configurations for molded heat spreaders. In some embodiments, a heat spreader includes a first insert having a first face and a first side, the first face positioned to form a bottom surface of a first cavity, and a second insert having a second face and a second side, the second face positioned to form a bottom surface of a second cavity. The second cavity may have a depth that is different from a depth of the first cavity. The heat spreader may further include a molding material disposed between the first and second inserts and coupled with the first side and the second side, the molding material forming at least a portion of a side wall of the first cavity and at least a portion of a side wall of the second cavity. Other embodiments may be described and/or claimed. | 2014-09-18 |
20140264822 | THERMOSETTING RESIN COMPOSITIONS WITH LOW COEFFICIENT OF THERMAL EXPANSION - Thermosetting resin compositions with low coefficient of thermal expansion are provided herein. | 2014-09-18 |
20140264823 | Systems and Methods for Fabricating Semiconductor Devices Having Larger Die Dimensions - A method of fabricating a semiconductor device is disclosed. A photosensitive material is coated over the device. A plurality of masks for a chip layout are obtained. The plurality of masks are exposed to encompass a chip area of the device using at least one reticle repeatedly. The at least one reticle is of a set of reticles. The chip area has a resultant dimension greater than a dimension of the at least one reticle. A developer is used to remove soluble portions of the photosensitive material forming a resist pattern in the chip area. level shifter system | 2014-09-18 |
20140264824 | Methods and Apparatus of Packaging Semiconductor Devices - Methods and apparatus are disclosed which reduce the stress concentration at the redistribution layers (RDLs) of a package device. A package device may comprise a seed layer above a passivation layer, covering an opening of the passivation layer, and covering and in contact with a contact pad. A RDL is formed above the passivation layer, above and in contact with the seed layer, covering the opening of the passivation layer, and electrically connected to the contact pad through the seed layer. The RDL has an end portion with a surface that is smooth without a right angle. The surface of the end portion of the RDL may have an obtuse angle, or a curved surface. | 2014-09-18 |
20140264825 | Ultra-Low Resistivity Contacts - Contacts for semiconductor devices and methods of making thereof are disclosed. A method comprises forming a first layer on a semiconductor, the first layer comprising one or more metals; forming a second layer on the first layer, the second layer comprising the one or more metals, nitrogen and oxygen; and heating the first and second layer such that oxygen migrates from the second layer into the first layer and the first layer comprises a sub-stoichiometric metal oxide after heating. Exemplary embodiments use transition metals such as Ti in the first layer. After heating there is a sub-stoichiometric oxide layer of about 2.5 nm thickness between a metal nitride conductor and the semiconductor. The specific contact resistivity is less than about 7×10 | 2014-09-18 |
20140264826 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE FABRICATION METHOD - A semiconductor device has a structure including a substrate, a first insulating film formed over a part of a principal plane of the substrate, a conductive portion formed over a surface of the first insulating film, and a second insulating film which covers the principal plane of the substrate, the first insulating film, and the conductive portion and whose moisture resistance is higher than moisture resistance of the first insulating film. The first insulating film is placed between the substrate and the conductive portion to prevent the generation of parasitic capacitance. The first insulating film is covered with the second insulating film whose moisture resistance is higher than the moisture resistance of the first insulating film. The second insulating film prevents the first insulating film from absorbing moisture. | 2014-09-18 |
20140264827 | METHODS OF FORMING WAFER LEVEL UNDERFILL MATERIALS AND STRUCTURES FORMED THEREBY - Methods of forming microelectronic packaging structures and associated structures formed thereby are described. Those methods and structures may include forming a wafer level underfill (WLUF) material comprising a resin material, and adding at least one of a UV absorber, a sterically hindered amine light stabilizer (HALS), an organic surface protectant (OSP), and a fluxing agent to form the WLUF material. The WLUF is then applied to a top surface of a wafer comprising a plurality of die. | 2014-09-18 |
20140264828 | Method and Apparatus for a Conductive Pillar Structure - A method and apparatus for a conductive pillar structure is provided. A device may be provided, which may include a substrate, a first passivation layer formed over the substrate, a conductive interconnect extending through the first passivation layer and into the substrate, a conductive pad formed over the first passivation layer, and a second passivation layer formed over the interconnect pad and the second passivation layer. A portion of the interconnect pad may be exposed from the second passivation layer. The conductive pillar may be formed directly over the interconnect pad using one or more electroless plating processes. The conductive pillar may have a first and a second width and a first height corresponding to a distance between the first width and the second width. | 2014-09-18 |
20140264829 | ELECTRONIC ASSEMBLY WITH COPPER PILLAR ATTACH SUBSTRATE - An electronic assembly includes a copper pillar attach substrate that has a dielectric layer and a solder resist layer overlying the dielectric layer. The solder resist layer has a plurality of solder resist openings. A plurality of parallel traces are formed on the dielectric layer. Each trace has a first end portion, a second end portion and an intermediate portion. The first and second end portions of each trace are covered by the solder resist layer and the intermediate portions are positioned in the solder resist openings. Each of the intermediate portions has at least one conductive coating layer on it and has a height measured from the dielectric layer to the top of the topmost conductive coating layer that is at least as great as the solder resist layer thickness. | 2014-09-18 |
20140264830 | BUMPLESS BUILD-UP LAYER (BBUL) SEMICONDUCTOR PACKAGE WITH ULTRA-THIN DIELECTRIC LAYER - Bumpless build-up layer (BBUL) semiconductor packages with ultra-thin dielectric layers are described. For example, an apparatus includes a semiconductor die including an integrated circuit having a plurality of external conductive bumps. A semiconductor package houses the semiconductor die. The semiconductor package includes a dielectric layer disposed above the plurality of external conductive bumps. A conductive via is disposed in the dielectric layer and coupled to one of the plurality of conductive bumps. A conductive line is disposed on the dielectric layer and coupled to the conductive via. | 2014-09-18 |
20140264831 | CHIP ARRANGEMENT AND A METHOD FOR MANUFACTURING A CHIP ARRANGEMENT - A chip arrangement may include: a first semiconductor chip having a first side and a second side opposite the first side; a second semiconductor chip having a first side and a second side opposite the first side, the second semiconductor chip disposed at the first side of the first semiconductor chip and electrically coupled to the first semiconductor chip, the first side of the second semiconductor chip facing the first side of the first semiconductor chip; an encapsulation layer at least partially encapsulating the first semiconductor chip and the second semiconductor chip, the encapsulation layer having a first side and a second side opposite the first side, the second side facing in a same direction as the second side of the second semiconductor chip; and an interconnect structure disposed at least partially within the encapsulation layer and electrically coupled to at least one of the first and second semiconductor chips, wherein the interconnect structure may extend to the second side of the encapsulation layer. | 2014-09-18 |
20140264832 | CHIP ARRANGEMENTS - A chip arrangement may include: a first chip including a first contact, a second contact, and a redistribution structure electrically coupling the first contact to the second contact; a second chip including a contact; and a plurality of interconnects electrically coupled to the second contact of the first chip, wherein at least one interconnect of the plurality of interconnects electrically couples the second contact of the first chip to the contact of the second chip. | 2014-09-18 |
20140264833 | SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME - A semiconductor package includes through-chip vias each penetrating through a semiconductor substrate and having a protrusion that is protruded from the backside of the semiconductor substrate; and a passivation layer formed on the backside of the semiconductor substrate and planarized corresponding to the surface of the protrusions of the through-chip vias, wherein the passivation layer includes a first insulation layer formed on the side of the protrusions of the through-chip vias and the backside of the semiconductor substrate, and a second insulation layer formed over the first insulation layer. | 2014-09-18 |
20140264834 | Low Cost and Ultra-Thin Chip on Wafer on Substrate (CoWoS) Formation - Methods of making and an integrated circuit device. An embodiment method includes patterning a first polymer layer disposed over a first copper seed layer, electroplating a through polymer via in the first polymer layer using the first copper seed layer, a via end surface offset from a first polymer layer surface, forming a second polymer layer over the first polymer layer, the second polymer layer patterned to expose the via end surface, and electroplating an interconnect in the second polymer layer to cap the via end surface using a second copper seed layer. | 2014-09-18 |
20140264835 | SEMICONDUCTOR PACKAGES AND METHODS OF PACKAGING SEMICONDUCTOR DEVICES - Package substrate, semiconductor packages and methods for forming a semiconductor package are presented. The package substrate includes a base substrate having first and second major surfaces and a plurality of via contacts extending through the first to the second major surfaces of the base substrate. A first conductive layer having a plurality of openings is disposed over the first surface of the base substrate and via contacts. The openings are configured to match conductive trace layout of the package substrate. Conductive traces are disposed over the first conductive layer. The conductive traces are directly coupled to the via contacts through some of the openings of the first conductive layer. | 2014-09-18 |
20140264836 | SYSTEM-IN-PACKAGE WITH INTERPOSER PITCH ADAPTER - An integrated circuit package is disclosed that includes a first-pitch die and a second-pitch die. The second-pitch die interconnects to the second-pitch substrate through second-pitch substrates. The first-pitch die interconnects through first-pitch interconnects to an interposer adapter. The pitch of the first-pitch interconnects is too fine for the second-pitch substrate. But the interposer adapter interconnects through second-pitch interconnects to the second-pitch substrate and includes through substrate vias so that I/O signaling between the first-pitch die and the second-pitch die can be conducted through the second-pitch substrate and through the through substrate vias in the interposer adapter. | 2014-09-18 |
20140264837 | SEMICONDUCTOR DEVICE WITH POST-PASSIVATION INTERCONNECT STRUCTURE AND METHOD OF FORMING THE SAME - A semiconductor device, including a protective layer overlying a contact pad and a dummy pad on a semiconductor substrate, an interconnect structure overlying the protective layer and contacting part of the dummy pad through a contact via passing through the protective layer, a bump overlying the interconnect structure positioned over the dummy pad. | 2014-09-18 |
20140264838 | Method and Apparatus for a Conductive Bump Structure - A method and apparatus for a conductive bump structure is provided. The conductive bump structure may include a conductive layer and a conductive bump formed over a through via (“TV”). The TV may be formed through a substrate and a passivation layer. The TV may have a top surface extending above a top surface of the passivation layer. The conductive layer may be formed directly over the TV using one or more electroless plating processes. The conductive layer may have sides that may taper from a top surface of the conductive layer to the top surface of the passivation layer. The conductive layer may include a plurality of layers, wherein each layer may be formed using one or more electroless plating processes. The conductive bump may be formed on the conductive layer and may be reflowed to couple the conductive bump to the conductive layer. | 2014-09-18 |
20140264839 | Packaged Semiconductor Devices, Methods of Packaging Semiconductor Devices, and PoP Devices - Packaged semiconductor devices, methods of packaging semiconductor devices, and package-on-package (PoP) devices are disclosed. In some embodiments, a method of packaging a semiconductor device includes forming through-package vias (TPVs) over a carrier, and coupling a semiconductor device to the carrier. The semiconductor device includes contact pads disposed on a surface thereof and an insulating material disposed over the contact pads. A molding material is formed over the carrier between the TPVs and the semiconductor device. Openings are formed in the insulating material using a laser drilling process over the contact pads, and a redistribution layer (RDL) is formed over the insulating material and the openings in the insulating material. A portion of the RDL is coupled to a top surface of each of the contact pads. | 2014-09-18 |
20140264840 | Package-on-Package Structure - A device comprises a top package mounted on a bottom package, wherein the bottom package comprises a plurality of interconnection components and the bottom package comprises a plurality of first bumps formed on a first side of the bottom package, a semiconductor die is bonded on a second side of the bottom package, wherein the semiconductor die is electrically coupled to the first bumps through the interconnection components and the semiconductor die is located between the top package and the bottom package, and an underfill layer formed between the top package and the bottom package. | 2014-09-18 |
20140264841 | Surface Treatment in Electroless Process for Adhesion Enhancement - An embodiment method of forming and a bump structure are disclosed. The bump structure includes a passivation layer formed over a metal pad, the passivation layer having a recess exposing a portion of the metal pad, and a metal bump formed over the metal pad, the metal bump having a lip extending beneath the passivation layer, the lip anchoring the metal bump to the passivation layer. | 2014-09-18 |
20140264842 | Package-on-Package Structure and Method of Forming Same - A device comprises a bottom package comprising interconnect structures, first bumps on a first side and metal bumps on a second side, a semiconductor die bonded on the bottom package, wherein the semiconductor die is electrically coupled to the first bumps through the interconnect structures. The device further comprises a top package bonded on the second side of the bottom package, wherein the top package comprises second bumps, and wherein each second bump and a corresponding metal bump form a joint structure between the top package and the bottom package and an underfill layer formed between the top package and the bottom package, wherein the metal bumps are embedded in the underfill layer. | 2014-09-18 |
20140264843 | Integrated Circuit Structure Having Dies with Connectors - An embodiment is an integrated circuit structure including a first die having a bump structure, and a second die having a pad structure. The first die is attached to the second die by bonding the bump structure and the pad structure. The bump structure includes a metal pillar, a metal cap layer on the metal pillar, a metal insertion layer on the metal cap layer, and a solder layer on the metal insertion layer. The pad structure includes at least one of a nickel (Ni) layer, a palladium (Pd) layer or a gold (Au) layer. | 2014-09-18 |
20140264844 | SEMICONDUCTOR DEVICE HAVING A DIE AND THROUGH SUBSTRATE-VIA - Semiconductor devices are described that have a through-substrate via formed therein. In one or more implementations, the semiconductor devices include a semiconductor wafer and an integrated circuit die bonded together with an adhesive material. The semiconductor wafer and the integrated circuit die include one or more integrated circuits formed therein. The integrated circuits are connected to one or more conductive layers deployed over the surfaces of the semiconductor wafer and an integrated circuit die. A via is formed through the semiconductor wafer and the patterned adhesive material so that an electrical interconnection can be formed between the integrated circuits formed in the semiconductor wafer and the integrated circuits formed in the integrated circuit die. The via includes a conductive material that furnishes the electrical interconnection between the semiconductor wafer and the integrated circuit die. | 2014-09-18 |
20140264845 | WAFER-LEVEL PACKAGE DEVICE HAVING HIGH-STANDOFF PERIPHERAL SOLDER BUMPS - A wafer-level package device and techniques for fabricating the device are described that include a second integrated circuit chip electrically coupled to a base integrated circuit chip, where the second integrated circuit chip is placed on and connected to the base integrated circuit chip between multiple high-standoff peripheral pillars with solder bumps. In implementations, the wafer-level package device that employs example techniques in accordance with the present disclosure includes a base integrated circuit chip, multiple high-standoff peripheral pillars with solder bumps, and a second integrated circuit chip electrically coupled to the base integrated circuit chip and placed on the base integrated circuit chip in the center of an array of high-standoff peripheral pillars with solder bumps. | 2014-09-18 |
20140264846 | Packaging Devices, Methods of Manufacture Thereof, and Packaging Methods - Packaging devices, methods of manufacture thereof, and packaging methods are disclosed. In some embodiments, a packaging device includes a first substrate including a post passivation interconnect (PPI) structure including a PPI pad disposed thereon, and a second substrate including a contact pad disposed thereon. A conductive bump is coupled between the PPI pad and the contact pad. A molding material is disposed over portions of the PPI structure proximate the conductive bump. A top surface of the molding material contacts the conductive bump at a height of the conductive bump having a width C, and the contact pad has a width B. A ratio R of C:B comprises about 1.0 or greater. | 2014-09-18 |
20140264847 | SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of electrodes disposed on a surface in a first column and a second column parallel to the first and separated by a first distance. The adjacent electrodes in the first column are spaced from each other by at least a second distance. Adjacent electrodes in the second column are spaced from each other by at least a third distance. The distance between adjacent columns is not equal to the spacing distance of electrodes in the first column and the electrodes form a staggered lattice in which no electrode in the first column is aligned perpendicularly with any electrode in the second column. | 2014-09-18 |
20140264848 | SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME - A semiconductor package includes through-substrate vias each penetrating through a semiconductor substrate and having a protrusion that is protruded from the backside of the semiconductor substrate, and a passivation layer formed on a sidewall of the protrusion and the backside of the semiconductor substrate, wherein a bottom surface of the protrusion and a bottom surface of the passivation layer are substantially coplanar. | 2014-09-18 |
20140264849 | Package-on-Package Structure - A device comprises a bottom package mounted on a printed circuit board, wherein the bottom package comprises a plurality of first bumps formed between the bottom package and the printed circuit board, a first underfill layer formed between the printed circuit board and the bottom package, a semiconductor die mounted on the bottom package and a top package bonded on the bottom package, wherein the top package comprises a plurality of second bumps and the top package and the bottom package form a ladder shaped structure. The device further comprises a second underfill layer formed between the bottom package and the top package, wherein the second underfill layer is formed of a same material as the first underfill layer. | 2014-09-18 |
20140264850 | Semiconductor Device and Method of Forming a Dual UBM Structure for Lead Free Bump Connections - A semiconductor device has a substrate with a contact pad. A first insulation layer is formed over the substrate and contact pad. A first under bump metallization (UBM) is formed over the first insulating layer and is electrically connected to the contact pad. A second insulation layer is formed over the first UBM. A second UBM is formed over the second insulation layer after the second insulation layer is cured. The second UBM is electrically connected to the first UBM. The second insulation layer is between and separates portions of the first and second UBMs. A photoresist layer with an opening over the contact pad is formed over the second UBM. A conductive bump material is deposited within the opening in the photoresist layer. The photoresist layer is removed and the conductive bump material is reflowed to form a spherical bump. | 2014-09-18 |
20140264851 | Semiconductor Device and Method of Forming UBM Structure on Back Surface of TSV Semiconductor Wafer - A semiconductor device has a plurality of conductive vias formed through the semiconductor die with a first insulating layer around the conductive vias. A recess is formed in the first insulating layer around the conductive vias by LDA. A portion of the semiconductor wafer is removed by LDA after forming the recess in the first insulating layer so that the conductive vias extend above a surface of the semiconductor wafer. The first insulating layer extends to the surface of the semiconductor wafer or above the surface of the semiconductor wafer. A second insulating layer is formed over the surface of the semiconductor wafer and conductive vias. A first portion of the second insulating layer is removed by LDA, while leaving a second portion of the second insulating layer over the surface of the semiconductor wafer around the conductive vias. An electroless plated bump is formed over the conductive vias. | 2014-09-18 |
20140264852 | METHOD FOR FORMING BUMPS IN SUBSTRATES WITH THROUGH VIAS - A method for manufacturing solder bumps for through vias in a substrate having a first surface and a second surface opposed to each other. The method includes the steps of forming a blind hole extending in the substrate from the first surface for each via and filling each blind hole with a conductive filler; a deepest part of each filler includes a bump portion made of a solder material. The method further includes the step of removing a part of the substrate extending from the second surface to have at least the bump portions protrude from the substrate. The non-protruding part of each filler defines the corresponding via and the bump portion defines the corresponding bump. | 2014-09-18 |
20140264853 | Adhesion between Post-Passivation Interconnect Structure and Polymer - An embodiment integrated circuit structure includes a substrate, a metal pad over the substrate, a post-passivation interconnect (PPI) structure over the substrate and electronically connected to the metal pad, a thin oxide film layer directly over a top surface of the PPI structure, and a polymer layer over the thin oxide film layer and PPI structure. | 2014-09-18 |
20140264854 | MULTI-CHIP MODULE WITH SELF-POPULATING POSITIVE FEATURES - A multi-chip module (MCM) is described. This MCM includes at least two substrates that are mechanically coupled and aligned by positive and negative features on facing surfaces of the substrates. These positive and negative features may mate and self-lock with each other. The positive features may be self-populated into the negative features on at least one of the substrates using a hydrophilic layer in the negative feature. This hydrophilic layer may be used in conjunction with a hydrophobic layer surrounding the negative features on a top surface of at least one of the substrates. | 2014-09-18 |
20140264855 | SEMICONDUCTOR COMPOSITE LAYER STRUCTURE AND SEMICONDUCTOR PACKAGING STRUCTURE HAVING THE SAME THEREOF - A semiconductor composite layer structure disposed on a substrate having an electronic circuit structure and a first conductive layer is disclosed. The semiconductor composite layer structure comprises a plurality of dielectric layers, a first wetting layer, a stiff layer and a second wetting layer. The dielectric layers are disposed on the substrate separately. The first wetting layer is disposed on the dielectric layer and the substrate between the dielectric layers. The stiff layer is disposed on the first wetting layer. The second wetting layer is disposed on stiff layer, for contacting with a second conductive layer. | 2014-09-18 |
20140264856 | Package-on-Package Structures and Methods for Forming the Same - A package includes a package component, which further includes a top surface and a metal pad at the top surface of the package component. The package further includes a non-reflowable electrical connector over and bonded to the metal pad, and a molding material over the package component. The non-reflowable electrical connector is molded in the molding material and in contact with the molding material. The non-reflowable electrical connector has a top surface lower than a top surface of the molding compound. | 2014-09-18 |
20140264857 | Package-on-Package with Via on Pad Connections - An interposer includes a core dielectric material, a conductive pipe penetrating through the core dielectric material, and a metal pad underlying the conductive pipe. The metal pad includes a center portion overlapped by a region encircled by the conductive pipe, and an outer portion in contact with the conductive pipe. A dielectric layer is underlying the core dielectric material and the metal pad. A via is in the dielectric layer, wherein the via is in physical contact with the center portion of the metal pad. | 2014-09-18 |
20140264858 | Package-on-Package Joint Structure with Molding Open Bumps - A device comprises a bottom package comprising a plurality of metal bumps formed on a first side of the bottom package and a plurality of first bumps formed on a second side of the bottom package, a top package bonded on the bottom package, wherein the top package comprises a plurality of second bumps, and wherein second bumps and respective metal bumps form a joint structure and an underfill layer formed between the top package and the bottom package, wherein the metal bumps are embedded in the underfill layer. | 2014-09-18 |
20140264859 | Packaging Devices and Methods of Manufacture Thereof - Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a method of manufacturing a packaging device includes forming an interconnect wiring over a substrate, and forming conductive balls over portions of the interconnect wiring. A molding material is deposited over the conductive balls and the substrate, and a portion of the molding material is removed from over scribe line regions of the substrate. | 2014-09-18 |
20140264860 | RECTIFIER DIODE - A rectifier diode includes a substrate defining an even number of through holes, one or a number of bare chip diodes placed on the top surface of the substrate with even number of conducting grooves thereof respectively kept in alignment with respective through holes of the substrate, and a conducting unit including a metal interface layer coated on exposed surfaces of each bare chip diode and the substrate using, a conductive metal thin film covered over the metal interface layer and defining an electroplating space within each through hole of the substrate and the corresponding conducting groove of one bare chip diode and a conducting medium coated in each electroplating space to form an electrode pin and a bond pad. | 2014-09-18 |