38th week of 2014 patent applcation highlights part 55 |
Patent application number | Title | Published |
20140264661 | MEMS Devices and Methods for Forming Same - Embodiments of the present disclosure include MEMS devices and methods for forming MEMS devices. An embodiment is a method for forming a microelectromechanical system (MEMS) device, the method including forming a MEMS wafer having a first cavity, the first cavity having a first pressure, and bonding a carrier wafer to a first side of the MEMS wafer, the bonding forming a second cavity, the second cavity having a second pressure, the second pressure being greater than the first pressure. The method further includes bonding a cap wafer to a second side of the MEMS wafer, the second side being opposite the first side, the bonding forming a third cavity, the third cavity having a third pressure, the third pressure being greater than the first pressure and less than the second pressure. | 2014-09-18 |
20140264662 | MEMS Integrated Pressure Sensor and Microphone Devices and Methods of Forming Same - A method embodiment for forming a micro-electromechanical (MEMS) device includes providing a MEMS wafer, wherein a portion of the MEMS wafer is patterned to provide a first membrane for a microphone device and a second membrane for a pressure sensor device. A carrier wafer is bonded to the MEMS wafer, and the carrier wafer is etched to expose the first membrane for the microphone device to an ambient environment. A MEMS substrate is patterned and portions of a first sacrificial layer are removed of the MEMS wafer to form a MEMS structure. A cap wafer is bonded to a side of the MEMS wafer opposing the carrier wafer to form a first sealed cavity including the MEMS structure. A second sealed cavity and a cavity exposed to an ambient environment on opposing sides of the second membrane for the pressure sensor device are formed. | 2014-09-18 |
20140264663 | MEMORY CELLS, METHODS OF FABRICATION, SEMICONDUCTOR DEVICE STRUCTURES, AND MEMORY SYSTEMS - Magnetic memory cells, methods of fabrication, semiconductor device structures, and memory systems are disclosed. A magnetic cell core includes at least one magnetic region (e.g., a free region or a fixed region) configured to exhibit a vertical magnetic orientation, at least one oxide-based region, which may be a tunnel junction region or an oxide capping region, and at least one magnetic interface region, which may comprise or consist of iron (Fe). In some embodiments, the magnetic interface region is spaced from at least one oxide-based region by a magnetic region. The presence of the magnetic interface region enhances the perpendicular magnetic anisotropy (PMA) strength of the magnetic cell core. In some embodiments, the PMA strength may be enhanced more than 50% compared to that of the same magnetic cell core structure lacking the magnetic interface region. | 2014-09-18 |
20140264664 | PARALLEL SHUNT PATHS IN THERMALLY ASSISTED MAGNETIC MEMORY CELLS - A thermally assisted magnetic memory cell device includes a substrate, a first electrode disposed on the substrate, a magnetic tunnel junction disposed on the first electrode, a second electrode disposed on the magnetic tunnel junction, a conductive hard mask disposed on the second electrode and a parallel shunt path coupled to the magnetic tunnel junction, thereby electrically coupling the first and second electrodes. | 2014-09-18 |
20140264665 | Reader Sensor Structure and its Method of Construction - A TMR (tunneling magnetoresistive) read sensor is formed in which a portion of the sensor stack containing the ferromagnetic free layer and the tunneling barrier layer is patterned to define a narrow trackwidth, but a synthetic antiferromagnetic pinning/pinned layer is left substantially unpatterned and extends in substantially as-deposited form beyond the lateral edges bounding the patterned portion. The narrow trackwidth of the patterned portion permits high resolution for densely recorded data. The larger pinning/pinned layer significantly improves magnetic stability and reduces thermal noise, while the method of formation eliminates possible ion beam etch (IBE) or reactive ion etch (RIE) damage to the edges of the pinning/pinned layer. | 2014-09-18 |
20140264666 | CELL DESIGN FOR EMBEDDED THERMALLY-ASSISTED MRAM - A thermally assisted magnetoresistive random access memory cell, a corresponding array, and a method for fabricating the array. An example cell includes a first metal layer, a second metal layer, an interlayer, a first magnetic stack, and a first non-magnetic via. The first metal layer includes a pad and a first metal line, with the pad not in direct contact with the first metal line. The second metal layer includes a second metal line and a metal strap. The second metal line is perpendicular to the first metal line and not in contact with the metal strap. The interlayer is located between the first and second metal layers. The first metal line is not in direct contact with the interlayer. The first magnetic stack is in direct contact with the interlayer and the metal strap. The first non-magnetic via is in direct contact with the pad and the metal strap. | 2014-09-18 |
20140264667 | Vertical Hall Effect Element With Structures to Improve Sensitivity - A vertical Hall Effect element includes one or more of: a low voltage P-well region disposed at a position between pickups of the vertical Hall Effect element, Light-N regions disposed under the pickups, a pre-epi implant region, or two epi regions to result in an improved sensitivity of the vertical Hall Effect element. A method results in the vertical Hall Effect element having the improved sensitivity. | 2014-09-18 |
20140264668 | LOGIC CHIP INCLUDING EMBEDDED MAGNETIC TUNNEL JUNCTIONS - An embodiment integrates memory, such as spin-torque transfer magnetoresistive random access memory (STT-MRAM) within a logic chip. The STT-MRAM includes a magnetic tunnel junction (MTJ) that has an upper MTJ layer, a lower MTJ layer, and a tunnel barrier directly contacting the upper MTJ layer and the lower MTJ layer; wherein the upper MTJ layer includes an upper MTJ layer sidewall and the lower MTJ layer includes a lower MTJ sidewall horizontally offset from the upper MTJ layer. Another embodiment includes a memory area, comprising a MTJ, and a logic area located on a substrate; wherein a horizontal plane intersects the MTJ, a first Inter-Layer Dielectric (ILD) material adjacent the MTJ, and a second ILD material included in the logic area, the first and second ILD materials being unequal to one another. Other embodiments are described herein. | 2014-09-18 |
20140264669 | MAGNETIC MEMORY ELEMENT - A magnetic memory element includes a memory layer having magnetic anisotropy on the film surface thereof in the perpendicular direction and in which the magnetization direction is variable, a reference layer having magnetic anisotropy on the film surface thereof in the perpendicular direction and in which the magnetization direction is not variable, and a tunnel barrier layer which is interposed between the memory layer and the reference layer. The memory layer is made of an alloy including cobalt (Co) andiron (Fe). A plurality of oxygen atoms are present on both interfaces of the memory layer. | 2014-09-18 |
20140264670 | CELL DESIGN FOR EMBEDDED THERMALLY-ASSISTED MRAM - A thermally assisted magnetoresistive random access memory cell, a corresponding array, and a method for fabricating the array. An example cell includes a first metal layer, a second metal layer, an interlayer, a first magnetic stack, and a first non-magnetic via. The first metal layer includes a pad and a first metal line, with the pad not in direct contact with the first metal line. The second metal layer includes a second metal line and a metal strap. The second metal line is perpendicular to the first metal line and not in contact with the metal strap. The interlayer is located between the first and second metal layers. The first metal line is not in direct contact with the interlayer. The first magnetic stack is in direct contact with the interlayer and the metal strap. The first non-magnetic via is in direct contact with the pad and the metal strap. | 2014-09-18 |
20140264671 | MAGNETIC JUNCTIONS HAVING INSERTION LAYERS AND MAGNETIC MEMORIES USING THE MAGNETIC JUNCTIONS - A method and system for providing a magnetic junction usable in a magnetic device are described. The magnetic junction includes a reference layer, a nonmagnetic spacer layer and a free layer. The nonmagnetic spacer layer is between the reference layer and the free layer. The magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction. A portion of the magnetic junction includes at least one magnetic substructure. The magnetic substructure includes at least one Fe layer and at least one nonmagnetic insertion layer. The at least one Fe layer shares at least one interface with the at least one nonmagnetic insertion layer. Each of the at least one nonmagnetic insertion layer consists of at least one of W, I, Hf, Bi, Zn, Mo, Ag, Cd, Os and In. | 2014-09-18 |
20140264672 | MAGNETORESISTIVE RANDOM ACCESS MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - In a method of an MRAM device, first and second patterns are formed on a substrate alternately and repeatedly in a second direction. Each first pattern and each second pattern extend in a first direction perpendicular to the second direction. Some of the second patterns are removed to form first openings extending in the first direction. Source lines filling the first openings are formed. A mask is formed on the first and second patterns and the source lines. The mask includes second openings in the first direction, each of which extends in the second direction. Portions of the second patterns exposed by the second openings are removed to form third openings. Third patterns filling the third openings are formed. The second patterns surrounded by the first and third patterns are removed to form fourth openings. Contact plugs filling the fourth openings are formed. | 2014-09-18 |
20140264673 | MAGNETORESISTIVE ELEMENT AND MAGNETIC MEMORY - According to one embodiment, a magnetoresistive element includes a first magnetic layer having a variable magnetization direction; a second magnetic layer having an invariable magnetization direction; and a tunnel barrier layer provided between the first magnetic layer and the second magnetic layer and including an MgFeO film, wherein the MgFeO film contains at least one element selected from a group consisting of Ti, V, Mn, and Cu. | 2014-09-18 |
20140264674 | STORAGE ELEMENT AND MEMORY - A storage element includes a storage layer, a fixed magnetization layer, a spin barrier layer, and a spin absorption layer. The storage layer stores information based on a magnetization state of a magnetic material. The fixed magnetization layer is provided for the storage layer through a tunnel insulating layer. The spin barrier layer suppresses diffusion of spin-polarized electrons and is provided on the side of the storage layer opposite the fixed magnetization layer. The spin absorption layer is formed of a nonmagnetic metal layer causing spin pumping and provided on the side of the spin barrier layer opposite the storage layer. A direction of magnetization in the storage layer is changed by passing current in a layering direction to inject spin-polarized electrons so that information is recorded in the storage layer and the spin barrier layer includes at least a material selected from oxides, nitrides, and fluorides. | 2014-09-18 |
20140264675 | MEMORY CELL HAVING NONMAGNETIC FILAMENT CONTACT AND METHODS OF OPERATING AND FABRICATING THE SAME - A magnetic cell structure including a nonmagnetic filament contact, and methods of fabricating the structure are provided. The magnetic cell structure includes a free layer, a pinned layer, an insulative layer between the free and pinned layers, and a nonmagnetic filament contact in the insulative layer which electrically connects the free and pinned layers. The nonmagnetic filament contact is formed from a nonmagnetic source layer, also between the free and pinned layers. The filament contact directs a programming current through the magnetic cell structure such that the cross sectional area of the programming current in the free layer is less than the cross section of the structure. The decrease in the cross sectional area of the programming current in the free layer enables a lower programming current to reach a critical switching current density in the free layer and switch the magnetization of the free layer, programming the magnetic cell. | 2014-09-18 |
20140264676 | FORMING MAGNETIC MICROELECTROMECHANICAL INDUCTIVE COMPONENTS - A micro-electromechanical device and method of manufacture are disclosed. A sacrificial layer is formed on a silicon substrate. A metal layer is formed on a top surface of the sacrificial layer. Soft magnetic material is electrolessly deposited on the metal layer to manufacture the micro-electromechanical device. The sacrificial layer is removed to produce a metal beam separated from the silicon substrate by a space. | 2014-09-18 |
20140264677 | Chip Package with Isolated Pin, Isolated Pad or Isolated Chip Carrier and Method of Making the Same - A chip package with isolated pin, isolated pad or isolated chip carrier and a method of making the same are disclosed. In one embodiment a chip package includes a chip, a package encapsulating the chip, pads or pins disposed on a first side of the package and an isolation pad or an isolation pin disposed on a second side of the package, the isolation pin or the isolation pad electrically isolated from the chip, wherein the chip comprises a magnetic field sensor configured to measure a magnetic field generated outside of the package. | 2014-09-18 |
20140264678 | PACKAGING FOR AN ELECTRONIC DEVICE - In one aspect, a method includes processing a metal substrate, performing a first etch on a first surface of the metal substrate to form, for an integrated circuit package, secondary leads and a curved component having two primary leads and performing a second etch, on a second surface of the substrate opposite the first surface, at locations on the secondary leads and locations on the curved component to provide a locking mechanism. Each primary lead located at a respective end of the curved component. | 2014-09-18 |
20140264679 | LOGIC CHIP INCLUDING EMBEDDED MAGNETIC TUNNEL JUNCTIONS - An embodiment integrates memory, such as spin-torque transfer magnetoresistive random access memory (STT-MRAM) within a logic chip. The STT-MRAM includes a magnetic tunnel junction (MTJ) with an upper MTJ layer, lower MTJ layer, and tunnel barrier directly contacting the upper MTJ layer and the lower MTJ layer; wherein the upper MTJ layer includes an upper MTJ layer sidewall and the lower MTJ layer includes a lower MTJ sidewall horizontally offset from the upper MTJ layer. Another embodiment includes a memory area, comprising a MTJ, and a logic area located on a substrate; wherein a horizontal plane intersects the MTJ, a first Inter-Layer Dielectric (ILD) material adjacent the MTJ, and a second ILD material included in the logic area, the first and second ILD materials being unequal to one another. In an embodiment the first and second ILDs directly contact one another. Other embodiments are described herein. | 2014-09-18 |
20140264680 | Non-Volatile Memory Devices and Methods of Fabricating the Same - A nonvolatile memory device is provided. The nonvolatile memory device comprises a plurality of impurity regions formed in a substrate, a first contact electrically connected to at least one of the impurity regions, a second contact electrically connected to at least one of the impurity regions, a first information storage portion formed at a first height from the substrate and electrically connected to the first contact, and a second information storage portion formed at a second height, which is different from the first height, from the substrate and electrically connected to the second contact. | 2014-09-18 |
20140264681 | POLARIZATION INSENSITIVE PHOTOCONDUCTIVE SWITCH - A photoconductive switch semiconductor device including a semiconductor substrate including a region functioning as a photoconductive switch; and a metallization layer disposed on the surface of the semiconductor substrate including a first component including a first terminal, and an inwardly spiraling first middle portion, and a first end portion, and a second component including a second terminal, and an inwardly spiraling second middle portion, and a second end portion, wherein the first component and the second component are electrically isolated. | 2014-09-18 |
20140264682 | Interconnect Sructure for Stacked Device and Method - A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element and a second semiconductor element bonded on the first semiconductor element. The first semiconductor element includes a first substrate, a common conductive feature in the first substrate, a first inter-level dielectric (ILD) layer, a first interconnection feature and a conductive plug connecting the first interconnection feature to the common conductive feature. The second semiconductor element includes a second substrate, a second ILD layers over the second substrate and a second interconnection feature in second ILD layers. The device also includes a conductive deep plug connecting to the common conductive feature in the first semiconductor element and the second interconnection feature. The conductive deep plug is separated with the conductive plug by the first ILD layer. | 2014-09-18 |
20140264683 | Imaging Sensor Structure and Method - The present disclosure provides an embodiment of a method for fabricating a three dimensional (3D) image sensor structure. The method includes providing to an image sensor substrate having image sensors formed therein and a first interconnect structure formed thereon, and a logic substrate having a logic circuit formed therein and a first interconnect structure formed thereon; bonding the logic substrate to the image sensor substrate in a configuration that the first and second interconnect structures are sandwiched between the logic substrate and the image sensor substrate; and forming a conductive feature extending from the logic substrate to the first interconnect structure, thereby electrically coupling the logic circuit to the image sensors. | 2014-09-18 |
20140264684 | PHOTOCONDUCTIVE SEMICONDUCTOR SWITCH - A photoconductive semiconductor switch comprising a photoconductive GaAs substrate having a pair of spaced metal contacts on a surface thereof, the spaced metal contacts opposite ends of a switching gap, the switching gap having a plurality of lateral current flow preventing channels therein, the channels being formed by ion implantation of the GaAs substrate in the channels. | 2014-09-18 |
20140264685 | IMAGE SENSOR WITH STACKED GRID STRUCTURE - Among other things, one or more image sensors and techniques for guiding light towards a photodiode are provided. An image sensor comprises a metal grid configured to direct light towards a corresponding photodiode and away from other photodiodes. The image sensor also comprises a dielectric grid and a filler grid over the metal grid to direct light towards the corresponding photodiode and away from other photodiodes, where the filler grid has a different refractive index than the dielectric grid. In this way, crosstalk, otherwise resulting from detection of light by incorrect photodiodes, is mitigated. | 2014-09-18 |
20140264686 | SOLID-STATE IMAGING DEVICES - A solid-state imaging device is provided. The solid-state imaging device includes a semiconductor substrate containing a plurality of image sensors. A color filter including a plurality of color filter segments is disposed above the semiconductor substrate. Each of the color filter segments corresponds to one of the image sensors. Further, a plurality of partitions is disposed between the color filter segments. Each of the partitions is disposed between any two adjacent color filter segments. The partition has a height smaller than the height of the color filter segment, wherein the height of the partition is based on the bottom of the color filter segment to the top of the partition, and the height of the color filter segment is based on the bottom of the color filter segment to the top of the color filter segment. | 2014-09-18 |
20140264687 | IMAGE SENSOR WITH TRENCHED FILLER GRID - Among other things, one or more image sensors and techniques for forming such image sensors are provided. An image sensor comprises a photodiode array configured to detect light. A filler grid is formed over the photodiode array, such as over a dielectric grid. The filler grid comprises one or more filler structures, such as a first filler structure that provides a light propagation path to a first photodiode that is primarily through the first filler structure. In this way, signal strength decay of light along the light propagation path before detection by the first photodiode is mitigated. The image sensor comprises a reflective layer that channels light towards corresponding photodiodes. For example, a first reflective layer portion guides light towards the first photodiode and away from a second photodiode. In this way, crosstalk, otherwise resulting from detection of light by incorrect photodiodes, is mitigated. | 2014-09-18 |
20140264688 | SOLID STATE IMAGING DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a solid state imaging device includes a silicon substrate unit, a color filter layer, first, second and third optical layers. The silicon substrate unit includes imaging units provided in a plane parallel to a major surface. The color filter layer is apart from the silicon substrate unit. The color filter has a lower refractive index than the silicon substrate unit. The first optical layer has a lower first refractive index than the color filter layer and the silicon substrate unit, and is light transmissive. The second optical layer has a second refractive index higher than the first refractive index and lower than the refractive index of the silicon substrate unit, is light transmissive. The third optical layer has a third refractive index lower than the refractive index of the color filter layer and lower than the second refractive index, and is light transmissive. | 2014-09-18 |
20140264689 | OPTICAL SENSORS FOR DETECTING RELATIVE MOTION AND/OR POSITION AND METHODS AND SYSTEMS FOR USING SUCH OPTICAL SENSORS - An optical sensor, according to an embodiment of the present invention, includes a photodetector region and a plurality of slats over the photodetector region. In an embodiment, the slats are made up of a plurality of metal layers connected in a stacked configuration with a plurality of metal columns. The metal columns can be made of metal vias, metal contacts and/or metal plugs. In an embodiment, the slats are angled relative to a surface of the photodetector region, wherein the angling of the slats is achieved by the metal layers being laterally offset relative to one another and/or metal columns being laterally offset relative to one another. In an alternative embodiment, the slats are made of an opaque polymer material, such as an opaque photoresist. | 2014-09-18 |
20140264690 | SOLID STATE IMAGING DEVICE AND METHOD FOR MANUFACTURING SOLID STATE IMAGING DEVICE - Certain embodiments provide a solid state imaging device including a plurality of pixels. Each of the pixels has a semiconductor layer which has a charge accumulating layer at a front surface thereof and a filter layer provided above a rear surface of the semiconductor layer. Transmissive wavelength bands of the filter layers included in the pixels are different from each other, and thicknesses which a plurality of the semiconductor layers included in the pixels and including a plurality of the charge accumulating layers have are different from each other. | 2014-09-18 |
20140264691 | Low Profile Image Sensor - A sensor package comprising a host substrate with opposing first and second surfaces, an aperture extending therethrough, circuit layers, and first contact pads. A second substrate at least partially in the aperture has opposing first and second surfaces, a plurality of photo detectors, second contact pads at the second substrate first surface and electrically coupled to the photo detectors, and trenches formed into the second substrate first surface, conductive traces extending from the second contact pads and into the trenches. A third substrate has a first surface mounted to the first surface of the second substrate. The third substrate includes a cavity formed into its first surface and positioned over the photo detectors. Electrical connectors connect the first contact pads and conductive traces. A lens module is mounted to the host substrate for focusing light through the third substrate and onto the photo detectors. | 2014-09-18 |
20140264692 | Low Profile Sensor Module And Method Of Making Same - A host substrate assembly includes a first substrate with opposing first and second surfaces, an aperture extending therethrough, circuit layers, and first contact pads electrically coupled to the circuit layers. A sensor chip includes a second substrate with opposing first and second surfaces, a plurality of photo detectors formed on or in the second substrate and configured to receive light incident on the second substrate first surface, and a plurality of second contact pads formed at the second substrate first or second surfaces and are electrically coupled to the photo detectors. A spacer is mounted to the second substrate first surface. A protective substrate is mounted to the spacer and disposed over the photo detectors. Electrically conductive conduits each extend through the spacer and are in electrical contact with one of the second contact pads. Electrical connectors electrically connect the first contact pads and the conduits. | 2014-09-18 |
20140264693 | Cover-Free Sensor Module And Method Of Making Same - A sensor package includes host substrate assembly includes a first substrate, circuit layers in the first substrate, and first contact pads electrically coupled to the circuit layers. A sensor chip includes a second substrate with opposing first and second surfaces, sensor(s) formed on or under the first surface of the second substrate, a plurality of second contact pads formed at the first surface of the second substrate and which are electrically coupled to the sensor(s), a plurality of holes each formed into the second surface of the second substrate and extends through the second substrate to one of the second contact pads, and conductive leads each extending from one of the second contact pads, through one of the plurality of holes, and along the second surface of the second substrate. A plurality of electrical connectors each electrically connect one of the first contact pads and one of the conductive leads. | 2014-09-18 |
20140264694 | SOLID STATE IMAGING DEVICE AND MANUFACTURING METHOD, AND ELECTRONIC APPARATUS - A solid state imaging device includes a substrate, in which the substrate includes a photoelectric conversion unit that generates a charge according to a light amount of incident light by a pixel unit, an accumulation unit that divides the charge of the pixel unit which is generated in the photoelectric conversion unit and accumulates the charge, a first element isolation unit that is formed at a boundary of the photoelectric conversion unit of the pixel unit, and a second element isolation unit that is formed at a boundary of the accumulation unit of a divided unit of the pixel. | 2014-09-18 |
20140264695 | Image Sensor and Method of Manufacturing the Same - An image sensor includes a semiconductor layer having a first surface and a second surface opposite to each other and including a photodiode and a hydrogen containing region adjacent the first surface. A crystalline anti-reflective layer is on the first surface of the semiconductor layer, and is configured to allow hydrogen atoms to penetrate into the first surface of the semiconductor layer. Driving transistors and wires are on the second surface of the semiconductor layer, and a color filter and a micro lens are on the anti-reflective layer. The hydrogen containing region contains hydrogen atoms that combine with defects at the first surface. | 2014-09-18 |
20140264696 | DIELECTRIC FILM FOR IMAGE SENSOR - Among other things, one or more image sensors and techniques for forming such image sensors are provided. An image sensor comprises a photodiode array configured to detect light. The image sensor comprises a calibration region configured to detect a color level for image reproduction, such as a black calibration region configured to detect a black level for an image detected by the photodiode array. The image sensor comprises a dielectric film that is formed over the photodiode array and the calibration region. The dielectric film is configured to balance stress between the photodiode and the calibration region in order to improve accuracy of the calibration region. | 2014-09-18 |
20140264697 | IMAGE PICKUP MODULE AND IMAGE PICKUP UNIT - An image pickup module includes: a wiring board including a first main surface on which chip electrodes are disposed and a second main surface on which the cable electrodes connected respectively to the chip electrodes via respective through wirings are disposed; an image pickup device chip including external electrodes bonded respectively to the chip electrodes; and a cable including conductive wires bonded respectively to the cable electrodes, in which all of the cable electrodes are disposed in a region not facing a region where the chip electrodes are disposed. | 2014-09-18 |
20140264698 | Image Sensor Device and Method - A system and method for blocking heat from reaching an image sensor in a three dimensional stack with a semiconductor device. In an embodiment a heat sink is formed in a back end of line process either on the semiconductor device or else on the image sensor itself when the image sensor is in a backside illuminated configuration. The heat sink may be a grid in either a single layer or in two layers, a zig-zag pattern, or in an interleaved fingers configuration. | 2014-09-18 |
20140264699 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package includes a substrate, an image sensor chip mounted on the substrate, a holder disposed on the substrate and surrounding the image sensor chip, and the holder has an inner surface facing the image sensor chip and an outer surface opposite to the inner surface. The semiconductor package further includes a transparent cover combined with the holder, and the transparent cover is spaced apart from and faces the substrate. The holder includes: a hole penetrating the holder from the inner surface to the outer surface. In addition, the semiconductor package further includes a first stopper disposed in the hole and a second stopper disposed at a position corresponding to the hole on the outer surface of the holder. | 2014-09-18 |
20140264700 | MONOLITHIC SUN SENSORS, ASSEMBLIES THEREOF, AND METHODS OF MAKING AND USING SAME - Under one aspect of the present invention, a monolithic sun sensor includes a photosensor; a spacer material disposed over the photosensor; and a patterned mask disposed over the spacer material and defining an aperture over the photosensor. The spacer material has a thickness selected such that the patterned mask casts a shadow onto the photosensor that varies as a function of the monolithic sun sensor's angle relative to the sun. The sun sensor may further include a substrate in which the photosensor is embedded or on which the photosensor is disposed. The spacer material may be transparent, and may include a layer of inorganic oxide, or a plurality of layers of inorganic oxide. The patterned mask may include a conductive material, such as a metal. The aperture may be lithographically defined, and may be square. The sun sensor may further include a transparent overlayer disposed over the patterned mask. | 2014-09-18 |
20140264701 | Image Sensor Device and Method - A system and method for blocking light from regions around a photodiode in a pixel of an image sensor is provided. In an embodiment a first optical block layer is formed on a first glue layer and a second glue layer is formed on the first optical block layer. The formation of the first optical block layer and the second glue layer is repeated one or more times to form multiple optical block layers and multiple glue layers. As such, if voids open up in the optical block layers during further processing, there is another optical block layer to block any light that may have penetrated through the void. | 2014-09-18 |
20140264702 | OPTICAL SENSOR - An integrated circuit device includes an active semiconductor substrate comprising an array of photodiodes. The integrated circuit device also includes a dielectric layer disposed adjacent to the active semiconductor substrate proximate to the array of photodiodes. The dielectric layer has a first side adjacent to the active semiconductor substrate and a second side opposite from the active semiconductor substrate. The dielectric layer includes a layer of at least substantially opaque material. The layer of at least substantially opaque material defines an aperture configured to permit electromagnetic radiation incident upon the second side of the dielectric layer to reach the array of photodiodes. | 2014-09-18 |
20140264703 | SOLID-STATE IMAGE SENSING DEVICE AND SEMICONDUCTOR DISPLAY DEVICE - To provide a solid-state image sensing device or a semiconductor display device, which can easily obtain the positional data of an object without contact. Included are a plurality of first photosensors on which light with a first incident angle is incident from a first incident direction and a plurality of second photosensors on which light with a second incident angle is incident from a second incident direction. The first incident angle of light incident on one of the plurality of first photosensors is larger than that of light incident on one of the other first photosensors. The second incident angle of light incident on one of the plurality of second photosensors is larger than that of light incident on one of the other second photosensors. | 2014-09-18 |
20140264704 | LOW CROSS-TALK FOR SMALL PIXEL BARRIER DETECTORS - Methods and structures of barrier detectors are described. The structure may include an absorber that is at least partially reticulated. The at least partially reticulated absorber may also include an integrated electricity conductivity structure. The structure may include at least two contact regions isolated from one another. The structure may further include a barrier layer disposed between the absorber and at least two contact regions. | 2014-09-18 |
20140264705 | IMAGING DEVICE - An imaging device includes: a plurality of first absorption layers that absorb an infrared ray with a given wavelength range, and generate pixel signals of a plurality of pixels, respectively; at least one second absorption layer that absorbs an infrared ray with a wavelength range which is different from the given wavelength range of the first absorption layers, and generates a pixel signal common to the pixels; a plurality of first electrodes that take out the pixel signals from the first absorption layers, respectively; and a second electrode that takes out the pixel signal from the at least one second absorption layer. | 2014-09-18 |
20140264706 | SOLID STATE IMAGING DEVICE, METHOD OF MANUFACTURING THE SAME, AND IMAGING APPARATUS - A solid state imaging device including: a plurality of sensor sections formed in a semiconductor substrate in order to convert incident light into an electric signal; a peripheral circuit section formed in the semiconductor substrate so as to be positioned beside the sensor sections; and a layer having negative fixed electric charges that is formed on a light incidence side of the sensor sections in order to form a hole accumulation layer on light receiving surfaces of the sensor sections. | 2014-09-18 |
20140264707 | NOVEL CONDITION BEFORE TMAH IMPROVED DEVICE PERFORMANCE - The present disclosure relates to a back-side illuminated CMOS image sensor (BSI CIS). In some embodiments, the BSI CSI has a semiconductor substrate with a front-side and a back-side. A plurality of photodetectors are located within the front-side of the semiconductor substrate. An implantation region is located within the semiconductor substrate at a position separated from the plurality of photodetectors. The implantation region is disposed below the plurality of photodetectors and has a non-uniform doping concentration along a lateral plane parallel to the back-side of the semiconductor substrate. The non-uniform doping concentration allows for the BSI CSI to achieve a small total thickness variation (TTV) between one or more photodetectors and a back-side of a thinned semiconductor substrate that provides for good device performance. | 2014-09-18 |
20140264708 | Optical Absorbers - Optical absorbers, solar cells comprising the absorbers, and methods for making the absorbers are disclosed. The optical absorber comprises a semiconductor layer having a bandgap of between about 1.0 eV and about 1.6 eV disposed on a substrate, wherein the semiconductor comprises two or more earth abundant elements. The bandgap of the optical absorber is graded through the thickness of the layer by partial substitution of at least one grading element from the same group in the periodic table as the at least one of the two or more earth abundant elements. | 2014-09-18 |
20140264709 | Interconnect Structure for Connecting Dies and Methods of Forming the Same - A structure includes a first chip having a first substrate, and first dielectric layers underlying the first substrate, with a first metal pad in the first dielectric layers. A second chip includes a second substrate, second dielectric layers over the second substrate and bonded to the first dielectric layers, and a second metal pad in the second dielectric layers. A conductive plug includes a first portion extending from a top surface of the first substrate to a top surface of the first metal pad, and a second portion extending from the top surface of the first metal pad to a top surface of the second metal pad. An edge of the second portion is in physical contact with a sidewall of the first metal pad. A dielectric layer spaces the first portion of the conductive plug from the first plurality of dielectric layers. | 2014-09-18 |
20140264710 | SEAL RING STRUCTURE WITH ROUNDED CORNERS FOR SEMICONDUCTOR DEVICES - Seal ring structures are provided with rounded corner junctions or corner junctions that include polygons. The seal rings surround generally rectangular semiconductor devices such as integrated circuits, image sensors and other devices. The seal ring includes a configuration of two sets of generally parallel opposed sides and the corner junctions are the junctions at which adjacent orthogonal seal ring sides are joined. The seal rings are trench structures or filled trench structures in various embodiments. The rounded corner junctions are formed by a curved arc or multiple line segments joined together at various angles. The corner junctions that include one or more enclosed polygons include polygons with at least one polygon side being formed by one of the seal ring sides. | 2014-09-18 |
20140264711 | LIGHT SENSOR WITH VERTICAL DIODE JUNCTIONS - Light sensors are described that include a trench structure integrated therein. In an implementation, the light sensor includes a substrate having a dopant material of a first conductivity type and multiple trenches disposed therein. The light sensor also includes a diffusion region formed proximate to the multiple trenches. The diffusion region includes a dopant material of a second conductivity type. A depletion region is created at the interface of the dopant material of the first conductivity type and the dopant material of the second conductivity type. The depletion region is configured to attract charge carriers to the depletion region, at least substantially a majority of the charge carriers generated due to light incident upon the substrate. | 2014-09-18 |
20140264712 | INFRARED DETECTOR MADE UP OF SUSPENDED BOLOMETRIC MICRO-PLATES - An array bolometric detector for detecting an electromagnetic radiation in a predetermined infrared or terahertz wavelength range, including a substrate, and an array of bolometric microplates for the detection of the radiation, suspended above the substrate by support elements. The detector includes a membrane arranged above each microplate, and having patterns having a refractive index smaller than that of the membrane formed therein. The patterns are placed periodically along at least one axis of the membrane, according to a period shorter than or equal to | 2014-09-18 |
20140264713 | GATE CONTACT FOR A SEMICONDUCTOR DEVICE AND METHODS OF FABRICATION THEREOF - Embodiments of a gate contact for a semiconductor device and methods of fabrication thereof are disclosed. In one embodiment, a semiconductor device includes a semiconductor structure and a dielectric layer on a surface of the semiconductor structure, where the dielectric layer has an opening that exposes an area of the semiconductor structure. A gate contact for the semiconductor device is formed on the exposed area of the semiconductor structure through the opening in the dielectric layer. The gate contact includes a proximal end on a portion of the exposed area of the semiconductor structure, a distal end opposite the proximal end, and sidewalls that each extend between the proximal end and the distal end of the gate contact. For each sidewall of the gate contact, an air region separates the sidewall and the distal end of the gate contact from the dielectric layer. | 2014-09-18 |
20140264714 | POWER SEMICONDUCTOR DEVICES INCORPORATING SINGLE CRYSTALLINE ALUMINUM NITRIDE SUBSTRATE - The invention provides a power semiconductor device including an aluminum nitride single crystalline substrate, wherein the dislocation density of the substrate is less than about 10 | 2014-09-18 |
20140264715 | METHODS AND APPARATUS FOR CONGESTION-AWARE BUFFERING USING VOLTAGE ISOLATION PATHWAYS FOR INTEGRATED CIRCUIT DESIGNS WITH MULTI-POWER DOMAINS - A semiconductor apparatus is provided herein for buffering of nets routed through one or more areas associated with a first power domain that is different from a second power domain associated with the buffers and the buffered nets by limiting placement of these buffers in patterned areas associated with the second power domain. This provides for the routing of the buffered nets to be determined not only based on the shortest distance to travel from Point A to Point B, but also takes into account routing congestion on the semiconductor apparatus. Consequently, if an area on the semiconductor apparatus is congested, the buffered nets may be routed around the congestion. As such, although a path taken by a particular signal through the integrated circuit is not a direct route, it may still be of a distance to support a speed at which the particular signal needs to be transferred. | 2014-09-18 |
20140264716 | SEMICONDUCTOR WAFER, SEMICONDUCTOR PROCESS AND SEMICONDUCTOR PACKAGE - The present invention provides a semiconductor wafer, semiconductor package and semiconductor process. The semiconductor wafer includes a substrate, at least one metal segment and a plurality of dielectric layers. The semiconductor wafer is defined as a plurality of die areas and a plurality of trench areas, each of the die areas has an integrated circuit including a plurality of patterned metal layers disposed between the dielectric layers. The trench areas are disposed between the die areas, and the at least one metal segment is disposed in the trench area and insulated from the integrated circuit of the die area. | 2014-09-18 |
20140264717 | Method of Fabricating a FinFET Device - A method of forming a fin structure of a semiconductor device includes providing a substrate, creating a mandrel pattern over the substrate, depositing a first spacer layer over the mandrel pattern, and removing portions of the first spacer layer to form first spacer fins. The method also includes performing a first fin cut process to remove a subset of the first spacer fins, depositing a second spacer layer over the un-removed first spacer fins, and removing portions of the second spacer layer to form second spacer fins. The method further includes forming fin structures, and performing a second fin cut process to remove a subset of the fin structures. | 2014-09-18 |
20140264718 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A nonvolatile semiconductor memory device comprises a memory string, and a wiring. The memory string comprises a semiconductor layer, a charge storage layer, and a plurality of first conductive layers. The plurality of first conductive layers comprises a stepped portion formed in a stepped shape such that positions of ends of the plurality of first conductive layers differ from one another. The wiring comprises a plurality of second conductive layers extending upwardly from an upper surface of the first conductive layers comprising the stepped portion. The plurality of second conductive layers are formed such that upper ends thereof are aligned with a surface parallel to the substrate, and such that a diameter thereof decreases from the upper end thereof to a lower end thereof. The plurality of second conductive layers are formed such that the greater a length thereof in the perpendicular direction, the larger a diameter of the upper end thereof. | 2014-09-18 |
20140264719 | Varied STI Liners for Isolation Structures in Image Sensing Devices - An integrated circuit device incorporating a plurality of isolation trench structures configured for disparate applications and a method of forming the integrated circuit are disclosed. In an exemplary embodiment, a substrate having a first region and a second region is received. A first isolation trench is formed in the first region, and a second isolation trench is formed in the second region. A first liner layer is formed in the first isolation trench, and a second liner layer is formed in the second isolation trench. The second liner layer has a physical characteristic that is different from a corresponding physical characteristic of the first liner layer. An implantation procedure is performed on the second isolation trench and the second liner layer formed therein. The physical characteristic of the second liner layer may be selected to enhance an implantation depth or an implantation uniformity compared to the first liner layer. | 2014-09-18 |
20140264720 | Method and Structure for Nitrogen-Doped Shallow-Trench Isolation Dielectric - An isolation feature with a nitrogen-doped fill dielectric and a method of forming the isolation feature are disclosed. In an exemplary embodiment, the method of forming the isolation feature comprises receiving a substrate having a top surface. A recess is etched in the substrate, the recess extending from the top surface into the substrate. A dielectric is deposited within the recess such that the depositing of the dielectric includes introducing nitrogen during a chemical vapor deposition process. Accordingly, the deposited dielectric includes a nitrogen-doped dielectric. The deposited dielectric may include a nitrogen-doped silicon oxide. In some embodiments, the depositing of the dielectric disposes the nitrogen-doped dielectric in contact with a surface of the recess. In further embodiments, a liner material is deposited within the recess prior to the depositing of the dielectric within the recess. | 2014-09-18 |
20140264721 | ISOLATION STRUCTURE IN A SEMICONDUCTOR DEVICE PROCESSES AND STRUCTURES - Substantially planar or even layers in semiconductor trenches allow for even distribution of subsequent layers in semiconductor processing and reduce divots in semiconductor device layers. A semiconductor device may include an isolation structure formed in a trench. The isolation structure may have a cover oxide layer and a base oxide layer holding the cover oxide layer. The top surface of the isolation structure is substantially planar. An oxidation process may substantially eliminate nitrogen from a top portion of the isolation structure, resulting in a balanced etch rate in the top portion and a substantially even isolation structure top surface. | 2014-09-18 |
20140264722 | SEMICONDUCTOR DEVICE - A semiconductor chip includes a first circuit and a second circuit having different reference potentials. A first potential which is a reference potential of the first circuit is applied to the semiconductor chip through any of plural lead terminals, and a second potential which is a reference potential of the second circuit is applied to the semiconductor chip through any of plural lead terminals. A substrate of the semiconductor chip has a structure in which a buried insulating layer and a semiconductor layer of a first conductivity type are laminated on a semiconductor substrate such as a SOI substrate. A fixed potential is applied to the semiconductor substrate through a die pad and a lead terminal for a substrate potential. The fixed potential is applied to the semiconductor chip through a different route from the reference potential of the first circuit and the reference potential of the second circuit. | 2014-09-18 |
20140264723 | DEVICES INCLUDING A DIAMOND LAYER - A device includes a substrate layer, a diamond layer, and a device layer. The device layer is patterned. The diamond layer is to conform to a pattern associated with the device layer. | 2014-09-18 |
20140264724 | DEEP TRENCH ISOLATION - An integrated semiconductor device includes a substrate of a first conductivity type, a buried layer located over the substrate, an isolated region located over a first portion of the buried layer, and an isolation trench located around the isolated region. A punch-through structure is located around at least a portion of the isolation trench. The punch-through structure includes a second portion of the buried layer, a first region located over the second portion of the buried layer, the first region having a second conductivity type, and a second region located over the first region, the second region having the first conductivity type. | 2014-09-18 |
20140264725 | SILICON RECESS ETCH AND EPITAXIAL DEPOSIT FOR SHALLOW TRENCH ISOLATION (STI) - The embodiments described provide methods and semiconductor device areas for etching an active area region on a semiconductor body and epitaxially depositing a semiconductor layer overlying the active region. The methods enable the mitigation or elimination of problems encountered in subsequent manufacturing associated with STI divots. | 2014-09-18 |
20140264726 | STRUCTURE AND METHOD FOR PROTECTED PERIPHERY SEMICONDUCTOR DEVICE - A semiconductor device is provided having reduced corner thinning in a shallow trench isolation (STI) structure of the periphery region. The semiconductor device may be substantially free of any corner thinning at a corner of a STI structure of the periphery region. Methods of manufacturing such a semiconductor device are also provided. | 2014-09-18 |
20140264727 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - A semiconductor device includes a substrate with an active pattern, the active pattern having a first extension portion extending in a first direction substantially parallel to a top surface of the substrate, a second extension portion extending from a first end of the first extension portion in a third direction oriented obliquely to the first direction, a third extension portion extending from a second end of the first extension portion in a direction opposed to the third direction, a first projection portion protruding from the second extension portion in a direction opposed to the first direction, the first projection portion being spaced apart from the first extension portion, and a second projection portion protruding from the third extension portion in the first direction, the second projection portion being spaced apart from the first extension portion. | 2014-09-18 |
20140264728 | Active Tiling Placement for Improved Latch-up Immunity - A semiconductor device includes CMP dummy tiles ( | 2014-09-18 |
20140264729 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes a substrate, a conductive pattern, a side spacer, and an air gap. The substrate includes an interlayer insulating layer and a trench penetrating the interlayer insulating layer. The conductive pattern is disposed within the trench of the substrate. The side spacer is disposed within the trench. The side spacer covers an upper side surface of the conductive pattern. The air gap is disposed within the trench. The air gap is bounded by a sidewall of the trench, the side spacer, and a lower side surface of the conductive pattern. A level of a bottom surface of the conductive pattern is lower than a level of bottom surfaces of the side spacer. | 2014-09-18 |
20140264730 | MICROELECTRONIC ELEMENTS WITH MASTER/SLAVE CONFIGURABILITY - A semiconductor chip that may be configured to function as either a master chip or a slave chip. The semiconductor chip may be included in a microelectronic assembly including a plurality of vertically stacked semiconductor chips, with each of the chips containing functional circuit blocks that enable each semiconductor chip to function as either a master chip or a slave chip under in accordance with a state input stored on the same chip, or received from another chip in the stacked assembly or from another component of a system in which the stacked assembly is configured to operate. | 2014-09-18 |
20140264731 | PROGRAMMABLE E-FUSE FOR AN INTEGRATED CIRCUIT PRODUCT - One illustrative e-fuse device disclosed herein includes first and second conductive structures, a first electrically conductive heat cage element that is conductively coupled to the first conductive structure, wherein the first heat cage element is adapted to carry an electrical current, a second electrically conductive heat cage element that is conductively coupled to the second conductive structure, wherein the second heat cage element is adapted to carry the electrical current, and a programmable, electrically conductive e-fuse element that is conductively coupled to each of the first and second electrically conductive heat cage elements and adapted to carry the electrical current, wherein the e-fuse element is positioned adjacent to each of the first and second electrically conductive heat cage elements. | 2014-09-18 |
20140264732 | MAGNETIC CORE INDUCTOR (MCI) STRUCTURES FOR INTEGRATED VOLTAGE REGULATORS - Semiconductor packages including magnetic core inductor (MCI) structures for integrated voltage regulators are described. In an example, a semiconductor package includes a package substrate and a semiconductor die coupled to a first surface of the package substrate. The semiconductor die has a first plurality of metal-insulator-metal (MIM) capacitor layers thereon. The semiconductor package also includes a magnetic core inductor (MCI) die coupled to a second surface of the package substrate. The MCI die includes one or more slotted inductors and has a second plurality of MIM capacitor layers thereon. | 2014-09-18 |
20140264733 | DEVICE WITH INTEGRATED PASSIVE COMPONENT - Semiconductor devices and methods for forming a semiconductor device are presented. The semiconductor device includes a die which includes a die substrate having first and second major surfaces. The semiconductor device includes a passive component disposed below the second major surface of the die substrate. The passive component is electrically coupled to the die through through silicon via (TSV) contacts. | 2014-09-18 |
20140264734 | Inductor With Magnetic Material - In accordance with an embodiment, a semiconductor device comprises a semiconductor die, an interposer, and conductive bumps bonding the semiconductor die to the interposer. The semiconductor die comprises a first metallization layer, and the first metallization layer comprises a first conductive pattern. The interposer comprises a second metallization layer, and the second metallization layer comprises a second conductive pattern. Some of the conductive bumps electrically couple the first conductive pattern to the second conductive pattern to form a coil. A magnetic layer is positioned within the coil. In another embodiment, a coil is formed on a single substrate, wherein a magnetic layer is positioned within the coil. Other embodiments contemplate other configurations of coils, inductors, and/or transformers, and contemplate methods of manufacture. | 2014-09-18 |
20140264735 | Inductor System and Method - A system and method for providing and manufacturing an inductor is provided. In an embodiment similar masks are reutilized to form differently sized inductors. For example, a two turn inductor and a three turn inductor may share masks for interconnects and coils, while only masks necessary for connections between the interconnects and coils may need to be newly developed. | 2014-09-18 |
20140264736 | Semiconductor Device and Method of Forming an Inductor on Polymer Matrix Composite Substrate - A semiconductor device has a first insulating layer formed over a first surface of a polymer matrix composite substrate. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first insulating layer and first conductive layer. A second conductive layer is formed over the second insulating layer and first conductive layer. The second conductive layer is wound to exhibit inductive properties. A third conductive layer is formed between the first conductive layer and second conductive layer. A third insulating layer is formed over the second insulating layer and second conductive layer. A bump is formed over the second conductive layer. A fourth insulating layer can be formed over a second surface of the polymer matrix composite substrate. Alternatively, the fourth insulating layer can be formed over the first insulating layer prior to forming the first conductive layer. | 2014-09-18 |
20140264737 | COMPONENT-EMBEDDED SUBSTRATE - A component-embedded substrate having a multilayer substrate formed by laminating a plurality of thermoplastic sheets in a predetermined direction, an internal component provided in the multilayer substrate, and a surface-mount component mounted on a surface of the multilayer substrate using bumps. The surface-mount component, when viewed in a plan view in the predetermined direction, is positioned so as to cross an outline of the internal component, with the bumps on the surface-mount component located 50 μm or more from the outline of the internal component. | 2014-09-18 |
20140264738 | FOLDED CONICAL INDUCTOR - A semiconductor inductor structure may include a first spiral structure, located on a first metal layer, having a first outer-spiral electrically conductive track and a first inner-spiral electrically conductive track separated from the first outer-spiral electrically conductive track by a first dielectric material. A second spiral structure, located on a second metal layer, having a second outer-spiral electrically conductive track and a second inner-spiral electrically conductive track separated from the second outer-spiral electrically conductive track by a second dielectric material may also be provided. The first outer-spiral electrically conductive track may be electrically coupled to the second outer-spiral electrically conductive track and the first inner-spiral electrically conductive track may be electrically coupled to the second inner-spiral electrically conductive track. The first outer-spiral conductive track is laterally offset relative to the second outer-spiral conductive track and the first inner-spiral conductive track is laterally offset relative to the second inner-spiral conductive track. | 2014-09-18 |
20140264739 | METHODS OF FORMING UNDER DEVICE INTERCONNECT STRUCTURES - Methods of forming microelectronic interconnect under device structures are described. Those methods and structures may include forming a device layer in a first substrate, forming at least one routing layer in a second substrate, and then coupling the first substrate with the second substrate, wherein the first substrate is bonded to the second substrate. | 2014-09-18 |
20140264740 | Semiconductor Device - A semiconductor device comprising:
| 2014-09-18 |
20140264741 | CAPACITOR USING BARRIER LAYER METALLURGY - A metal-insulator-metal (MIM) capacitor using barrier layer metallurgy and methods of manufacture are disclosed. The method includes forming a bottom plate of a metal-insulator-metal (MIM) capacitor and a bonding pad using a single masking process. The method further includes forming a MIM dielectric on the bottom plate. The method further includes forming a top plate of the MIM capacitor on the MIM dielectric. The method further includes forming a solder connection on the bonding pad. | 2014-09-18 |
20140264742 | Integrated Capacitor - A structure includes first, second, and third conductive leaf structures. The first conductive leaf structure includes a first conductive midrib and conductive veins. The second conductive leaf structure is electrically connected to the first conductive leaf structure, and includes a second conductive midrib, conductive veins extending toward the first conductive midrib, and conductive veins extending away from the first conductive midrib. The third conductive leaf structure includes a third conductive midrib between the first conductive midrib and the second conductive midrib, conductive veins extending toward the first conductive midrib, and conductive veins extending toward the second conductive midrib. | 2014-09-18 |
20140264743 | NOVEL STRUCTURE OF METAL GATE MIM - First and second multi-layer structures are formed within respective openings in at least one dielectric layer formed over a semiconductor substrate. The first multi-layer structure comprises a gate electrode, and the second multi-layer structure comprises a resistor and a first electrode of a metal-insulator-metal (MIM) capacitor structure. The MIM capacitor structure is completed by forming a dielectric film on the at least one dielectric layer and forming a second electrode on the dielectric film. | 2014-09-18 |
20140264744 | STACKED SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A stacked semiconductor device includes a first substrate. A multilayer interconnect is disposed over the first substrate. Metal sections are disposed over the multilayer interconnect. First bonding features are over the metal sections. A second substrate has a front surface. A cavity extends from the front surface into a depth D in the second substrate. The cavity has an interior surface. A stop layer is disposed over the interior surface of the cavity. A movable structure is disposed over the front surface of the second substrate and suspending over the cavity. The movable structure includes a dielectric membrane, metal units over the dielectric membrane and a cap dielectric layer over the metal units. Second bonding features are over the cap dielectric layer and bonded to the first bonding features. The second bonding features extend through the cap dielectric layer and electrically coupled to the metal units. | 2014-09-18 |
20140264745 | Transmission Line Formed Adjacent Seal Ring - An integrated circuit device includes a semiconductor body, active components formed over the semiconductor body, one or more seal rings surrounding the active components, and a signal line. One or more of the seal rings are configured to provide the primary return path for current flowing through the signal line. | 2014-09-18 |
20140264746 | SELF ALIGNED CAPACITOR FABRICATION - A capacitor and method for fabricating the same. In one configuration, the capacitor has a silicon substrate, a first and a second silicon dioxide layer over the silicon substrate, and silicon nitride fins between the silicon dioxide layers. The capacitor further includes a dielectric layer over the silicon nitride fins and metal vias in the dielectric layer. | 2014-09-18 |
20140264747 | Deposition of Anisotropic Dielectric Layers Orientationally Matched to the Physically Separated Substrate - A dielectric layer can achieve a crystallography orientation similar to a base dielectric layer with a conductive layer disposed between the two dielectric layers. By providing a conductive layer having similar crystal structure and lattice parameters with the base dielectric layer, the crystallography orientation can be carried from the base dielectric layer, across the conductive layer to affect the dielectric layer. The process can be used to form capacitor structure for anisotropic dielectric materials, along the direction of high dielectric constant. | 2014-09-18 |
20140264748 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A step of forming a stacked film serving as a lower electrode, a step of forming an insulating film serving as a capacitive film on the stacked film, and a step of patterning the insulating film and the stacked film are performed. In the step of forming the stacked film, a film containing titanium, a film containing titanium and nitrogen, a main conductive film containing aluminum, a film containing titanium, and a film containing titanium and nitrogen are sequentially formed from below. The ratio of the surface roughness of the upper surface of the stacked film to the thickness of the insulating film is 14% or less. | 2014-09-18 |
20140264749 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first insulating layer, a contact plug formed in the first insulating layer, a first etch stop layer over the first insulating layer, a second etch stop layer over the first etch stop layer, a second insulating layer over the second etch stop layer and having a contact opening over the contact plug, and a conductive layer disposed in the contact opening and over the contact plug. The contact opening is substantially free of the second etch stop layer, and the first etch stop layer is present in the contact opening. | 2014-09-18 |
20140264750 | Resistor and Metal-Insulator-Metal Capacitor Structure and Method - A passive circuit device incorporating a resistor and a capacitor and a method of forming the circuit device are disclosed. In an exemplary embodiment, the circuit device comprises a substrate and a passive device disposed on the substrate. The passive device includes a bottom plate disposed over the substrate, a top plate disposed over the bottom plate, a spacing dielectric disposed between the bottom plate and the top plate, a first contact and a second contact electrically coupled to the top plate, and a third contact electrically coupled to the bottom plate. The passive device is configured to provide a target capacitance and a first target resistance. The passive device may also include a second top plate disposed over the bottom plate and configured to provide a second target resistance, such that the second target resistance is different from the first target resistance. | 2014-09-18 |
20140264751 | METAL-INSULATOR-METAL (MIM) CAPACITOR - In one embodiment, a chip comprises a capacitor and a resistor. The capacitor comprises a first capacitor terminal, a second capacitor terminal, and a dielectric layer between the first and second capacitor terminals. The second capacitor terminal and the resistor are both fabricated from a resistor metal layer. | 2014-09-18 |
20140264752 | DUAL THREE-DIMENSIONAL (3D) RESISTOR AND METHODS OF FORMING - Various embodiments include dual three-dimensional (3D) resistor structures and methods of forming such structures. In some embodiments, a dual 3D resistor structure includes: a dielectric layer having a first set of trenches extending in a first direction through the dielectric layer; and a second set of trenches overlayed on the first set of trenches, the second set of trenches extending in a second direction through the dielectric layer, the second set of trenches and the first set of trenches forming at least one dual 3D trench; and a resistor material overlying the dielectric layer and at least partially filling the at least one dual 3D trench along the first direction and the second direction. | 2014-09-18 |
20140264753 | Novel Structure of W-Resistor - A plurality of openings is formed in a dielectric layer formed on a semiconductor substrate. The plurality of openings comprises a first opening extending to the semiconductor substrate, a second opening extending to a first depth that is substantially less than a thickness of the dielectric layer, and a third opening extending to a second depth that is substantially greater than the first depth. A multi-layer gate electrode is formed in the first opening. A thin resistor structure is formed in the second opening, and a connection structure is formed in the third opening, by filling the second and third openings substantially simultaneously with a resistor metal. | 2014-09-18 |
20140264754 | METHODS OF FORMING DOPED ELEMENTS AND RELATED SEMICONDUCTOR DEVICE STRUCTURES - Methods of forming doped elements of semiconductor device structures include forming trenches having undercut portions separating stem portions of a substrate. The stem portions extend between a base portion of the substrate and overlying broader portions of the substrate material. A carrier material including a dopant is formed at least on the sides of the stems in the undercut portions of the trenches. The dopant is diffused from the carrier material into the stems. As such, the narrow stem portions of the substrate become doped with a targeted dopant-delivery method. The doped stems may form or be incorporated within buried, doped, conductive elements of semiconductor device structures, such as digit lines of memory arrays. Also disclosed are related semiconductor device structures. | 2014-09-18 |
20140264755 | STRAINED SILICON NFET AND SILICON GERMANIUM PFET ON SAME WAFER - Various embodiments form silicon and silicon germanium fins on a semiconductor wafer. In one embodiment a semiconductor wafer is obtained. The semiconductor wafer comprises a substrate, a dielectric layer, and a semiconductor layer including silicon germanium (SiGe). At least one SiGe fin is formed from at least a first SiGe region of the semiconductor layer in at least one PFET region of the semiconductor wafer. Strained silicon is epitaxially grown on at least a second SiGe region of the semiconductor layer. At least one strained silicon fin is formed from the strained silicon in at least one NFET region of the semiconductor wafer. | 2014-09-18 |
20140264756 | STACKED INTEGRATED CIRCUIT - The formation of TSVs (through substrate vias) for 3D applications has proven to be defect dependent upon the type of starting semiconductor substrate employed. In addition to the initial formation of TSVs via Bosch processing, backside 3D wafer processing has also shown a defect dependency on substrate type. High yield of TSV formation can be achieved by utilizing a substrate that embodies bulk micro defects (BMD) at a density between 1e4/cc (particles per cubic centimeter) and 1e7/cc and having equivalent diameter less than 55 nm (nanometers). | 2014-09-18 |
20140264757 | METAL STRUCTURES AND METHODS OF USING SAME FOR TRANSPORTING OR GETTERING MATERIALS DISPOSED WITHIN SEMICONDUCTOR SUBSTRATES - Embodiments of the present invention provide metal structures for transporting or gettering materials disposed on or within a semiconductor substrate. A structure for transporting a material disposed on or within a semiconductor substrate may include a metal structure disposed within the semiconductor substrate and at a spaced distance from the material. The metal structure is configured to transport the material through the semiconductor substrate and to concentrate the material at the metal structure. The material may include a contaminant disposed within the semiconductor substrate, e.g., that originates from electronic circuitry on the substrate. | 2014-09-18 |
20140264758 | METHODS OF FORMING A PROTECTION LAYER TO PROTECT A METAL HARD MASK LAYER DURING LITHOGRAPHY REWORKING PROCESSES - One method disclosed herein includes forming a layer of insulating material above a semiconductor substrate, forming a hard mask layer comprised of a metal-containing material above the layer of insulating material, forming a blanket protection layer on the hard mask layer, forming a masking layer above the protection layer, performing at least one etching process on the masking layer to form a patterned masking layer having an opening that stops on and exposes a portion of the blanket protection layer, confirming that the patterned masking layer is properly positioned relative to at least one underlying structure or layer and, after confirming that the patterned masking layer is properly positioned, performing at least one etching process through the patterned masking layer to pattern at least the blanket protection layer. | 2014-09-18 |
20140264759 | STACKED WAFER WITH COOLANT CHANNELS - A wafer assembly with internal fluid channels. The assembly is fabricated by creating one or more channels in a first surface of a first semiconductor wafer and creating an oxide surface on the first surface of the first semiconductor wafer. An oxide surface is also created on a first surface of a second semiconductor wafer. The assembly is fabricated by bonding the oxide surface of the first surface of the first semiconductor wafer to the oxide surface of the first surface of the second semiconductor wafer to create a wafer assembly and to seal the one or more channels at edges defined by the bonded first and second surfaces. | 2014-09-18 |
20140264760 | Layout Optimization of a Main Pattern and a Cut Pattern - A method for feature pattern modification includes extracting both a main pattern and a cut pattern from a design pattern, the main pattern being laid out under a set of process guidelines that improve the process window during formation of the main pattern, and modifying at least one of: the main pattern and the cut pattern if either feature pattern is in violation of a layout rule. | 2014-09-18 |