38th week of 2014 patent applcation highlights part 224 |
Patent application number | Title | Published |
20140281605 | POWER MANAGEMENT FOR A COMPUTER SYSTEM - Embodiments include a method for managing power in a computer system including a main processor and an active memory device including powered units, the active memory device in communication with the main processor by a memory link, the powered units including a processing element. The method includes the main processor executing a program on a program thread, encountering a first section of code to be executed by the active memory device, changing, by a first command, a power state of a powered unit on the active memory device based on the main processor encountering the first section of code, the first command including a store command. The method also includes the processing element executing the first section of code at a second time, changing a power state of the main processor from a power use state to a power saving state based on the processing element executing the first section. | 2014-09-18 |
20140281606 | DATA STORAGE POWER CONSUMPTION THRESHOLD - A power consumption threshold is implemented to manage power consumed by a plurality of devices. A power consumption threshold may be selected for a data storage system having multiple drives. Policies may control operation of storage devices such as hard disk drives to ensure the power consumption threshold is not exceeded. The policies may implement procedures for scheduling hard disk drive operations based on disk drive power characteristics, scheduling maintenance tasks, managing device power states, and strategically scheduling device operations based on their current state. The policies may be implemented by a data manager application in communication with multiple tiers of a data storage system. | 2014-09-18 |
20140281607 | METHOD AND APPARATUS FOR DISPLAYING A PREDETERMINED IMAGE ON A DISPLAY PANEL OF AN ELECTRONIC DEVICE WHEN THE ELECTRONIC DEVICE IS OPERATING IN A REDUCED POWER MODE OF OPERATION - A display controller for use within an electronic device includes a dedicated memory and a low power display processor for displaying information when the electronic device is operating in a reduced power mode of operation (e.g., sleep mode). The memory stores display data for a predetermined image and the display processor supplies the display data to a display panel of the electronic device when the electronic device is operating in the reduced power mode. The display controller may also include a processor interface for receiving control information from the electronic device's device processor to enable the display processor to determine that the electronic device is operating in reduced power mode. The display processor may be configured to scale the stored display data when, due to memory size constraints, the memory stores the display data at a resolution that is different from (e.g., less than) the display panel resolution. | 2014-09-18 |
20140281608 | Battery Usage Throttling for Mobile Devices - A computing device may be configured to determine a power supply usage rate of the computing device based on operations of applications and power-consuming components of the computing device. The computing device may be configured to obtain a target power supply depletion rate. Based on the power supply usage rate exceeding the target power supply depletion rate, the computing device may be configured to adjust an operation of an application of the applications and/or an operation of a power-consuming component of the power-consuming components so as to cause the power supply usage rate to substantially meet the target power supply depletion rate. | 2014-09-18 |
20140281609 | DETERMINING PARAMETERS THAT AFFECT PROCESSOR ENERGY EFFICIENCY - An example process for controlling a processor may include: (i) obtaining parameters associated with operation of a processor, where each of the parameters has a different time scale; (ii) performing an iterative process to identify ones of the parameters that achieve a particular energy efficiency in the processor, where the energy efficiency of the processor corresponds to a quasi-concave function having a maximum that corresponds to the ones of the parameters; and (iii) controlling the processor using the ones of the parameters. | 2014-09-18 |
20140281610 | EXPLOITING PROCESS VARIATION IN A MULTICORE PROCESSOR - A disclosed method includes accessing characterization data indicating first and second sets of performance characteristics for first and second processing cores of a processor; determining, based on a performance objective and the characterization data, a first power state for the first processing core and a second power state for the second processing core; and applying the first power performance objective to the first processing core and the second power performance objective to the second processing core. | 2014-09-18 |
20140281611 | POWER MANAGEMENT FOR A MEMORY DEVICE - An improved method and apparatus for performing power management in a memory device is disclosed. | 2014-09-18 |
20140281612 | MEASUREMENT OF PERFORMANCE SCALABILITY IN A MICROPROCESSOR - A scalability algorithm causes a processor to initialize a performance indicator counter, operate at an initial frequency of the first clock signal for a first duration, and determine, based on the performance indicator counter, an initial performance of the first processing core. The algorithm may then cause the processor to operate at a second frequency of the first clock signal for a second duration and determine, based on the performance indicator counter, a second performance of the first processing core. A performance scalability of the first processing core may be determined based on the initial performance and the second performance and an operational parameter, such as one or more clock frequencies and/or supply voltage(s), may be changed based on the determined scalability. | 2014-09-18 |
20140281613 | FREQUENCY CONTROL DEVICE AND FREQUENCY CONTROL METHOD - For every application, a storage unit stores performance information which indicates processing performance required for processing of the application. A derivation unit derives processing performance required for processing of an application executed in a processor on the basis of the performance information. A frequency control unit controls an operation frequency of a CPU in accordance with the processing performance derived by the derivation unit. | 2014-09-18 |
20140281614 | SYSTEM AND METHOD OF RACK MANAGEMENT - A rack management method and system is disclosed. The method includes detecting the presence of a computing device releasably mounted in a frame, the detecting based on an electrical connection established between a configuration bar disposed in a rear portion of the frame and the computing device, and determining a physical location of the computing device within the frame based on the electrical connection. The method also includes retrieving management information about the computing device from a profile storage disposed within the computing device via the electrical connection and storing the management information in a management table, the management table associating the computing device with the physical location within the frame. | 2014-09-18 |
20140281615 | TECHNIQUES FOR POWER SAVING ON GRAPHICS-RELATED WORKLOADS - Various embodiments are generally directed to an apparatus, method and other techniques for monitoring a task of a graphics processing unit (GPU) by a graphics driver, determining if the task is complete, determining an average task completion time for the task if the task is not complete and enabling a sleep state for a processing circuit for a sleep state time if the average task completion time is greater than the sleep state time. | 2014-09-18 |
20140281616 | PLATFORM AGNOSTIC POWER MANAGEMENT - In an embodiment, a processor includes at least one functional block and a central power controller. The at least one functional block may include at least one block component and block power logic. The block power logic may be to: receive a first request to initiate a first reduced power mode in the at least one functional block, and in response to the first request, send a notification signal to a central power controller. The central power controller may be to, in response to the notification signal: store a first state of the at least one functional block, and initiate the first reduced power mode in the at least one functional block. Other embodiments are described and claimed. | 2014-09-18 |
20140281617 | PREVENTING SLEEP MODE FOR DEVICES BASED ON SENSOR INPUTS - A data processing device may receive, from an application running on the data processing device, an indication that one or more sensors may be associated with a user input for the application. Based on sensing information collected from the one or more sensors, a characteristic of the user input may be determined by the data processing device. The data processing device may refrain from entering a sleep mode if the characteristic of the user input matches a specific characteristic condition specified by the application. The data processing device may allow entering the sleep mode if the characteristic of the user input does not match the specific characteristic condition for a specific timeout period specified by the application. The data processing device may receive the indication, information on the specific characteristic condition and/or information on the specific timeout period via invoking, by the application, one or more application programming interfaces (APIs). | 2014-09-18 |
20140281618 | Systems And Methods For Providing Auxiliary Reserve Current For Powering Information Handling Sytems - Systems and methods are disclosed for providing auxiliary reserve current to power a system load of an information handing system using an auxiliary energy storage power source as an energy cache to selectably provide auxiliary reserve current to at least partially supplement the normal operating power supply (e.g., battery pack, AC adapter, AC/DC power source, etc.) of an information handling system during temporary times of increased current need by the system load of the information handling system. | 2014-09-18 |
20140281619 | SYSTEMS AND METHODS FOR MODIFYING POWER STATES IN A VIRTUAL ENVIRONMENT - Systems, methods, and software are described herein for operating a power management system including identifying a virtual machine load in a virtual machine environment, identifying a power state for at least one real machine in the virtual machine environment based on the virtual machine load, and modifying the power state for the at least one real machine. | 2014-09-18 |
20140281620 | Control System for Power Control - A power control system for saving power by powering on enough application servers to satisfy the current load workload as well as any required reserve capacity based on administrative settings is disclosed. As the load increases, more servers are powered on. As the load decreases some servers are powered off. The power control system provides a reasonable end user experience at the least cost based on power consumption of the servers. | 2014-09-18 |
20140281621 | STEALTH POWER MANAGEMENT IN STORAGE ARRAY - Increased power savings is provided by powering down idle storage devices and emulating storage device responses to host requests which do not require data access. A virtual target emulates the hard disk drive, has information associated with the hard disk drive, and provides information in response to host requests to satisfy the host. For host requests that do require data access, the storage device is powered on and storage device control is provided to the host. If the storage device is not ready to communicate with a host, a virtual target communicates with the host to emulate the storage device and prevent the host from timing out while the storage device is powering up to get ready. | 2014-09-18 |
20140281622 | METHOD, APPARATUS, AND SYSTEM FOR IMPROVING RESUME TIMES FOR ROOT PORTS AND ROOT PORT INTEGRATED ENDPOINTS - A device is determined to be in a low power state. A transition from the low power state to an active state is initiated, where a fixed minimum recovery time is defined for transitions from the low power state to the active state. A capability of the device is identified corresponding to transition of the device from the low power state to the active state, and the transition of the device from the low power state to the active state is completed based at least in part on the capability, such that the transition is to be completed prior to expiration of the fixed minimum recovery time. | 2014-09-18 |
20140281623 | WIRELESS DEVICE INCLUDING SYSTEM-ON-A-CHIP HAVING LOW POWER CONSUMPTION - A wireless station is disclosed that may quickly enter and/or exit a sleep state and that may reduce power consumption associated with waking up from the sleep state to perform selected low power operations by performing such operations using a set of first instructions stored within an internal memory of the station's processor. If more complex operations such as processing downlink data received from an access point are subsequently desired, then the processor may jump to execution of a set of second instructions stored in an external memory that is coupled to the processor. | 2014-09-18 |
20140281624 | Power Management Device - A power management device is adapted to reduce power consumption, particularly in battery-powered applications such as within a node in a utility network (e.g., in a gas, water, or other utility application). In one example, a low-current voltage regulator provides power to a processor during low-power “sleep” states. A high-current voltage regulator provides power to the processor, metrology devices and/or a radio during “awake” states. A buck-boost device may provide power to a transmitter during radio frequency (RF) transmissions. A max device may determine a greater of voltages output by a battery and the buck-boost device, and use the higher to power the high-current voltage regulator. The power management device may include a state machine, which may include several states and operations to perform within each state. In one state, the processor enters a sleep state prior to recovery of battery voltage after a transmission state. | 2014-09-18 |
20140281625 | Storing System Data During Low Power Mode Operation - Apparatus and method for operating a device in a low power mode. In accordance with some embodiments, the apparatus comprises a memory and a system on chip (SOC) integrated circuit. The SOC has a first region with a processing core and a second region electrically isolated from the first region as an always on domain power island with a power control block. In response to a sleep command, the processing core transfers system data to the memory and the power control block enters a low power mode in which no electrical power is supplied to the first region. In response to a wake up command, power is restored to the first region and the processing core performs a reinitialization operation responsive to status information communicated by the power control block indicative of a state of the system during the low power mode. | 2014-09-18 |
20140281626 | PHY Based Wake Up From Low Power Mode Operation - Apparatus and method for supplying electrical power to a device. A system on chip (SOC) integrated circuit includes a first region having a processing core and a second region characterized as an always on domain (AOD) power island having a power control block with an energy detector coupled to a host input line. First and second power supply modules respectively supply power to the first and second regions. The second power supply module includes a main switch between the first power supply module and a host input voltage terminal. The power control block opens the main switch to enter a low power mode during which no power is supplied to the first region, and the power control block closes the main switch to resume application of power to the first region responsive to the energy detector detecting electrical energy on the host input line. | 2014-09-18 |
20140281627 | Device Sleep Partitioning and Keys - A data storage device includes a device sleep state pin and device sleep state logic to allow the data storage device to store security keys and necessary device sleep state logic together in a volatile logical data storage element. The volatile logical data storage element may be on-chip or off-chip. Device sleep state logic parameters for powering down PHYs while in a device sleep state determine the power characteristics of the device sleep state. | 2014-09-18 |
20140281628 | Always-On Low-Power Keyword spotting - The invention relates to an electronic device that includes a wake-up system that operates at a substantially low power level and is applied to wake up the electronic device from a sleep mode. The wake-up system comprises a sound transducer that converts a received sound signal to an electrical signal and a keyword detection logic that preliminarily identifies a speech energy profile that corresponds to at least one of a plurality of keywords in a part of the electrical signal. In some embodiments, a keyword finder is further activated to identify with an enhanced accuracy whether the at least one keyword exists in the part of the electrical signal, and generates a wake-up control to activate a host of the electronic device from its sleep mode. | 2014-09-18 |
20140281629 | POWER MANAGEMENT FOR A COMPUTER SYSTEM - Embodiments include a method for managing power in a computer system including a main processor and an active memory device including powered units, the active memory device in communication with the main processor by a memory link, the powered units including a processing element. The method includes the main processor executing a program on a program thread, encountering a first section of code to be executed by the active memory device, changing, by a first command, a power state of a powered unit on the active memory device based on the main processor encountering the first section of code, the first command including a store command. The method also includes the processing element executing the first section of code at a second time, changing a power state of the main processor from a power use state to a power saving state based on the processing element executing the first section. | 2014-09-18 |
20140281630 | ELECTRONIC DEVICE WITH TWO DRIVING STRUCTURES - An electronic device with two driving structures is capable of switching between a standby state and a working state. The electronic device includes a power supply, a processor and a driving circuit. The power supply is capable of outputting a first driving voltage or a second driving voltage. The processor detects whether the power supply outputs a first driving voltage and whether the electronic device receives a power-on instruction for powering on the electronic device. The processor outputs different controlling signals to control the driving circuit to output different voltages. The processor works in different states of different driving structures based on the received voltage outputted by the driving circuit. | 2014-09-18 |
20140281631 | ELECTRONIC DEVICE, POWER CONTROL METHOD AND STORAGE MEDIUM STORING PROGRAM THEREOF - In an electronic device, a first sensor detects a detection target on a first region. A second sensor detects a detection target on a second region. A third sensor detects a detection target on a third region. A power control unit turns on the second sensor in a case where the first sensor detects the detection target on the first region. The power control unit turns on the third sensor and turns off the first sensor in a case where the second sensor detects the detection target on the second region. | 2014-09-18 |
20140281632 | ELECTRONIC APPARATUS THAT MEASURES POWER DURING POWER SAVING STATE, METHOD OF CONTROLLING THE SAME, AND STORAGE MEDIUM - An electronic apparatus capable of accurately measuring an amount of electric power consumed during a power saving state while reducing an amount of electric power necessary for electric power measurement in the power saving state to a minimum. The apparatus is equipped with a power saving function for switching an operation mode between a normal state and a power saving state. A power measurement section measures a power of the image forming apparatus. A controller manages the power of apparatus based on the power measured by the power measurement section. When it is determined that the operation mode is the power saving state, the power measurement section stores the measured power without sending the same to the controller. | 2014-09-18 |
20140281633 | Magnet Key - A device for affecting a sleep mode of an electronic device includes an elongate member and a magnet. The magnet is disposed within the elongate member, and the elongate member and the magnet are shaped and sized to activate a magnetic sleep sensor of the electronic device in response to the magnet being placed in proximity of the magnetic sleep sensor. A system for affecting a sleep mode of an electronic device includes a housing to receive the electronic device, and a device for activating a sleep mode of the electronic device. The housing has an aperture, and the device has a magnet. The device is configured to activate a magnetic sleep sensor on the electronic device. | 2014-09-18 |
20140281634 | CONTROLLING POWER SUPPLY UNIT POWER CONSUMPTION DURING IDLE STATE - Methods and apparatus relating to controlling power consumption by a Power Supply Unit (PSU) during idle state are described. In one embodiment, a power supply unit enters a lower power consumption state (e.g. S9) based on power state information, corresponding to one or more components of the platform, and comparison of a first value (corresponding to a frequency/frequentness of entry into the lower power consumption state) to a first threshold value. Other embodiments are also disclosed and claimed. | 2014-09-18 |
20140281635 | REDUCING POWER CONSUMPTION DURING IDLE STATE - Methods and apparatus relating to power consumption reduction during idle state(s) are described. In one embodiment, logic transfers control of a power state of a device to one or more general purpose input output signals. The logic generates a signal to control the power state of the device via a switch. Also, the logic generates the signal, at least in part, based on the one or more general purpose input output signals and a control enable signal. Other embodiments are also claimed and disclosed. | 2014-09-18 |
20140281636 | MOBILE SYSTEMS WITH SEAMLESS TRANSITION BY ACTIVATING SECOND SUBSYSTEM TO CONTINUE OPERATION OF APPLICATION EXECUTED BY FIRST SUBSYSTEM AS IT ENTERS SLEEP MODE - A computer system includes two or more subsystems. In one example, a first subsystem is executing a multimedia application using data stored in a first storage device. A copy of the data is also stored in a second storage device associated with a second subsystem. The second subsystem may be a dedicated multimedia player controller. When the first subsystem is to enter a sleep state, the second subsystem may continue to process the multimedia data stored in the second storage device. The second subsystem may also use the same audio port that the first subsystem was using before it enters the sleep state. Appropriate transition point may be determined by the second subsystem to ease audio disruption. | 2014-09-18 |
20140281637 | MEMORY STATE MANAGEMENT FOR ELECTRONIC DEVICE - In one embodiment a controller comprises logic to determine whether an electronic device is operating in a low power state and in response to a determination that the electronic device is operating in a low power state, implement a memory state management routine which reduces power to at least a section of volatile memory in the memory system. Other embodiments may be described. | 2014-09-18 |
20140281638 | APPLICATION OF NORMALLY CLOSED POWER SEMICONDUCTOR DEVICES - A power source delivers power from a main power source using switching by a normally on transistor. A driver switches on and off the normally on transistor under a control signal by a controller during regular operation. A housekeeping power supply delivers auxiliary power to the driver. The driver switches off the normally on transistor during irregular operation. Irregular operation occurs at least when the control signal is absent or no auxiliary power is available or during transients such a power up or down. Bridge block pairs thereof can be arranged to form a half bridge power switch, an H bridge switch, a three phase bridge switch, a multi-phase switch, a buck converter, a buck-boost converter, or a boost converter. | 2014-09-18 |
20140281639 | DEVICE POWER MANAGEMENT STATE TRANSITION LATENCY ADVERTISEMENT FOR FASTER BOOT TIME - Methods and apparatus relating to device power management state transition latency advertisement for faster boot time are described. In some embodiments, a storage unit stores a value corresponding to a requisite transition delay period for a first agent to exit from a low power consumption state. The first agent writes the value to the storage unit and a second agent waits for the requisite transition delay period (after the first agent initiates its exit from the low power consumption state) before the second agent attempts to communicate with the first agent via a link. Other embodiments are also disclosed and claimed. | 2014-09-18 |
20140281640 | INTELLIGENT FRONT PANEL - The front panel includes intelligence for controlling power, reset and power down functions for a storage enclosure having multiple servers, service processors, and enclosure management devices. The front panel may display information pertaining to system power state, disk activity, Ethernet activity, and other information. The front panel may implement sequencing rules for changes in power state. The front panel provides information for multiple servers and other devices through a single panel. | 2014-09-18 |
20140281641 | METHOD AND APPARATUS FOR CONTROLLED RESET SEQUENCES WITHOUT PARALLEL FUSES AND PLL'S - A system, semiconductor device and method for providing a controlled system reset sequence with lower power consumption without dependency on fuses, PLL's and external XTAL's. A method to simplify a boot sequence by using a ring oscillator that compensates for voltage and temperature variations while also removing the dependency on parallel fuses, PLL's and external XTAL's. | 2014-09-18 |
20140281642 | RESOLUTION PROGRAMMABLE DYNAMIC IR-DROP SENSOR WITH PEAK IR-DROP TRACKING ABILITIES - A data processing system on an integrated circuit includes a core that performs switching operations responsive to a system clock that draws current from the power supply network. An IR-drop detector includes a resistor ladder having outputs representative of an IR-drop caused by the core during the switching operations. The system further includes a plurality of amplifiers coupled to the outputs indicative of the IR-drop, a plurality of flip-flops coupled to the amplifiers, and a variable clock generator. The variable clock generator outputs a sampling clock comprising a group consisting of a variable phase or a variable frequency to the plurality of flip-flops. The flip-flops are triggered by the sampling clock so that the IR-drop at a time during a clock cycle of the system clock can be detected, and the peak IR-drop value for can be tracked. | 2014-09-18 |
20140281643 | Apparatus and method for detecting clock tampering - Disclosed is a method for detecting clock tampering. In the method a plurality of resettable delay line segments are provided. Resettable delay line segments between a resettable delay line segment associated with a minimum delay time and a resettable delay line segment associated with a maximum delay time are each associated with discretely increasing delay times. A monotone signal is provided during a clock evaluate time period associated with a clock. The monotone signal is delayed using each of the plurality of resettable delay line segments to generate a respective plurality of delayed monotone signals. The clock is used to trigger an evaluate circuit that uses the plurality of delayed monotone signals to detect a clock fault. | 2014-09-18 |
20140281644 | CONTROL SYSTEM FOR POWER CONTROL - A power control system for saving power by powering on enough application servers to satisfy the current load workload as well as any required reserve capacity based on administrative settings is disclosed. As the load increases, more servers are powered on. As the load decreases some servers are powered off. The power control system provides a reasonable end user experience at the least cost based on power consumption of the servers. | 2014-09-18 |
20140281645 | ENCHANCED GRID RELIABILITY THROUGH PREDICTIVE ANALYSIS AND DYNAMIC ACTION FOR STABLE POWER DISTRIBUTION - A power grid stabilizing system may include a processor and a network interface executable by the processor to monitor for new event data from power consumption devices over a network. The new event data may include information such as device location, operating information, and sensor data. The system may include an estimation engine operable to analyze the new event data to determine power consumption behavior of a consumption device, and a predictor operable to anticipate an occurrence of a future event responsive to the analysis. The predictor may also predict the outcome of the future event based on analysis of the new event data in relation to past behavior data of the consumption device. The network interface may further communicate the anticipated future event and the predicted outcome to one or more of the other consumption devices. | 2014-09-18 |
20140281646 | POWER MANAGEMENT METHOD FOR SERVER SYSTEM - A power management method for a server system is provided. At least any one of a power status indication signal and an alert signal from a power supply is detected to judge whether an input voltage is normal. If it is judged that the input voltage is abnormal, a motherboard sends the power status indication signal to a battery backup unit (BBU) to inform the BBU to supply power to the motherboard. If it is judged that the input voltage is abnormal, the motherboard lowers its loading. | 2014-09-18 |
20140281647 | MANAGING THE OPERATION OF A COMPUTING SYSTEM - A method and system for managing the operation of a computing system are described herein. The method includes determining a number of workloads on the computing system. The method also includes determining a number of performance-power states for each workload and a corresponding performance range and power consumption range for each performance-power state. The method further includes managing performance and power consumption of the computing system based on the performance-power states. | 2014-09-18 |
20140281648 | Systems and Methods for Power Awareness in Mobile Applications - A data processing device may comprise one or more applications. Based on communication from a particular application, the data processing device may be operable to provide, to the particular application, power consumption information of the data processing device associated with each of a plurality of application states of the particular application and/or information related to one or more power-consuming components in the data processing device. The particular application may register with the data processing device to receive a notification when a power consuming component is available for use. The particular application may also perform operations based on the provided power consumption information and/or the provided information related to the one or more power-consuming components. The plurality of application states may comprise an application idle state and one or more application active states. | 2014-09-18 |
20140281649 | Method For Automatic Mapping Of AC Phase Conductors And Identification Of AC Buses In A Multi-Bus Power System - A system is disclosed for detecting if a remote device is associated with a power supply. The system may have a controller having machine readable, non-transitory executable code running thereon for varying a characteristic of a signal being applied to the power supply. The controller further may be configured to compare a measurement obtained from a measurement subsystem relating to a measured signal present at the remote device. The controller may also be configured to make a comparison between the signal being applied to the power supply and the measured signal obtained at the remote device, and to determine whether the remote device is electrically associated with the power supply. | 2014-09-18 |
20140281650 | PASSIVE MONITORING SYSTEM - Embodiments discussed herein provide a passive monitoring system for use in a residential independent living framework. In some exemplary embodiments, the system may be used to alert a primary caregiver of a possible decline or change in an activity of daily living (“ADL”) of the monitored individual. The system may collect usage data associated with, for example, electrical devices at the living quarters of the monitored individual. The collected data may include data pairs of time samples and voltage data associated with one or more electrical devices that the monitored individual is expected to utilize. Applying various filters to the collected data, a possible decline or change in ADL of the monitored individual may be identified. | 2014-09-18 |
20140281651 | SERIAL PERIPHERAL INTERFACE AND METHODS OF OPERATING SAME - Serial peripheral interfaces and methods of operating the same are provided. An apparatus can have a serial peripheral interface (SPI) including a first command state machine (CSM), and a second CSM. | 2014-09-18 |
20140281652 | DATA SYNCHRONIZATION ACROSS ASYNCHRONOUS BOUNDARIES USING SELECTABLE SYNCHRONIZERS TO MINIMIZE LATENCY - A system and apparatus that include a selectable synchronizer circuit for synchronizing data across asynchronous boundaries are disclosed. The apparatus includes a unit associated with a first clock domain and a synchronizer sub-unit (SSU) coupled to the unit and associated with a second clock domain. The synchronizer sub-unit includes two or more synchronizers and selector logic configured to select one output of the two or more synchronizers. | 2014-09-18 |
20140281653 | REESTABLISHING SYNCHRONIZATION IN A MEMORY SYSTEM - Embodiments relate to reestablishing synchronization across multiple channels in a memory system. One aspect is a system that includes a plurality of channels, each providing communication with a memory buffer chip and a plurality of memory devices. A memory control unit is coupled to the plurality of channels. The memory control unit is configured to perform a method that includes receiving an out-of-synchronization indication associated with at least one of the channels. The memory control unit performs a first stage of reestablishing synchronization that includes selectively stopping new traffic on the plurality of channels, waiting for a first time period to expire, resuming traffic on the plurality of channels based on the first time period expiring, and verifying that synchronization is reestablished for a second time period. | 2014-09-18 |
20140281654 | SYNCHRONIZING DATA TRANSFER FROM A CORE TO A PHYSICAL INTERFACE - In one example implementation, the present disclosure provides a system that includes circuitry and one or more electronic components for synchronizing data transfer from a core to a physical interface. One example can involve an apparatus for interfacing a digital core with at least one physical interface that includes a macro configured on the digital core, the macro having at least one data output, a first data input, a reset input and a sync reset output, the macro to be clocked by a first clock having a first clock rate. The first clock can be configured to clock in data from the digital core on the first data input; clock in a reset signal from the digital core on the reset input, wherein a synchronized reset signal is output on the sync reset output. The apparatus can also include physical interface circuitry and a reset sampling input. | 2014-09-18 |
20140281655 | Transducer Clock Signal Distribution - An array of ultrasonic transducers can be controlled to produce a steerable beam. Beam steering can be skewed by buffer delays in the distribution of a clock signal. The skew can be at least approximately linearized by distributing the clock signal in a diagonal fashion across an array of buffers corresponding to ultrasonic transducer controllers. Potential error in beam steering that can arise from clock skew can be corrected based on the linear tilt. | 2014-09-18 |
20140281656 | Global Synchronous Clock - Processor clock signals are generated for each processor in a HPC system, such that all the processor clock signals are of the same frequency. Furthermore, as part of a startup (boot) procedure, a process sets all time stamp counters (TSCs) of the processors, such they indicate identical times. Each blade of the HPC system recovers a recovered clock signal from a synchronous communication network, to which the blade is coupled. The blade generates a processor clock from the recovered clock signal and provides the processor clock to processor(s) on the blade. Each chassis is coupled to a second, system-wide, synchronous communication network, and each chassis synchronizes its chassis synchronous communication network with the system-wide synchronous communication system. Thus, all the processor clock signals are generated with the same frequency. | 2014-09-18 |
20140281657 | PROCESSOR CORE CLOCK RATE SELECTION - Techniques described herein generally relate to multi-core processors including two or more processor cores. Example embodiments may set forth devices, methods, and computer programs related to calculating a clock rate for one or more of the processor cores in the multi-core processor. One example method may include determining a first estimated workload for a first processor core and a second estimated workload for a second processor core within a scheduling interval in a periodic scheduling environment. In addition, a first clock rate for the first processor core may be calculated based on one or more of the first estimated workload, a maximum clock rate supported by the multi-core processor and/or the scheduling interval. Similarly, a second clock rate for the second processor core may also be calculated based on one or more of the second estimated workload, the maximum clock rate, and/or the scheduling interval. | 2014-09-18 |
20140281658 | COMPRESSED SAMPLING AND MEMORY - Aspects of a low power memory buffer are described. In one embodiment, a sampling rate of a signal is adjusted to identify extrema of a signal. An extrema pulse is generated and, in response to the extrema pulse, a time segment and potential value of the signal are stored in a memory. In other aspects, rising and falling slopes of the signal are tracked to identify a local maximum and a local minimum of the signal. In this scenario, an extrema pulse is generated for each of the local maximum and minimum, and time segment and potential values are stored for the local maximum and minimum. Generally, the storage of analog values of the signal at an adjusted sampling rate is achieved with low power, and the signal may be reconstructed at a later time. | 2014-09-18 |
20140281659 | INTELLIGENT MODULES IN A PARTICLE COUNTER - An airborne, gas, or liquid particle sensor with one or more intelligent modules either within the instrument or attached to the instrument. These modules comprising sub-systems with local controllers or memory. | 2014-09-18 |
20140281660 | INFORMATION PROCESSING DEVICE, TIME ADJUSTING METHOD, AND TIME ADJUSTING PROGRAM - One embodiment provides an information processing device which includes a clock unit, a file access unit and a setting unit. The clock unit is configured to count up an elapsed time from a prescribed reference time if an origin time has not been set, and to count up an elapsed time from the origin time if the origin time has been set. The file access unit is configured to access a file which has time information given by an external device or the information processing device. The file is stored in a storage device. The setting unit is configured to acquire the time information from the file via the file access unit, and to set the acquired time information into the clock unit as the origin time. | 2014-09-18 |
20140281661 | Hybrid Memory System With Configurable Error Thresholds And Failure Analysis Capability - A system and method for configuring fault tolerance in nonvolatile memory (NVM) are operative to set a first threshold value, declare one or more portions of NVM invalid based on an error criterion, track the number of declared invalid NVM portions, determine if the tracked number exceeds the first threshold value, and if the tracked number exceeds the first threshold value, perform one or more remediation actions, such as issue a warning or prevent backup of volatile memory data in a hybrid memory system. In the event of backup failure, an extent of the backup can still be assessed by determining the amount of erased NVM that has remained erased after the backup, or by comparing a predicted backup end point with an actual endpoint. | 2014-09-18 |
20140281662 | DYNAMICALLY ADAPTIVE BIT-LEVELING FOR DATA INTERFACES - A circuit and method for implementing a adaptive bit-leveling function in an integrated circuit interface is disclosed. During a calibration operation, a pre-loaded data bit pattern is continuously sent from a sending device and is continuously read from an external bus by a receiving device. A programmable delay line both advances and delays each individual data bit relative to a sampling point in time, and delay counts relative to a reference point in time are recorded for different sampled data bit values, enabling a delay to be determined that best samples a data bit at its midpoint. During the advancing and delaying of a data bit, jitter on the data bit signal may cause an ambiguity in the determination of the midpoint, and solutions are disclosed for detecting jitter and for resolving a midpoint for sampling a data bit even in the presence of the jitter. | 2014-09-18 |
20140281663 | RE-FORMING AN APPLICATION CONTROL TREE WITHOUT TERMINATING THE APPLICATION - A reconnection system re-forms a control tree for an application that is executed in parallel without terminating execution of the application. The reconnection system detects when a node of a control tree has failed and directs the nodes that have not failed to reconnect to effect the re-forming of the control tree without the failed node and without terminating the application. Upon being directed to reconnect, a node identifies new child nodes that are to be its child nodes in the re-formed control tree. The node maintains the existing connection with each of its current child nodes that is also a new child node, terminates the existing connection with each of its current child nodes that is not also a new child node, establishes a new connection with any new child node that is not a current child node, and directs each new child node to reconnect. | 2014-09-18 |
20140281664 | METHOD AND SYSTEM FOR DETERMINING DEVICE CONFIGURATION SETTINGS - A method and system for determining and updating configuration settings on a device are provided herein. In some embodiments, a method for updating configuration settings on a device may include detecting an error condition produced by executing an app on the device, collecting information associated with the error condition, the app and the device responsive to the detected error condition, sending a request for new configuration settings, wherein the request includes the collected information, receiving one or more new configuration settings in response to the request, and updating one or more configuration settings of at least one of the device or the app using the new configuration settings received. | 2014-09-18 |
20140281665 | AUTOMATED PATCH GENERATION - A computer-implemented method, computer program product, and computing system is provided for generating software patches. In an implementation, a method may include receiving an indication of a software product and a product level of the software product. An indication of a specific defect associated with the software product and the product level may be received. A defect change-set associated with a correction of the specific defect may be identified. An overlapping change-set may be determined based on, at least in part, a source control history associated with the software product. The overlapping change set may occur between the product level and the defect change-set in the source control history and may implicate at least one common with the defect change-set. A software patch correcting the specific defect may be generated based on the defect change-set and the overlapping change-set. | 2014-09-18 |
20140281666 | METHODS FOR DYNAMICALLY ADAPTIVE BIT-LEVELING BY INCREMENTAL SAMPLING, JITTER DETECTION, AND EXCEPTION HANDLING - A circuit and method for implementing a adaptive bit-leveling function in an integrated circuit interface is disclosed. During a calibration operation, a pre-loaded data bit pattern is continuously sent from a sending device and is continuously read from an external bus by a receiving device. A programmable delay line both advances and delays each individual data bit relative to a sampling point in time, and delay counts relative to a reference point in time are recorded for different sampled data bit values, enabling a delay to be determined that best samples a data bit at its midpoint. During the advancing and delaying of a data bit, jitter on the data bit signal may cause an ambiguity in the determination of the midpoint, and solutions are disclosed for detecting jitter and for resolving a midpoint for sampling a data bit even in the presence of the jitter. | 2014-09-18 |
20140281667 | Fault Detection Method, Gateway, User Equipment, and Communications System - Embodiments of the present invention provide a fault detection method, including discovering that a fault occurs in a DNS server or a service server related to a UE; performing, by a gateway, fault detection on the DNS server or the service server; and, after the fault is rectified, instructing the UE to establish a connection to the DNS server or the service server. Correspondingly, the embodiments of the present invention further provide a gateway, a UE, and a communications system, thereby avoiding frequent air interface release and connections, and frequent bearer deactivation and activation, which reduces the signaling overhead of the system, and enhances stability of a mobile network. | 2014-09-18 |
20140281668 | ADAPTIVE CONTROL LOOP PROTECTION FOR FAST AND ROBUST RECOVERY FROM LOW-POWER STATES IN HIGH SPEED SERIAL I/O APPLICATIONS - Methods and apparatus related to adaptive control loop protection for fast and robust recovery from low-power states in high speed serial I/O applications are described. In some embodiments, a first bit pattern is detected, at a first agent, that indicates a speculative entry by a second agent into a low power consumption state and one or more control loops are frozen. A second bit pattern is detected (after entering the low power consumption state) that indicates exit from the low power consumption state by the second agent and the one or more control loops are unfrozen (e.g., in a specific order). Other embodiments are also claimed and/or disclosed. | 2014-09-18 |
20140281669 | OpenFlow Controller Master-slave Initialization Protocol - A method for network controller initialization that includes identifying a controller connected to a network as a primary controller that manages switches in the network. One or more other controllers connected to the network are identified as secondary controllers. A failover priority table is created. The failover table indicates an order that the one or more other controllers will replace the controller as the primary controller in the event that the controller enters a failure mode. The failover priority table is broadcast to the switches in the network. | 2014-09-18 |
20140281670 | PROVIDING A BACKUP NETWORK TOPOLOGY WITHOUT SERVICE DISRUPTION - In one embodiment, a primary root node may detect one or more neighboring root nodes based on information received from a first-hop node and may select a backup root node among the neighboring root nodes. Once selected, the backup root node may send the primary root node a networking identification and a corresponding group mesh key which the primary root node may forward to the first-hop nodes to cause the first-hop nodes to migrate to the backup root node when connectivity to the primary root node fails. In addition, the first-hop root nodes may migrate back to the primary root node when connectivity to the primary root node is restored. | 2014-09-18 |
20140281671 | ENHANCED FAILOVER MECHANISM IN A NETWORK VIRTUALIZED ENVIRONMENT - An embodiment of the invention is associated with a virtualized environment that includes a hypervisor, client LPARs, and virtual servers that each has a SEA, wherein one SEA is selected to be primary SEA for connecting an LPAR and specified physical resources. A first SEA of a virtual server sends a call to the hypervisor, and in response the hypervisor enters physical adapter capability information, contained in the call and pertaining to the first SEA, into a table. Further in response to receiving the call, the hypervisor decides whether or not the first SEA of the virtual server should then be the primary SEA. The hypervisor sends a return call indicating its decision to the first SEA. | 2014-09-18 |
20140281672 | PERFORMING NETWORK ACTIVITIES IN A NETWORK - Techniques and systems for performing a network activity within a network. The technique includes assigning one or a plurality of network devices subnets with network devices for performing network activities. Network devices within the assigned network device subnets can be assigned to act as a primary network device and a backup network device. The primary network device can perform the network activity. The backup network devices can monitor the primary network device and continue performing the network activities if the primary network device fails or is rogue. | 2014-09-18 |
20140281673 | HIGH AVAILABILITY SERVER CONFIGURATION - A switch may be configured with multiple zones to provide access to an external storage to certain processing systems. For example, the switch may be configured with two zones, in which a first zone configuration provides access to the external storage for a first processing system and a second zone configuration provides access to the external storage for a second processing system. Thus, the switch may provide high availability of the external storage and allow seamless transition from one computer system to another computer system. | 2014-09-18 |
20140281674 | FAULT TOLERANT SERVER - The virtual computer of the active system includes a memory configured of small regions grouped in a first group and small regions grouped in a second group. When a checkpoint is detected by the checkpoint detection unit, the transfer control unit suspends the virtual computer, copies, to a transfer buffer (not shown), data of the small regions in the first group among the small regions of the memory having been updated after a previous checkpoint, and after inhibiting writing to the small regions in the second group, restarts the virtual computer. Further, the transfer control unit copies data of the small regions, in which writing is inhibited, to the transfer buffer and releases write inhibit, and transfers the data of the small regions, having been copied to the transfer buffer, to the physical computer. | 2014-09-18 |
20140281675 | FLEXIBLE FAILOVER POLICIES IN HIGH AVAILABILITY COMPUTING SYSTEMS - A system for implementing a failover policy includes a cluster infrastructure for managing a plurality of nodes, a high availability infrastructure for providing group and cluster membership services, and a high availability script execution component operative to receive a failover script and at least one failover attribute and operative to produce a failover domain. In addition, a method for determining a target node for a failover comprises executing a failover script that produces a failover domain, the failover domain having an ordered list of nodes, receiving a failover attribute and based on the failover attribute and failover domain, selecting a node upon which to locate a resource. | 2014-09-18 |
20140281676 | SYSTEM-LEVEL ISSUE DETECTION AND HANDLING - Issue detection and handling technology in which issue definitions that enable detection of issues at different devices of an enterprise level system that operate different applications are maintained. Solution definitions that relate to resolving issues detected based on the issue definitions are also maintained. Issue detection logic based on the issue definitions is provided to each of the different devices of the enterprise level system. Issue detection information collected based on the issue detection logic is received from at least one of the different devices of the enterprise level system. Based on the issue detection information, an issue at the at least one device is determined. A solution definition related to resolving the determined issue is accessed from the solution definitions. Based on the accessed solution definition, an operation directed to handling the determined issue is performed. | 2014-09-18 |
20140281677 | ERROR CORRECTION METHOD AND DEVICE AND INFORMATION STORING DEVICE - Error correction is carried out on first data stored in an external memory after determining that the first data contains a correctable error. Prior to starting the error correction of the first data, other accesses to the first data are blocked. Thereafter, the first data is corrected and overwritten by the corrected data (second data). After storing the second data in the external memory, accesses to the second data are permitted. | 2014-09-18 |
20140281678 | MEMORY CONTROLLER AND MEMORY SYSTEM - According to one embodiment, a memory controller includes a plurality of operation units respectively provided for a plurality of stages and each performing an error correcting operation for data supplied from an external device or data read from a nonvolatile semiconductor memory. | 2014-09-18 |
20140281679 | SELECTIVE FAULT STALLING FOR A GPU MEMORY PIPELINE IN A UNIFIED VIRTUAL MEMORY SYSTEM - One embodiment of the present invention is a parallel processing unit (PPU) that includes one or more streaming multiprocessors (SMs) and implements a selective fault-stalling pipeline. Upon detecting a memory access fault associated with an operation executing on a particular SM, a replay unit in the selective fault-stalling pipeline considers the operation as a faulting operation. Subsequently, instead of notifying the SM of the memory access fault, the replay unit recirculates the operation—reinserting the operation into the selective fault-stalling pipeline. Recirculating faulting operations in such a fashion enables the SM to execute other operation while the replay unit stalls the faulting request until the associated access fault is resolved. Advantageously, the overall performance of the PPU is improved compared to conventional PPUs that, upon detecting a memory access fault, cancel the associated operation and subsequent operations. | 2014-09-18 |
20140281680 | DUAL DATA RATE BRIDGE CONTROLLER WITH ONE-STEP MAJORITY LOGIC DECODABLE CODES FOR MULTIPLE BIT ERROR CORRECTIONS WITH LOW LATENCY - A memory module includes a bridge controller having a first interface and a second interface. The first interface receives commands and data from a host and the second interface is coupled to one or more memory components. The bridge controller performs multiple-bit error detection and correction on data stored in the one or more memory components. | 2014-09-18 |
20140281681 | ERROR CORRECTION FOR MEMORY SYSTEMS - According to one embodiment, a method for error correction in a memory module having ranks is provided where each rank has memory devices. The method includes determining a first mark condition for a first rank of the memory module, the first mark condition based on one or more uncorrectable error occurring in a first memory device in the first rank, placing a first mark in the first memory device, determining a second mark condition for the first rank, the second mark condition based on one or more uncorrectable error occurring in a second memory device in the first rank, placing a second mark in a third memory device in a second rank of the memory module and configuring the first memory device to respond to commands directed to the second rank, wherein configuring the first memory device is based on placing of the first mark and the second mark. | 2014-09-18 |
20140281682 | Systems and Methods for Performing Defect Detection and Data Recovery in a Memory System - Systems and methods for performing defect detection and data recovery within a memory system are disclosed. A controller of a memory system may receive a command to write data in a memory of the memory system; determine a physical location of the memory that is associated with the data write; write data associated with the data write to the physical location; and store the physical location of the memory that is associated with the data write in a Tag cache. The controller may further identify a data keep cache of a plurality of data keep caches that is associated with the data write based on the physical location of the memory that is associated with the data write; update an XOR sum based on the data of the data write; and store the updated XOR sum in the identified data keep cache. | 2014-09-18 |
20140281683 | FLASH MEMORY TECHNIQUES FOR RECOVERING FROM WRITE INTERRUPT RESULTING FROM VOLTAGE FAULT - Techniques, related to a flash memory device having a non-volatile memory array (NVM), for recovering from a write interrupt resulting from host-supplied memory voltage fault are disclosed. A memory controller is configured to control a response to an occurrence of the write-interrupt, the response including writing to the NVM, after the memory voltage is verified as being within an acceptable range, one or more of a safe copy of a portion of a first sector of upper-page data and a safe copy of a portion of a second sector of lower-page data, and terminating the write interrupt. Terminating the write-interrupt may include receiving new data from the host while avoiding sending an error message to the host. | 2014-09-18 |
20140281684 | Data Storage Devices Based on Supplementation - New data storage devices and techniques are provided. In some aspects of the invention, a new remote supplementation based media and system are provided. A local file and control system comprises a data density distribution that varies depending on Media Depth. A remote supplementation source and control system are also provided in a common network with the local control system. The local control system reports local file attributes, authorization and factors impacting media depth in real time, and the supplementation control system delivers permanent and streaming data corrections, supplementation and format updates to the local control system. In additional aspects of the invention, a patterned reference media device aids in building the local data density distribution. In some embodiments, the 3D arrangement, or other attributes, of structural storage device elements may serve as the patterned reference device. | 2014-09-18 |
20140281685 | PROBABILITY-BASED REMEDIAL ACTION FOR READ DISTURB EFFECTS - A method may be performed in a data storage device that includes a memory including a three-dimensional (3D) memory and a controller, in response to a request to read data from the memory. The data is located within a first word line of the memory. The method includes accessing the data from the first word line and determining, based on a probability threshold, whether to perform a remedial action with respect to a second word line. | 2014-09-18 |
20140281686 | COOPERATIVE MEMORY ERROR DETECTION AND REPAIR - Some embodiments include apparatuses and methods having a memory structure included in a memory device and a control unit included in the memory device. The control unit can provide information obtained from the memory structure during a memory operation to a host device (e.g., a processor) in response to a command from the host device. If the control unit receives a notification from the host device indicating that the host device has detected an error in the information obtained from the memory structure, then a repair unit included in the memory device performs a memory repair operation to repair a portion in the memory structure. | 2014-09-18 |
20140281687 | PERFORMANCE OF A SYSTEM HAVING NON-VOLATILE MEMORY - Systems and methods are disclosed for improving performance of a system having non-volatile memory (“NVM”). The system can vertically re-vector defective blocks of a user region of the NVM to other blocks having the same plane or die's plane (“DIP”) but corresponding to a dead region of the NVM. Then, the system can select any band with more than one defective block and vertically re-vector one of its defective blocks to a band that has no defective blocks. At run-time, the system can monitor the number of vertical re-vectors per DIP. If at least one vertical re-vector has been performed on all DIPs of the NVM, a band of the user region can be allocated for the dead region. | 2014-09-18 |
20140281688 | METHOD AND SYSTEM OF DATA RECOVERY IN A RAID CONTROLLER - Disclosed is a system and method for providing data integrity for pinned cache even if a RAID controller card fails while it has pinned cache or a memory module goes bad. A controller is enabled to use complete cache lines even if pinned cache is present, thereby enabling other virtual disks to run in write-back mode when pinned cache is present. | 2014-09-18 |
20140281689 | METHOD AND SYSTEM FOR REBUILDING DATA FOLLOWING A DISK FAILURE WITHIN A RAID STORAGE SYSTEM - A method and system for rebuilding data following a disk failure within a RAID storage system. The rebuild process keeps track of the relative number of READ operations across a RAID group so that following a RAID disk failure, the most frequently read areas of the RAID group can be rebuilt before less frequently accessed areas. Host READs to the rebuilt area will no longer necessitate on-the-fly rebuild from parity data, and thus host performance will be much less impacted than with prior rebuild processes. | 2014-09-18 |
20140281690 | Automatic Failure Recovery Using Snapshots and Replicas - In one embodiment, a method of coordinating data recovery in a storage stack with a hierarchy of layers includes, upon an input/output (I/O) request from a layer of the stack, issuing a help response to recover the data from a higher layer in hierarchy order. The method further includes processing the help response, at the higher layer, by issuing a return code of success or further help response to an even higher layer. | 2014-09-18 |
20140281691 | MASS STORAGE DEVICE AND METHOD OF OPERATING THE SAME TO STORE PARITY DATA - A mass storage memory device is disclosed. The device includes a plurality of blades where two blades are used to store parity data corresponding to data stored in the other blades. The device also includes a controller configured to write data to the blades along stripes extending from the other blades to the two blades, where the parity data within a stripe is based on the data written to the other blades in the stripe, and wherein the parity data includes two or more types of parity data. | 2014-09-18 |
20140281692 | Virtual Disk Recovery and Redistribution - Techniques for recovery and redistribution of data from a virtual disk storage system are described herein. In one or more implementations, a storage scheme derived for a virtual disk configuration is configured to implement various recovery and redistribution designed to improve recovery performance. The storage scheme implements one or more allocation techniques to produce substantially uniform or nearly uniform distributions of data across physical storage devices associated with a virtual disk. The allocation facilitates concurrent regeneration and rebalancing operations for recovery of data in the event of failures. Additionally, the storage scheme is configured to implements parallelization techniques to perform the concurrent operations including but not limited to controlling multiple parallel read/writes during recovery. | 2014-09-18 |
20140281693 | APPARATUSES AND METHODS FOR MEMORY TESTING AND REPAIR - Some embodiments include apparatuses and methods having a first interface to communicate with a processing unit, a second interface to communicate with a memory device, and a module coupled to the first and second interfaces. In at least one of the embodiments, the module can be configured to obtain information stored in the memory device and perform at least one of testing and repairing of a memory structure of the memory device based at least in part on the information. | 2014-09-18 |
20140281694 | MEMORY DEGENERACY METHOD AND INFORMATION PROCESSING DEVICE - A memory degeneracy method is executed by an information processing device in which a plurality of virtual machines operate. The memory degeneracy method includes storing, in a storage unit, a physical address or address information of a memory module, which corresponds to a virtual physical address relevant to a fault, in response to detecting the fault in a memory area assigned to a first virtual machine; changing an association relationship between virtual physical addresses and physical addresses relevant to the first virtual machine, before an operating system operating on the first virtual machine is rebooted in response to detecting the fault; and removing, from a usage target of the operating system, the virtual physical address corresponding to the physical address or the address information of the memory module stored in the storage unit. | 2014-09-18 |
20140281695 | PROCESSOR HANG DETECTION AND RECOVERY - Various aspects provide forced halt functionality for a processor to facilitate troubleshooting of processor hang situations. In the event that the processor initiates a transaction that does not receive a completion acknowledgement, halt detection logic can initiate a forced halt sequence that causes the processor to abort all pending transactions and transition to a debug state so that the internal state of the processor can be viewed. In addition, the processor can maintain a record of the processor state at the time that the hung transaction was dispatched, which can be viewed during debug mode to facilitate determining a cause of the hung transaction. | 2014-09-18 |
20140281696 | DETERMINE VOLTAGE SUPPLIED TO A CORE - Techniques for determining the voltage to be supplied to a core of a central processing unit are provided. A core of a central processing unit is monitored for errors. The voltage to be supplied to the core is determined based on the monitored errors. The voltage supplied to the core is altered based on the determined voltage. | 2014-09-18 |
20140281697 | Cooperative Data Recovery In A Storage Stack - In one embodiment, a method of coordinating data recovery in a storage stack with a hierarchy of layers includes, upon an input/output (I/O) request from a layer of the stack, issuing a help response to recover the data from a higher layer in hierarchy order. The method further includes processing the help response, at the higher layer, by issuing a return code of success or further help response to an even higher layer. | 2014-09-18 |
20140281698 | METHOD AND APPARTUS FOR DETECTING ANOMALIES WITHIN INDOOR INFORMATION - Methods, systems, computer-readable media, and apparatuses for detection of anomalies within indoor map information are presented. In some embodiments, the method includes receiving a digital map. The method may further include identifying one or more anomalies within the digital map using a software-based anomaly detection tool. The method may also include displaying one or more suggested corrections to a user based on the one or more identified anomalies. The method may additionally include correcting the one or more identified anomalies within the digital map. | 2014-09-18 |
20140281699 | Avoiding Restart On Error In Data Integration - According to one embodiment of the present invention, a system avoids restart on an error in a data integration process. The system processes data received from a data source in accordance with a parallel processing pipeline and partitioning scheme and submits said processed data to a destination. In response to an indication of an error, the system pauses receiving of data and saves unprocessed data received from the source. After correction of the error, the system resumes processing of the received and saved data in an order of the parallel processing pipeline and partitioning scheme. Embodiments of the present invention further include a method and computer program product for avoiding restart on an error in a data integration process in substantially the same manners described above. | 2014-09-18 |
20140281700 | COORDINATING FAULT RECOVERY IN A DISTRIBUTED SYSTEM - In various embodiments, methods and systems for coordinating, between a host and a tenant, fault recovery of tenant infrastructure in a distributed system is provided. A fault occurrence is determined for a tenant infrastructure in the distributed system. The fault occurrence may be a software failure or hardware failure of the tenant infrastructure supporting a service application of the tenant. A fault recovery plan is communicated to the tenant to notify the tenant of the fault occurrence and actions taken to restore the tenant infrastructure. It is determined whether a fault recovery plan response is received from the tenant; the fault recovery plan response is an acknowledgement from the tenant of the fault recovery plan. Upon receiving the fault recovery plan response or at the expiration of a predefined time limit, the fault recovery plan is executed to restore the tenant infrastructure. | 2014-09-18 |
20140281701 | ENHANCED FAILOVER MECHANISM IN A NETWORK VIRTUALIZED ENVIRONMENT - An embodiment of the invention is associated with a virtualized environment that includes a hypervisor, client LPARs, and virtual servers that each has a SEA, wherein one SEA is selected to be primary SEA for connecting an LPAR and specified physical resources. A first SEA of a virtual server sends a call to the hypervisor, and in response the hypervisor enters physical adapter capability information, contained in the call and pertaining to the first SEA, into a table. Further in response to receiving the call, the hypervisor decides whether or not the first SEA of the virtual server should then be the primary SEA. The hypervisor sends a return call indicating its decision to the first SEA. | 2014-09-18 |
20140281702 | DATA ERROR RECOVERY FOR A STORAGE DEVICE - A storage device is described that detects a data error and then notifies a distributed file system, for example, of such error. A data recovery can then be initiated in many ways, one way by the storage device. | 2014-09-18 |
20140281703 | Local Repair Signature Handling for Repairable Memories - A method is disclosed for independent repair signature load into a repairable memory within a chip set of a design without halting operation of other repairable memories within the design. At initial power up, the repair signature is received from nonvolatile memory and parallelly stored within a memory repair register and within a local memory repair shadow register. During intermediate power ups after an operational power savings scheme shut down, the method avoids serially re-loading the signature from the nonvolatile memory and loads the repair signature from the local memory repair shadow register. During local repair signature loading, the method disables the chip select for the memory to prevent memory operations until the repair signature is fully loaded. | 2014-09-18 |
20140281704 | DEPLOYING PARALLEL DATA INTEGRATION APPLICATIONS TO DISTRIBUTED COMPUTING ENVIRONMENTS - System, method, and computer program product to process parallel computing tasks on a distributed computing system, by computing an execution plan for a parallel computing job to be executed on the distributed computing system, the distributed computing system comprising a plurality of compute nodes, generating, based on the execution plan, an ordered set of tasks, the ordered set of tasks comprising: (i) configuration tasks, and (ii) execution tasks for executing the parallel computing job on the distributed computing system, and launching a distributed computing application to assign the tasks of the ordered set of tasks to the plurality of compute nodes to execute the parallel computing job on the distributed computing system. | 2014-09-18 |