38th week of 2014 patent applcation highlights part 141 |
Patent application number | Title | Published |
20140273287 | METHOD OF MANUFACTURING THE SAME - A method of manufacturing magnetoresistive random access memory (MRAM) device includes foaming first and second patterns on a substrate in an alternating and repeating arrangement, forming a first capping layer on top surfaces of the first and second patterns, and removing first portions of the first capping layer and a portion of the second patterns thereunder to form first openings exposing the substrate. The method further includes forming source lines filling lower portions of the first openings, respectively, forming second capping layer patterns filling upper portions of the first openings, respectively, and removing second portions of the first capping layer and a portion of the second patterns thereunder to form second openings exposing the substrate. Then, contact plugs and pad layers are integrally formed and sequentially stacked on the substrate to fill the second openings. | 2014-09-18 |
20140273288 | METHOD OF FORMING A MAGNETIC TUNNEL JUNCTION DEVICE - A method of forming a magnetic tunnel junction device is disclosed that includes forming a trench in a substrate, the trench including a plurality of sidewalls and a bottom wall. The method includes depositing a first conductive material within the trench proximate to one of the sidewalls and depositing a second conductive material within the trench. The method further includes depositing a material to form a magnetic tunnel junction (MTJ) structure within the trench. The MTJ structure includes a fixed magnetic layer having a magnetic field with a fixed magnetic orientation, a tunnel junction layer, and a free magnetic layer having a magnetic field with a configurable magnetic orientation. The method further includes selectively removing a portion of the MTJ structure to create an opening in the MTJ structure. | 2014-09-18 |
20140273289 | METHOD OF DETACHING SEALING MEMBER OF LIGHT EMITTING DEVICE - A method of detaching a sealing member of a light emitting device which has a substrate, a light emitting element mounted on the substrate and a sealing member that seals the light emitting element, wherein a release layer and/or an air layer is/are provided between the substrate and the sealing member; and the sealing member is detached from the substrate at the release layer and/or the air layer. | 2014-09-18 |
20140273290 | SOLVENT ANNEAL PROCESSING FOR DIRECTED-SELF ASSEMBLY APPLICATIONS - A method and apparatus for solvent annealing a layered substrate including a layer of a block copolymer are provided. The method includes (a) introducing an annealing gas into a processing chamber; (b) maintaining the annealing gas in the processing chamber for a first time period; (c) removing the annealing gas from the processing chamber; and (d) repeating steps (a)-(c) a plurality of times in order induce the block copolymer to undergo cyclic self-assembly. The apparatus includes a processing chamber comprising a process space; a substrate support in the process space; an annealing gas supply and a purge gas supply, both in fluid communication with the process space; a heating element positioned within the processing chamber; an exhaust port in the processing chamber; and a sequencing device programmed to control the annealing gas supply, the heating element, the isolation valve of the exhaust port, and the purge gas supply. | 2014-09-18 |
20140273291 | Wafer Strength by Control of Uniformity of Edge Bulk Micro Defects - A method is provided for qualifying a semiconductor wafer for subsequent processing, such as thermal processing. A plurality of locations are defined about a periphery of the semiconductor wafer, and one or more properties, such as oxygen concentration and a density of bulk micro defects present, are measured at each of the plurality of locations. A statistical profile associated with the periphery of the semiconductor wafer is determined based on the one or more properties measured at the plurality of locations. The semiconductor wafer is subsequently thermally treated when the statistical profile falls within a predetermined range. The semiconductor wafer is rejected from subsequent processing when the statistical profile deviates from the predetermined range. As such, wafers prone to distortion, warpage, and breakage are rejected from subsequent thermal processing. | 2014-09-18 |
20140273292 | METHODS OF FORMING SILICON NITRIDE SPACERS - Embodiments of methods of forming silicon nitride spacers are provided herein. In some embodiments, a method of forming silicon nitride spacers atop a substrate includes: depositing a silicon nitride layer atop an exposed silicon containing layer and an at least partially formed gate stack disposed atop a substrate; modifying a portion of the silicon nitride layer by exposing the silicon nitride layer to a hydrogen or helium containing plasma that is substantially free of fluorine; and removing the modified portion of the silicon nitride layer by performing a wet cleaning process to form the silicon nitride spacers, wherein the wet cleaning process removes the modified portion of the silicon nitride layer selectively to the silicon containing layer. | 2014-09-18 |
20140273293 | Portable Wireless Sensor - The present disclosure provides an apparatus for fabricating a semiconductor device. The apparatus includes a portable device. The portable device includes first and second sensors that respectively measure first and second fabrication process parameters. The first fabrication process parameter is different from the second fabrication process parameter. The portable device also includes a wireless transceiver that is coupled to the first and second sensors. The wireless transceiver receives the first and second fabrication process parameters and transmits wireless signals containing the first and second fabrication process parameters. | 2014-09-18 |
20140273294 | System and Method for Forming a Semiconductor Device - A system and method for forming a semiconductor device is provided. The system may measure characteristics of the substrate to determine an amount of induced stress on the substrate. The measured characteristics may include warpage, reflectivity and/or crack information about the substrate. The induced stress may be determined, at least in part, based on the measured characteristics. The system may compare the induced stress on the substrate to a maximum intrinsic strength of the substrate and adjust an anneal for the substrate based on the comparison. The adjustment may reduce or limit breakage of the substrate during the anneal. The system may control at least one of a peak anneal temperature and a maximum anneal duration for an anneal unit, which may perform an anneal on the substrate. The measurements and control may be performed ex-situ or in-situ with the anneal. | 2014-09-18 |
20140273295 | Optical Control Of Multi-Stage Thin Film Solar Cell Production - Embodiments include methods of depositing and controlling the deposition of a film in multiple stages. The disclosed deposition and deposition control methods include the optical monitoring of a deposition matrix to determine a time when at least one transition point occurs. In certain embodiments, the transition point or transition points are a stoichiometry point. Methods may also include controlling the length of time in which material is deposited during a deposition stage or controlling the amount of the first, second or subsequent materials deposited during any deposition stage in response to a determination of the time when a selected transition point occurs. | 2014-09-18 |
20140273296 | METRIC FOR RECOGNIZING CORRECT LIBRARY SPECTRUM - A method of controlling polishing of a substrate is described. A controller stores a library having a plurality of reference spectra. The controller polishes a substrate and measures a sequence of spectra of light from the substrate during polishing. For each measured spectrum of the sequence of spectra, the controller finds a best matching reference spectrum from the plurality of reference spectra and generates a sequence of best matching reference spectra. The controller uses a cell counting technique for finding the best matching reference spectrum. The controller determines at least one of a polishing endpoint or an adjustment for a polishing rate based on the sequence of best matching reference spectra. | 2014-09-18 |
20140273297 | EMBEDDED TEST STRUCTURE FOR TRIMMING PROCESS CONTROL - In some embodiments, a method of controlling a photoresist trimming process in a semiconductor manufacturing process may include forming a photoresist layer atop a first surface of a substrate, wherein the photoresist layer comprises a lower layer having a first pattern to be etched into the first surface of the substrate, and an upper layer having a second pattern that is not etched into the first surface of the substrate; trimming the photoresist layer in a direction parallel to the first surface of the substrate; measuring a trim rate of the second pattern using an optical measuring tool during the trimming process; and correlating the trim rate of the second pattern to a trim rate of the first pattern to control the trim rate of the first pattern during the trimming process. | 2014-09-18 |
20140273298 | Techniques for Quantifying Fin-Thickness Variation in FINFET Technology - Techniques for quantifying ΔDfin in FINFET technology are provided. In one aspect, a method for quantifying ΔDfin between a pair of long channel FINFET devices includes the steps of: (a) obtaining Vth values for each of the long channel FINFET devices in the pair; (b) determining a ΔVth for the pair of long channel FINFET devices; and (c) using the ΔVth to determine the ΔDfin between the pair of long channel FINFET devices, wherein the ΔVth is a function of a difference in a Qbody and a gate capacitance between the pair of long channel FINFET devices, and wherein the Qbody is a function of Dfin and Nch for each of the long channel FINFET devices in the pair, and as such the ΔVth is proportional to the ΔDfin between the pair of long channel FINFET devices. | 2014-09-18 |
20140273299 | SYSTEMS AND METHODS FOR FABRICATING SEMICONDUCTOR DEVICE STRUCTURES USING DIFFERENT METROLOGY TOOLS - Methods and systems are provided for fabricating and measuring physical features of a semiconductor device structure. An exemplary method of fabricating a semiconductor device structure involves obtaining a first measurement of a first attribute of the semiconductor device structure from a first metrology tool, obtaining process information pertaining to fabrication of one or more features of the semiconductor device structure by a first processing tool, and determining an adjusted measurement for the first attribute based at least in part on the first measurement in a manner that is influenced by the process information. | 2014-09-18 |
20140273300 | Method for Forming ReRAM Chips Operating at Low Operating Temperatures - Forming a resistive memory structure at a temperature well above the operating temperature can reduce the forming voltage and create a defect distribution with higher stability and lower programming voltages. The forming temperature can be up to 200 C above the operating temperature. The memory chip can include an embedded heater in the chip package, allowing for a chip forming process after packaging. | 2014-09-18 |
20140273301 | MOVEABLE AND ADJUSTABLE GAS INJECTORS FOR AN ETCHING CHAMBER - An apparatus for increasing the uniformity in a critical dimension of chemical vapor deposition and etching during substrate processing, comprising a plurality of gas injectors for admitting a processing gas into an etching chamber. Each gas injector of the plurality of gas injectors is disposed along a track within the etching chamber and moveable along the track. Further, each gas injector is coupled with a throttling valve or nozzle to permit adjustment of processing gas flow rate. A method for increasing the uniformity in a critical dimension of chemical vapor deposition and etching during substrate processing includes performing a chemical deposition or etch using the plurality of moveable and adjustable gas injectors and measuring the critical dimension uniformity. Adjustments to the location of at least one gas injector or the processing gas flow rate to at least one gas injector are made to increase critical dimension uniformity. | 2014-09-18 |
20140273302 | Fine Temperature Controllable Wafer Heating System - Disclosed are a method and a system for processing wafers in fabricating a semiconductor device where disposing chemicals and wafer heating are needed for chemical reaction. A wafer is placed above a wafer heater such that a second surface faces the wafer heater, and heated from the second surface. A chemical layer is formed on an opposing first surface. The wafer heater is sized and configured to be capable of heating the entire second surface, and adapted to produce a locally differential temperature profile if needed. During heating, an actual temperature profile on the wafer may be monitored and transmitted to a computing system, which may generate a target temperature profile and control the wafer heater to adjust local temperatures on the wafer according to the target temperature profile. A supplemental heater for heating the chemicals may be used for finer control of the wafer temperature. | 2014-09-18 |
20140273303 | System and Method for an Etch Process with Silicon Concentration Control - The present disclosure provides one embodiment of an etch system. The etch system includes a tank designed to hold an etch solution for etching; a silicon monitor configured to measure silicon concentration of the etch solution; a drain module coupled to the tank and being operable to drain the etch solution; and a supply module being operable to fill in the tank with a fresh etch solution. | 2014-09-18 |
20140273304 | METHODS FOR REDUCING ETCH NONUNIFORMITY IN THE PRESENCE OF A WEAK MAGNETIC FIELD IN AN INDUCTIVELY COUPLED PLASMA REACTOR - Methods and apparatus for plasma-enhanced substrate processing are provided herein. In some embodiments, a method is provided for processing a substrate in a process chamber having a plurality of electromagnets disposed about the process chamber to form a magnetic field within the process chamber at least at a substrate level. In some embodiments, the method includes determining a first direction of an external magnetic field present within the process chamber while providing no current to the plurality of electromagnets; providing a range of currents to the plurality of electromagnets to create a magnetic field within the process chamber having a second direction opposing the first direction; determining a desired magnitude in the second direction of the magnetic field over the range of currents; and processing a substrate in the process chamber using a plasma while statically providing the magnetic field at the desired magnitude. | 2014-09-18 |
20140273305 | METHOD OF CURING SOLAR CELLS TO REDUCE LAMINATION INDUCED EFFICIENCY LOSS - A method for encapsulating solar cells includes a curing step that renders CIGS or other types of solar cell absorber layers resistant to degradation by high-temperature lamination processes. The curing process takes place after IV test and prior to the lamination of an encapsulant film. The curing step is carried out in conjunction with a light soaking step that takes place prior to the IV test. The curing process takes place for a time that may range from 10 minutes to two days and at a high relative humidity, RH. Relative humidities of 20-90% are used and have been effective in passivating selenium vacancy defects associated with the absorber layers. The cured absorber layers are resistant to degradation and produce a solar cell with a high solar cell efficiency. | 2014-09-18 |
20140273306 | METHODS FOR FABRICATING INTEGRATED CIRCUITS INCLUDING MULTI-PATTERNING OF MASKS FOR EXTREME ULTRAVIOLET LITHOGRAPHY - Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes patterning a first photoresist layer overlying a mask blank that is mounted on a first chuck to form a first patterned photoresist layer. The mask blank is selectively etched using the first patterned photoresist layer to form a first patterned mask. The first patterned mask is mounted on a second chuck and a non-flatness compensation is determined. The first patterned mask is mounted on the first chuck and a second photoresist layer is patterned overlying the first patterned mask to form a second patterned photoresist layer. The second patterned photoresist layer includes a device pattern that has been adjusted using the non-flatness compensation. The first patterned mask is selectively etched using the second patterned photoresist layer to form a second patterned mask. | 2014-09-18 |
20140273307 | Method and Apparatus for Semiconductor Testing at Low Temperature - A method for testing a plurality of semiconductor devices arranged on a strip may include forming an array of semiconductor devices on a frame, wherein contact pads of adjacent semiconductor devices are shorted, partially cutting the strip to electrically isolate individual semiconductor devices in the array, placing the strip on an adhesive tape configured to withstand low temperatures (e.g., below −20° C. or below −50° C.), arranging the strip and tape on a test chuck, exposing the test chuck, strip, and tape to temperatures below an ambient temperature and testing the plurality of semiconductor devices while exposed to a low temperature. In one embodiment a KAPTON™ film is used as the adhesive tape. | 2014-09-18 |
20140273308 | METHOD OF MEASURING SURFACE PROPERTIES OF POLISHING PAD - The present invention relates to a method of measuring surface properties of a polishing pad which measures surface properties such as surface topography or surface condition of a polishing pad used for polishing a substrate such as a semiconductor wafer. The method of measuring surface properties of a polishing pad includes applying a laser beam to the polishing pad, detecting scattered light that is reflected and scattered by the polishing pad with a photodetector and performing an optical Fourier transform on the detected scattered light to produce an intensity distribution corresponding to a spatial wavelength spectrum based on surface topography of the polishing pad, and calculating a numerical value representing surface properties of the polishing pad based on the intensity distribution corresponding to two different prescribed spatial wavelength ranges. | 2014-09-18 |
20140273309 | Controlling Radical Lifetimes in a Remote Plasma Chamber - Remote-plasma treatments of surfaces, for example in semiconductor manufacture, can be improved by preferentially exposing the surface to only a selected subset of the plasma species generated by the plasma source. The probability that a selected species reaches the surface, or that an unselected species is quenched or otherwise converted or diverted before reaching the surface, can be manipulated by introducing additional gases with selected properties either at the plasma source or in the process chamber, varying chamber pressure or flow rate to increase or decrease collisions, or changing the dimensions or geometry of the injection ports, conduits and other passages traversed by the species. Some example processes treat surfaces preferentially with relatively low-energy radicals, vary the concentration of radicals at the surface in real time, or clean and passivate in the same unit process. | 2014-09-18 |
20140273310 | MONITORING PATTERN FOR DEVICES - Reticle and methods for forming a device or reticle are presented. A reticle is provided with a device pattern and a first monitoring pattern. The first monitoring pattern includes a plurality of first test cells having a first test cell area and a first test pattern. The first test cells have different first pitch ratios to an anchor pitch and the first test pattern fills the first test cell area of a first test cell. A wafer with a resist layer is exposed with a lithographic system using the reticle. The resist is developed to form a patterned resist layer on the wafer and the wafer is processed using the patterned resist layer. | 2014-09-18 |
20140273311 | Optical Absorbers - Optical absorbers and methods are disclosed. The methods comprise depositing a plurality of precursor layers comprising one or more of Cu, Ga, and In on a substrate, and heating the layers in a chalcogenizing atmosphere. The plurality of precursor layers can be one or more sets of layers comprising at least two layers, wherein each layer in each set of layers comprises one or more of Cu, Ga, and In exhibiting a single phase. The layers can be deposited using two or three targets selected from Ag and In containing less than 21% In by weight, Cu and Ga where the Cu and Ga target comprises less than 45% Ga by weight, Cu(In,Ga), wherein the Cu(In,Ga) target has an atomic ratio of Cu to (In+Ga) greater than 2 and an atomic ratio of Ga to (Ga+In) greater than 0.5, elemental In, elemental Cu, and In | 2014-09-18 |
20140273312 | PIN HOLE EVALUATION METHOD OF DIELECTRIC FILMS FOR METAL OXIDE SEMICONDUCTOR TFT - The present invention generally relates to methods measuring pinhole determination. In one aspect, a method of measuring pinholes in a stack, such as a TFT stack, is provided. The method can include forming an active layer on a deposition surface of a substrate, forming a dielectric layer over the active layer, delivering an etchant to at least the dielectric layer, to etch both the dielectric layer and any pinholes formed therein and optically measuring the pinhole density of the etched dielectric layer using the active layer. | 2014-09-18 |
20140273313 | METHOD AND APPARATUS PROVIDING INLINE PHOTOLUMINESCENCE ANALYSIS OF A PHOTOVOLTAIC DEVICE - A method and apparatus are disclosed which use a photoluminescent light intensity signature to characterize a processed photovoltaic substrate. | 2014-09-18 |
20140273314 | High Productivity Combinatorial Workflow to Screen and Design Chalcogenide Materials as Non Volatile Memory Current Selector - Combinatorial workflow is provided for evaluating materials and processes for current selector devices in a cross point memory array. Blanket layers, metal-insulator-metal devices, and compete memory structures are combinatorially fabricated on multiple regions of a substrate, with each region having a different material and process condition for the current selector devices. The current selector devices are then characterized, and the data are compared to obtain the optimum materials and processes. | 2014-09-18 |
20140273315 | METHODS AND OPHTHALMIC DEVICES WITH ORGANIC SEMICONDUCTOR LAYER - This invention discloses methods and apparatus to form organic semiconductor transistors upon three-dimensionally formed insert devices. In some embodiments, the present invention includes incorporating the three-dimensional surfaces with organic semiconductor-based thin film transistors, electrical interconnects, and energization elements into an insert for incorporation into ophthalmic lenses. In some embodiments, the formed insert may be directly used as an ophthalmic device or incorporated into an ophthalmic device. | 2014-09-18 |
20140273316 | METHODS AND OPHTHALMIC DEVICES WITH THIN FILM TRANSISTORS - This invention discloses methods and apparatus to form organic semiconductor transistors upon three-dimensionally formed insert devices. In some embodiments, the present invention includes incorporating the three-dimensional surfaces with organic semiconductor-based thin film transistors, electrical interconnects, and energization elements into an insert for incorporation into ophthalmic lenses. In some embodiments, the formed insert may be directly used as an ophthalmic device or incorporated into an ophthalmic device. | 2014-09-18 |
20140273317 | LIGHT-EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - A highly reliable light-emitting device and a manufacturing method thereof are provided. A light-emitting element and a terminal electrode are formed over an element formation substrate; a first substrate having an opening is formed over the light-emitting element and the terminal electrode with a bonding layer provided therebetween; an embedded layer is formed in the opening; a transfer substrate is formed over the first substrate and the embedded layer; the element formation substrate is separated; a second substrate is formed under the light-emitting element and the terminal electrode; and the transfer substrate and the embedded layer are removed. In addition, an anisotropic conductive connection layer is formed in the opening, and an electrode is formed over the anisotropic conductive connection layer. The terminal electrode and the electrode are electrically connected to each other through the anisotropic conductive connection layer. | 2014-09-18 |
20140273318 | METHOD OF FORMING METALLIC BONDING LAYER AND METHOD OF MANUFACTURING SEMICONDUCTOR LIGHT EMITTING DEVICE THEREWITH - A method of forming a metal bonding layer includes forming a first bonding metal layer and a second bonding metal layer on surfaces of first and second bonding target objects, respectively. The second bonding target object is disposed on the first bonding target object to allow the first and second bonding metal layers to face each other. A eutectic metal bonding layer is formed through a reaction between the first and second bonding metal layers. At least one of the first and second bonding metal layers includes a reaction delaying layer formed of a metal for delaying the reaction between the first and second bonding metal layers. | 2014-09-18 |
20140273319 | FULL-COLOR ACTIVE MATRIX ORGANIC LIGHT EMITTING DISPLAY WITH HYBRID - A full-color AM OLED includes a transparent substrate, a color filter positioned on an upper surface of the substrate, and a metal oxide thin film transistor backpanel positioned in overlying relationship on the color filter and defining an array of pixels. An array of OLEDs is formed on the backpanel and positioned to emit light downwardly through the backpanel, the color filter, and the substrate in a full-color display. Light emitted by each OLED includes a first emission band with wavelengths extending across the range of two of the primary colors and a second emission band with wavelengths extending across the range of the remaining primary color. The color filter includes for each pixel, two zones separating the first emission band into two separate primary colors and a third zone passing the second emission band. | 2014-09-18 |
20140273320 | Semiconductor Light-Emitting Device with a Protection Layer and the Manufacturing Method Thereof - The present application discloses a method for making a light-emitting device comprising steps of: providing a light-emitting unit comprising an epitaxial structure; providing a protection layer; connecting the light-emitting unit with the protection layer by a second connecting layer; providing a heat dispersion substrate; and connecting the heat dispersion substrate with the protection layer by a first connecting layer. | 2014-09-18 |
20140273321 | Light-Emitting Element, Light-Emitting Module, Light-Emitting Panel, and Light-Emitting Device - A light-emitting element, a light-emitting module, a light-emitting panel, or a light-emitting device in which loss due to electrical resistance is reduced is provided. The present invention focuses on a surface of an electrode containing a metal and on a layer containing a light-emitting organic compound. The layer containing a light-emitting organic compound is provided between one electrode including a first metal, whose surface is provided with a conductive inclusion, and the other electrode. | 2014-09-18 |
20140273322 | METHOD OF MAKING DIODE HAVING REFLECTIVE LAYER - A method of forming a light emitting diode includes forming a transparent substrate and a GaN buffer layer on the transparent substrate. An n-GaN layer is formed on the buffer layer. An active layer is formed on the n-GaN layer. A p-GaN layer is formed on the active layer. A p-electrode is formed on the p-GaN layer and an n-electrode is formed on the n-GaN layer. A reflective layer is formed on a second side of the transparent substrate. A scribe line is formed on the substrate for separating the diodes on the substrate. Also, a cladding layer of AlGaN is between the p-GaN layer and the active layer. | 2014-09-18 |
20140273323 | METHOD OF MANUFACTURE OF ADVANCED HETEROJUNCTION TRANSISTOR AND TRANSISTOR LASER - Methods of manufacture of advanced heterojunction transistors and transistor lasers, and their related structures, are described herein. Other embodiments are also disclosed herein. | 2014-09-18 |
20140273324 | METHODS FOR MANUFACTURING CHEMICAL SENSORS WITH EXTENDED SENSOR SURFACES - In one implementation, a method for manufacturing a chemical sensor is described. The method includes forming a chemically-sensitive field effect transistor including a floating gate conductor having an upper surface. A dielectric material is formed defining an opening extending to the upper surface of the floating gate conductor. A conductive material is formed within the opening and on an upper surface of the dielectric material. A fill material is formed on the conductive material. The fill material is used as a protect mask to remove the conductive material on the upper surface of the dielectric material. The fill material is then removed to expose remaining conductive material on a sidewall of the opening. | 2014-09-18 |
20140273325 | THERMOELECTRIC CONVERSION MODULE AND PRODUCTION METHOD THEREFOR - A production method for a thermoelectric conversion module having a thermoelectric conversion element and an electrode, which are metallurgically bonded together via a porous metal layer. The porous metal layer is made of nickel or silver and has a density ratio of 50 to 90%. | 2014-09-18 |
20140273326 | METHODS FOR IMPROVING SOLAR CELL LIFETIME AND EFFICIENCY - Methods for protecting a texturized region and a lightly doped diffusion region of a solar cell to improve solar cell lifetime and efficiency are disclosed. In an embodiment, an example method includes providing a solar cell having a front side which faces the sun during normal operation and a back side opposite the front side, a silicon substrate and where the silicon substrate includes a texturized region and a lightly doped diffusion region. The method includes placing the solar cell on a receiving medium with the front side of the solar cell placed on an upper surface of the receiving medium, where the upper surface of the receiving medium prevents damage to the to the lightly doped diffusion region and damage to the texturized region on the front side of the solar cell during a contact printing process or transferring. In an embodiment, the lightly doped diffusion region has a doping concentration below 1×10 | 2014-09-18 |
20140273327 | SOLID STATE IMAGING DEVICE, METHOD OF PRODUCING SOLID STATE IMAGING DEVICE, AND ELECTRONIC APPARATUS - A solid state imaging device includes: a substrate; a photoelectric conversion unit that is formed on the substrate to generate and accumulate signal charges according to light quantity of incident light; a vertical transmission gate electrode that is formed to be embedded in a groove portion formed in a depth direction from one side face of the substrate according to a depth of the photoelectric conversion unit; and an overflow path that is formed on a bottom portion of the transmission gate to overflow the signal charges accumulated in the photoelectric conversion unit. | 2014-09-18 |
20140273328 | SEMICONDUCTOR ELEMENT PRODUCING METHOD - A semiconductor device is fabricated by performing the steps of: (a) implanting dopant ions into a semiconductor base member, which is made of single-crystal Si, to define at least one of an n-type region and a p-type region in the semiconductor base member; (b) conducting a first heat treatment on the semiconductor base member, in which the n-type or p-type region has been defined, at a temperature rise/fall rate of 40° C./sec or more and with the highest temperature to reach set within the range of 1000° C. to 1200° C.; and (c) conducting a second heat treatment on the semiconductor base member, which has gone through the first heat treatment, at a lower temperature rise/fall rate than in the first heat treatment. | 2014-09-18 |
20140273329 | SOLAR CELL LASER SCRIBING METHODS - A multi-step scribing operation is provided for forming scribe lines in solar panels to form multiple interconnected cells on a solar panel substrate. The multi-step scribing operation includes at least one step utilizing a nanosecond laser cutting operation. The nanosecond laser cutting operation is followed by a mechanical cutting operation or a subsequent nanosecond laser cutting operation. In some embodiments, the multi-step scribing operation produces a two-tiered scribe line profile and the method prevents local shunting and minimizes active area loss on the solar panel. | 2014-09-18 |
20140273330 | METHOD OF FORMING SINGLE SIDE TEXTURED SEMICONDUCTOR WORKPIECES - Methods of creating a workpiece having a smooth side and a textured side are disclosed. In some embodiments, a first side of a workpiece is doped, using ion implantation or diffusion, to create a doped layer. This doped layer of the first side may be more resistant to chemical treatment than the second side of the workpiece. This allows the second side of the workpiece to be textured without capping or otherwise protecting the doped first side, even though the doped layer of the first side physically contacts the chemical treatment. In some embodiments, a p-type dopant is used to create the doped layer. In some embodiments, the workpiece is processed to form a solar cell. | 2014-09-18 |
20140273331 | METHODS FOR WET CHEMISTRY POLISHING FOR IMPROVED LOW VISCOSITY PRINTING IN SOLAR CELL FABRICATION - A method of fabricating a solar cell is disclosed. The method includes forming a polished surface on a silicon substrate and forming a first flowable matrix in an interdigitated pattern on the polished surface, where the polished surface allows the first flowable matrix to form an interdigitated pattern comprising features of uniform thickness and width. In an embodiment, the method includes forming the silicon substrate using a method such as, but not limited to, of diamond wire or slurry wafering processes. In another embodiment, the method includes forming the polished surface on the silicon substrate using a chemical etchant such as, but not limited to, sulfuric acid (H | 2014-09-18 |
20140273332 | METHOD FOR PRODUCING PHOTOVOLTAIC DEVICE ISOLATED BY POROUS SILICON - Photovoltaic devices are produced using a minimally modified standard process flow by forming lateral P-I-N light-sensitive diodes on silicon islands that are isolated laterally by trenches performed by RIE, and from an underlying support substrate by porous silicon regions. P+ and N+ doped regions are formed in a P− epitaxial layer, trenches are etched through the epitaxial layer into a P+ substrate, a protective layer (e.g., SiN) is formed on the trench walls, and then porous silicon is formed (e.g., using HF solution) in the trenches that grows laterally through the P+ substrate and merges under the island. The method is either utilized to form low-cost embedded photovoltaic arrays on CMOS IC devices, or the devices are separated from the P+ substrate by etching through the porous silicon to produce low-cost, high voltage solar arrays for solar energy sources, e.g., solar concentrators. | 2014-09-18 |
20140273333 | Methods for fabricating ZnOSe alloys - Methods of forming absorber layers in a TFPV device are provided. Methods are described to provide the formation of metal oxide films and heating the metal oxide films in the presence of a chalcogen to form a metal-oxygen-chalcogen alloy. Methods are described to provide the formation of metal oxide films, forming a layer of elemental chalcogen on the metal oxide film, and heating the stack to form a metal-oxygen-chalcogen alloy. In some embodiments, the metal oxide film includes zinc oxide and the chalcogen includes selenium. | 2014-09-18 |
20140273334 | METHOD OF MANUFACTURING A PHOTOVOLTAIC DEVICE - A method to improve CdTe-based photovoltaic device efficiency is disclosed, the method including steps for removing surface contaminants from a semiconductor absorber layer prior to the deposition or formation of a back contact layer on the semiconductor absorber layer, the surface contaminants removed using at least one of a dry etching process and a wet etching process. | 2014-09-18 |
20140273335 | METHOD AND APPARATUS FOR DEPOSITING COPPER-INDIUM-GALLIUM SELENIDE (CuInGaSe2-CIGS) THIN FILMS AND OTHER MATERIALS ON A SUBSTRATE - An apparatus for deposition of a plurality of elements onto a solar cell substrate comprising: a housing; a transporting apparatus to transport said substrate in and out of said housing; a first tubing apparatus to deliver powders of a first elements to said housing wherein said first tubing apparatus is comprised of a first feeder tube located outside of said housing and joined to said housing; a first source material tube located outside of said housing and joined to said feeder tube; a valves located inside of said first source material tube sufficient to block access between said first source material tube and said first feeder tube; a first heating tube located inside of said housing and connected to said first feeder tube; a second tubing apparatus to deliver powders of a second elements to said housing wherein said second tubing apparatus is comprised of a second feeder tube located outside of said housing and joined to said housing; a second source material tube located outside of said housing and joined to said second feeder tube; valves located inside of said second source material tube sufficient to block access between said second source material tube and said second feeder tube; a second heating tube located inside of said housing and connected to said second feeder tube; a loading station for loading said substrate onto said transporting apparatus; one or more thermal sources to heat said housing and said first heating tube and said second heating tube. | 2014-09-18 |
20140273336 | Method of Forming Cu(InxGa1-x)S2 and Cu(InxGa1-x)Se2 Nanoparticles - A method for synthesizing Cu(In | 2014-09-18 |
20140273337 | Cu2ZnSnS4 Nanoparticles - Materials and methods for preparing Cu | 2014-09-18 |
20140273338 | METHODS OF FORMING SOLAR CELLS AND SOLAR CELL MODULES - Embodiments of the present invention are directed to processes for making solar cells by simultaneously co-firing metal layers disposed both on a first and a second surface of a bifacial solar cell substrate. Embodiments of the invention may also provide a method forming a solar cell structure that utilize a reduced amount of a silver paste on a front surface of the solar cell substrate and a patterned aluminum metallization paste on a rear surface of the solar cell substrate to form a rear surface contact structure. Embodiments can be used to form passivated emitter and rear cells (PERC), passivated emitter rear locally diffused solar cells (PERL), passivated emitter, rear totally-diffused (PERT), “iPERC,” Crystalline Reduced-cost Aluminum Fire-Through (CRAFT), pCRAFT, nCRAFT or other high efficiency cell concepts. | 2014-09-18 |
20140273339 | Semiconductor Polymers - Disclosed is a semiconductor polymer having the following structure: | 2014-09-18 |
20140273340 | High Productivity Combinatorial Screening for Stable Metal Oxide TFTs - Methods for HPC techniques are applied to the processing of site-isolated regions (SIR) on a substrate to form at least a portion of a TFT device used in display applications. The processing may be applied to at least one of gate electrode deposition, gate electrode patterning, gate dielectric deposition, gate dielectric patterning, metal-based semiconductor material (e.g. IGZO) deposition, metal-based semiconductor material (e.g. IGZO) patterning, etch stop deposition, etch stop patterning, source/drain deposition, source/drain patterning, passivation deposition, or passivation patterning. The SIRs may be defined during the deposition process with uniform deposition within each SIR or the SIRs may be defined subsequent to the deposition of layers wherein the layers are deposited with a gradient in one or more properties across the substrate. | 2014-09-18 |
20140273341 | Methods for Forming Back-Channel-Etch Devices with Copper-Based Electrodes - Embodiments described herein provide methods for forming indium-gallium-zinc oxide (IGZO) devices. A substrate is provided. An IGZO layer is formed above the substrate. A copper-containing layer is formed above the IGZO layer. A wet etch process is performed on the copper-containing layer to form a source region and a drain region above the IGZO layer. The performing of the wet etch process on the copper-containing layer includes exposing the copper-containing layer to an etching solution including a peroxide compound and one of citric acid, formic acid, malonic acid, lactic acid, etidronic acid, phosphonic acid, or a combination thereof. | 2014-09-18 |
20140273342 | VTH CONTROL METHOD OF MULTIPLE ACTIVE LAYER METAL OXIDE SEMICONDUCTOR TFT - The present invention generally relates to TFTs and methods for fabricating TFTs. When multiple layers are used for the semiconductor material in a TFT, a negative Vth shift may result. By exposing the semiconductor layer to an oxygen containing plasma and/or forming an etch stop layer thereover, the negative Vth shift may be negated. | 2014-09-18 |
20140273343 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - An object is to manufacture a semiconductor device including an oxide semiconductor at low cost with high productivity in such a manner that a photolithography process is simplified by reducing the number of light-exposure masks. In a method for manufacturing a semiconductor device including a channel-etched inverted-staggered thin film transistor, an oxide semiconductor film and a conductive film are etched using a mask layer formed with the use of a multi-tone mask which is a light-exposure mask through which light is transmitted so as to have a plurality of intensities. In etching steps, a first etching step is performed by dry etching in which an etching gas is used, and a second etching step is performed by wet etching in which an etchant is used. | 2014-09-18 |
20140273344 | METHOD FOR FABRICATING STACK DIE PACKAGE - In one embodiment, a method can include coupling a gate and a source of a first die to a lead frame. The first die can include the gate and the source that are located on a first surface of the first die and a drain that is located on a second surface of the first die that is opposite the first surface. In addition, the method can include coupling a source of a second die to the drain of the first die. The second die can include a gate and a drain that are located on a first surface of the second die and the source that is located on a second surface of the second die that is opposite the first surface. | 2014-09-18 |
20140273345 | METHODS FOR BONDING A HERMETIC MODULE TO AN ELECTRODE ARRAY - A method for bonding a hermetic module to an electrode array including the steps of: providing the electrode array having a flexible substrate with a top surface and a bottom surface and including a plurality of pads in the top surface of the substrate; attaching the hermetic module to the bottom surface of the electrode array, the hermetic module having a plurality of bond-pads wherein each bond-pad is adjacent to the bottom surface of the electrode array and aligns with a respective pad; drill holes through each pad to the corresponding bond-pad; filling each hole with biocompatible conductive ink; forming a rivet on the biocompatible conductive ink over each pad; and overmolding the electrode array with a moisture barrier material. | 2014-09-18 |
20140273346 | MANUFACTURE OF FACE-DOWN MICROELECTRONIC PACKAGES - In a high volume method for manufacturing a microelectronic package, a spacer element and a first die, i.e., microelectronic element, can be attached face-down to a surface of a substrate, contacts on the first die facing a first through opening of the substrate. Then, a second die can be attached face-down atop the first die and the spacer element, contacts on the second die disposed beyond an edge of the first die and facing a second through opening in the substrate. Electrical connections can then be formed between each of the first and second dies and the substrate. The first and second dies can be transferred from positions of a single diced wafer which are selected to maximize compound speed bin yield of the microelectronic package. | 2014-09-18 |
20140273347 | Methods for Hybrid Wafer Bonding Integrated with CMOS Processing - Methods for forming an integrated device using CMOS processing with wafer bonding. In an embodiment, a method is disclosed that includes defining an integrated circuit function using a front-end substrate having one or more active devices and a back-end substrate having connections formed in metal layers in dielectric material, wherein the back-end substrate is free from active devices; manufacturing the front-end substrate in a first semiconductor process; more or less simultaneously, manufacturing the back-end substrate in a second semiconductor process; physically contacting bonding surfaces of the front-end substrate and the back-end substrate; and performing wafer bonding to form bonds between the front-end and back-end substrates to form an integrated circuit. Additional methods are disclosed. | 2014-09-18 |
20140273348 | PACKAGE-ON-PACKAGE ELECTRONIC DEVICES INCLUDING SEALING LAYERS AND RELATED METHODS OF FORMING THE SAME - A package-on-package (POP) electronic device may include first and second packaging substrates, a solder interconnection providing electrical and mechanical coupling between the first and second packaging substrates, and first and second sealing layers between the first and second packaging substrates. The first and second sealing layers may be respective first and second epoxy sealing layers. Moreover, the second epoxy sealing layer may include a solder flux agent, and the first epoxy sealing layer may have a lower concentration of the solder flux agent than the second epoxy sealing layer. | 2014-09-18 |
20140273349 | Power Module Having Stacked Flip-Chip and Method for Fabricating the Power Module - Provided are a power module having a stacked flip-chip and a method of fabricating the power module. The power module includes a lead frame; a control device part including a control device chip; a power device part including a power device chip and being electrically connected to the lead frame; and an interconnecting substrate of which the control and power device parts are respectively disposed at upper and lower portions, and each of the control and power device chips may be attached to one of the lead frame and the interconnecting substrate using a flip-chip bonding method. The method includes forming bumps on power and control device chips on a wafer level; separately sawing the power and control device chips into individual chips; adhering the power device chip onto a thermal substrate and the control device chip onto an interconnecting substrate; combining a lead frame, the thermal substrate, and the interconnecting substrate with one another in a multi-jig; and sealing the power and control device chips, and the control and power device chips may be attached to one of the lead frame and the interconnecting substrate using a flip-chip bonding method. | 2014-09-18 |
20140273350 | METHOD OF FABRICATING SEMICONDUCTOR MULTI-CHIP STACK PACKAGES - Provided is a method of fabricating a multi-chip stack package. The method includes preparing single-bodied lower chips having a single-bodied lower chip substrate having a first surface and a second surface disposed opposite the first surface, bonding unit package substrates onto the first surface of the single-bodied lower chip substrate to form a single-bodied substrate-chip bonding structure, separating the single-bodied substrate-chip bonding structure into a plurality of unit substrate-chip bonding structures, preparing single-bodied upper chips having a single-bodied upper chip substrate, bonding the plurality of unit substrate-chip bonding structures onto a first surface of the single-bodied upper chip substrate to form a single-bodied semiconductor chip stack structure, and separating the single-bodied semiconductor chip stack structure into a plurality of unit semiconductor chip stack structures. | 2014-09-18 |
20140273351 | METHOD OF ENCAPSULATING A MICRO-DEVICE BY ANODIC BONDING - A method for encapsulating at least one micro-device, comprising at least the following steps:
| 2014-09-18 |
20140273352 | SEMICONDUCTOR DEVICE - A method includes forming a packaged integrated circuit that includes forming a lead frame by separating an outer portion of the metal structure into a plurality of leads by stamping. The plurality of leads have sides with a first concavity. The lead frame is further formed by performing an etch on the sides of the plurality of leads to achieve a second concavity on the sides of leads. The second concavity is greater than the first concavity. A semiconductor die is attached to a center portion of the metal structure. Electrical attachments are made between the die and the leads. | 2014-09-18 |
20140273353 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - To improve reliability of a semiconductor device in which wire bonding using a wire made of copper is performed. A semiconductor device is configured so that one of end parts (wide width part) of a copper wire is joined via a bump on a pad (electrode pad) formed over a main surface (first main surface) of a semiconductor chip of the semiconductor device. The bump is made of gold, which is a metal material having a hardness lower than that of copper, and the width of the bump is narrower than the width of the wide width part of the wire. | 2014-09-18 |
20140273354 | FABRICATION OF 3D CHIP STACKS WITHOUT CARRIER PLATES - A method of fabricating a 3D chip stack uses an interposer and an electronic circuit substrate comprising a plurality of electronic circuits. The electrical contacts of the electronic circuit substrate are bonded and electrically coupled to bumps of the interposer. A molding compound is applied over the electronic circuits to form a molded structure. The molded structure is thinned to have a second molded thickness that is less than the first molded thickness, and the interposer is thinned to a second interposer thickness that is less than a first interposer thickness. | 2014-09-18 |
20140273355 | METHOD OF MAKING PACKAGE WITH INTERPOSER FRAME - A method of forming a package on package structure includes bonding a semiconductor die and an interposer frame to a substrate, and the interposer frame surrounds the semiconductor die. The semiconductor die is disposed in an opening of the interposer frame, and the interposer frame has a plurality of TSHs. The plurality of TSHs is aligned with a plurality of bumps on the substrate. The method also includes positioning a packaged die over the semiconductor die and the interposer frame. The packaged die has a plurality of bumps aligned with the plurality of TSHs of the interposer. The method further includes performing a reflow process to allow solder of the plurality of bumps of the substrate and the solder of the plurality of bumps of the packaged die to fill the plurality of TSHs. | 2014-09-18 |
20140273356 | SEMICONDUCTOR DEVICES AND METHODS OF MAKING THE SAME - In one embodiment, methods for making semiconductor devices are disclosed. | 2014-09-18 |
20140273357 | Vertical Power MOSFET And IGBT Fabrication Process With Two Fewer Photomasks - A process for fabrication of a power semiconductor device is disclosed in which a single photomask is used to define each of p-conductivity well regions and n-conductivity type source regions. In the process a single photomask is deposited on a layer of polysilicon on a wafer, the polysilicon layer is removed from first regions of the power semiconductor device where the p-conductivity well regions and the n-conductivity type source regions are to be formed, and both p-conductivity type and n-conductivity type dopants are introduced into the wafer through the first regions. | 2014-09-18 |
20140273358 | Circuit Structures, Memory Circuitry, And Methods - A circuit structure includes a substrate having an array region and a peripheral region. The substrate in the array and peripheral regions includes insulator material over first semiconductor material, conductive material over the insulator material, and second semiconductor material over the conductive material. The array region includes vertical circuit devices which include the second semiconductor material. The peripheral region includes horizontal circuit devices which include the second semiconductor material. The horizontal circuit devices in the peripheral region individually have a floating body which includes the second semiconductor material. The conductive material in the peripheral region is under and electrically coupled to the second semiconductor material of the floating bodies. Conductive straps in the array region are under the vertical circuit devices. The conductive straps include the conductive material and individually are electrically coupled to a plurality of the vertical circuit devices in the array region. Other implementations are disclosed. | 2014-09-18 |
20140273359 | SEMICONDUCTOR DEVICE HAVING BLOCKING PATTERN AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device is provided. The method includes forming a gate pattern which intersects a fin-type active pattern protruding upward from a device isolation layer. A first blocking pattern is formed on a portion of the fin-type active pattern, which does not overlap the gate pattern. Side surfaces of the portion of the fin-type active pattern are exposed. A semiconductor pattern is formed on the exposed side surfaces of the portion of the fin-type active pattern after the forming of the first blocking pattern. | 2014-09-18 |
20140273360 | FACETED SEMICONDUCTOR NANOWIRE - Selective epitaxy of a semiconductor material is performed on a semiconductor fin to form a semiconductor nanowire. Surfaces of the semiconductor nanowire include facets that are non-horizontal and non-vertical. A gate electrode can be formed over the semiconductor nanowire such that the faceted surfaces can be employed as channel surfaces. The epitaxially deposited portions of the faceted semiconductor nanowire can apply stress to the channels. Further, an additional semiconductor material may be added to form an outer shell of the faceted semiconductor nanowire prior to forming a gate electrode thereupon. The faceted surfaces of the semiconductor nanowire provide well-defined charge carrier transport properties, which can be advantageously employed to provide a semiconductor device with well-controlled device characteristics. | 2014-09-18 |
20140273361 | METHODS FOR THE FABRICATION OF GRAPHENE NANORIBBON ARRAYS USING BLOCK COPOLYMER LITHOGRAPHY - Methods of fabricating patterned substrates, including patterned graphene substrates, using etch masks formed from self-assembled block copolymer films are provided. Some embodiments of the methods are based on block copolymer (BCP) lithography in combination with graphoepitaxy. Some embodiments of the methods are based on BCP lithography techniques that utilize hybrid organic/inorganic etch masks derived from BCP templates. Also provided are field effect transistors incorporating graphene nanoribbon arrays as the conducting channel and methods for fabricating such transistors. | 2014-09-18 |
20140273362 | METHOD FOR MANUFACTURING THIN FILM TRANSISTOR AND ARRAY SUBSTRATE - The embodiments of the present invention provide a method for manufacturing a thin film transistor and a method for manufacturing an array substrate. The method for manufacturing the thin film transistor comprises: forming a gate electrode on a transparent substrate; forming a gate insulation layer; forming a transparent semiconductor film and patterning the transparent semiconductor film to form a semiconductor layer with photoresist being remained over the semiconductor layer; from a side of the transparent substrate opposite to the side on which the gate electrode is formed, exposing and developing the remained photoresist by using the gate electrode as a mask to form a channel position photoresist part corresponding to the gate electrode; forming a source/drain metal film and lifting off the channel position photoresist part and the source/drain metal film located over the channel position photoresist part; and patterning the remained source/drain metal film to form a source electrode and a drain electrode. The embodiments of the present invention are suitable to manufacture the product or device containing thin film transistors. | 2014-09-18 |
20140273363 | METHOD OF PATTERNING FEATURES OF A SEMICONDUCTOR DEVICE - The present disclosure provides a method of semiconductor device fabrication including forming a mandrel on a semiconductor substrate is provided. The method continues to include oxidizing a region the mandrel to form an oxidized region, wherein the oxidized region abuts a sidewall of the mandrel. The mandrel is then removed from the semiconductor substrate. After removing the mandrel, the oxidized region is used to pattern an underlying layer formed on the semiconductor substrate. | 2014-09-18 |
20140273364 | METHOD OF DEPOSITING THE METAL BARRIER LAYER COMPRISING SILICON DIOXIDE - The present invention discloses to a method of depositing the metal barrier layer comprising silicon dioxide. It is applied in the transistor device comprising a silicon substrate, a gate and a gate side wall. The method comprises the following steps: ions are implanted into the silicon substrate to form an active region in the said silicon substrate; a first dense silicon dioxide film is deposited; a second normal silicon dioxide film is deposited; the said transistor device is high temperature annealed. The present invention ensures that the implanted ion is not separated out of the substrate during the annealing. And it prevents the warping and fragment of the silicon surface. | 2014-09-18 |
20140273365 | METHODS OF FORMING CONTACTS TO SOURCE/DRAIN REGIONS OF FINFET DEVICES BY FORMING A REGION THAT INCLUDES A SCHOTTKY BARRIER LOWERING MATERIAL - Various methods of forming conductive contacts to the source/drain regions of FinFET devices that involves forming a region comprised of a Schottkky barrier lowering material are disclosed. The method disclosed herein includes forming at least one fin for an N-type FinFET device (or a P-type FinFET device) in a semiconducting substrate, performing at least one process operation to form a region in the at least one fin that contains a Schottky barrier lowering material, depositing a layer of a valence band metal (for an N-type device) or a conduction band metal (for a P-type device) on the region and forming a metal silicide region on the fin, wherein the metal silicide is comprised of the valance band metal (for the N-type device) or a conduction band metal (for the P-type device). | 2014-09-18 |
20140273366 | Semiconductor Devices and Methods of Manufacture Thereof - Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes providing a workpiece including an n-type field effect transistor (N-FET) region, a p-type FET (P-FET) region, and an insulating material disposed over the N-FET region and the P-FET region. The method includes patterning the insulating material to expose a portion of the N-FET region and a portion of the P-FET region, and forming an oxide layer over the exposed portion of the N-FET region and the exposed portion of the P-FET region. The oxide layer over the P-FET region is altered, and a metal layer is formed over a portion of the N-FET region and the P-FET region. The workpiece is annealed to form a metal-insulator-semiconductor (MIS) tunnel diode over the N-FET region and a silicide or germinide material over the P-FET region. | 2014-09-18 |
20140273367 | INTEGRATED CIRCUITS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH GATE ELECTRODE STRUCTURE PROTECTION - Integrated circuits and methods for fabricating integrated circuits are provided herein. In an embodiment of a method for fabricating integrated circuits, a P-type gate electrode structure and an N-type gate electrode structure are formed overlying a semiconductor substrate. The gate electrode structures each include a gate electrode that overlies a gate dielectric layer and a nitride cap that overlies the gate electrode. Conductivity determining ions are implanted into the semiconductor substrate using the P-type gate electrode structure and the N-type gate electrode structure as masks to form a source region and a drain region for the P-type gate electrode structure and the N-type gate electrode structure. The nitride cap remains overlying the N-type gate electrode structure during implantation of the conductivity determining ions into the semiconductor substrate to form the source region and the drain region for the N-type gate electrode structure. | 2014-09-18 |
20140273368 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES - A method of manufacturing a semiconductor device including the steps of providing a substrate having first type semiconductor regions and second type semiconductor regions, forming a conformal first epitaxy mask layer on the substrate, forming first type epitaxial layer in the substrate of the first type semiconductor regions, forming a conformal second epitaxy mask layer on the substrate, forming second type epitaxial layer in the substrate of the second type semiconductor regions, and removing the second epitaxy mask layer. | 2014-09-18 |
20140273369 | METHODS OF FORMING CONTACTS TO SOURCE/DRAIN REGIONS OF FINFET DEVICES - In one example, the method disclosed herein includes forming at least one fin for a FinFET device in a semiconducting substrate, performing at least one process operation to form a region in the at least one fin that contains a metal diffusion inhibiting material, depositing a layer of metal on the region in the at least one fin and forming a metal silicide region on the at least one fin. | 2014-09-18 |
20140273370 | TECHNIQUE FOR MANUFACTURING SEMICONDUCTOR DEVICES COMPRISING TRANSISTORS WITH DIFFERENT THRESHOLD VOLTAGES - When forming semiconductor devices including transistors with different threshold voltages, the different threshold voltages of transistors of the same conductivity type are substantially defined by performing different halo implantations. As the other implantations performed typically in the same manufacturing step, such as pre-amorphization, source and drain extension implantation and extra diffusion engineering implantations, may be identical for different threshold voltages, these implantations, in addition to a common halo base implantation, may be performed for all transistors of the same conductivity type in a common implantation sequence. Higher threshold voltages of specific transistors may be subsequently achieved by an additional low-dose halo implantation while the other transistors are covered by a resist mask. Thus, the amount of atoms of the implant species in the required resist masks is reduced so that removal of the resist masks is facilitated. Furthermore, the number of implantation steps is decreased compared to conventional manufacturing processes. | 2014-09-18 |
20140273371 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a transistor region and a resistor region; forming a shallow trench isolation (STI) on the resistor region of the substrate; forming a tank in the STI; and forming a resistor in the tank and on two sides of the top surface of the STI outside the tank. | 2014-09-18 |
20140273372 | METHOD OF MANUFACTURING NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a method includes forming a gate insulating layer structure covering first and second stacked layer structures, forming a first conductive layer on the gate insulating layer structure, forming a sacrifice layer on the first conductive layer, patterning the first conductive layer and the sacrifice layer with a line & space pattern, filling an insulating layer in spaces of the line & space pattern, the insulating layer having an etching characteristic different from the sacrifice layer, forming trenches in lines of the line & space pattern by removing the sacrifice layer selectively, the trenches exposing the first conductive layer between the first and second stacked layer structures, and forming a second conductive layer on the first conductive layer in the trenches. | 2014-09-18 |
20140273373 | METHOD OF MAKING A VERTICAL NAND DEVICE USING SEQUENTIAL ETCHING OF MULTILAYER STACKS - A method of making a vertical NAND device includes forming a lower portion of a memory stack over a substrate, forming a lower portion of memory openings in the lower portion of the memory stack, and at least partially filling the lower portion of the memory openings with a sacrificial material. The method also includes forming an upper portion of the memory stack over the lower portion of the memory stack and over the sacrificial material, forming an upper portion of the memory openings in the upper portion of the memory stack to expose the sacrificial material in the lower portion of the memory openings, removing the sacrificial material to connect the lower portion of the memory openings with a respective upper portion of the memory openings to form continuous memory openings, and forming a semiconductor channel in each continuous memory opening. | 2014-09-18 |
20140273374 | Vertical Doping and Capacitive Balancing for Power Semiconductor Devices - Vertical doping in power semiconductor devices and methods for making such dopant profiles are described. The methods include providing a semiconductor substrate, providing an epitaxial layer on the substrate, the epitaxial layer comprising a bottom portion containing a first conductivity type dopant in a substantially constant, first concentration throughout the bottom portion; and an upper portion containing a first conductivity type dopant having a second concentration lower than the first concentration; providing a trench in the epitaxial layer; forming a transistor structure in the trench; and forming a well region in the upper part of the epitaxial layer adjacent the trench, the well region containing a second conductivity type dopant that is opposite the first conductivity type. Other embodiments are described. | 2014-09-18 |
20140273375 | METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH SEMICONDUCTOR SUBSTRATE PROTECTION - Methods for fabricating an integrated circuit are provided herein. In an embodiment, a method for fabricating an integrated circuit includes forming a gate electrode structure overlying a semiconductor substrate. A first sacrificial oxide layer is formed overlying the semiconductor substrate and a first implant mask is patterned overlying the first sacrificial oxide layer to expose a portion of the first sacrificial oxide layer adjacent the gate electrode structure. Conductivity determining ions are implanted into the semiconductor substrate, through the first sacrificial oxide layer. The first implant mask and the first sacrificial oxide layer are removed after implanting the conductivity determining ions into the semiconductor substrate. | 2014-09-18 |
20140273376 | SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF - A semiconductor arrangement and method of formation are provided. A method of semiconductor formation includes using a single photoresist to mask off an area where low voltage devices are to be formed as well as gate structures of high voltage devices while performing high energy implants for the high voltage devices. Another method of semiconductor fabrication includes performing high energy implants for high voltage devices through a patterned photoresist where the photoresist is patterned prior to forming gate structures for high voltage devices and prior to forming gate structures for low voltage devices. After the high energy implants are performed, subsequent processing is performed to form high voltage devices and low voltage devices. High voltage device and low voltage devices are thus formed in a CMOS process without need for additional masks. | 2014-09-18 |
20140273377 | METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes forming a plurality of gate patterns including a top portion and a bottom portion on a substrate, forming a sacrificial layer contacting the bottom portions of the gate patterns, forming a first spacer on lateral surfaces of the top portions of the gate patterns after forming the sacrificial layer, removing the sacrificial layer after forming the first spacer, and forming a plurality of first recesses on lateral surfaces of the gate patterns after removing the sacrificial layer. | 2014-09-18 |
20140273378 | METHODS OF FABRICATING INTEGRATED CIRCUIT DEVICE WITH FIN TRANSISTORS HAVING DIFFERENT THRESHOLD VOLTAGES - Methods of fabricating integrated circuit device with fin transistors having different threshold voltages are provided. The methods may include forming first and second semiconductor fins including first and second semiconductor materials, respectively, and covering at least one among the first and second semiconductor fins with a mask. The methods may further include depositing a compound semiconductor layer including the first and second semiconductor materials directly onto sidewalls of the first and second semiconductor fins not covered by the mask and oxidizing the compound semiconductor layer. The oxidization process oxidizes the first semiconductor material within the compound semiconductor layer while driving the second semiconductor material within the compound semiconductor layer into the sidewalls of the first and second semiconductor fins not covered by the mask. | 2014-09-18 |
20140273379 | EPITAXIAL GROWTH OF DOPED FILM FOR SOURCE AND DRAIN REGIONS - Embodiments of mechanisms for epitaxially growing one or more doped silicon-containing materials to form source and drain regions of finFET devices are provided in this disclosure. The dopants in the one or more doped silicon-containing materials can be driven into the neighboring lightly-doped-drain (LDD) regions by thermal anneal to dope the regions. The epitaxially growing process uses a cyclical deposition/deposition/etch (CDDE) process. In each cycle of the CDDE process, a first and a second doped materials are formed and a following etch removes most of the second doped material. The first doped material has a higher dopant concentration than the second material and is protected from the etching process by the second doped material. The CDDE process enables forming a highly doped silicon-containing material. | 2014-09-18 |
20140273380 | FinFETs with Regrown Source/Drain and Methods for Forming the Same - A method includes etching a semiconductor substrate to form a recess in the semiconductor substrate, and reacting a surface layer of the semiconductor substrate to generate a reacted layer. The surface layer of the semiconductor substrate is in the recess. The reacted layer is then removed. An epitaxy is performed to grow a semiconductor material in the recess. | 2014-09-18 |
20140273381 | METHOD AND STRUCTURE FOR pFET JUNCTION PROFILE WITH SiGe CHANNEL - A semiconductor structure including a p-channel field effect transistor (pFET) device located on a surface of a silicon germanium (SiGe) channel is provided in which the junction profile of the source/drain region is abrupt. The abrupt source/drain junctions for pFET devices are provided by forming an N- or C-doped Si layer directly beneath a SiGe channel layer which is located above a Si substrate. A structure is provided in which the N- or C-doped Si layer (sandwiched between the SiGe channel layer and the Si substrate) has approximately the same diffusion rate for a p-type dopant as the overlying SiGe channel layer. Since the N- or C-doped Si layer and the overlying SiGe channel layer have substantially the same diffusivity for a p-type dopant and because the N- or C-doped Si layer retards diffusion of the p-type dopant into the underlying Si substrate, abrupt source/drain junctions can be formed. | 2014-09-18 |
20140273382 | METHODS OF FABRICATING SEMICONDUCTOR DEVICES - A substrate including an NMOS transistor region and a PMOS transistor region is prepared. A silicon-germanium layer is formed on the PMOS transistor region. Nitrogen atoms are injected in an upper portion of the silicon-germanium layer. A first gate dielectric layer is formed on the NMOS transistor region and the PMOS transistor region. The nitrogen atoms are injected into the upper portion of the silicon-germanium layer before forming the first gate dielectric layer. | 2014-09-18 |
20140273383 | MOSFETs with Channels on Nothing and Methods for Forming the Same - A method includes performing an epitaxy to grow a semiconductor layer, which includes a top portion over a semiconductor region. The semiconductor region is between two insulation regions that are in a substrate. The method further includes recessing the insulation regions to expose portions of sidewalls of the semiconductor region, and etching a portion of the semiconductor region, wherein the etched portion of the semiconductor region is under and contacting a bottom surface of the semiconductor layer, wherein the semiconductor layer is spaced apart from an underlying region by an air gap. A gate dielectric and a gate electrode are formed over the semiconductor layer. | 2014-09-18 |
20140273384 | POWER TRANSISTOR WITH INCREASED AVALANCHE CURRENT AND ENERGY RATING - A field-effect transistor involves a drain electrode, a drift region, a body region, a source region, a gate insulator layer, and a gate electrode. The drift region is disposed above the drain electrode. The body region extends down into the drift region from a first upper semiconductor surface. The source region is ladder-shaped and extends down in the body region from a second upper semiconductor surface. The first and second upper semiconductor surfaces are substantially planar and are not coplanar. A first portion of the body region is surrounded laterally by a second portion of the body region. The second portion of the body region and the drift region meet at a body-to-drift boundary. The body-to-drift boundary has a central portion that is non-planar. A gate insulator layer is disposed over the source region and a gate electrode is disposed over the gate insulator. | 2014-09-18 |
20140273385 | INTERFACE FOR METAL GATE INTEGRATION - A metal oxide semiconductor field effect transistor (MOSFET) includes a semiconductor substrate and an interlayer dielectric (ILD) over the semiconductor substrate. A gate structure is formed within the ILD and disposed on the semiconductor substrate, wherein the gate structure includes a high-k dielectric material layer and a metal gate stack. One or more portions of a protection layer are formed over the gate stack, and a contact etch stop layer is formed over the ILD and over the one or more portions of the protection layer. The metal gate stack includes aluminum and the protection layer includes aluminum oxide. | 2014-09-18 |
20140273386 | METHOD OF FORMING METAL SILICIDE LAYER - A method of forming a metal silicide layer includes the following steps. At first, at least a gate structure, at least a source/drain region and a first dielectric layer are formed on a substrate, and the gate structure is aligned with the first dielectric layer. Subsequently, a cap layer covering the gate structure is formed, and the cap layer does not overlap the first dielectric layer and the source/drain region. Afterwards, the first dielectric layer is removed to expose the source/drain region, and a metal silicide layer totally covering the source/drain region is formed. | 2014-09-18 |