38th week of 2008 patent applcation highlights part 20 |
Patent application number | Title | Published |
20080224668 | Generator Device for Independently Charging At Least Two Batteries - A generator device, e.g. a motor vehicle alternator, has a generator and can be electrically coupled to at least two batteries at the output end. The generator device is provided with one respective rectifier circuit for the at least two batteries. The rectifier circuits are configured and can be controlled such that power generated by the generator can be fed to the respective battery independently of the at least one other battery. | 2008-09-18 |
20080224669 | Battery Connection Detection Circuit - A battery connection detection circuit is disclosed that is able to correctly determine an operation condition of a secondary battery and a connection condition between the secondary battery and a charging device. A determination circuit monitors both the voltage Vt | 2008-09-18 |
20080224670 | ELECTRICAL POWER GENERATION SYSTEM - An electrical power generation system and method for generating electrical power are provided. The electrical power generation system utilizes a master controller for controlling operation of devices coupled to an AC electrical grid and DC electrical grid based on parameter values associated with a renewable power generator. | 2008-09-18 |
20080224671 | Electric power generation control apparatus for vehicle alternator - An electric power generation control apparatus for a vehicle alternator mounted on a motor vehicle performs one of a constant output voltage control a constant torque control and a constant exciting current control in order to suppress a hunting phenomenon of the vehicle alternator. First of all, the electric power generation control apparatus performs the constant output voltage control when a rotation speed is within an idling rotation speed range or a periodic change of the rotation speed is not less than a predetermined value. After completion of the constant output voltage control, when judging that the idle hunting phenomenon is not adequately suppressed, the electric power generation control apparatus performs one of the constant torque control and the constant exciting current control. | 2008-09-18 |
20080224672 | DC/DC converter controlled by pulse width modulation with high efficiency for low output current - An embodiment of a DC voltage converter, producing an output voltage (VS) at an output terminal from an energy source, comprises: | 2008-09-18 |
20080224673 | Circuit for starting up a synchronous step-up DC/DC converter and the method thereof - The low voltage circuit for starting up a synchronous step-up DC/DC converter, which connects to a voltage source through an inductor, includes a P-type power transistor, an N-type power transistor and a controller. The P-type power transistor includes a body diode, and one end of the P-type power transistor acts as a power source of an oscillator. The N-type power transistor connects the P-type power transistor in series, and both of the power transistors are not enabled at the same time. The oscillator electrically connects to the controller, which enables the P-type power transistor at initialization time, and enables the N-type power transistor a period after the initialization time. | 2008-09-18 |
20080224674 | DC-DC CONVERTER AND POWER SUPPLY SYSTEM - A DC-DC converter prevents localization of switching operations at light loads and is able to improve power conversion efficiency. The DC-DC converter of some variations performs pulse frequency modulation control at light loads, and includes a reducing circuit configured to skip an oscillation frequency signal at light loads and to generate a skipped signal. | 2008-09-18 |
20080224675 | VOLTAGE REGULATOR AND VOLTAGE REGULATION METHOD - A voltage regulator converts a voltage from a direct current power supply into a predetermined voltage, and outputs the predetermined voltage from an output terminal thereof to supply electric power to a load. The voltage regulator includes a first power supply circuit and a second power supply circuit. The first power supply circuit supplies the electric power to the load in accordance with a switching signal, when a load current is relatively high. The second power supply circuit supplies the electric power to the load in accordance with the switching signal, when the load current is relatively low. A bias current for operating the second power supply circuit is set to be proportional to the load current during the supply of the electric power to the load by the second power supply circuit. | 2008-09-18 |
20080224676 | Voltage Clamp Circuit, a Switching Power Supply Device, a Semiconductor Integrated Circuit Device, and a Voltage Level Conversion Circuit - The present invention provides a voltage clamping circuit which is operated in a stable manner with the simple constitution and a switching power source device which enables a high-speed operation. In a switching power source device, one of source/drain routes is connected to an input terminal to which an input voltage is supplied, a predetermined voltage to be restricted is supplied to a gate, and using a MOSFET which provides a current source between another source/drain route and a ground potential of the circuit, a clamp output voltage which corresponds to the input voltage is obtained from another source/drain route. The switching power source device further includes a first switching element which controls a current which is made to flow in an inductor such that the output voltage assumes a predetermined voltage and a second switching element which clamps an reverse electromotive voltage generated in the inductor when the first switching element is turned off to a predetermined potential. In such a switching power source device, the voltage clamping circuit is used in a feedback route for setting a dead time. | 2008-09-18 |
20080224677 | DEAD TIME TRIMMING IN A CO-PACKAGE DEVICE - A method of obtaining an optimized dead time for a synchronous switching power supply comprising a control IC and two series-connected switches, comprising packaging the control IC and the series-connected switches in a co-packaged module; providing a dead time delay circuit within the control IC circuit which has variable dead time; testing the switching power supply; varying the dead time in a defined sequence during the step of testing; monitoring a parameter during testing of the switching power supply as the dead time is varied; determining an optimal dead time based upon monitoring the parameter; and setting the dead time at the optimal dead time. | 2008-09-18 |
20080224678 | SWITCHING POWER SUPPLY CONTROLLER WITH HIGH FREQUENCY CURRENT BALANCE - A controller for a multi-phase switching power supply shuffles the sequence of the phases in response to a load transient to prevent synchronization of one or more phases with high-frequency load transients. The sequence may be shuffled by varying the frequency and/or sequence of the switching control signals to introduce a random variation in the phases. | 2008-09-18 |
20080224679 | Regulator With Improved Load Regulation - A regulator to provide an output voltage of a constant level at an output node. In an embodiment, the regulator contains a pass transistor to provide a conductive path between a pair of terminals, with the resistance offered by the path being determined by a control voltage on a third terminal of the pass transistor and the conductive path coupling a first reference potential (e.g., power supply) to the output node. An amplifier generates the control voltage based on a difference of a reference voltage and a voltage proportionate to the output voltage. A control unit turns on a current source when the voltage at the output node is below the desired constant level and turns on a current sink when voltage at said output node is above the constant level, to quickly correct for any variations in the output voltage due to load changes. | 2008-09-18 |
20080224680 | Voltage regulator - To enhance a safety of a voltage regulator, provided is a control circuit ( | 2008-09-18 |
20080224681 | Controller for a DC to DC Converter - A controller for a DC to DC converter. The controller may include a resistor coupled to a switching node of the DC to DC converter. The switching node may be coupled to a high side switch and a low side switch of the DC to DC converter. A current level through the resistor may be responsive to a state of the high side switch and said low side switch. The controller may further include ramp generation circuitry responsive to the current level through the resistor to provide a ramp signal, and pulse width modulation (PWM) circuitry configured to generate a PWM signal in response to at least the ramp signal. | 2008-09-18 |
20080224682 | Voltage reference circuit - A reliable start-up circuit for starting a bandgap type voltage reference generator which ensures that the bandgap reference cell will operate at a stable operating point before the start-up circuit is disabled. | 2008-09-18 |
20080224683 | CONTROL SYSTEM FOR DYNAMICALLY ADJUSTING OUTPUT VOLTAGE OF VOLTAGE CONVERTER - A control system for dynamically adjusting an output voltage of a voltage converter includes a signal calculation circuit, a pulse width modulator, a voltage converter, a nonlinear calibration circuit and a signal converter. The signal calculation circuit, the pulse width modulator, the voltage converter and the signal converter form a long-tail loop. The signal calculation circuit simultaneously receives a target value and a detection value from the signal converter to generate an error value for adjusting the output of the pulse width modulator. The voltage converter and the nonlinear calibration circuit form a local pulse-squashing loop. Pulse widths of an input signal to the voltage converter can be timely and effectively calibrated and controlled, thereby decreasing power consumption of the voltage converter and providing an effective protective mechanism. | 2008-09-18 |
20080224684 | Device and Method for Compensating for Voltage Drops - A device that includes a voltage supply unit and an integrated circuit, the device is characterized by including a voltage sampling circuit adapted to sample voltage levels at multiple sampling points within the integrated circuit, to provide multiple sampled voltages, wherein the multiple sampled voltages reflect the voltage drops; and wherein the voltage supply unit is adapted to adjust a supply voltage provided to the integrated circuit in response to at least one sampled voltage. A method for voltage drop compensation; the method includes providing a supply voltage to an integrated circuit; the method is characterized by sampling voltage levels at multiple sampling points within the integrated circuit, to provide multiple sampled voltages, wherein the multiple sampled voltages reflect the voltage drops; and adjusting a supply voltage provided to the integrated circuit in response to at least one sampled voltage. | 2008-09-18 |
20080224685 | METHOD AND APPARATUS TO MANAGE POWER CONSUMPTION OF A SEMICONDUCTOR DEVICE - Briefly, a method an apparatus of a power management system of a semiconductor device capable of managing a power consumption of the semiconductor device by varying an operating voltage of the semiconductor device according to a voltage value based on a reference number. | 2008-09-18 |
20080224686 | System and method for remotely identifying a connected RF cable - A system and method is provided for identifying, among a plurality of cables having respective first and second cable end portions, a connected cable connected to a selected antenna without interrupting service thereof. A signal emitter is connected to the respective first cable end portion, proximal the selected antenna, of the connected cable. A signal meter is connected to the respective second end portion of each cable. A signal is emitted from the signal emitter and the respective received signal amplitude of the signal received at the second respective cable end portion is measured. The cable for which the respective received signal amplitude of the signal received at the second respective cable end portion is greatest is the connected cable. | 2008-09-18 |
20080224687 | METHOD AND APPARATUS FOR MONITORING FUEL CELLS - Methods and apparatus are provided for monitoring a coolant conductivity of a fuel cell supplying power via positive and negative buses. The method includes measuring a first voltage of the positive bus, measuring a second voltage of the negative bus, applying a resistance between the positive bus and a reference potential, measuring a third voltage of the positive bus after a period of applying the resistance, and determining an isolation resistance based on the measured voltages. The isolation resistance is a function of the coolant conductivity. | 2008-09-18 |
20080224688 | Volumetric Induction Phase Shift Detection System for Determining Tissue Water Content Properties - A method of determining the condition of a bulk tissue sample, by: positioning a bulk tissue sample between a pair of induction coils (or antennae); passing a spectrum of alternating current (or voltage) through a first of the induction coils (or antennae); measuring spectrum of alternating current (or voltage) produced in the second of the induction coils (or antennae); and comparing the phase shift between the spectrum of alternating currents (or voltages) in the first and second induction coils (or antennae), thereby determining the condition of the bulk tissue sample. An apparatus for determining the condition of a bulk tissue sample, having: a first induction coil (or antenna); a second induction coil (or antenna); an alternating current power supply connected to the first induction coil (or antenna), the alternating current power supply configured to generate a spectrum of currents (or voltage) in the first induction coil (or antenna); and a measurement system connected to the second induction coil (or antenna), wherein the measurement system is configured to measure a phase shift difference in the spectrum of currents (or voltages) between the first and second induction coils (or antennae) when the first and second induction coils (or antennae) are positioned on opposite sides of a tissue sample. | 2008-09-18 |
20080224689 | Phase measurement device using inphase and quadrature components for phase estimation - A phasemeter for estimating the phase of a signal. For multi-tone signals, multiple phase estimates may be provided. An embodiment includes components operating in the digital domain, where a sampled input signal is multiplied by cosine and sine terms to provide estimates of the inphase and quadrature components. The quadrature component provides an error signal that is provided to a feedback loop, the feedback loop providing a model phase that tends to track the phase of a tone in the input signal. The cosine and sine terms are generated from the model phase. The inphase and quadrature components are used to form a residual phase, which is added to the model phase to provide an estimate of the phase of the input signal. Other embodiments are described and claimed. | 2008-09-18 |
20080224690 | Embedded Directional Power Sensing - A module incorporates power sensors coupled to a through line through directional couplers, all of which are mounted on a board within a housing, for measuring transmitted and received power of a system under test. | 2008-09-18 |
20080224691 | METHOD FOR TESTING ROTATION SPEED OF FAN - An exemplary method for testing rotating speed of a fan, includes the following steps: coupling a fan and a resistor in series to a power supply; coupling an oscilloscope in parallel with the resistor; plotting voltage across the resistor on a screen of the oscilloscope, and obtaining the period of the voltage according to the image; and obtaining the rotating speed of the fan. | 2008-09-18 |
20080224692 | Method and apparatus for position detection - A relative position of two articles is determined by generating a magnetic field using a magnetic element of a first article and determining a first measurement value and a second measurement value using a sensor arrangement of a second article, with the first and the second measurement values correlated to the size of the magnetic field in two different spatial directions and correspond to two different magnetic field components. The sensor arrangement is selected such that the first magnetic field component is essentially parallel to the direction of relative movement of the articles and the second magnetic field component is essentially perpendicular to the relative direction of movement of the articles. A difference signal of the absolute magnitudes of the first and second measured values is used to determine the relative position of the first and second articles. A position detector is also provided. | 2008-09-18 |
20080224693 | ABNORMALITY DETECTION APPARATUS FOR ROTARY TYPE ABSOLUTE ENCODER - In order to cope with many rotor diameters using a single type of stator portion, two stator portions, each having a built-in signal processing circuit for detecting absolute positions independently, are disposed in opposition at positions which differ from each other with respect to a rotational center of a rotor portion. When one of the stator portions receives a request command RX from an external device, it transmits a detected serial communication signal. The other stator portion receives the transmitted serial communication signal, determines a position detection abnormality, and notifies the abnormality to the external device when a difference between the received absolute position and the absolute position detected by the other stator portion exceeds a deviation previously set for 180 degrees. | 2008-09-18 |
20080224694 | Semiconductor component and method for testing such a component - A semiconductor component on a semiconductor chip comprises at least one sensor element for measuring a physical quantity and an evaluator. The semiconductor component can be switched between a first and a second operating mode. In the first operating mode, the sensor element is sensitive to the physical quantity to be measured and a measurement signal output of the sensor element is connected to an input connection of the evaluator. In the second operating mode, the sensor element is not sensitive to the physical quantity to be measured and/or the signal path between the measurement signal output and the input connection is interrupted. A test signal source for generating a test signal simulating the measurement signal of the sensor element is arranged on the semiconductor chip. In the second operating mode, the test signal source is connected or capable of being connected to the input connection of the evaluator. | 2008-09-18 |
20080224695 | Method of Measuring a Weak Magnetic Field and Magnetic Field Sensor of Improved Sensitivity - A magnetic field sensor comprises a magnetoresistive element ( | 2008-09-18 |
20080224696 | Nuclear quadrupole resonance logging tool and methods for imaging therewith - An instrument for investigating properties of an earth formation includes a body housing a nuclear quadrupole resonance (NQR) probe, the probe having at least one coil wound around a core material and an electronics coupling, the body being adapted for insertion into a wellbore within the earth formation. A method and computer program product are provided. | 2008-09-18 |
20080224697 | METHOD AND APPARATUS FOR ENHANCED MAGNETIC PREPARATION IN MR IMAGING - The present invention provides a system and method of enhanced magnetic preparation in MR imaging. An imaging technique is disclosed such that k-space is segmented into a number of partitions, wherein the central regions of k-space is acquired prior to the periphery of k-space. The imaging technique also includes the application of magnetic preparation pulses at a variable rate. In this regard, the rate of application of magnetic preparations pulses is varied as a function of the distance from the center of k-space. The amplitude of the magnetic preparation pulses is also varied based on the incremental distance of a partition from the center of k-space. | 2008-09-18 |
20080224698 | MAGNETIC RESONANCE IMAGING APPARATUS AND MAGNETIC RESONANCE IMAGING METHOD - A magnetic resonance imaging apparatus which executes a mask scan for acquiring, as mask data, magnetic resonance signals produced in an imaging area in which a fluid flows through a subject, in a state in which a contrast agent is not injected into the fluid, and an imaging scan for acquiring, as imaging data, magnetic resonance signals produced in the imaging area in which the fluid containing the contrast agent flows after the injection of the contrast agent into the fluid, so as to correspond to a TRICKS method, thereby sequentially generating images about the imaging area along a time base, said magnetic resonance imaging apparatus includes
| 2008-09-18 |
20080224699 | MAGNETIC RESONANCE METHOD AND APPARATUS WITH NUCLEAR SPINS TYPE-SPECIFIC SIGNAL SUPPRESSION - A method in the form of a sequence for magnetic resonance imaging with which image data of a subject to be examined are acquired and with which signals of nuclear spins of a specific type are suppressed, includes the steps of (a) application of a suppression module to suppress signals of the nuclear spins of the specific type, (b) application of an acquisition module after a wait time to acquire measurement data, (c) repetition of the steps (a) and (b) one or more times, respectively after a repetition time and, (d) before the steps (a), (b) and (c), application of a spin preparation module that shifts a magnetization of the nuclear spins of the specific type into a steady state condition that is maintained through the application of the subsequent steps (a), (b) and (c). Alternatively, instead of the spin preparation module the first suppression module can be fashioned such that it has an RF pulse with a flip angle selected such that the magnetization of the nuclear spins of the specific type is shifted into a steady state condition. | 2008-09-18 |
20080224700 | System and method for displaying medical imaging spectral data as hypsometric maps - A system and method for displaying MR spectroscopy data acquired using a magnetic resonance imaging (MRI) system includes acquiring MR spectroscopy data from a region of interest using the MRI system. The MR spectroscopy data is processed to determine relative spectral amplitudes of each of a plurality of points in the MR spectroscopy data resulting from frequency components of molecules in the region of interest. Each of the plurality of points is mapped to a particular optical parameter based at least upon on the relative spectral amplitude associated with each point and a point is generated for each of the plurality of points having the optical parameter mapped thereto. The points for each of the plurality of points are arranged to form a hypsometric map. | 2008-09-18 |
20080224701 | Magnetic resonance imaging apparatus and radio freqeuncy coil unit - A radio frequency coil unit includes a plurality of surface coils and a distributing/combining unit. The plurality of surface coils are arranged in a body-axis direction. The distributing/combining unit distributes and combines reception signals output from the plurality of surface coils to generate a new reception signal. | 2008-09-18 |
20080224702 | FIELD DISTRIBUTION CORRECTION ELEMENT AND METHOD FOR GENERATING A MAGNETIC RESONANCE EXPOSURE THEREWITH - A field distribution correction element for positioning on an examination subject in a magnetic resonance system for local influencing of the radio-frequency field distribution during a magnetic resonance acquisition has a system of electrically conductive dipole strips essentially running in parallel, arranged on a carrier element. In a corresponding method for generation of magnetic resonance exposures of an examination subject in a magnetic resonance system, for local influencing of the radio-frequency field distribution, such a field distribution correction element is positioned on the patient. | 2008-09-18 |
20080224703 | Method and device for magnetic resonance analysis - A device for NMR spectroscopy is disclosed. The device comprises a sealed capillary having therein a lock material. | 2008-09-18 |
20080224704 | Apparatus and method for detecting and identifying ferrous and non-ferrous metals - A metal detector using a linear current ramp followed by an abrupt current transition to energize the transmitter coil. The constant emf imposed on the target during the current ramp permits separation of transient voltages generated in response to eddy currents in the target and its environment from the voltages arising as a result of an inductive imbalance of the coil system The temporal separation of the various voltages makes reliable differentiation between ferrous and non-ferrous targets possible. | 2008-09-18 |
20080224705 | Electromagnetic Probe - An electromagnetic probe | 2008-09-18 |
20080224706 | Use of Electrodes and Multi-Frequency Focusing to Correct Eccentricity and Misalignment Effects on Transversal Induction Measurements - A multicomponent induction logging tool uses a nonconducting mandrel. A central conducting member including wires that electrically connect at least one of the antennas to another of the antennas. Electrodes disposed about the transmitter antenna form a conductive path through a borehole fluid to the central conducting member. | 2008-09-18 |
20080224707 | Array Antenna for Measurement-While-Drilling - An electromagnetic antenna for Measurement-While-Drilling (MWD) applications is disclosed. The antenna can include several array elements that can act alone or together in various measurement modes. The antenna elements can be disposed in tool body recesses to be protected from damage. The antenna elements can include a ferrite plate crossed or looped by independent current carrying conductors in two or more directions forming a bi-directional or crossed magnetic dipole. Although disclosed as a MWD system conveyed by a drill string, basic concepts of the system are applicable to other types of borehole conveyance. | 2008-09-18 |
20080224708 | Method and a Device for Detecting Signal Lamps in a Vehicle - Provided are a device and a method of detecting signal lamps in a vehicle, in particular in a large vehicle, being provided with a plurality of signal lamps each being capable of switching between an OFF-phase and an ON-phase. The method includes the steps of during the OFF-phase of a vehicle signal lamp to be probed inducing a probing current by connecting an electric current generator to said vehicle signal lamp circuit, where the probing current is lower than the nominal current for the lamp in question. The next step is to detect the electric voltage level over the lamp circuit and determining vehicle signal lamp characteristics such as type and condition based on said electric voltage level detection. The result of the determination is that the signal lamp is a LED lamp being connected, when the detected voltage level is within a predetermined interval between a first voltage level and a second voltage level. | 2008-09-18 |
20080224709 | Battery management system and driving method thereof - In a battery management system and a driving method thereof, the system includes a sensor and a micro control unit (MCU). The sensor senses a voltage and a current of a battery, and generates an estimation current of the battery using a result of cumulatively calculating the battery current by a unit of a predetermined period. The MCU receives the battery voltage and the estimation current, sets a voltage of the battery in a key-on state as a first voltage, sets a voltage of the battery after a first period as a second voltage, and calculates an internal resistance of the battery using a difference between the first and second voltages and an average value of the estimation current. | 2008-09-18 |
20080224710 | HEAVY DUTY BATTERY SYSTEM TESTER AND METHOD - A systematic method and system for testing the charging and starting systems of a vehicle, which requires each individual test to pass before proceeding is provided. In addition, the invention incorporates an improved alternator test that determines whether the alternator belt is slipping using data read using a vehicle data port. Further, the invention provides a battery bank test that correlates the voltage before and after a load is applied to the battery bank to the batteries' conditions. When testing the starter, the oil temperature is read via the vehicle data port, allowing for a determination of whether the current draw is abnormally high. | 2008-09-18 |
20080224711 | IONIZATION VACUUM GAUGE - An ionization vacuum gauge includes a cathode electrode, a gate electrode, and an ion collector. The gate electrode is disposed adjacent to the cathode electrode with a distance therebetween. The ion collector is disposed adjacent to the gate electrode also with a distance therebetween. The cathode electrode includes a base and a field emission film disposed thereon facing the ion collector. | 2008-09-18 |
20080224712 | Non-Contact Cable State Testing - A method of determining the state of a cable comprising at least one electrical conductor, uses a generated test signal and applies it to at least one conductor by a non-contact coupling transmitter. The resulting signal is propagated along the at least one conductor and a non-contact electrical coupling receiver picks up a reflected signal, and compares the reflected signal to expected state signal values for the cable to determine its current state. | 2008-09-18 |
20080224713 | Device for measuring the loss factor - Disclosed is a device for measuring the loss factor and/or measuring the phase angle between a voltage and a current and/or recording a voltage decay and/or current decay and/or recording partial discharge processes and/or measuring the propagation time on test objects that are to be tested. Said device comprises a housing in which at least one measuring circuit is arranged for measuring and/or recording purposes. A terminal adapter ( | 2008-09-18 |
20080224714 | System and Method of Integrated Circuit Control for in Situ Impedance Measurement - A system and method of integrated circuit control for in situ impedance measurement including a system with a plurality of functional partitions in a clocked logic type integrated circuit, the functional partitions having a communication controller and a modulation gate, the modulation gate receiving a clock signal and a modulation signal and generating a modulated clock signal for the functional partition; at least one of the communication controllers receiving an in-band signal and selectively communicating the in-band signal to the other communication controllers; and at least one of the functional partitions having a modulator, the modulator receiving the clock signal and a modulation control signal and generating the modulation signal. | 2008-09-18 |
20080224715 | LIGHT-DRIVING SYSTEM CAPABLE OF PROVIDING SIGNAL-MEASURED CALIBRATION AND A METHOD FOR PERFORMING THE SAME - This present invention discloses a light-driving system capable of providing an accurate calibration of signal measurement and a method for performing the same, including an automatic power control (APC) circuit which is pre-calibrated for a signal measurement process. By enlarging at least one measured pad of the APC circuit, multiple grounding paths are established via a plurality of probes of a test instrument. An impedance effect predicted on the contact between the probes and the pad is diminished greatly. A voltage value on the pad can be accurately measured. Thus, a reference voltage value input to a first input of a comparator of the APC circuit can be determined on a basis of a specific condition when a ramping voltage value input to a second input of the comparator is substantially equal to a sum of a predetermined reference voltage value and the voltage value of the pad. | 2008-09-18 |
20080224716 | Method and System For Determining Freshness and Palatability and Assessing Organ Vitality - A method and system to determine freshness and palatability (tenderness, juiciness, and flavor) of live foodstuffs (meat, fish, fowl, fruit and vegetables) including the steps of; utilizing bioelectrical impedance analysis in a biological subject model for measurement and composition analysis; and a system of using the results of the utilizing step procedure to illustrate an objective scale of palatability; a ‘Palatability Index’. Also a method of whole body and regional organ and tissue vitality assessment in a biological entity, human, animal, fruit or vegetable, including the steps of: utilizing bioelectric impedance analysis in a biological model for composition analysis; and using the results of the utilizing step to provide an objective assessment of volume and distribution of fluid and tissues, and electrical health of cells and membranes of the organ or tissue. | 2008-09-18 |
20080224717 | SUSPENDED NANOWIRE SENSOR AND METHOD FOR FABRICATING THE SAME - Provided is a suspended nanowire sensor having good sensing characteristics and suitable for mass production, a method for fabricating the suspended nanowire sensor. The suspended nanowire sensor includes: first and second sensor electrodes formed on upper portions of a substrate and physically separated from each other; and a nanowire sensor material piece extending from the first sensor electrode to the second sensor electrode and physically suspended between the first and second sensor electrodes. | 2008-09-18 |
20080224718 | Battery ohmic resistance calculation system and method - An apparatus that estimates the ohmic resistances of N batteries includes voltage and current measurement modules that respectively measure the voltage and current of each of the N batteries. An ohmic resistance estimating module over N+1 time periods receives the voltage and current measurements of each of the N batteries and receives consecutive voltage and current measurements for one of the N batteries. N is a positive integer and the ohmic resistance estimating module estimates the ohmic resistance of the battery that is associated with the consecutive voltage and current measurements. | 2008-09-18 |
20080224719 | Diagnostic test device - A diagnostic test device comprising means for sampling a liquid biological sample, means for reacting the sample with at least one reagent to provide one or more visible indicia and an optical detector for detecting the presence of said one or more indicia, the device further comprising a releasable tether which is released by contact with the liquid sample, thereby to cause the optical detector to detect the said one or more indicia. | 2008-09-18 |
20080224720 | Support Member Assembly for Conductive Contact Members - Provided is a support member assembly suitable for use in a contact probe head comprising a support member formed with a plurality of holder holes for supporting conductive contact members in a mutually parallel relationship, and a reinforcing member integrally formed with the support member and extending in a part of the support member devoid of any holder holes. The reinforcing member increases the overall mechanical strength of the support member assembly, and prevents the thermal deformation of the support member. Because the holder holes are formed in the support member made of material suitable for forming holes, such as plastic material and ceramic material, the holder holes can be formed at high precision and at low cost. | 2008-09-18 |
20080224721 | APPARATUS, UNIT AND METHOD FOR TESTING IMAGE SENSOR PACKAGES - The present invention relates to an apparatus, unit and method for testing image sensor packages, which can automatically test whether the image sensor packages are defective before they are assembled into camera modules. An apparatus for testing image sensor packages according to the present invention comprises a seating unit on which image sensor packages are seated for tests; a testing section having a lens and a light source above the image sensor packages to perform an open and short test and an image test for the image sensor packages; and a controlling and processing unit having a tester module for performing the open and short test and the image test for the image sensor packages. A method for testing image sensor packages according to the present invention comprises the steps of connecting the image sensor packages to a tester module for performing tests for checking whether the image sensor packages are defective; and carrying out an open and short test and an image test for the image sensor packages while irradiating light on the image sensor packages through a lens or blocking the light. | 2008-09-18 |
20080224722 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a clock generator which generates a first clock, a test data generator which modulates a phase of the first clock, and generates test data to which jitter is added by using the modulated clock, a data extractor which samples the test data and extracts recovery data, and a detector which detects an error of the recovery data. | 2008-09-18 |
20080224723 | METHOD FOR TESTING A SEMICONDUCTOR WAFER AND APPARATUS THEREOF - Reliability of results of a test such as a wafer burn-in test is raised. The present invention is a method for testing a plurality of semiconductor devices in a semiconductor wafer held in a cartridge. Each of the semiconductor devices has electrodes and the cartridge has a lower cartridge portion provided with a chuck holding the semiconductor wafer thereon, and an upper cartridge portion provided with a probe assembly having probes capable of contacting said electrodes. After constituting the cartridge and before placing the cartridge in the thermostatic chamber, a contact check to determine whether or not electrical contact between the electrodes of the semiconductor devices in the cartridge and the probes of the probe assembly is appropriate is performed. | 2008-09-18 |
20080224724 | Photoconductive Based Electrical Testing of Transistor Arrays - Apparatus for testing microelectronic components on a substrate, including a scanner operative to scan a light beam over a plurality of thin film transistors disposed on a substrate, one transistor at a time, so as to induce a photoconductive response in the plurality of transistors, one transistor at a time; current sensing circuitry operative, synchronously with said scanner, to measure an output induced by the photoconductive response associated with a transistor and to generate photoconductive response output values, the photoconductive response output values representing a photoconductive response induced by the light beam, for one transistor at a time from among the plurality of transistors; and diagnostic apparatus operative to analyze the electronic response output values and to characterize each of the transistors in accordance therewith. | 2008-09-18 |
20080224725 | TEST CIRCUIT, WAFER, MEASURING APPARATUS, MEASURING METHOD, DEVICE MANUFACTURING METHOD AND DISPLAY APPARATUS - There is provided a wafer on which a plurality of electronic devices and circuits under test are to be formed, where each circuit under test includes a plurality of transistors under measurement provided in electrically parallel, a selecting section which sequentially selects the respective transistors under measurement, and an output section which sequentially outputs the source voltages of the transistors under measurement sequentially selected by the selecting section. | 2008-09-18 |
20080224726 | Quasi-Particle Interferometry For Logical Gates - A quantum computer can only function stably if it can execute gates with extreme accuracy. “Topological protection” is a road to such accuracies. Quasi-particle interferometry is a tool for constructing topologically protected gates. Assuming the corrections of the Moore-Read Model for ν=5/2's FQHE (Nucl. Phys. B 360, 362 (1991)) we show how to manipulate the collective state of two e/4-charge anti-dots in order to switch said collective state from one carrying trivial SU(2) charge, |1>, to one carrying a fermionic SU(2) charge |ε>. This is a NOT gate on the {|1>, |ε>} qubit and is effected by braiding of an electrically charged quasi particle σ which carries an additional SU(2)-charge. Read-out is accomplished by σ-particle interferometry. | 2008-09-18 |
20080224727 | Logic System for Dpa and/or Side Channel Attach Resistance - DPA-resistant logic circuits and routing are described. An architecture and methodology are suitable for integration in a common automated EDA design tool flow. The architecture and design methodology can be used in logic circuits, gate arrays, FPGAs, cryptographic processors, etc. In one embodiment, the implementation details of how to create a secure encryption module can be hidden from the designer. The designer is thus, able to write the code for the design of DPA-resistant logic circuits using the same design techniques used for conventional logic circuits. Contrary to other complicated DPA-blocking techniques, the designer does not need specialized knowledge and understanding of the methodology. In one embodiment, the automated design flow generates a secure design from a Verilog or VHDL netlist. The resulting encryption module has a relatively constant power consumption that does not depend on the input signals and is thus relatively independent of which logic operations are performed. | 2008-09-18 |
20080224728 | On-die termination circuit of semiconductor memory apparatus - An on-die termination circuit of a semiconductor memory apparatus includes a comparator that compares a voltage corresponding to a normal code with a reference voltage to output a comparison signal. A code adjusting unit varies the normal code according to the comparison signal, outputs the varied normal code, and resets the normal code to a predetermined reset code or a variable fuse code. | 2008-09-18 |
20080224729 | INTEGRATED CIRCUITS WITH REDUCED LEAKAGE CURRENT - In one embodiment, NMOS transistors have their source coupled to a common source node such that the NMOS transistors conduct a leakage current if the common source node is grounded. To reduce this leakage current, the common source node is raised in potential. Similarly, PMOS transistors have their source coupled to a common source node such that the PMOS transistors conduct a leakage current if the common source node is charged to a power supply voltage VDD. To reduce this leakage current, the common source node is lowered in potential. | 2008-09-18 |
20080224730 | CONFIGURATION NETWORK FOR A CONFIGURABLE IC - Some embodiments of the invention provide a configurable integrated circuit (IC) that includes several configurable circuits grouped in several tiles. The configurable IC also includes a configuration network for loading configuration data into the IC, where the configuration data is for configuring several of the configurable circuit. In some embodiments, the configuration network includes several registers at several boundaries between the tiles, where the registers allow multiple configuration data sets to be routed to multiple tiles concurrently. The configuration network in some embodiments includes several address counters at several tiles, where each address counter allows one address to be loaded for a tile and then to be successively incremented based on increment instructions sent over the configuration network. At least, two different addresses specified by an address counter of a particular tile identify two different resources within the particular tile. | 2008-09-18 |
20080224731 | NON-VOLATILE MEMORY ARCHITECTURE FOR PROGRAMMABLE-LOGIC-BASED SYSTEM ON A CHIP - A programmable system-on-a-chip integrated circuit device includes a programmable logic block. A digital input/output circuit block is coupled to the programmable logic block. A SRAM block is coupled to the programmable logic block. At least one non-volatile memory block is coupled to the programmable logic block. A JTAG port is coupled to the programmable logic block. An analog circuit block including an analog-to-digital converter may be coupled to the programmable logic block and an analog input/output circuit block may be coupled to the analog circuit block. | 2008-09-18 |
20080224732 | Logic Modules for Semiconductor Integrated Circuits - A logic module ( | 2008-09-18 |
20080224733 | ELECTRONIC CIRCUIT FOR MAINTAINING AND CONTROLLING DATA BUS STATE - The inventions herein are directed to an inventive bus keeper and logic circuit for use with an I/O circuit, for example, for use on the receiver side of the I/O buffer circuit. The inventive circuit connects one data line of an IC function to one line of a tri-state bus (one bit of data per bus line or wire). The bus keeper and logic control circuit is maintained in isolation from I/O functional driver and is responsive to a tri-state signal (TS), normally provided by the IC or SOC, or the I/O circuit during normal I/O receiver side operation. The inventive bus keeper and logic circuit selectively enables any of a tri-state state, a pull-up state, pull-down state and bus keep mode state at the driver output pad in the presence of the tri-state enable signal, and is disabled when the I/O bus drive buffer circuit is in drive mode. | 2008-09-18 |
20080224734 | Multi-terminal chalcogenide logic circuits - Logic circuits are disclosed that include one or more three-terminal chalcogenide devices. The three-terminal chalcogenide devices are electrically interconnected and configured to perform one or more logic operations, including AND, OR, NOT, NAND, NOR, XOR, and XNOR. Embodiments include series and parallel configurations of three-terminal chalcogenide devices. The chalcogenide devices include a chalcogenide switching material as the working medium along with three electrical terminals in electrical communication therewith. | 2008-09-18 |
20080224735 | Frequency Synthesis Rational Division - A system and method are provided for synthesizing signal frequencies using rational division. The method accepts a reference frequency value and a synthesized frequency value. In response to dividing the synthesized frequency value by the reference frequency value, an integer value numerator (dp) and an integer value denominator (dq) are determined. The method reduces the ratio of dp/dq to an integer N and a ratio of p/q (dp/dq=N(p/q)), where p/q<1 (decimal). The numerator (p) and the denominator (q) are supplied to a flexible accumulator module, and a divisor is generated as a result. N is summed with a k-bit quotient to create the divisor. In a phase-locked loop (PLL), the divisor and the reference signal are used to generate a synthesized signal having a frequency equal to the synthesized frequency value. | 2008-09-18 |
20080224736 | SEMICONDUCTOR DEVICE SUPPLYING CHARGING CURRENT TO ELEMENT TO BE CHARGED - A semiconductor device supplying a charging current to a charging-target element includes: a semiconductor layer of a first conductivity type; a first semiconductor region of a second conductivity type formed on a main surface of the semiconductor layer and having a first node coupled to a first electrode of the charging-target element and a second node coupled to a power supply potential node supplied with a power supply voltage; a second semiconductor region of the first conductivity type formed in a surface of the first semiconductor region at a distance from the semiconductor layer and having a third node coupled to the power supply potential node; and a charge carrier drift restriction portion restricting drift of charge carrier from the third node to the semiconductor layer. | 2008-09-18 |
20080224737 | Current mirror circuit - Provided is a semiconductor device capable of evenly distributing an effect of charge on each gate of adjacent MOS transistors, which form a current mirror circuit, during a production process of the semiconductor device, by directly connecting the gates of the adjacent MOS transistors, which form the current mirror circuit, to each other with polysilicon and by further connecting a fuse, which is connected to a substrate, to a gate portion that is connected with the polysilicon, and capable of reducing the effect by dissipating the charge to the substrate. The fuse is cut off during a trimming process. | 2008-09-18 |
20080224738 | HIGH-SIDE SWITCH WITH A ZERO-CROSSING DETECTOR - A circuit arrangement comprising a high-side semiconductor switch with a first load terminal connected to a first supply terminal receiving an input voltage, a second load terminal connected to an output terminal providing an output signal, and a control terminal, a floating driver circuit connected to the control terminal for driving the semiconductor switch, a level shifter receiving an input signal and providing a floating input signal dependent on the input signal, a floating control logic receiving the output signal and the floating input signal and providing at least one control signal to the floating driver circuit, wherein the floating control logic comprises means for detecting an edge in the output signal and means for generating the control signal dependent on the result of the edge detection. | 2008-09-18 |
20080224739 | Equalizing Transceiver With Reduced Parasitic Capacitance - A signaling circuit having reduced parasitic capacitance. The signaling circuit includes a plurality of driver circuits each having an output coupled to a first output node, and a plurality of select circuits each having an output coupled to a control input of a corresponding one of the driver circuits. Each of the select circuits includes a control input to receive a respective select signal and a plurality of data inputs to receive a plurality of data signals. Each of the select circuits is adapted to select, according to the respective select signal, one of the plurality of data signals to be output to the control input of the corresponding one of the driver circuits. | 2008-09-18 |
20080224740 | FREQUENCY MIXER HAVING FERROMAGNETIC FILM - A frequency conversion device, which may include a radiofrequency (RF) mixer device, includes a substrate and a ferromagnetic film disposed over a surface of the substrate. An insulator is disposed over the ferromagnetic film and at least one microstrip antenna is disposed over the insulator. The ferromagnetic film provides a non-linear response to the frequency conversion device. The frequency conversion device may be used for signal mixing and amplification. The frequency conversion device may also be used in data encryption applications. | 2008-09-18 |
20080224741 | Waveform generating circuit and spread spectrum clock generator - A spread spectrum clock generator is provided which improves the spread spectrum effect with little increasing the circuit cost by modifying the shape of a triangular wave used for frequency modulation by a simple method. The output signal of the modulation waveform generating circuit has such a modulation waveform as indicated by solid lines in FIG. | 2008-09-18 |
20080224742 | SMALL SCALE CLOCK MULTIPLIER CIRCUIT FOR FIXED SPEED TESTING - An on-chip clock multiplier for outputting a fast clock that is approximately a predetermined multiple n of a slow clock. The multiplier utilizing a high-speed oscillator to generate a high-frequency base signal. A lower frequency signal is generated using the high-frequency base signal as a function of the output of a rollover counter that counts from a seed value to a terminal value. A saturation counter is used to determine whether no more than n pulses of the lower frequency signal occur within a single cycle of the slow clock. If not, the lower frequency signal is iteratively slowed by changing the seed value until no more than n pulses of the lower frequency signal occur within a single cycle of the slow clock. When this iteration is done, the fast clock having a frequency that is approximately n times the frequency of the slow clock is output. | 2008-09-18 |
20080224743 | SEQUENCE INDEPENDENT NON-OVERLAPPING DIGITAL SIGNAL GENERATOR WITH PROGRAMMABLE DELAY - A circuit for generating non-overlapping clock signals includes a programmable delayed reference clock signals circuit to produce a plurality of delayed reference clock signals and a plurality of delay clock signal generators, operatively connected to the programmable delayed reference clock signals circuit, to generate non-overlapping clock signals. Each delay clock signal generator includes a latch or flip-flop to control a delay in a rising edge of a clock signal and to output a first signal, another latch or flip-flop to control a delay in a falling edge of a delayed clock signal and to output a first signal, and a logic circuit to generate the clock signal from the first and second signals. The latches or flip-flops independently control a delay in the rising edge of the clock signal in response to one of the plurality of delayed reference clock signals. | 2008-09-18 |
20080224744 | CONTROL DEVICE, CONTROL CIRCUIT, CONTROL METHOD, AND RECORDING MEDIUM WITH A CONTROL PROGRAM RECORDED THEREIN - The present invention provides a control device capable of performing feedback control so that a signal-wavelength input to a control target object becomes a specific signal-wavelength, using an input signal whose duty value is other than 50%. Accordingly, the control device according to the present invention is a control device for performing feedback control so that a signal-wavelength input to a control target object ( | 2008-09-18 |
20080224745 | PHASE-LOCKED LOOP AND COMPOUND MOS CAPACITOR THEREOF - Compound MOS capacitors and phase-locked loop with the compound MOS capacitors are disclosed. In the phase-locked loop, the compound MOS capacitors of the loop filter are HV (high voltage) devices, and the voltage control oscillator is a LV (low voltage) device. The compound MOS capacitor comprises a HV PMOS capacitor having a base coupled to a source terminal of a low voltage source and a HV NMOS capacitor having a base coupled to a ground terminal of the low voltage source. The gates of the HV PMOS capacitor and the HV NMOS capacitor are connected together to receive a control voltage. The capacitance of the compound MOS capacitor is near constant in any control voltage. | 2008-09-18 |
20080224746 | Charge Pump Circuit - A charge pump circuit including an input rail, an output rail, a voltage rail, a control line, an MOS input transistor including a gate and a channel connected between the input rail and the voltage rail, and an MOS output transistor including a gate and a channel connected between the output rail and the voltage rail. The gate of the input transistor is connected to the gate of the output transistor and a switch connects the channel of the output transistor to the voltage rail in response to a signal on the control line. The channel of an input cascode transistor connects the channel of the input transistor to the input rail and the channel of an output cascode transistor connects the channel of the output transistor to the output rail. The gate of the input cascode transistor is connected to the gate of the output cascode transistor. | 2008-09-18 |
20080224747 | VARIABLE DELAY CIRCUIT, VARIABLE DELAY DEVICE, AND VCO CIRCUIT - Herein disclosed is a variable delay circuit, including a first delay portion that delays an input signal; an output portion; and a variable impedance portion provided coupled between the first delay portion and an the output portion. | 2008-09-18 |
20080224748 | DIFFERENTIAL LATCH, DIFFERENTIAL FLIP-FLOP, LSI, DIFFERENTIAL LATCH CONFIGURATION METHOD, AND DIFFERENTIAL FLIP-FLOP CONFIGURATION METHOD - A differential latch comprising a data holding transistor, the differential latch comprising: a resetting transistor that is connected to a gate electrode of the data holding transistor and is controlled by a reset signal; and a switching transistor that is connected to the gate electrode of the data holding transistor and is controlled by a switch signal, being an inverted version of the reset signal. | 2008-09-18 |
20080224749 | SYSTEM AND METHOD FOR PROVIDING STABLE CONTROL FOR POWER SYSTEMS - System and method for providing stable control for power systems. According to an embodiment, the present invention provides an apparatus for providing one or more control signals for a power system. The apparatus includes an input terminal for receiving an electrical energy, which can be characterized by a first input voltage. The apparatus includes a control component that is configured to generate a first control signal based on at least information associated with the first input voltage. The apparatus additionally includes an output terminal for sending the first control signal. Moreover, the apparatus includes a timing component that is coupled to the control component. The control component is configured to process at least information associated with a first value of the first input voltage at a first time and a first reference voltage and to generate a second control signal. | 2008-09-18 |
20080224750 | Digital delay architecture - A digital delay architecture and a digital delay method are provided. The digital delay architecture includes at least one shifter, at least one adder connected to the at least one shifter and a plurality of registers storing at least an output of the at least one adder and an original sampled signal. The plurality of registers are selectable to define a fractional delay value. | 2008-09-18 |
20080224751 | Delay Circuit - A delay circuit, including: a plurality of first delay units coupled in series and each configured to generate a delay time that is approximately double a unit delay time; a second delay unit configured to generate the unit delay time and coupled to a last stage of the plurality of first delay units; and a selector configured to select either an output signal of the last stage of the plurality of first delay units or an output signal of the second delay unit, wherein an external input signal is input to the first delay unit and to each second delay unit, and the first delay unit and the second delay unit each include a switch circuit configured to output with a delay either an output signal of a previous stage delay unit or the external input signal. | 2008-09-18 |
20080224752 | INTERNAL CLOCK GENERATOR, SYSTEM AND METHOD - An internal clock generator, system and method of generating the internal clock are disclosed. The method comprises detecting the level of an operating voltage within the system, comparing the level of the operating voltage to a target voltage level and generating a corresponding detection signal, and selecting between a normal clock and an alternate clock having a period longer than the period of the normal clock in relation to the detection signal and generating an internal clock on the basis of the selection. | 2008-09-18 |
20080224753 | Clock generator circuit, clock selector circuit, and semiconductor integrated circuit - A clock generator circuit provides an output clock without an abnormal waveform pulse which causes faulty operation in other function circuits. A phase synchronizing circuit outputs a second clock synchronized with a first clock. A selector signal generator circuit outputs a switching signal when detecting the abnormal waveform pulse in the second clock. A selector outputs the first clock instead of the second clock as the output clock based on the switching signal. A delay circuit delays the second clock input to the selector so that the selector switches the output clock from the second clock to the first clock before the abnormal waveform pulse is input to the selector. | 2008-09-18 |
20080224754 | HIGH-SPEED SERIAL LINK RECEIVER WITH CENTRALLY CONTROLLED OFFSET CANCELLATION AND METHOD - A high-speed serial link receiver includes variable offset comparators with centrally controlled offset cancellation. The receiver includes a comparator stage to receive a high-speed differential input signal. Comparator elements of the comparator stage have first and second current sources to provide current to corresponding differential amplifier half-circuits. An offset cancellation controller provides an offset cancellation signal for setting current provided by one of the current sources to at least partially offset an output offset between the differential amplifier half-circuits. A receiver system may be comprised of a plurality of receiver units for receiving a corresponding plurality of channels over high-speed serial links. A state machine may sequentially determine an offset cancellation code for the comparator elements of the receiver units. | 2008-09-18 |
20080224755 | LEVEL-SHIFT CIRCUIT, ELECTRO-OPTICAL DEVICE, AND LEVEL SHIFT METHOD - A level shift circuit that converts a level of an input signal having a logic level at a first input electric potential and a logic level at a second input electric potential and that generates an output signal having a logic level at a first output electric potential corresponding to the first input electric potential and a logic level at a second output electric potential corresponding to the second input electric potential. The level shift circuit includes a first power-supply node to which the first output electric potential is supplied, a second power-supply node to which the second output electric potential is supplied, a latch unit having an input node and an output node from which the output signal is output, the latch unit being configured to receive power from the first power-supply node and the second power-supply node and to maintain, if an electric potential of the input node is identical to one of the first output electric potential and the second output electric potential, an electric potential of the output node to be the other one of the first output electric potential and the second output electric potential, a switching element that is provided between the first power-supply node and the input node and controlled to be in an ON state or an OFF state, a control unit that controls the switching element to be in the ON state at a timing corresponding to the time when a level of the input signal changes from the first input electric potential to the second input electric potential, and a setting unit that changes an electric potential of the output node to the first output electric potential in a predetermined period just before the logic level of the input signal changes. | 2008-09-18 |
20080224756 | DIGITAL PULSE-WIDTH MODULATOR BASED ON NON-SYMMETRIC SELF-OSCILLATING CIRCUIT - A low-power digital pulse-width modulator (DPWM) architecture for high frequency dc-dc switch-mode power supplies (SMPS) is disclosed that is well-suited for integration in power management systems of small handheld devices. The DPWM can operate in a stand-alone mode, without external clock, and can be implemented on a portion of silicon area needed for other DPWM solutions. In addition it has low power consumption and provides a good linearity of the input-to-output characteristic, also not characteristic for other architectures. | 2008-09-18 |
20080224757 | METHOD AND APPARATUS FOR REDUCING SIMULTANEOUS SWITCHING OUTPUTS - The disclosure provides a method for reducing an amount of simultaneous switching outputs (SSO) of a device. The method of reducing the amount of simultaneous switching outputs can include driving outputs of the device to a first set of values, scrambling a second set of values to reduce an amount of simultaneous switching outputs resulting from the switching of the first to the second set of values, and driving the outputs of the device to the scrambled second set of values. Further, the method can include descrambling the scrambled second set of values back to the second set of values. | 2008-09-18 |
20080224758 | Capacitive Proximity Switch, and Domestic Appliance Comprising the Same - A capacitive proximity switch includes an electrically conductive sensor area, which is covered by an electrically-insulating cover plate, as part of a capacitor having a capacitance which varies as a result of proximity. An associated evaluation circuit is provided, and an electrically-conducting body, via which the sensor area is connected to the evaluation circuit and which is arranged between the electrically-insulating cover plate and a mount disposed at a distance therefrom. A domestic appliance includes such a proximity switch. At least one electronic component of the evaluation circuit is arranged on the mount such that it protrudes into a cavity, which is surrounded by the electrically conductive body. | 2008-09-18 |
20080224759 | Low noise voltage reference circuit - A low noise voltage reference circuit is described. The reference circuit utilizes a bandgap reference component and may include at least one of a current shunt or filter to reduce high and low noise contributions to the output. Further modifications may include a curvature correction component. | 2008-09-18 |
20080224760 | REFERENCE VOLTAGE GENERATOR AND INTEGRATED CIRCUIT INCLUDING A REFERENCE VOLTAGE GENERATOR - A reference voltage generator and an integrated circuit including the reference voltage generator. The reference voltage generator includes a band gap reference circuit and a start-up circuit. The band gap reference circuit provides a reference voltage to a load. The start-up circuit increases the provided reference voltage by providing a boosting current to the load based on a difference between the provided reference voltage and a target reference voltage responsive to a start-up signal, thereby reducing a time in which the provided reference voltage reaches the target reference voltage. Therefore, the reference voltage generator is configured to provide a target reference voltage within a predetermined time. | 2008-09-18 |
20080224761 | OPAMP-LESS BANDGAP VOLTAGE REFERENCE WITH HIGH PSRR AND LOW VOLTAGE IN CMOS PROCESS - A circuit includes an OPAMP-less bandgap voltage generating core circuit connected between a regulated voltage and a ground reference to generate an output bandgap voltage. A preregulator circuit generates the regulated voltage from an unregulated supply voltage. The preregulator circuit includes a negative feedback loop operable to stabilize the regulated voltage and a current source operable to source current for the regulated voltage, the current source mirroring a PTAT current of the OPAMP-less bandgap voltage generating core circuit. The core circuit further includes a negative feedback loop and a positive feedback loop, the negative and positive feedback loops functioning to equalize two internal voltages within the core. | 2008-09-18 |
20080224762 | Noise reduction for switched capacitor assemblies - An integrated circuit comprises an assembly of switched capacitors operated under control of a system clock signal. It further comprises a signal driver for generating a binary output signal at an output pad. The system clock signal is suppressed for a certain time period after each transition of the output signal, thereby preventing voltage droop generated by the transition to introduce noise in the signals of the assembly of switched capacitors. | 2008-09-18 |
20080224763 | Transferred-Impedance Filtering in Rf Receivers - The specification and drawings present a new method and apparatus for using transferred-impedance filtering in RF (radio frequency) receivers (e.g., inside of a mobile communication device), wherein said filtering can be done with MOS-switches transferring impedance of a regular RC or RCL circuit to RF frequency filtering inside an RFIC (radio frequency integrated circuit). | 2008-09-18 |
20080224764 | Switched capacitor notch filter circuits - Switched capacitor notch filter circuits are disclosed. An example switched capacitor notch filter circuit described herein includes a switched capacitor amplifier to receive an input signal and a first feedback signal, to amplify the input signal and the first feedback signal, and to output an output signal, a first integrator to receive the output signal and a second feedback signal, to integrate the output signal and the second feedback signal, and to output the first feedback signal, a second integrator to receive the first feedback signal, to integrate the first feedback signal, and to output the second feedback signal, a sample and hold to receive the output signal, to periodically store a value of the output signal, and to output the value of the output signal, and a first switch to couple the sample and hold to the output signal when the sample and hold is to store the value of the output signal and to isolate the sample and hold from the output signal when the sample and hold is to output the value of the output signal. | 2008-09-18 |
20080224765 | Control interface and protocol - In one embodiment, a method for a control interface includes: receiving a signal conveying bits of information over a single line; and for each bit of information, comparing the proportion of time that the signal on the single line is low versus the proportion of time that the signal on the single line is high for a respective bit period defined from one operative edge of the signal to the next operative edge of the signal in order to determine a logic value for that bit of information. | 2008-09-18 |
20080224766 | DEMODULATION CIRCUIT - A modulation ratio enhancement circuit increases the modulation ratio of a current signal which is ASK-modulated with signal data. A branch unit, an average value detection unit, a comparator and a buffer constitute a demodulation unit so that the signal data is demodulated from a current signal of which the modulation ratio is increased by the modulation ratio enhancement circuit. | 2008-09-18 |
20080224767 | SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD FOR ADJUSTING A CAPACITANCE VALUE OF A PHASE COMPENSATING CAPACITOR - A semiconductor integrated circuit has an amplifier circuit which includes a phase compensating capacitor and has a feedback loop, and a stability determining and adjusting circuit which measures an amplitude of a voltage outputted from the amplifier circuit at a predetermined plurality of frequencies and adjusts a capacitance value of the phase compensating capacitor on the basis of a ratio between measured values of the amplitude. | 2008-09-18 |