38th week of 2020 patent applcation highlights part 72 |
Patent application number | Title | Published |
20200295734 | ACOUSTIC WAVE FILTER, MULTIPLEXER, AND COMMUNICATION APPARATUS - An acoustic wave filter | 2020-09-17 |
20200295735 | FILTER DEVICE AND MULTIPLEXER - A filter device utilizing surface acoustic waves includes one or more series arm resonators connected to each other along a path between a first input/output terminal and a second input/output terminal, and three or more parallel arm resonators each connected between a connection node provided on the path and ground and defining the pass band of the filter device. Parallel arm resonators having different anti-resonant frequencies from each other are included. Parallel arm resonators among the three or more parallel arm resonators are connected to the same connection node provided along the path. Remaining parallel arm resonators are connected to different connection nodes from the same connection node. The anti-resonant frequencies of the parallel arm resonators connected to the same connection node are identical and are the lowest anti-resonant frequencies among the anti-resonant frequencies of the three or more parallel arm resonators. | 2020-09-17 |
20200295736 | MULTIPLEXER, RADIO-FREQUENCY MODULE, AND COMMUNICATION DEVICE - Provided is a multiplexer that includes a first filter (first transmission filter), a second filter (second reception filter), a third filter (third reception filter), a first inductor, and a second inductor. The first inductor is connected in series with one parallel arm resonator (second parallel arm resonator) of the first filter between the one parallel arm resonator and ground. The second inductor is connected in series with another parallel arm resonator (third parallel arm resonator) of the first filter between the other parallel arm resonator and ground. The first inductor and the second inductor have the same winding direction as each other from the first filter side toward the ground side thereof. | 2020-09-17 |
20200295737 | MULTIPLEXER - A multiplexer includes a common terminal, a first terminal, a second terminal, a first filter device including acoustic wave resonators including series resonators and parallel resonators, an inductor provided between an acoustic wave resonator and the first terminal, and a second filter device. The first filter device further includes a first ground terminal to which a parallel resonator is electrically connected, a second ground terminal to which the parallel resonators are electrically connected, and a wiring provided between the inductor and an acoustic wave resonator. In the first filter device, the wiring is electrically connected to the first ground terminal, and the first ground terminal is not connected to the second ground terminal. | 2020-09-17 |
20200295738 | DYNAMIC SIGNAL PROCESSING - As part of a signal processing event, the maximum frequency of an input signal can be determined with a processor. The maximum frequency can be compared to a value generated with a decimator/interpolator. Based on the comparison, the sampling rate for sampling the input signal with the processor can be set as part of the digital signal processing event. The sampling rate can be adjusted as the frequency of the input signal varies during the signal processing event. | 2020-09-17 |
20200295739 | INTEGRATING RAMP CIRCUIT WITH REDUCED RAMP SETTLING TIME - A ramp generator includes an integrator including a first stage having first and second inputs and first and second outputs, and a second stage including first and second transistors coupled between a power supply rail and ground. A node between the first and second transistors is coupled to the output of the integrator amplifier. A control terminal of the first transistor is coupled to the first output of the first stage, and a control terminal of the second transistor is coupled to the second output of the first stage. A first current flows from the output to ground during a ramp event in the ramp signal generated from the output. Trimming circuitry is coupled to the output of the integrator amplifier to provide a second current to the output of the integrator amplifier in response to trimming inputs. The second current substantially matches the first current. | 2020-09-17 |
20200295740 | SYSTEM AND METHOD FOR NARROW BAND NEGATIVE FEEDBACK CONTROL - A system, feedback controller and method are disclosed. For example, the feedback controller includes a phase-sensitive quadrature controller configured to generate a first control signal associated with a controlled signal, a phase-sensitive in-phase controller configured to generate a second control signal associated with the controlled signal, a summer configured to add the first control signal and the second control signal, and a subtractor configured to subtract the summed first and second control signals from an uncontrolled signal. | 2020-09-17 |
20200295741 | DIGITAL NOISE FILTER - An aspect of the present invention provides a digital noise filter capable of reducing jitter. A digital noise filter ( | 2020-09-17 |
20200295742 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a memory cell array, first to third circuits. The first circuit is configured to control duty cycles of first and second signals based on a third signal, and output fourth and fifth signals. The second circuit is configured to acquire information regarding duty cycles. The third circuit is configured to control the third signal. The second circuit includes a switching circuit and a comparator. The switching circuit is configured to transfer the fourth and fifth signals to first and second nodes. The comparator is configured to compare a signal voltages in the first and second nodes, and output the comparison result to the third circuit. | 2020-09-17 |
20200295743 | POWER CIRCUIT SWITCHING DEVICE HAVING A PASSIVE PROTECTION CIRCUIT - A power circuit switching device comprises two switching terminals, a high-voltage depletion mode transistor and a low-voltage enhancement mode transistor arranged in series between the two switching terminals, a first terminal for receiving a switching signal and electrically connected via a driver circuit to the gate of the high-voltage transistor, and a second terminal for receiving a control signal and electrically connected to the gate of the low-voltage transistor. The device comprises a normally-on protection circuit electrically connected between the second terminal and the gate of the high-voltage transistor to keep the high-voltage transistor in an off-state when the driver circuit is not electrically powered. | 2020-09-17 |
20200295744 | SEMICONDUCTOR INTEGRATED CIRCUIT - According to one embodiment, there is provided a semiconductor integrated circuit including a first switch transistor, a first reference transistor, a differential amplifier circuit, and a current source. The first switch transistor is electrically connected between a first node on an input terminal side and a second node on an output terminal side. The first reference transistor is electrically connected between the first node and a third node. The differential amplifier circuit has a first input terminal electrically connected to the second node, a second input terminal electrically connected to the third node, and an output terminal electrically connected to a gate of the first switch transistor and a gate of the first reference transistor. The current source is electrically connected between the third node and a reference potential. The first reference transistor has dimensions smaller than dimensions of the first switch transistor. | 2020-09-17 |
20200295745 | HIGH-SIDE GATE DRIVER - A selection circuit generates a voltage V | 2020-09-17 |
20200295746 | DRIVE CONTROL DEVICE, DRIVE CIRCUIT, AND VEHICLE - Provided is a drive control device including: a first output node coupled to a gate node of a high-side transistor; a second output node coupled to a drive node; a first transistor provided between a first power supply node and the first output node; and a current limiting circuit and a second transistor provided in series between the first output node and the second output node, in which the current limiting circuit limits a current from the drive node toward the first output node to a predetermined value. The current limiting circuit is, for example, a transistor having a direction opposite to that of the second transistor. | 2020-09-17 |
20200295747 | SWITCHING APPARATUS AND METHOD FOR OPERATING A SWITCHING APPARATUS - A switching apparatus electrically connects an electrical load to an energy source and contains a main current path which has a switching unit with a circuit breaker, via which the electrical load is connected to the energy source in a supply mode. An auxiliary current path is connected in parallel with the main current path and in which a first switch is arranged. A disconnection mode is performed in which the circuit breaker is open and the electrical load is connected only to the auxiliary current path to reduce electrical energy stored inside the electrical load. A diagnostic mode is also provided, in which the switching unit is open and the electrical load is connected to the energy source only via the auxiliary current path to supply the electrical load. A control unit for activating the diagnostic mode is also provided. | 2020-09-17 |
20200295748 | SOURCE DOWN POWER FET WITH INTEGRATED TEMPERATURE SENSOR - A device includes an epitaxial layer located over a semiconductor substrate, the epitaxial layer and the substrate both having a first conductivity type. A field-effect transistor (FET) includes source and drain regions having an opposite second conductivity type disposed in the epitaxial layer, and a gate structure over the substrate and between the source and drain regions. A diode includes first and second p-type regions and an n-type region all disposed in the epitaxial layer, the n-type region touching the first p-type region. A conductive plug electrically connects the first p-type region to the source region via the substrate. | 2020-09-17 |
20200295749 | DRIVE CIRCUIT - A drive circuit of a power device, including an internal power supply, a set-side pulse generation circuit and a reset-side pulse generation circuit that are connected to the internal power supply, for generating a set signal and a reset signal respectively upon detecting that a logic input signal changes from a first logic level to a second logic level, or changes from the second logic level to the first logic level, a set-side level shift circuit and a reset-side level shift circuit that respectively level-shift the set signal and the reset signal, a control circuit that turns on and off the power device respectively responsive to the level-shifted set signal and the level-shifted reset signal, and an ensuring circuit that ensures a first state and a second state, in which the power device is respectively off and on, when the logic input signal is at the first logic level and the second logic level. | 2020-09-17 |
20200295750 | Devices and Methods for Improving Voltage Handling and/or Bi-Directionality of Stacks of Elements When Connected Between Terminals - Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack. | 2020-09-17 |
20200295751 | METHOD AND APPARATUS FOR USE IN IMPROVING LINEARITY OF MOSFETS USING AN ACCUMULATED CHARGE SINK - A method and apparatus for use in improving the linearity characteristics of MOSFET devices using an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one exemplary embodiment, a circuit having at least one SOI MOSFET is configured to operate in an accumulated charge regime. An accumulated charge sink, operatively coupled to the body of the SOI MOSFET, eliminates, removes or otherwise controls accumulated charge when the FET is operated in the accumulated charge regime, thereby reducing the nonlinearity of the parasitic off-state source-to-drain capacitance of the SOI MOSFET. In RF switch circuits implemented with the improved SOI MOSFET devices, harmonic and intermodulation distortion is reduced by removing or otherwise controlling the accumulated charge when the SOI MOSFET operates in an accumulated charge regime. | 2020-09-17 |
20200295752 | Chip Reset via Communication Interface Terminals - In an embodiment, an integrated circuit includes a communication interface configured to be coupled to a communication bus and an input circuit. The communication interface has a plurality of terminals. The input circuit has a first input coupled to a first terminal of the plurality of terminals, and a second input coupled to a second terminal of the plurality of terminals. The first input of the input circuit is configured to receive a first signal and the second input of the input circuit is configured to receive a second signal. The input circuit is configured to generate a reset signal at an output of the input circuit based on the first and second signals while the communication interface is unselected. | 2020-09-17 |
20200295753 | CIRCUIT STRUCTURE AND POWER-ON METHOD THEREOF - A circuit structure is electrically connected to a power source. The circuit structure includes a first circuit module and a second circuit module. The first circuit module includes a first module power switch and a plurality of circuits. The first module power switch is electrically connected to the power source. The first circuit module has a first module current. The second circuit module includes a second module power switch and a plurality of circuits. The second power switch is electrically connected to the power source. The second circuit module has a second module current. A turn-on order of the first module power switch and the second power switch is determined based on the first module current and the second module current. | 2020-09-17 |
20200295754 | SWITCH NETWORK HOUSING - A housing for a switch network is provided, comprising a plurality of switch blocks, each of the switch blocks being adapted to receive a radio frequency switch, and one or more interlink waveguides. At least one of the waveguides is arranged to connect a respective two or more of the switch blocks to each other and arranged externally with respect to the two switch blocks. At least one of the one or more waveguides is integrally formed with at least one of the switch blocks. A method of manufacturing the housing is also provided. | 2020-09-17 |
20200295755 | BUS DRIVER WITH RISE/FALL TIME CONTROL - A driver includes an open drain output transistor, a capacitor, a first current source, and first and second transistors. Upon assertion of a transmit signal to turn on the first transistor, a controller asserts a second control signal to turn on the second transistor responsive to a voltage of the capacitor being less than a threshold voltage of the open drain output transistor to thereby increase the control terminal voltage for the open drain output transistor at a first time rate. The controller deasserts the second control signal to turn off the second transistor responsive to the capacitor voltage exceeding the threshold voltage. Responsive to the capacitor's voltage exceeding the threshold, the first current source charges the capacitor to further increase the control terminal voltage at a second time rate that is smaller than the first time rate. | 2020-09-17 |
20200295756 | Self-Powered Wireless Switch and Applications Thereof - A self-powered wireless switch includes at least one micro generator and a control panel for transmitting wireless control signals, the micro generator including a magnet assembly and a coil assembly being moved relatively to one another to generate an induced current within the coil assembly; the coil assembly including an iron core and a wire winding around the outside of the iron core to form a magnetic coil; the magnet assembly including a permanent magnet and magnet conductive plates arranged at two sides of the opposite magnetic poles of the permanent magnet. The self-powered wireless switch enables the magnetic assembly and the coil assembly to move relatively to one another and converts the mechanical energy to electricity, thereby achieving self-power generation and providing electricity to the control panel for transmission of wireless control signals. | 2020-09-17 |
20200295757 | MEMORY DEVICE - A memory device comprising: a plurality of memories, a plurality of access units and a controller configured to control data from an access unit according to operation cycle different to another access unit whose form factor is different to that of the access unit. | 2020-09-17 |
20200295758 | LOW POWER INTEGRATED CLOCK GATING SYSTEM AND METHOD - According to one general aspect, an apparatus may include a latch circuit configured to, depending in part upon a state or at least one enable signal, pass a clock signal to an output signal. The latch circuit may include an input stage controlled by the clock signal and the enable signal(s). The latch may include an output stage configured to produce the output signal. The input and output stages may share a common transistor controlled by the clock signal. | 2020-09-17 |
20200295759 | DRIVE CIRCUIT - A drive circuit of a power device, including a set-side level shift circuit that receives a set signal and generates a level-shifted set signal, a reset-side level shift circuit that receives a reset signal and generates a level-shifted reset signal, a control circuit that is connected to the set-side level shift circuit and the reset-side level shift circuit, and that outputs a drive signal, a level of the drive signal changing between a first logic level for turning off the power device based on the level-shifted reset signal and a second logic level for turning on the power device based on the level-shifted set signal, and an ensuring circuit that ensures, based on the drive signal, that the control circuit controls to turn on the power device responsive to the level-shifted set signal, and to turn off the power device responsive to the level-shifted reset signal. | 2020-09-17 |
20200295760 | Interface Circuit - An interface circuit includes a phase inverter. An input end of the phase inverter is connected to a signal output end of a first power domain circuit, and an output end of the phase inverter is connected to a signal input end of a second power domain circuit. A power end of the phase inverter is connected to a power supply of the first power domain circuit, and a ground end of the phase inverter is connected to a reference ground of the second power domain circuit. Alternatively, a power end of the phase inverter is connected to a power supply of the second power domain circuit, and a ground end of the phase inverter is connected to a reference ground of the first power domain circuit. | 2020-09-17 |
20200295761 | RECONFIGURABLE CIRCUIT AND THE METHOD FOR USING THE SAME - A reconfigurable circuit comprising: a first line; a first switch element disposed between the first line and a first power source line of first voltage; a second line; a second switch element disposed between the second line and a second power source line of second voltage which is different from the first voltage; and a resistive switch assembly disposed between the first line and the second line. The resistive switch assembly including a first non-volatile resistive switch, and a second non-volatile resistive switch whose first end is coupled to a first end of the first non-volatile resistive switch. The second end of the first non-volatile resistive switch is coupled to the first line, and the second end of the second non-volatile resistive switch is coupled to the second line. | 2020-09-17 |
20200295762 | Multiplier-Accumulator Circuitry, and Processing Pipeline including Same - An integrated circuit comprising a plurality of multiply-accumulator circuitry, configurable in a concatenation architecture, to perform a plurality of multiply and accumulate operations, wherein the plurality of multiply-accumulator circuitry is organized into a plurality of groups, including a first group of multiply-accumulator circuitry and a second group of multiply-accumulator circuitry, wherein each group includes: a plurality of MAC circuits, each including a multiplier to multiply data by a multiplier weight data and generate a product data, and an accumulator to add input data and the product data to generate sum data, and wherein the plurality of MAC circuits of each group is organized in at least one row and connected in series to perform a plurality of concatenated multiply and accumulate operations. The integrated circuit also includes configurable interface circuitry to connect and/or disconnect the plurality of MAC circuits of the first and second groups of multiply-accumulator circuitry. | 2020-09-17 |
20200295763 | PHYSICALLY UNCLONABLE CAMOUFLAGE STRUCTURE AND METHODS FOR FABRICATING SAME - An application specific integrated circuit (ASIC) and a method for its design and fabrication is disclosed. In one embodiment, the camouflaged application specific integrated circuit (ASIC), comprises a plurality of interconnected functional logic cells that together perform one or more ASIC logical functions, wherein the functional logic cells comprise a camouflage cell including: a source region of a first conductivity type, a drain region of the first conductivity type, and a camouflage region of a second conductivity type disposed between the source region and the drain region. The camouflage region renders the camouflage cell always off in a first camouflage cell configuration and always on in a second camouflage cell configuration having a planar layout substantially indistinguishable from the first configuration. | 2020-09-17 |
20200295764 | RECONFIGURABLE CIRCUIT AND THE METHOD FOR USING THE SAME - A reconfigurable circuit includes: a first line; a first switch element disposed between the first line and a first power source line of first voltage; a second line; a second switch element disposed between the second line and a second power source line of second voltage which is different from the first voltage; and a resistive switch assembly disposed between the first line and the second line. The resistive switch assembly includes: a first non-volatile resistive switch; and a second non-volatile resistive switch whose first end is coupled to a first end of the first non-volatile resistive switch. The second end of the first non-volatile resistive switch is coupled to the first line, and the second end of the second non-volatile resistive switch is coupled to the second line. | 2020-09-17 |
20200295765 | QUADRATURE LOCAL OSCILLATOR SIGNAL GENERATION SYSTEMS AND METHODS - A quadrature based voltage controlled oscillator (VCO) local oscillator (LO) system is disclosed. The system includes a phase detector, a quadrature phase VCO, a quadrature control path, an in-phase control path, and an in-phase VCO. The phase detector is configured to compare and generate phase error between a reference clock and an in-phase VCO output. The quadrature control path configured to generate a quadrature control voltage based on a quadrature VCO output and the in-phase VCO output. The quadrature phase VCO configured to generate the quadrature VCO output based on the quadrature control voltage and the generated phase error. The in-phase control path configured to generate an in-phase control voltage based on the quadrature VCO output and the in-phase VCO output. The in-phase VCO is configured to generate the in-phase VCO output based on the in-phase control voltage and the generated phase error. An all digital dual mode phase locked/phase tracking loop LO generate system is also disclosed. | 2020-09-17 |
20200295766 | FAST PHASE FREQUENCY DETECTOR - Disclosed a fast phase frequency detector, comprising: two fast pulsed-latches, a NAND gate and an adjustable delay circuit. The fast pulsed-latches comprises: a pulse generating circuit, a reset circuit, and an output latch circuit; the pulse generating circuit is configured to generate a power supply pulse signal when a rising edge of the clock signal arrives, the power supply pulse signal causing the input of the output latch circuit to be a low level; the output latch circuit is configured to maintain its current output state when the clock signal or the reset signal is invalid; the reset circuit is configured to set the input of the output latch circuit to be a high level. By using fast pulsed-latches with clock and reset control, the fast phase frequency detector of the present application shortens the reset loop delay and increases the maximum operating frequency of the phase frequency detector. | 2020-09-17 |
20200295767 | CHARGE PUMP WITH LOAD DRIVING CLOCK FREQUENCY MANAGEMENT - A charge pump circuit has load driven clock frequency management. The charge pump circuit includes a CCO generating a CCO output signal that has a frequency generally proportional to a feedback current, and a charge pump operated by the CCO output signal and boosting a supply voltage to produce a charge pump output voltage at an output coupled to a load. A current sensing circuit senses a load current drawn by the load and generates the feedback current as having a magnitude that varies as a function of the sensed load current if a magnitude of the load current is between a lower load current threshold and an upper load current threshold. The magnitude of the feedback current does not vary with the sensed load current if the magnitude of the sensed load current is not between the lower load current threshold and the upper load current threshold. | 2020-09-17 |
20200295768 | CRYSTAL-FREE OSCILLATOR FOR CHANNEL-BASED HIGH-FREQUENCY RADIO COMMUNICATION - The present invention relates to a crystal-free oscillator circuit ( | 2020-09-17 |
20200295769 | PHASE MODULATOR HAVING FRACTIONAL SAMPLE INTERVAL TIMING SKEW FOR FREQUENCY CONTROL INPUT - An example method in accordance with some embodiments includes: determining an output frequency control word (FCW) having a plurality of bits, the output FCW being configured to control an oscillator, the oscillator including a plurality of capacitor banks, the plurality of capacitor banks respectively corresponding to the plurality of bits of the output FCW; storing the output FCW in a clocked delay cell; providing an input clock to the clocked delay cell, wherein the input clock is provided to delay the output FCW by an amount of delay; and, in accordance with the input clock, releasing the delayed output FCW from the clocked delay cell, and respectively applying the plurality of bits of the delayed output FCW to the plurality of capacitor banks of the oscillator. | 2020-09-17 |
20200295770 | FREQUENCY-CONVERTED SELF-INJECTION-LOCKED RADAR - By changing frequencies of an oscillation signal and an injection signal, a frequency-converted self-injection-locked radar has an oscillation frequency different to a frequency of a transmitted signal from a transceiver antenna element such that the frequency-converted self-injection-locked radar with high sensitivity and penetration or with high sensitivity and low cost is achieved. | 2020-09-17 |
20200295771 | LEAKAGE REDUCTION FOR MULTI-FUNCTION CONFIGURABLE CIRCUIT - Systems for monitoring or control can include reconfigurable input and output channels. Such reconfigurable channels can include as few as a single terminal and a ground pin, or such channels can include three or four terminal configuration such as for use in four-terminal resistance measurements. Channel reconfiguration can be accomplished such as using software-enabled or firmware-enabled control of channel hardware. Such channel hardware can include analog-to-digital and digital-to-analog conversion capability, including use of a digital-to-analog converter to provide field power or biasing. In an example, compensation can be provided to suppress a leakage current from flowing through a digital output to a load connected to the reconfigurable channel terminal, particularly when the digital output is disabled. | 2020-09-17 |
20200295772 | SIGNAL PROCESSING SYSTEM USING ANALOG-TO-DIGITAL CONVERTER WITH DIGITAL-TO-ANALOG CONVERTER CIRCUITS OPERATING IN DIFFERENT VOLTAGE DOMAINS AND EMPLOYING MISMATCH ERROR SHAPING TECHNIQUE AND ASSOCIATED SIGNAL PROCESSING METHOD - A signal processing system includes an analog-to-digital converter (ADC) that is used to convert a first analog value into a first digital value and convert a second analog value into a second digital value. The ADC includes a first digital-to-analog converter (DAC) circuit and a second DAC circuit operating in different voltage domains. A first bit segment and a second bit segment of each digital value are determined via the first DAC circuit and the second DAC circuit, respectively. An analog injection value is injected to the second analog value, the analog injection value is converted from a digital injection value formed by a subset of bits of the second bit segment of the first digital value, and the second bit segment of the second digital value is derived from injecting the digital injection value to a digital value determined by the second DAC circuit. | 2020-09-17 |
20200295773 | Analog to Digital (A/D) Converter with Internal Diagnostic Circuit - An analog to digital (A/D) converter includes a capacitor array having respective first terminals selectively coupled to a reference voltage or ground via a plurality of switches and having respective second terminals coupled to a sample and hold (S/H) output. The A/D converter also includes a voltage comparator having a first input coupled to the S/H output and having a second input coupled to a bias voltage. The voltage comparator is configured to output a comparison voltage responsive to a sampled charge at the S/H output and the bias voltage. The A/D converter also includes a successive approximation register coupled to receive the comparison voltage and configured to output an approximate digital code responsive to the comparison voltage, wherein the approximate digital code is varied by controlling an equivalent capacitance of the capacitor array. | 2020-09-17 |
20200295774 | METHOD AND CIRCUIT FOR CURRENT INTEGRATION - An input current (I | 2020-09-17 |
20200295775 | DIGITAL-TO-ANALOG CONVERSION CIRCUIT AND DATA DRIVER - A digital-to-analog conversion circuit includes: a decoder that, if set to a first selection state, selects two different reference voltages from a reference voltage group on the basis of a digital data signal and outputs the two reference voltages as first and second selection voltages, and if set to a second selection state, selects two reference voltages from the reference voltage group in a manner allowing redundancy and outputs the two reference voltages as the first and second selection voltages; and an amplifier circuit that amplifies and outputs a voltage obtained by averaging a combination of the first and second selection voltages with weighting factors set in advance. | 2020-09-17 |
20200295776 | DELTA-SIGMA MODULATOR WITH TRUNCATION ERROR COMPENSATION AND ASSOCIATED METHOD - A delta-sigma modulator includes a first combining circuit, a loop filter circuit, a quantizer circuit, a truncator circuit, a first digital-to-analog converter (DAC) circuit, and a compensation circuit. The first combining circuit generates a first analog signal by combining an analog feedback signal and an analog input signal. The loop filter circuit generates a loop-filtered signal according to the first analog signal. The quantizer circuit outputs a first digital signal that is indicative of a digital combination result of at least a truncation error compensation signal and the loop-filtered signal. The truncator circuit performs truncation upon the first digital signal to generate a second digital signal. The first DAC circuit generates the analog feedback signal according to the second digital signal. The compensation circuit generates the truncation error compensation signal according to a truncation error resulting from truncation performed upon the first digital signal. | 2020-09-17 |
20200295777 | METHODS AND APPARATUS FOR AN ANALOG-TO-DIGITAL CONVERTER - Various embodiments of the present technology may comprise methods and apparatus for an analog-to-digital converter. Methods and apparatus for an analog-to-digital converter (ADC) may be configured as a delta-sigma type ADC and include an integrator circuit formed using two switched-capacitor (SC) circuits that share a single operational amplifier. The switched-capacitor circuits receive various control signals such that one SC circuit performs sampling while the other SC circuit simultaneously performs integration. | 2020-09-17 |
20200295778 | BIT STRING CONVERSION - Systems, apparatuses, and methods related to bit string conversion are described. A memory resource and/or logic circuitry may be used in performance of bit string conversion operations. The logic circuitry can perform operations on bit strings, such as universal number and/or posit bit strings, to alter a level of precision (e.g., a dynamic range, resolution, etc.) of the bit strings. For instance, the memory resource can receive data comprising a bit string having a first quantity of bits that correspond to a first level of precision. The logic circuitry can determine that the bit string having the first quantity of bits has a particular data pattern and alter the first quantity of bits to a second quantity of bits that correspond to a second level of precision based, at least in part, on the determination that the bit string has the particular data pattern. | 2020-09-17 |
20200295779 | CONDITIONAL TRANSCODING FOR ENCODED DATA - A transcoder is disclosed. The transcoder may comprise a buffer to store input encoded data. An index mapper may map an input dictionary to an output dictionary. A current encode buffer may store a modified current encoded data, which may be responsive to the input encoded data, the input dictionary, and the map from the input dictionary to the output dictionary. A previous encode buffer may store a modified previous encoded data, which may be responsive to the input encoded data, the input dictionary, and the map from the input dictionary to the output dictionary. A rule evaluator may generate an output stream responsive to the modified current encoded data in the current encode buffer, the modified previous encoded data in the previous encode buffer, and transcoding rules. | 2020-09-17 |
20200295780 | VERIFYING THE CORRECTNESS OF A DEFLATE COMPRESSION ACCELERATOR - Embodiments of the invention are directed to a DEFLATE compression accelerator and to a method for verifying the correctness of the DEFLATE compression accelerator. The accelerator includes an input buffer and a Lempel-Ziv 77 (LZ77) compressor communicatively coupled to an output of the input buffer. A switch is communicatively coupled to the output of the input buffer and to the output of the LZ77 compressor. The switch is configured to bypass the LZ77 compressor during a compression test. The accelerator further includes a deflate Huffman encoder communicatively coupled to an output of the switch and an output buffer communicatively coupled to the deflate Huffman encoder. When the switch is not bypassed, the compressor can be modified to produce repeatable results. | 2020-09-17 |
20200295781 | VERIFYING THE CORRECTNESS OF A DEFLATE COMPRESSION ACCELERATOR - Embodiments of the invention are directed to a DEFLATE compression accelerator and to a method for verifying the correctness of the DEFLATE compression accelerator. The accelerator includes an input buffer and a Lempel-Ziv 77 (LZ77) compressor communicatively coupled to an output of the input buffer. A switch is communicatively coupled to the output of the input buffer and to the output of the LZ77 compressor. The switch is configured to bypass the LZ77 compressor during a compression test. The accelerator further includes a deflate Huffman encoder communicatively coupled to an output of the switch and an output buffer communicatively coupled to the deflate Huffman encoder. When the switch is not bypassed, the compressor can be modified to produce repeatable results. | 2020-09-17 |
20200295782 | APPARATUS AND METHOD FOR OFFSET OPTIMIZATION FOR LOW-DENSITY PARITY-CHECK (LDPC) CODE - An apparatus and method are provided. The apparatus includes a decoder including a first input configured to receive transport blocks, a second input, and an output configured to provide a decoded codeword, and an offset value updater including an input connected to the output of the decoder, and an output, connected to the second input of the decoder, configured to provide an updated offset value. | 2020-09-17 |
20200295783 | SUPER-HPC ERROR CORRECTION CODE - A memory controller is configured to perform first error correcting code (ECC) encoding on a plurality of first frames of data, generate a plurality of delta syndrome units corresponding, respectively, to the plurality of first frames of data, generate a delta syndrome codeword by performing second ECC encoding on the plurality of delta syndrome units, the delta syndrome codeword including one or more redundancy data units, perform third ECC encoding on at least one second frame of data such that the encoded at least one second frame of data is a first vector of bits, and determine a second vector of bits such that, adding the second vector of bits to the first vector of bits forms a combined vector of bits which is an ECC codeword having a delta syndrome a value of which is pre-fixed based on at least one of the one or more redundancy data units. | 2020-09-17 |
20200295784 | ACCELERATED ERASURE CODING SYSTEM AND METHOD - An accelerated erasure coding system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The processing core, storage medium, and computer instructions are configured to implement an erasure coding system, which includes: a data matrix for holding original data in the main memory; a check matrix for holding check data in the main memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the check data; and a thread for executing on the processing core. The thread includes: a parallel multiplier for concurrently multiplying multiple entries of the data matrix by a single entry of the encoding matrix; and a first sequencer for ordering operations through the data matrix and the encoding matrix using the parallel multiplier to generate the check data. | 2020-09-17 |
20200295785 | PIPELINED FORWARD ERROR CORRECTION FOR VECTOR SIGNALING CODE CHANNEL - Decoding sequentially received vector signaling codewords to obtain sequential sets of data bits, wherein elements of each vector signaling codeword are received in parallel over a plurality of wires, generating an incremental update of a plurality of error correction syndrome values based on each sequential set of data bits according to a check matrix, and upon decoding of a final vector signaling codeword, performing a final incremental update of the plurality of error correction syndrome values and responsively modifying data bits within the sequential sets of data bits by selecting a set of data bits from the sequential sets of data bits according to a symbol position index determined from the plurality of error correction syndrome values, the selected set of data bits altered according to a bit error mask determined from a first error correction syndrome value of the plurality of error correction syndrome values. | 2020-09-17 |
20200295786 | Adaptive-SCL Polar Decoder - A method of dynamically changing the list size of a successive cancellation list (SCL) decoder, the SCL decoder arranged to decode data received from a wireless communications system, the method comprising at each successive cancellation stage of the SCL decoder, determining a path metric of each path of the SCL decoder, selecting a differential path metric threshold, and dynamically changing the list size of the SCL decoder based on the differential path metric threshold and the path metric of each path of the cancellation stage, such that decoding sensitivity of the decoder is maintained and/or latency and error-correction performance of the decoder are balanced. | 2020-09-17 |
20200295787 | LOW LATENCY SEQUENTIAL LIST DECODING OF POLAR CODES - There is provided a method of recursive sequential list decoding of a codeword of a polar code comprising: obtaining an ordered sequence of constituent codes usable for the sequential decoding of the polar code, representable by a layered graph; generating a first candidate codeword (CCW) of a first constituent code, the first CCW being computed from an input model informative of a CCW of a second constituent code, the first constituent code and second constituent code being children of a third constituent code; using the first CCW and the second CCW to compute, by the decoder, a CCW of the third constituent code; using the CCW of the third constituent code to compute a group of symbol likelihoods indicating probabilities of symbols of a fourth (higher-layer) constituent code having been transmitted with a particular symbol value, and using the group of symbol likelihoods to decode the fourth constituent code. | 2020-09-17 |
20200295788 | NONVOLATILE MEMORY DEVICE AND READ AND COPY-BACK METHODS THEREOF - A read method of a nonvolatile memory device is provided. The method includes storing data sensed from selected memory cells of the nonvolatile memory device into a page buffer, performing an error decoding operation by performing error detection on the sensed data to detect and error, correcting the detected error if the error is detected, and overwriting the page buffer with the corrected data, and de-randomizing data stored in the page buffer by using a seed after the error decoding operation has completed. | 2020-09-17 |
20200295789 | Electronic Device With Millimeter Wave Antennas - An electronic device may be provided with wireless circuitry. The wireless circuitry may include one or more antennas. The antennas may include phased antenna arrays each of which includes multiple antenna elements. Phased antenna arrays may be mounted along edges of a housing for the electronic device, behind a dielectric window such as a dielectric logo window in the housing, in alignment with dielectric housing portions at corners of the housing, or elsewhere in the electronic device. A phased antenna array may include arrays of patch antenna elements on dielectric layers separated by a ground layer. A baseband processor may distribute wireless signals to the phased antenna arrays at intermediate frequencies over intermediate frequency signal paths. Transceiver circuits at the phased antenna arrays may include upconverters and downconverters coupled to the intermediate frequency signal paths. | 2020-09-17 |
20200295790 | DIGITAL PREDISTORTION OF SIGNALS - Systems, circuitries, and methods for predistorting a digital signal in a transmit chain based on a predistortion function are provided in which the function is determined based on a first digital signal or a first transmit chain state. A method includes: receiving a second digital signal that is input to the transmit chain, wherein the transmit chain is characterized by a present transmit chain state; performing a first operation on the second digital signal to generate an adapted digital signal, wherein the first operation is based on either a relationship between the first digital signal and the second digital signal, or a relationship between the first transmit chain state and the present transmit chain state; predistorting the adapted digital signal based on the predistortion function; and performing a second operation on the predistorted adapted signal, wherein the second operation corresponds to an inverse of the first operation. | 2020-09-17 |
20200295791 | SIGNAL PROCESSING DEVICE - A signal processing device includes a signal input, a signal output, a first amplifier, a second amplifier, a first distortion adjustment circuit, and a second distortion adjustment circuit. The signal input receives a RF signal to be amplified. The signal output outputs an amplified RF signal. Each of the first and second amplifiers includes an input coupled to the signal input and an output coupled to the signal output. The first distortion adjustment circuit includes a connection coupled to the input of the first amplifier. The second distortion adjustment circuit includes a connection coupled to the input of the second amplifier. The number of transistors in the first amplifier is different from the number of transistors in the second amplifier. | 2020-09-17 |
20200295792 | WIRELESS COMMUNICATION DEVICE - A receiver device includes an antenna that receives a high frequency signal having a bandwidth, a mixer connected to the antenna and a frequency multiplier. A filter that removes a noise signal whose frequency is different from that of the local signal is provided between the local oscillator and the frequency multiplier. The filter removes the noise signal that satisfies the condition that the absolute value of the frequency difference between the center frequency of the local signal and the center frequency of the noise signal is less than the bandwidth of the high frequency signal. | 2020-09-17 |
20200295793 | NONLINEAR SELF-INTERFERENCE CANCELLATION WITH SAMPLING RATE MISMATCH - A method for providing nonlinear self-interference cancellation of a wireless communication device includes: receiving digital samples of an interfering signal having a first sampling rate and a corrupted victim signal having a second sampling rate; generating a kernel vector based on the interfering signal, wherein the kernel vector has terms of nonlinear self-interference; estimating the nonlinear self-interference of the corrupted victim signal using the terms of the nonlinear self-interference; and providing an estimation of a desired signal by cancelling the nonlinear self-interference from the corrupted victim signal. | 2020-09-17 |
20200295794 | CONSOLIDATION OF CONTROLS ON AN AIRCRAFT RADIO - Methods and apparatus are provided for displaying the operational parameters of a radio system located onboard an aircraft. The apparatus comprises a permanent radio display bar that shows an active radio frequency in use by the radio system and a variable radio display pad. The variable radio display pad shows multiple historical past radio frequencies previously used by the radio system and multiple predicted future radio frequencies for use along a flight plan of the aircraft. It includes a change command that allows a crew member to manually change the active radio frequency in the permanent radio display bar. | 2020-09-17 |
20200295795 | CO-MOLDED MULTI-LAYERED PROTECTIVE CASE FOR MOBILE DEVICE - A protective case for a mobile device having a multi-layered construction is disclosed herein. The multi-layered construction includes three layers that are co-molded to one another. The construction is lightweight and low-profile, and also provides a high level of impact protection. The first layer generally forms the external back face surface of the case, the third layer generally forms the perimeter bumper of the case, and the second layer forms the internal liner and includes an elevated pattern of walls upon which the back face of the mobile device rests. The first layer is comprised of material that has a hardness greater than the other two layers. The third layer is comprised of a material that has a hardness that is greater than the hardness of the second layer. The layers are configured to interact with one another to distribute and absorb impact forces. | 2020-09-17 |
20200295796 | MOBILE PHONE CASE - A mobile phone case is provided for two phones that is capable of storing two mobile phones simultaneously. To this end, the mobile phone case for two phones according to the present invention includes a first case having a first support means on which a first mobile phone is mounted, and a second case having a second support means on which a second mobile phone is mounted. A third case is disposed between the first case and the second case. A first connecting portion is configured to connect the first case and the third case, and a second connecting portion is configured to connect the second case and the third case. A vertical width or a horizontal width of at least one of the first support means and the second support means is changeable. | 2020-09-17 |
20200295797 | SYSTEMS AND METHODS FOR GENERATING RADIO FREQUENCY SIGNALS - The present embodiments are directed to a device for generating radio frequency signals, including high power radio frequency signals. In certain embodiments, the device comprises multiple transmission lines driven in parallel at their input and connected in series at their output. The electromagnetic transit lengths of the transmission lines may be unequal. A series connection of the transmission lines at the output may produce an output signal from each transmission line driving the same polarity signal to the load. The series connection of transmission lines at the output may produce a bipolar output signal. One section of the device may convert a unipolar input signal into a bipolar signal. One section of the device may duplicate the input signal. Multiple sections may be arranged to convert a unipolar input signal into multiple radio frequency oscillations. | 2020-09-17 |
20200295798 | TRANSMIT-RECEIVE SWITCH WITH INTEGRATED POWER DETECTION - An apparatus includes a transmit-receive switch circuit and a detector circuit. The transmit-receive switch circuit may be connected between an input port, an output port, and a common port, and configured to switch a transmit radio-frequency signal from the input port to the common port in a transmit mode and a receive radio-frequency signal from the common port to the output port in a receive mode. The detector circuit may be integrated within the transmit-receive switch and may be configured to generate a power detection signal in response to at least one of the transmit radio-frequency signal or the receive radio-frequency signal. | 2020-09-17 |
20200295799 | RANDOM, SEQUENTIAL, OR SIMULTANEOUS MULTI-BEAM CIRCULAR ANTENNA ARRAY AND BEAM FORMING NETWORKS WITH UP TO 360.degree. COVERAGE - A beam forming network system includes a first beam forming network having first and second ports, in which each of the first ports is operatively coupled to an antenna element; and a second beam forming network including third and fourth ports, in which each of the third ports is operatively coupled to one of the second ports using at least one of a phase shifter, attenuator, power divider, and/or hybrid coupler. A method of beam forming includes coupling each of the first ports associated with a first beam forming network operatively to one antenna element, and coupling each of the third ports associated with a second beam forming network operatively to one of the second ports associated with the first beam forming network using at least one of a phase shifter, attenuator, power divider, and/or hybrid coupler. | 2020-09-17 |
20200295800 | Base Station Coordination for Cross-Link Interference Cancelation - Techniques and apparatuses are described for enabling base stations ( | 2020-09-17 |
20200295801 | WALL PLATE DATA/POWER EXCHANGE SYSTEM - Wall plates having integrated charging and/or data exchange components are described herein. The wall plates include a rearwardly protruding outlet connector to electrically couple the charging components with an electrical outlet and a data and/or power exchanging device. The data and/or power exchanging device can provide a wired or wireless connection to perform data exchanging functions and/or to charge the power source of a portable electronic device. | 2020-09-17 |
20200295802 | ADAPTIVE TONE POWER CONTROL IN PLC NETWORKS - In a powerline communications (PLC) network having a first node and at least a second node on a PLC channel utilizing a band including a plurality of tones, based on at least one channel quality indicator (CQI), the first node allocates for a tone map response payload only a single (1) power control bit for each of a plurality of subbands having two or more tones. The power control bit indicates a first power state or a second power state. The first node transmits a frame including the tone map response payload to the second node. The second node transmits a frame having boosted signal power for the tones in the subbands which have the first power state compared to a lower signal power for the tones in the subbands which have the second power state. | 2020-09-17 |
20200295803 | POWER-DATA DISTRIBUTION SYSTEM, FITTINGS, AND DEVICES - Various embodiments of a power-data distribution system, fittings, and devices are disclosed. In one embodiment, a power-data system comprises: an overhead power distribution system, including: a strut, a conductor wire within the strut, and an upper fitting engagement ledge; and a power-data device, including: a combined power and network output fitter mechanically engaged to the strut, the fitter including a fitter engagement element mechanically engaged to the upper fitting engagement ledge, the fitter including a conductor element able to move into the fitter and having at least one biasing element within the fitter; a powerline chipset, the powerline chipset including a powerline chipset and to an ethernet port; a data receiving device/power receiving device, the data receiving device/power receiving device including an ethernet port; and the ethernet port of the powerline chipset and the ethernet port of the data receiving device/power receiving device being connected by a transmission cable. | 2020-09-17 |
20200295804 | ANTENNA DEVICE AND ASSOCIATED APPARATUS - An antenna device for use with a wireless power charging operation and a near-field communication (NFC) operation is formed sets of electrically conductive loops. The sets include a first set of loops configured to form a NFC antenna and a second set of loops. The first and second sets of loops together are configured to form a wireless power charging antenna. | 2020-09-17 |
20200295805 | Low-Latency Inter-eNodeB Coordinated Multi-Point Transmission - Systems and methods are disclosed for supporting multi-point transmission. In one embodiment, a system for downlink multi-point transmission are disclosed, comprising: a first base station in radio frequency proximity to a user device and with a established control connection with the user device; a second base station also in radio frequency proximity to the user device; and a coordinating node coupled to the first and the second base station for coordinating transmissions to the first and the second base station to the user device, the coordinating node configured to: select the second base station based on selection criteria, the selection criteria including latency of each base station and perceived signal strength of each base station at the user device; and send scheduling instructions to each of the first and the second base stations to transmit data to the user device. | 2020-09-17 |
20200295806 | ANTENNA PATTERN MATCHING AND MOUNTING - A technique for improving wireless communication characteristics involving matching transmitter antenna patterns to receiver antenna patterns. In a specific implementation, the transmitter antenna pattern adapts to changing parameters, such as when a smartphone is initially held in a first orientation and is later held in a second orientation. Because the transmitter antenna pattern matches receiver antenna patterns, signal quality between stations improves. In some implementations, antennas are organized and mounted to maximize spatial diversity to cause peak gains in different directions. | 2020-09-17 |
20200295807 | CODEBOOK SUBSET RESTRICTION METHOD - A bit field indication manner is provided. A first field is determined, where the first field includes T | 2020-09-17 |
20200295808 | SIGNAL GENERATION METHOD AND SIGNAL GENERATION DEVICE - A transmission method simultaneously transmitting a first modulated signal and a second modulated signal at a common frequency performs precoding on both signals using a fixed precoding matrix and regularly changes the phase of at least one of the signals, thereby improving received data signal quality for a reception device. | 2020-09-17 |
20200295809 | LINEAR COMBINATION CODEBOOK BASED PER LAYER POWER ALLOCATION FEEDBACK FOR 5G OR OTHER NEXT GENERATION NETWORK - An enhanced linear combination codebook framework can support power allocation between transmission layers. Scaling between the layers of the codebook can be unequal so that power allocated between the layers can depend on the channel. For example, the network can configure the codebook to use radio resource control signaling to send codebook data to the user equipment. | 2020-09-17 |
20200295810 | ACKNOWLEDGEMENT SIGNALING FOR RADIO ACCESS NETWORKS - There is disclosed a method of operating a feedback radio node in a radio access network, the feedback radio node being configured with a set of feedback codebooks. Each codebook of the set indicates an arrangement of one or more subpatterns of feedback bits into feedback information. The method includes transmitting feedback signaling representing feedback information determined based on a codebook selected from the set of feedback codebooks. The disclosure also pertains to related methods and devices. | 2020-09-17 |
20200295811 | TRANSMISSION METHOD, TRANSMISSION DEVICE, RECEPTION METHOD AND RECEPTION DEVICE - A transmission method includes generating a first precoded signal and a second precoded signal by performing a precoding process on a first baseband signal and a second baseband signal, outputting a third signal by inserting a pilot signal into the first precoded signal, outputting a fourth signal by applying a first phase change to the second precoded signal, outputting a fifth signal by inserting a pilot signal into the fourth signal, and outputting a sixth signal by applying a second phase change to the fifth signal. | 2020-09-17 |
20200295812 | METHOD AND APPARATUS FOR MULTIPLEXING AND OMITTING CHANNEL STATE INFORMATION - A method for operating a UE for CSI reporting in a wireless communication system is provided. The method comprises receiving, from a BS, configuration information for a CSI report, the CSI report comprising a first CSI part and a second CSI part, the second CSI part including a total of K | 2020-09-17 |
20200295813 | METHOD AND APPARATUS FOR CODEBOOK SUBSET RESTRICTION - A method for operating a user equipment (UE) for channel state information (CSI) reporting in a wireless communication system comprises receiving, from a base station (BS), higher layer signaling including codebook subset restriction (CBSR) information, determining a bitmap sequence B based on the CBSR information, identifying, based on a portion of the bitmap sequence B, a restriction on P spatial domain (SD) vector groups out of a total of Q SD vector groups, generating a CSI report based on the P SD vector groups with the identified restriction and remaining Q minus P SD vector groups without any restrictions, and transmitting the CSI report to the BS, wherein the restriction on P SD vector groups corresponds to restricting an average amplitude (A | 2020-09-17 |
20200295814 | CHANNEL STATE INFORMATION REFERENCE SIGNAL - In a Multiple-Input Multiple-Output (MIMO) system including a large number of antenna ports, a base station such as a Node B communicates a total number of antenna ports by communicating the number of antenna ports per Channel State Information Reference Signal (CSI-RS) configuration and one or more CSI-RS configurations. A User Equipment determines the number of antenna ports from the information communicated by the base station by determining the number of CSI-RS configurations sent by the base station and multiplying that number by the number of antenna ports per CSI-RS configuration indicated by the base station. | 2020-09-17 |
20200295815 | TRANSMISSION METHOD, TRANSMISSION DEVICE, AND COMMUNICATION SYSTEM - An indicator in a master AP from among a plurality of APs obtains communication quality of communication with an AP which is a communication partner. In the case where the obtained communication quality is less than a threshold, the indicator causes the plurality of APs including the master AP to perform cooperative operation to transmit data. In the case where the obtained communication quality is not less than the threshold, the indicator causes the plurality of APs including the master AP to stop the cooperative operation. | 2020-09-17 |
20200295816 | APPARATUS AND METHOD FOR ESTIMATING DIRECTION OF ARRIVAL IN MIMO SYSTEM - An apparatus for estimating a DOA in a MIMO system includes a receiver and a signal processor. The receiver receives Rx signals from a target through Rx antennas after Tx signals having different phases are transmitted through Tx antennas, and transforms the Rx signals into time domain Rx signals. The processor transforms the time domain Rx signals into Rx signals in a frequency domain including a range-related domain and a velocity-related doppler domain; divides the doppler domain into regions according to a phase difference between the Tx signals; extracts signals from the regions; combines the signals to form first and second arrays; determines a minimum value for each of the first and second arrays using a DML algorithm; selects one of the first and second arrays having the minimum value as a true array; and estimates a DOA corresponding to the true array as an actual DOA of the target. | 2020-09-17 |
20200295817 | BEAMFORMING DEVICE AND METHOD, COMMUNICATION DEVICE AND COMMUNICATION SYSTEM - The improved beamforming devices for communication systems operating in the mm-wave spectrum are particularly designed for antenna architectures consisting of antenna arrays, comprising multiple antenna array elements. The disclosed approaches comprise intelligent two stage searches, wherein information from the first stage is used in the second stage. This significantly reduces the computational complexity compared to the known approaches, with minimal loss in performance. | 2020-09-17 |
20200295818 | MULTIPLE ANTENNA REPEATER ARCHITECTURE - Technology for a desktop signal booster is disclosed. The desktop signal booster can include a cellular signal amplifier, an integrated device antenna coupled to the cellular signal amplifier, an integrated node antenna coupled to the cellular signal amplifier, and wireless charging circuitry. The cellular signal amplifier can be configured to amplify signals for a wireless device, and the wireless device can be within a selected distance from the desktop signal booster. The integrated device antenna can be configured to transmit signals from the cellular signal amplifier to the wireless device. The integrated node antenna can be configured to transmit signals from the cellular signal amplifier to a base station. The wireless charging circuitry can be configured to wirelessly charge the wireless device when the wireless device is placed in proximity to the desktop signal booster. | 2020-09-17 |
20200295819 | WIRELESS VIDEO BRIDGE FOR REMOVING ELECTROMAGNETIC RADIATION NOISE, AND SYSTEM COMPRISING SAME - A wireless video bridge for removing electromagnetic radiation noise includes an interface and a shielding part configured to remove a harmonic signal generated in relation to the interface when the wireless video bridge is operating. The wireless video bridge may provide a technology capable of guaranteeing continuity of surveillance by increasing a data transmission rate when transmitting an image captured by a security camera | 2020-09-17 |
20200295820 | TERMINAL DEVICE FOR AIR-TO-GROUND COMMUNICATION, COMMUNICATION CONTROL METHOD THEREFOR, AND AIR-TO-GROUND COMMUNICATION SYSTEM - According to the present application, an aircraft terminal device for air-to-ground communication includes an in-flight communication controller configured to control communication with multiple user terminals and, and, when a counterpart based station device on the ground needs to reserve a communication resource for ground-to-ground communication, the in-flight communication controller cuts off communication with at least one of the multiple user terminals and. | 2020-09-17 |
20200295821 | REQUESTING WEATHER DATA BASED ON PRE-SELECTED EVENTS - A ground weather center may transmit information requests that carry at least one meteorological specific triggering command. An airborne system may translate the triggering command into detectable meteorological conditions and may arm the trigger(s) for specific weather sensors accordingly and downlink information upon the airborne system detects the triggering conditions. By using such a triggering command, the airborne system may be able transmit the same amount of valuable information with less bandwidth by reducing the number of redundant downlinked packets. | 2020-09-17 |
20200295822 | FLEXIBLE CAPACITY SATELLITE CONSTELLATION - Embodiments provide in-flight configuration of satellite pathways to flexibly service terra-link and cross-link traffic in a constellation of non-processed satellites, for example, to facilitate flexible forward-channel and return-channel capacity in a satellite communications system. For example, each satellite in the constellation can include one or more dynamically configurable pathway, and switching and/or beamforming can be used to configure each pathway to be a forward-channel pathway or a return-channel pathway in each of a number of timeslots according to a pathway configuration schedule. At least some of the pathways can be further selectively configured, in each timeslot, to carry “terra-link” traffic to and/or from terrestrial terminals and “cross-link” traffic to and/or from one or more other satellites of the constellation. | 2020-09-17 |
20200295823 | Experimental Smartphone Ground Station Grid System - This system and method provides for a plurality of satellite ground stations, distributed across some geographic region, and for these regions in turn to be scalable to cover large regions, including across the Earth or in orbit with planets or other celestial bodies using a combination of low-orbit satellites, terrestrial participant devices, and cloud-based communications. The invention in its simplest form is intended to solve the short temporal window problem inherent to the scenario where a single base or ground station is trying to track and communicate with a low-end OSAT or even a cube-satellite. | 2020-09-17 |
20200295824 | Uplink Transmission Timing For Non-Terrestrial Networks - Various examples and schemes pertaining to uplink (UL) transmission timing for non-terrestrial networking (NTN) are described. An apparatus receives, from a network, downlink control information (DCI) indicating an NTN offset for a scheduling delay. Accordingly, the apparatus performs one or more UL transmissions to a satellite with the scheduling delay which accounts for the | 2020-09-17 |
20200295825 | OPTICAL DEVICE, OPTICAL MODULE USING THE SAME, AND TEST METHOD FOR OPTICAL DEVICE - An optical device has an optical transmitter circuit formed in a substrate, a first port configured to output an optical signal generated by the optical transmitter circuit from an edge of the substrate during services and to input a test light from the edge of the substrate during a test, and a photodetector configured to detect the test light input from the first port. | 2020-09-17 |
20200295826 | MANAGEMENT DEVICE, AND IDENTIFICATION METHOD AND RECORDING MEDIUM STORING PROGRAM - A management device managements an optical transmission system provided with a transmission path in which each transmission route between first and second optical transmitting/receiving devices has a different transmission path length. The management device includes collecting unit that registers route delay information indicating a transmission delay time for each of the transmission routes, and collects a measurement delay time being a transmission delay time of the transmission path being measured by the first optical transmitting/receiving device, and identifying unit that identifies the transmission route corresponding to the measurement delay time, based on the route delay information and the measurement delay time. | 2020-09-17 |
20200295827 | COMMUNICATION APPARATUS AND COMMUNICATION METHOD - In order to reduce wire connections and achieve a wireless communication environment securing a sufficient communication band, the present invention provides a communication apparatus that includes a wireless communication means for transmitting and receiving a wireless signal, an optical communication means for transmitting and receiving spatial light as communication light, and a control means for performing signal conversion in a process for converting the wireless signal and the communication light and setting a transmission destination of the wireless signal and the communication light. | 2020-09-17 |
20200295828 | Use of Waveguides and Lenses to Improve Light Communication Reception in Devices - Devices implementing light communications use waveguides to efficiently collect light used for the light communications and propagate that collected light to a sensor. More particularly, light collected from one or more sensors propagates along a TIR waveguide until disrupted by a diffusive element, which effectively directs the propagating light to a sensor. In so doing, the solution presented herein increases the amount of light available for the light communications and/or reduces the number of sensors needed for the light communications, e.g., by providing light collected from multiple different locations to a single sensor. The waveguide solution presented herein may be implemented inside a device and/or along an exterior surface, e.g., housing or casing, of a device. | 2020-09-17 |
20200295829 | TRANSMITTING AND RECEIVING SYMBOLS VIA UNIPOLAR SIGNALS - A method of transmitting data via a unipolar signal comprises allocating a symbol to one or more signals among a plurality of signals, applying pulse shaping to the plurality of signals to obtain a plurality of filtered signals, wherein the filtered signals are orthogonal signals, and transmitting the sum of the filtered signals as a unipolar signal, wherein the transmitted signal is a weighted sum of the filtered signals. The data can be recovered at the receiver by applying a plurality of orthogonal matched filters to the received unipolar signal to obtain a plurality of filtered signals, and performing symbol detection on the plurality of filtered signals to determine the received symbol. Apparatus for transmitting and receiving unipolar signals are also disclosed. | 2020-09-17 |
20200295830 | Communication Method and Related Device - A communication method includes obtaining, by a first device, first target information, determining, by the first device based on the first target information, a data transmit array element from light emitting diodes (LEDs) of the first device, where each data transmit array element of the first device includes at least one LED, and sending, by the first device, to-be-sent data to a data receive array element of a second device using the data transmit array element, where each data receive array element of the second device includes at least one LED of the second device. | 2020-09-17 |
20200295831 | INTER-MOBILE-BODY COMMUNICATION SYSTEM, INTER-MOBILE-BODY COMMUNICATION METHOD, AND PROGRAM RECORDING MEDIUM - In order to reliably communicate with a communication object even when a relative positional relationship with the communication object cannot be accurately recognized, an inter-mobile-body communication system includes: a control device which performs control of switching between a first mode of transmitting wide-area signal light, and a second mode of transmitting selective signal light toward a communication object in response to response signal light responding to the wide-area signal light transmitted in the first mode, and performs control of selectively receiving the response signal light from the communication object; and a light transmitting/receiving device which transmits the wide-area signal light in the first mode, transmits the selective signal light toward the communication object in the second mode, and selectively receives the response signal light from the communication object, according to control by the control device. | 2020-09-17 |
20200295832 | Optical Data Interconnect System - A system for optical data interconnect of a source and a sink includes a first HDMI compatible electrical connector able to receive electrical signals from the source. A first signal converter is connected to the first HDMI compatible electrical connector and includes electronics for conversion of TMDS or FRL electrical signals to optical signals, with the electronics including an optical conversion device connectable to source ground to reduce noise. At least one optical fiber is connected to the first signal converter. A second signal converter is connected to the at least one optical fiber and includes electronics for conversion of optical signals to TMDS or FRL electrical signals. A power module for the second signal converter provides power to an electrical signal amplifier connectable to sink ground. A second HDMI compatible electrical connector is connected to the second signal converter and able to send signals to the sink. | 2020-09-17 |
20200295833 | REDUNDANCY IN A PUBLIC SAFETY DISTRIBUTED ANTENNA SYSTEM - A redundancy system for data transport in a Distributed Antenna System (DAS) includes a plurality of Digital Access Units (DAUs). Each of the plurality of DAUs is fed by a plurality of data streams and is operable to transport digital signals between others of the plurality of DAUs. The redundancy system also includes a plurality of Digital Distribution Units (DDUs). Each of the plurality of DDUs is in communication with each of the plurality of DAUs using cross connection communication paths. The redundancy system further includes a plurality of Digital Remote Units (DRUs). Each of the plurality of DRUs is in communication with each of the plurality of DDUs using cross connection communications paths. | 2020-09-17 |