38th week of 2020 patent applcation highlights part 63 |
Patent application number | Title | Published |
20200294831 | METHOD FOR AUTOMATIC SENDING CASSETTE POD - A system for sending a cassette pod is provided. The system includes a processing machine having a load port for receiving the cassette pod. The system further includes a manipulating apparatus positioned above the processing machine. The manipulating apparatus includes an intermediate module having a stage and a driving mechanism connected to the stage to change the position of the stage. The manipulating apparatus further includes a conveyor module having a gripper assembly for grasping the cassette pod. | 2020-09-17 |
20200294832 | APPARATUS FOR PROCESSING SUBSTRATE - The present disclosure relates to a substrate processing apparatus, and more specifically, to a substrate processing apparatus capable of blocking the introduction of external air and external particles into a chamber by forming an air curtain at a loading/unloading part when the chamber is open. | 2020-09-17 |
20200294833 | SUBSTRATE PROCESSING APPARATUS - There is provided a technique that includes: a reactor including a process chamber where substrate is processed, the reactor being fixed to a vacuum transfer chamber; a substrate mounting stand disposed in the reactor and having substrate mounting surface where the substrate is mounted; a heater heating the substrate; a gas supply part supplying gas into the process chamber; an extraction part extracting basic information for estimating position of the substrate mounting surface; a calculation part calculating estimated position information of center of the substrate mounting surface based on the basic information; a transfer robot disposed in the vacuum transfer chamber and including an end effector supporting the substrate when the substrate is transferred; and a controller performing control to set target coordinate of the end effector according to the estimated position information, move the end effector to the target coordinate, and mount the substrate on the substrate mounting surface. | 2020-09-17 |
20200294834 | CLUSTER TOOL AND METHOD USING THE SAME - A method includes transferring a wafer into a first process chamber of a cluster tool; performing a first process to the wafer in the first process chamber; transferring the wafer from the first process chamber to a second process chamber of the cluster tool after performing the first process; cleaning the first process chamber; performing a second process to the wafer in the second process chamber during cleaning the first process chamber. | 2020-09-17 |
20200294835 | METHOD TO IMPROVE NIKON WAFER LOADER REPEATABILITY - A microelectronic device is formed by loading a wafer, in which the microelectronic device is being formed, onto a pre-alignment stage for a wafer stepper. If the pre-alignment stage does not align the wafer properly using a notch pin, the wafer is loaded onto a wafer stepper stage of the wafer stepper. The wafer is positioned under a Field Image Alignment (FIA) camera of the wafer stepper, so that the FIA camera provides an image of the wafer notch. The wafer is rotated into a proper position. The wafer is transferred back to the pre-alignment stage. The wafer is aligned using the notch pin. The wafer is transferred to the wafer stepper stage. Fabrication is continued to form the microelectronic device. | 2020-09-17 |
20200294836 | TEMPERATURE TUNABLE MULTI-ZONE ELECTROSTATIC CHUCK - Implementations described herein provide a method for calibrating a temperature of a substrate support assembly which enables discrete tuning of the temperature profile of a substrate support assembly. In one embodiment, a system, comprises a memory, wherein the memory includes an application program configured to perform an operation on a substrate support assembly, a control board disposed in a substrate support assembly, wherein the control board comprises a processor having an wireless interface, a pulse width modification (PWM) heater controller, wherein the processor is connected with the memory to read and access the application program from the memory when in operation, and a heating element coupled to the pulse width modification (PWM) heater controller, wherein the heating element comprises a plurality of spatially tunable heaters that are individually tunable by the pulse width modification (PWM) heater controller | 2020-09-17 |
20200294837 | CERAMIC-CIRCUIT COMPOSITE STRUCTURE AND METHOD FOR MAKING THE SAME - The present invention provides a ceramic-circuit composite structure, comprising: a ceramic plate with a supporting surface that has a recessed supporting portion; a curved-surface circuit buried in the ceramic plate; and a power supply module electrically connected to the curved-surface circuit. Moreover, the present invention provides a method for making the ceramic-circuit composite structure. The ceramic-circuit composite structure of the present invention makes use of the curved-surface circuit to improve the prior art problem that a planar circuit has less static electricity or lower temperature at the center than in the peripheral region. | 2020-09-17 |
20200294838 | SUBSTRATE FIXING DEVICE - A substrate fixing device includes a base plate including therein a gas supply section, and an electrostatic chuck provided on the base plate. The electrostatic chuck includes a base having a mounting surface on which a target to be held by electrostatic attraction is mounted, an insertion hole, penetrating the base, having an inner surface that defines the insertion hole and is threaded to foLm a female thread, and a screw member, having an outer surface that is threaded to form a male thread, and inserted into the insertion hole to assume a mated state in which the male thread mates with the female thread. A gas from the gas supply section is supplied to the mounting surface via the screw member. | 2020-09-17 |
20200294839 | CHIP EJECTING APPARATUS - A chip ejecting apparatus includes a table configured to be provided with a dicing tape and a target chip adhered to an upper surface of the dicing tape, an ejector unit including a plurality of gas holes configured to inject a gas toward a lower surface of the dicing tape, and a control unit configured to separately control on/off operations of the plurality of gas holes and select an active gas hole group from the plurality of gas holes. The active gas hole group is selected to overlap the target chip, and is configured to inject the gas toward the dicing tape along a direction from a first edge of the target chip toward a second edge of the target chip opposite to the first edge of the target chip. | 2020-09-17 |
20200294840 | TRANSFER APPARATUS - A transfer apparatus holdes a plate-shaped workpiece under suction in a noncontact condition and transfers the workpiece. The transfer apparatus includes a base, a Bernoulli transfer pad fixed to the base for spraying air toward the workpiece to produce a vacuum, and a moving unit for moving the base. The Bernoulli transfer pad includes a cylindrical pad body. The pad body has a lower surface as a holding surface to which a fluid spraying portion opens and an annular pad mounting portion for mounting an annular pad. When the annular pad is mounted on the annular pad mounting portion, the holding surface is increased in a radial direction of the pad body to thereby increase a suction force for sucking the workpiece. | 2020-09-17 |
20200294841 | SUBSTRATE HOLDER FOR USE IN A LITHOGRAPHIC APPARATUS - A substrate holder for use in a lithographic apparatus and configured to support a substrate, the substrate holder having a main body having a main body surface, a plurality of main burls projecting from the main body surface, wherein each main burl has a distal end surface configured to support the substrate, a first seal member projecting from the main body surface and having an upper surface, the first seal member surrounding the plurality of main burls and configured to restrict the passage of liquid between the substrate and the main body surface radially inward past the first seal member, and a plurality of minor burls projecting from the upper surface of the first seal member, wherein each minor burl has a distal end surface configured to support the substrate. | 2020-09-17 |
20200294842 | Plasma Processing Apparatus - A plasma processing apparatus includes a stage provided in a chamber and having a heater therein, the stage being configured to place a substrate thereon, and an annular member provided around the stage to be spaced apart therefrom and formed of a dielectric material. At least one annular groove is formed in a lower surface of the annular member in a radial direction. | 2020-09-17 |
20200294843 | SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING METHOD - A substrate processing apparatus includes a substrate holding unit which holds and rotates a substrate in a horizontal orientation, a substrate heating unit which has a heating surface which faces the substrate, held by the substrate holding unit, from below and overlaps with an outermost periphery of the substrate in top view, and heats the substrate in a state of contacting a lower surface of the substrate, a transferring unit which transfers the substrate between the substrate holding unit and the substrate heating unit, and a processing fluid supplying unit which supplies a processing fluid toward the substrate held by the substrate holding unit. | 2020-09-17 |
20200294844 | Method of Manufacturing Semiconductor Device - A method of manufacturing a semiconductor device, the method including: a first film deposition process of stacking a polymer film on a substrate on which a recess is formed, wherein the polymer film is a film of a polymer having a urea bond and is formed by polymerizing a plurality of kinds of monomers; a second film deposition process of stacking a sealing film on the substrate in a state in which at least a bottom and a sidewall of the recess are covered with the polymer film; and a desorbing process of desorbing and diffusing the polymer film under the sealing film through the sealing film by depolymerizing the polymer film by heating the substrate to a first temperature. | 2020-09-17 |
20200294845 | Wafer Level Chip Scale Packaging Intermediate Structure Apparatus and Method - Presented herein is a WLCSP intermediate structure and method forming the same, the method comprising forming a first redistribution layer (RDL) on a carrier, the first RDL having mounting pads disposed on the first RDL, and mounting interposer dies on a second side of the first RDL. A second RDL is formed over a second side of the interposer dies, the second RDL having a first side adjacent to the interposer dies, one or more lands disposed on the second RDL, at least one of the one or more lands in electrical contact with at least one of the interposer dies or at least one of the mounting pads. A molding compound is formed around the interposer dies and over a portion of the first RDL prior to the forming the second RDL and the second RDL is formed over at least a portion of the molding compound. | 2020-09-17 |
20200294846 | FIN FIELD EFFECT TRANSISTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME - A method for forming a fin field effect transistor device structure includes forming fin structures over a substrate. The method also includes forming a gate structure across the fin structures. The method also includes forming source/drain epitaxial structures over the fin structures. The method also includes forming blocking structures between the source/drain epitaxial structures. The method also includes depositing contact structures over the source/drain epitaxial structures and between the blocking structures. The method also includes removing a top portion of the blocking structures. The method also includes depositing an etch stop layer over the blocking structures and the contact structures, so that an air gap is formed between the etch stop layer and the blocking structure. | 2020-09-17 |
20200294847 | METHOD FOR PROCESSING SUBSTRATE AND SUBSTRATE PROCESSING APPARATUS - Planarization is performed on heterogeneous films with high accuracy. According to one embodiment, a method for processing a substrate is provided. The substrate is formed of an insulating film layer where a groove is formed, a barrier metal layer, and a wiring metal layer in order from a bottom in at least a part of a region. The method includes (3) while the wiring metal layer, the barrier metal layer, and the insulating film layer are exposed to the surface of the substrate: a step of bringing the surface of the substrate into contact with a catalyst; a step of supplying a process liquid between the catalyst and the surface of the substrate; and a step of flowing a current between the catalyst and the surface of the substrate. | 2020-09-17 |
20200294848 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device having a semiconductor element (a thin film transistor, a thin film diode, a photoelectric conversion element of silicon PIN junction, or a silicon resistor element) which is light-weight, flexible (bendable), and thin as a whole is provided as well as a method of manufacturing the semiconductor device. In the present invention, the element is not formed on a plastic film. Instead, a flat board such as a substrate is used as a form, the space between the substrate (third substrate ( | 2020-09-17 |
20200294849 | STRUCTURE AND FORMATION METHOD OF DUAL DAMASCENE STRUCTURE - A structure and a formation method of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a conductive feature over the semiconductor substrate. The semiconductor device structure also includes a dielectric layer over the conductive feature and the semiconductor substrate and a via hole in the dielectric layer. The via hole has an oval cross section. The semiconductor device structure further includes a trench in the dielectric layer, and the via hole extends from a bottom portion of the trench. The trench has a trench width wider than a hole width of the via hole. In addition, the semiconductor device structure includes one or more conductive materials filling the via hole and the trench and electrically connected to the conductive feature. | 2020-09-17 |
20200294850 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A process of forming a 3D memory device includes forming a stacked structure with a plurality of stacked layers, etching the stacked structure to form stepped trenches each comprising a plurality of steps, forming a hard mask layer with a plurality of openings over the stepped trenches, forming a photoresist layer over the hard mask layer, and etching through the plurality of openings using the hard mask layer and the photoresist layers as an etch mask to extend a bottom of the stepped trenches to a lower depth. | 2020-09-17 |
20200294851 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor structure includes a semiconductor substrate, a gate structure, an etch stop layer, a dielectric structure, and a conductive material. The gate structure is on the semiconductor substrate. The etch stop layer is over the gate structure. The dielectric structure is over the etch stop layer, in which the dielectric structure has a ratio of silicon to nitrogen varying from a middle layer of the dielectric structure to a bottom layer of the dielectric structure. The conductive material extends through the dielectric structure. | 2020-09-17 |
20200294852 | Methods Of Forming Conductive Vias And Methods Of Forming Memory Circuitry - A method of forming conductive vias of integrated circuitry comprises forming first openings in a first masking material, with the first openings being spaced along a line passing across the first openings. Sidewalls of the first openings are lined with a second masking material to form a ring within individual of the first openings and a second opening within the individual first openings radially inside of the ring. The first masking material is removed along the line to form a void space between immediately-adjacent of the rings. A mask is formed that comprises the rings and a third opening in third masking material, with the third opening extending along the line above and across multiple of the rings and multiple of the second openings. The mask is used as an etch mask while etching into substrate material that is exposed through the third opening to form contact openings in the substrate material that are spaced along the line. Conductive material is formed in the contact openings to form conductive vias. | 2020-09-17 |
20200294853 | SEMICONDUCTOR DEVICE AND FORMING METHOD THEREOF - Semiconductor device and formation method are provided. The method includes providing a substrate, a first fin and a second fin on the substrate, an isolation structure covering a portion of sidewalls of the first and second fins, a gate structure across the first fin or the second fin, a first doped source/drain region in the first fin, a second doped source/drain region in the second fin, and an interlayer dielectric layer on the isolation structure, the first and second fins, and the gate structure. A first through hole is formed in the interlayer dielectric layer, exposing the first doped source/drain region or the second doped source/drain region. A second through hole is formed in the interlayer dielectric layer on the isolation structure to connect to the first through hole. A first plug is formed in the first through hole and a second plug is formed in the second through hole. | 2020-09-17 |
20200294854 | VIAS AND CONDUCTIVE ROUTING LAYERS IN SEMICONDUCTOR SUBSTRATES - Through vias and conductive routing layers in semiconductor substrates and associated methods of manufacturing are disclosed herein. In one embodiment, a method for processing a semiconductor substrate includes forming an aperture in a semiconductor substrate and through a dielectric on the semiconductor substrate. The aperture has a first end open at the dielectric and a second end opposite the first end. The method can also include forming a plurality of depressions in the dielectric, and simultaneously depositing a conductive material into the aperture and at least some of the depressions. | 2020-09-17 |
20200294855 | WAFER DICING WITH A FRAME FOR ENABLING A SHRINK - Aspects of the disclosure are directed to wafer dicing with a frame. Accordingly, the dicing of the wafer includes forming a substrate layer in the wafer, wherein the substrate layer comprises a first substrate layer edge associated with the first device and a second substrate layer edge associated with the second device; depositing a passivation layer onto the substrate layer; and depositing a frame in the wafer, wherein the frame abuts the passivation layer and wherein the frame comprises a first frame edge associated with the first device and a second frame edge associated with the second device; and wherein a front width is a first distance between the first frame edge and the second frame edge, and a back width is a second distance between the first substrate layer edge and the second substrate layer edge; and wherein the front width is less than the back width. | 2020-09-17 |
20200294856 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor wafer chip, a semiconductor device layer, and a reflectance reducing layer. The semiconductor wafer chip includes a device region and a peripheral region around the device region. The peripheral region includes a plurality of voids aligned along a side surface of the semiconductor wafer chip at a predetermined depth from a first surface of the semiconductor wafer chip. The semiconductor device element layer is on the first surface in the device region. The reflectance reducing layer is on the first surface of the semiconductor wafer chip in the peripheral region, that reduces a reflection of laser light incident from a second surface of the semiconductor wafer chip. | 2020-09-17 |
20200294857 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND ELECTRONIC APPARATUS - To more reliably suppress deterioration in characteristics due to signals (distortions) other than input and output waves while suppressing manufacturing cost. A semiconductor device according to the present disclosure includes a circuit substrate including an insulating film layer located above a predetermined semiconductor substrate and a semiconductor layer located above the insulating film layer, a plurality of passive elements provided on the circuit substrate and electrically connected with one another, and an electromagnetic shield layer locally provided in the insulating film layer corresponding to a portion where at least one of the plurality of passive elements is provided, and the electromagnetic shield layer and the semiconductor substrate are electrically separated from each other. | 2020-09-17 |
20200294858 | 3D Chip with Shared Clock Distribution Network - Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate. As further described below, the first and second dies in some embodiments are placed in a face-to-face arrangement (e.g., a vertically stacked arrangement) that has the first and second set of interconnect layers facing each other. In some embodiments, a subset of one or more interconnect layers of the second set interconnect layers of the second die has interconnect wiring that carries power, clock and/or data-bus signals that are supplied to the first IC die. | 2020-09-17 |
20200294859 | FinFETs and Methods of Forming FinFETs - An embodiment is a method including forming a multi-layer stack over a substrate, the multi-layer stack including alternating first layers and second layers, patterning the multi-layer stack to form a fin, forming an isolation region surrounding the fin, an upper portion of the fin extending above a top surface of the isolation region, forming a gate stack on sidewalls and a top surface of the upper portion of the fin, the gate stack defining a channel region of the fin, and removing the first layers from the fin outside of the gate stack, where after the removing the first layers, the channel region of the fin includes both the first layers and the second layers. | 2020-09-17 |
20200294860 | FIN FIELD EFFECT TRANSISTOR DEVICE STRUCTURE - A fin field effect transistor device structure includes a first fin structure formed on a substrate. The fin field effect transistor device structure also includes a spacer layer surrounding the first fin structure. The fin field effect transistor device structure further includes a power rail formed over the substrate besides a bottom portion of the first fin structure. The fin field effect transistor device structure further includes a first contact structure formed over the first fin structure and in contact with a portion of the power rail. | 2020-09-17 |
20200294861 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - According to one embodiment, a semiconductor device includes: a semiconductor substrate; a gate insulating film provided on the semiconductor substrate; a gate electrode film, provided on the gate insulating film, that includes boron; a side wall insulating film extending along a side surface of the gate electrode film; a barrier film including a first portion provided between the side surface of the gate electrode film and the side wall insulating film, and a second portion, connected to the first portion, that is provided between the gate insulating film and a bottom surface of the side wall insulating film. The barrier film includes carbon as a main component to limit diffusion of the boron in the gate electrode film. | 2020-09-17 |
20200294862 | Methods for Improving Interlayer Dielectric Layer Topography - Integrated circuit devices having improved interlayer dielectric (ILD) layer topography and methods of fabrication thereof are disclosed herein. An exemplary integrated circuit device includes a first gate structure having a first height disposed over a substrate in a first region and a second gate structure having a second height disposed over the substrate in a second region. The second height is less than the first height. A first contact etch stop layer is disposed over the first gate structure. A second contact etch stop layer disposed over the second gate structure. The first contact etch stop layer has a first thickness, the second contact etch stop layer has a second thickness, and the second thickness is greater than the first thickness. An interlayer dielectric layer is disposed over the first contact etch stop layer and the second contact etch stop layer. A difference between a first sum of the first height and the first thickness and a second sum of the second height and the second thickness is less than or equal to about 10%. | 2020-09-17 |
20200294863 | METHODS OF FABRICATING SEMICONDUCTOR DEVICES WITH MIXED THRESHOLD VOLTAGES BOUNDARY ISOLATION OF MULTIPLE GATES AND STRUCTURES FORMED THEREBY - A method of fabricating semiconductor devices includes forming a plurality of first and second nanosheets in p-type and n-type device regions, respectively. A p-type work function (PWF) layer is deposited to surround each of the first and second nanosheets. A first mask is formed on the PWF layer and not over the boundary between the p-type and n-type device regions, and then the PWF layer is etched in a first etching process to keep portions of the PWF layer between the second nanosheets. A second mask is formed on the PWF layer, and then the portions of the PWF layer between the second nanosheets are removed in a second etching process. An n-type work function layer is deposited in the n-type and the p-type device regions to surround each of the second nanosheets and on the PWF layer. | 2020-09-17 |
20200294864 | Selective Dual Silicide Formation - A semiconductor device and a method of making the same are provided. A method according to the present disclosure includes forming a first type epitaxial layer over a second type source/drain feature of a second type transistor, forming a second type epitaxial layer over a first type source/drain feature of a first type transistor, selectively depositing a first metal over the first type epitaxial layer to form a first metal layer while the first metal is substantially not deposited over the second type epitaxial layer over the first type source/drain feature, and depositing a second metal over the first metal layer and the second type epitaxial layer to form a second metal layer. | 2020-09-17 |
20200294865 | METHOD FOR FORMING SEMICONDUCTOR DEVICE STRUCTURE - A method for forming a semiconductor device structure is provided. The method includes forming a work function material around a first semiconductor layer in a first region and a second semiconductor layer in a second region. The method also includes forming a first gate electrode material over the work function material. The method also includes removing the first gate electrode material in the first region. The method also includes forming a second gate electrode material over the work function material in the first region. | 2020-09-17 |
20200294866 | VERTICAL STACKED NANOSHEET CMOS TRANSISTORS WITH DIFFERENT WORK FUNCTION METALS - A method for forming a semiconductor device includes forming a structure having at least a first nanosheet stack for a first device, a second nanosheet stack for a second device and disposed over the first nanosheet stack, a disposable gate structure, and a gate spacer. The disposable gate structure and sacrificial layers of the first and second nanosheet stacks are removed thereby forming a plurality of cavities. A conformal gate dielectric layer is formed in the plurality cavities and surrounding at least portions of the first and second nanosheet stacks. A first conformal work function layer is formed in contact with the gate dielectric layer. Portions of the first conformal work function layer are removed without using a mask from at least the second nanosheet stack. A second conformal work function layer is formed on exposed portions of the gate dielectric layer. | 2020-09-17 |
20200294867 | Assembly process for circuit carrier and circuit carrier - The invention concerns a process for the production of a circuit carrier ( | 2020-09-17 |
20200294868 | DEVICE/HEALTH OF LINE (HOL) AWARE EBEAM BASED OVERLAY (EBO OVL) STRUCTURE - The present disclosure relates to a method which includes generating a device layout of an eBeam based overlay (EBO OVL) structure with a minimum design rule, simulating a worst case process margin for the generated device layout of the EBO OVL structure, enabling a plurality of devices for the simulated worst case process margin for the generated device layout of the EBO OVL structure, and breaking a plurality of design rules for the enabled plurality of devices of the EBO OVL structure to generate an OVL measurement layout of the EBO OVL structure. | 2020-09-17 |
20200294869 | SEMICONDUCTOR PACKAGE, BUFFER WAFER FOR SEMICONDUCTOR PACKAGE, AND METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE - A semiconductor package includes a buffer wafer including: a first surface; and a second surface opposite to the first surface, a stacked structure including a plurality of chips being stacked on the first surface of the buffer wafer; a first detection line formed around a periphery of the stacked structure on the first surface of the buffer wafer; and a mold layer covering the stacked structure, the first detection line and the first surface of the buffer wafer. | 2020-09-17 |
20200294870 | Semiconductor Device Package and Method - In an embodiment, a method includes: stacking a plurality of first dies to form a device stack; revealing testing pads of a topmost die of the device stack; testing the device stack using the testing pads of the topmost die; and after testing the device stack, forming bonding pads in the topmost die, the bonding pads being different from the testing pads. | 2020-09-17 |
20200294871 | SEMICONDUCTOR STRUCTURE - A semiconductor structure includes a substrate, a device, a contact via, a metal/dielectric layer, and a test structure. The device is over the substrate. The contact via is connected to the device. The metal/dielectric layer is over the contact via. The metal/dielectric layer includes a first portion and a second portion. The first portion of the metal/dielectric layer has a metallization pattern connected to the contact via. The second portion of the metal/dielectric layer is void of metal. The test structure is over the second portion of the metal/dielectric layer. | 2020-09-17 |
20200294872 | SEMICONDUCTOR PACKAGE, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor package including a metal base, a side wall, and at least one metal lead is disclosed. The metal base has a main surface to mount at least one semiconductor element. The side wall has a frame shape and is disposed on the main surface. The side wall includes a first side wall portion made of a resin and a second side wall portion made of a resin. The second side wall portion is placed on the first side wall portion and joined to the first side wall portion with an adhesive. The metal lead is partially sandwiched between the first side wall portion and the second side wall portion. A first end of the metal lead is exposed inside of the side wall, and a second end of the metal lead is located outside of the side wall. | 2020-09-17 |
20200294873 | SEMICONDUCTOR DEVICE - A semiconductor device includes upper and lower electrode plates, and semiconductor elements therebetween. First and second metal plates are disposed between the upper electrode plate and a first semiconductor element, and between the upper electrode plate and a second semiconductor element, respectively. The first semiconductor element is disposed between central portions of the upper and lower electrode plates. The upper electrode plate includes a first upper pole electrically connected to the first semiconductor element and a second upper pole electrically connected to the second semiconductor element. A first total length is a sum of a height of the first upper pole and thicknesses of the first semiconductor element and the first metal plate. A second total length longer than the first total length is a sum of a height of the second upper pole and thicknesses of the second semiconductor element and the second metal plate. | 2020-09-17 |
20200294874 | SEMICONDUCTOR DEVICE - A case includes a terminal disposition portion which includes a disposition surface projecting from an inner wall surface toward an open area, exposes an exposure region on a front surface of an external connecting terminal, and embeds therein a rear surface of the external connecting terminal. In the case, at at least part of both sides along a pair of opposite sides of the exposure region, the disposition surface is located between the front surface and the rear surface to have a level difference to the front surface. In a semiconductor device with the above-described configuration, the case does not extend to the exposure region on the front surface of the external connecting terminal. Therefore, no encapsulation resin flows into an interfacial debonding gap between the external connecting terminal and the case, thus curbing further advance of the interfacial debonding. | 2020-09-17 |
20200294875 | SENSOR PACKAGE AND MANUFACTURING METHOD THEREOF - A fingerprint sensor device and a method of making a fingerprint sensor device. As non-limiting examples, various aspects of this disclosure provide various fingerprint sensor devices, and methods of manufacturing thereof, that comprise an interconnection structure, for example a bond wire, at least a portion of which extends into a dielectric layer utilized to mount a plate, and/or that comprise an interconnection structure that extends upward from the semiconductor die at a location that is laterally offset from the plate. | 2020-09-17 |
20200294876 | ELECTRONIC DEVICE HAVING PRODUCT INFORMATION AND METHOD FOR READING THE PRODUCT INFORMATION - An electronic device has a function part | 2020-09-17 |
20200294877 | Molded Semiconductor Package with Mold Surface Modification - A molded semiconductor package includes a semiconductor die embedded in a mold compound, and a plurality of metal leads embedded in the mold compound and electrically connected to the semiconductor die. A first plurality of features is formed in an exterior surface of the mold compound. The first plurality of features disrupts a planarity of the exterior surface of the mold compound and is arranged along a direction which is transverse to a lengthwise extension of the plurality of metal leads. Corresponding methods of manufacturing such a molded semiconductor package are also described. | 2020-09-17 |
20200294878 | INTEGRATED PACKAGING DEVICES AND METHODS WITH BACKSIDE INTERCONNECTIONS - This disclosure provides devices and methods for 3-D device packaging with backside interconnections. One or more device elements can be hermetically sealed from an ambient environment, such as by vacuum lamination and bonding. One or more via connections provide electrical interconnection from a device element to a back side of a device substrate, and provide electrical interconnection from the device substrate to external circuitry on the back side of the device. The external circuitry can include a printed circuit board or flex circuit. In some implementations, an electrically conductive pad is provided on the back side, which is electrically connected to at least one of the via connections. In some implementations, the one or more via connections are electrically connected to one or more electrical components or interconnections, such as a TFT or a routing line. | 2020-09-17 |
20200294879 | CHIP MOUNTING STRUCTURE AND CHIP MOUNTING DEVICE - A chip mounting structure and a chip mounting device are provided. The chip mounting structure includes a circuit substrate and a plurality of micro heaters. The circuit substrate has a plurality of solder pads. A plurality of micro heaters are disposed on the circuit substrate adjacent to the solder pad. The plurality of chips are disposed on the circuit substrate, and the chip is electrically connected to the solder pad by a solder ball. Therefore, the soldering yield of the process can be reduced by the chip mounting structure and the chip mounting device. | 2020-09-17 |
20200294880 | Heterogeneous Thermal Interface Material for Corner and or Edge Degradation Mitigation - Embodiments of the present invention relate to an heterogenous thermal interface material (TIM). The heterogenous TIM includes two or more different materials. One material has a low elastic modulus, also known as Young's modulus, and is utilized primarily to transfer heat from one component to another component. Another material has a higher elastic modulus and is primarily utilized to bond or connect the corners and/or edges of one component to the other component. The high elastic modulus material is generally located within the heterogenous TIM where TIM strain is or is expected to be high. For example, the high elastic modulus material may be located at the corner and/or edge regions of the heterogenous TIM. | 2020-09-17 |
20200294881 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a transistor and a heat dissipation structure. The substrate includes first and second semiconductor layers, and includes an insulating layer disposed between the first and second semiconductor layers. The substrate has a recess extending into the insulating layer from a surface of the first semiconductor layer. The transistor includes a hetero-junction structure, a gate electrode, a drain electrode and a source electrode. The hetero-junction structure is disposed on the second semiconductor layer. The gate, drain and source electrodes are disposed over the hetero-junction structure. The gate electrode is located between the drain electrode and the source electrode, and an active area of the hetero-junction structure located between the drain electrode and the source electrode is overlapped with the recess of the substrate. The heat dissipation structure is disposed on the surface of the first semiconductor layer, and extends into the recess. | 2020-09-17 |
20200294882 | BONDED BODY, INSULATED CIRCUIT BOARD WITH HEAT SINK, AND HEAT SINK - An aluminum alloy member is made of an aluminum alloy having a Mg concentration set in a range of 0.4 mass % or more and 7.0 mass % or less and a Si concentration set to less than 1 mass %, the aluminum alloy member and a copper member are bonded to each other through solid-phase diffusion, and a compound layer made up of a first intermetallic compound layer that is disposed on the aluminum alloy member side and made of a θ phase of an intermetallic compound of Cu and Al, a second intermetallic compound layer that is disposed on the copper member side and made of a γ | 2020-09-17 |
20200294883 | SELF-HEALING PDMS ENCAPSULATION AND REPAIR OF POWER MODULES - A power electronics assembly is provided with a self-healing feature. The power electronics assembly may include a semiconductor electronics device and an insulating substrate coupled to the semiconductor electronics device. A base metal structural component may be provided, coupled to the insulating substrate. The assembly may include a frame component cooperating with the base metal structural component and defining an enclosure containing the semiconductor electronics device and the insulating substrate. The assembly further includes a self-healing polymer comprising disulfide bonds. The self-healing polymer is disposed within the enclosure; additional potting material may also be provided as a multi-layered encapsulation. In various aspects, the self-healing polymer may include polydimethylsiloxane based polyurethane (PDMS-PU) modified with disulfide bonds. The frame component may be configured to direct or confine heat to areas of the assembly where ESD may be problematic. | 2020-09-17 |
20200294884 | THERMOELECTRIC COOLERS COMBINED WITH PHASE-CHANGE MATERIAL IN INTEGRATED CIRCUIT PACKAGES - An Integrated Circuit (IC) assembly, comprising an IC package coupled to a substrate, and a subassembly comprising a thermal interface layer. The thermal interface layer comprises a phase change material (PCM) over the IC package. At least one thermoelectric cooling (TEC) apparatus is thermally coupled to the thermal interface layer. | 2020-09-17 |
20200294885 | Electronic Module Comprising a Semiconductor Package with Integrated Clip and Fastening Element - An electronic module includes a semiconductor package, and a clip connected to the semiconductor package. The clip is connected to or includes at least one fastening element which is configured to make a connection to an external heat sink. | 2020-09-17 |
20200294886 | THERMAL MANAGEMENT SOLUTIONS USING SELF-HEALING POLYMERIC THERMAL INTERFACE MATERIALS - A thermal interface material may be formed comprising a polymer material and a self-healing constituent. The thermal interface material may be used in an integrated circuit assembly between at least one integrated and a heat dissipation device, wherein the self-healing constituent changes the physical properties of the thermal interface material in response to thermo-mechanical stresses to prevent failure modes from occurring during the operation of the integrated circuit assembly. | 2020-09-17 |
20200294887 | SEMICONDUCTOR DEVICE - The semiconductor device includes a heat sink including fins and a base portion, and provided with a semiconductor module on a first surface and the fins on a second surface of the base portion; a housing attached to the base portion and covering the first surface of the base portion, the semiconductor module, electronic component, and a circuit board; a fan configured to cool the fins; and a first ventilation port and a second ventilation port each communicating inside and outside of the housing. The first ventilation port is provided above the half-height of the highest part in height of the electronic component from the circuit board. The second ventilation port extends through the first surface in the housing and the second surface of the base portion. The first ventilation port and the second ventilation port form a wind path in the housing. | 2020-09-17 |
20200294888 | POWER SEMICONDUCTOR DEVICE - An object of the invention is to improve the reliability of a power semiconductor device. The power semiconductor device according to the invention includes a semiconductor element, a first terminal and a second terminal that transmit current to the semiconductor element, a first base and a second base that are disposed to face each other while interposing a part of the first terminal, a part of the second terminal, and the semiconductor element between the first base and the second base, and a sealing material that is provided in a space between the first base and the second base. The second terminal includes an intermediate portion formed in such a way that a distance from the first terminal increases along a direction away from the semiconductor element. The intermediate portion is provided between the first base and the second base and in the sealing material. | 2020-09-17 |
20200294889 | SEMICONDUCTOR PACKAGES INCLUDING A BRIDGE DIE - A semiconductor package includes a semiconductor die and a bridge die. The bridge die is configured to include a through via formed in a body of the bridge die and a capacitor electrically coupled to the through via. | 2020-09-17 |
20200294890 | Semiconductor Device and Method of Forming a Fan-Out PoP Device with PWB Vertical Interconnect Units - A semiconductor device has a semiconductor package and an interposer disposed over the semiconductor package. The semiconductor package has a first semiconductor die and a modular interconnect unit disposed in a peripheral region around the first semiconductor die. A second semiconductor die is disposed over the interposer opposite the semiconductor package. An interconnect structure is formed between the interposer and the modular interconnect unit. The interconnect structure is a conductive pillar or stud bump. The modular interconnect unit has a core substrate and a plurality of vertical interconnects formed through the core substrate. A build-up interconnect structure is formed over the first semiconductor die and modular interconnect unit. The vertical interconnects of the modular interconnect unit are exposed by laser direct ablation. An underfill is deposited between the interposer and semiconductor package. A total thickness of the semiconductor package and build-up interconnect structure is less than 0.4 millimeters. | 2020-09-17 |
20200294891 | HIGH-FREQUENCY DEVICE AND MANUFACTURING METHOD THEREOF - A high-frequency device manufacturing method is provided. The method includes providing a substrate; forming a conductive material on the substrate; standing the substrate and the conductive material for a first time duration; forming a conductive layer by sequentially repeating the steps of forming the conductive material and standing at least once; and patterning the conductive layer. The thickness of the conductive layer is in a range from 0.9 μm to 10 μm. A high-frequency device is also provided. | 2020-09-17 |
20200294892 | PACKAGE STRUCTURE AND COMMUNICATIONS DEVICE - A package structure is disclosed, the package structure includes a substrate, a chip, a bonding layer, and a coating. A plurality of grooves are disposed on the substrate. Silver bonding materials are disposed in the grooves and on a surface of the substrate, to form the bonding layer. The chip is connected to the substrate by using the bonding layer. The grooves are symmetrically arranged along a first and a second axis that are perpendicular to each other, a vertical projection of the chip on the substrate is centrosymmetric about the first and the second axis, and the vertical projection of the chip on the substrate covers a partial area of an outer-ring groove which faces a periphery of the chip. The coating covers a surface that is of the bonding layer and not in contact with the substrate or the chip, used to prevent migration of silver ions. | 2020-09-17 |
20200294893 | COMPONENT STRUCTURE, POWER MODULE AND POWER MODULE ASSEMBLY STRUCTURE - The present disclosure relates to a component structure, a power module and a power module assembly structure having the component structure. The component structure comprises: a first bus bar, having one end extending to a first plane to form a first connecting terminal; a second bus bar, comprising a front portion of the second bus bar and a rear portion of the second bus bar, wherein the front portion of the second bus bar is laminated in parallel with the first bus bar, and the rear portion of the second bus bar is extended to a second plane to form a second connecting terminal; and an external circuit comprising a third bus bar, wherein the third bus bar is settled in parallel with the rear portion of the second bus bar, to reduce a parasitic inductance between the first connecting terminal and the second connecting terminal. | 2020-09-17 |
20200294894 | Semiconductor Device Having a Die Pad with a Dam-Like Configuration - A semiconductor device includes a semiconductor substrate, a power transistor formed in the semiconductor substrate, the power transistor including an active area in which one or more power transistor cells are formed, a first metal pad formed above the semiconductor substrate and covering substantially all of the active area of the power transistor, the first metal pad being electrically connected to a source or emitter region in the active area of the power transistor, the first metal pad including an interior region laterally surrounded by a peripheral region, the peripheral region being thicker than the interior region, and a first interconnect plate or a semiconductor die attached to the interior region of the first metal pad by a die attach material. Corresponding methods of manufacture are also described. | 2020-09-17 |
20200294895 | SEMICONDUCTOR DEVICE - A semiconductor device includes a die pad; a semiconductor chip mounted on a front surface of the die pad; a bonding layer placed between the die pad and the semiconductor chip; a first resin member being positioned between the bonding layer and the semiconductor chip; and a second resin member covering the semiconductor chip and the front surface of the die pad. The first resin member is provided along a periphery of the semiconductor chip. The bonding layer includes a first portion and a second portion. The first portion is positioned between the semiconductor chip and the die pad, and contacts the semiconductor chip. The second portion is positioned between the first resin member and the die pad. | 2020-09-17 |
20200294896 | Lead Frame Stabilizer for Improved Lead Planarity - A packaged semiconductor device includes a die paddle, a semiconductor die mounted on the die paddle, a plurality of fused leads extending away from a first side of the die paddle, a discrete lead that extends away from the first side of the die paddle and is physically detached from the plurality of fused leads, a first electrical connection between a first terminal of the semiconductor die and the discrete lead, an encapsulation material that encapsulates the semiconductor die, and a stabilizer bar connected to a first outer edge side of the discrete lead. The first outer edge side of the discrete lead is opposite from a second outer edge side of the discrete lead which faces the plurality of fused leads. | 2020-09-17 |
20200294897 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - A semiconductor device includes a semiconductor body; an electrode provided on the semiconductor body and electrically connected to the semiconductor body; a first metal layer selectively provided on the electrode; an insulating layer surrounding the first metal layer on the electrode; and a second metal layer provided on the first metal layer. The insulating layer includes a first surface and a second surface adjacent to the first surface. The first surface contacts a top surface of the first metal layer at an outer edge of the first metal layer. The second metal layer has an outer edge contacting the second surface of the insulating layer. | 2020-09-17 |
20200294898 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device comprises a circuit board and a semiconductor package mounted on the circuit board. The semiconductor package comprises a semiconductor chip, a first connector on a bottom surface of the semiconductor package and electrically connected to the semiconductor chip, and a metal bump coupled to the first connector and electrically connected to a second connector on the circuit board. The first connector has a contact surface facing the second connector. The contact surface has a recessed portion into which the metal bump extends. | 2020-09-17 |
20200294899 | PACKAGE SUBSTRATE WITH PARTIALLY RECESSED CAPACITOR - A semiconductor package includes a multilayer substrate including a dielectric layer, a first conductive layer forming a first set of electrical contacts, a second conductive layer forming package electrical contacts and two capacitor electrical contacts, conductive vias extending through the dielectric layer between the first conductive layer with the second conductive layer, and a solder mask layer over the second conductive layer. The semiconductor package further includes a semiconductor die on the first side of the multilayer substrate electrically connected a capacitor on the second side of the multilayer substrate. A recessed portion of the capacitor is within a capacitor opening of the solder mask layer between the two capacitor electrical contacts and a board-side surface of the solder mask layer. | 2020-09-17 |
20200294900 | Component Carrier Comprising a Component Having Vertical Through Connection - A component carrier and a method of manufacturing the same are disclosed. The component carrier includes a stack having at least one electrically conductive layer structure and/or at least one electrically insulating layer structure, a component embedded in the stack, and at least one vertical through connection extending between two opposing main surfaces of and through the component. | 2020-09-17 |
20200294901 | ZERO-MISALIGNMENT TWO-VIA STRUCTURES - Device package and a method of forming a device package are described. The device package includes an interposer with interconnects on an interconnect package layer and a conductive layer on the interposer. The device package has dies on the conductive layer, where the package layer includes a zero-misalignment two-via stack (ZM2VS) and a dielectric. The ZM2VS directly coupled to the interconnect. The ZM2VS further includes the dielectric on a conductive pad, a first via on a first seed, and first seed on a top surface of the conductive pad, where the first via extends through dielectric. The ZM2VS also has a conductive trace on dielectric, and a second via on a second seed, the second seed is on the dielectric, where the conductive trace connects to first and second vias, where second via connects to an edge of conductive trace opposite from first via. | 2020-09-17 |
20200294902 | SEMICONDUCTOR DEVICE - A semiconductor device comprising: substrate having main surface facing thickness direction; wirings arranged on main surface; semiconductor element having back surface facing the main surface and electrodes formed on back surface, wherein the electrodes are bonded to the wirings; and columnar wirings located outside the semiconductor element as viewed along the thickness direction, protrude in direction away from the main surface in the thickness direction, and are arranged on the wirings, wherein the semiconductor element includes first circuit and second circuit, wherein the electrodes include first electrodes electrically connected to the first circuit and second electrodes electrically connected to the second circuit, wherein the columnar wirings include first columnar portions electrically connected to the first electrodes and second columnar portions electrically connected to the second electrodes, and wherein area of each first columnar portions is larger than area of each second columnar portions in the thickness direction. | 2020-09-17 |
20200294903 | WIRING BOARD - A wiring board includes a semiconductor chip mounting surface, an external connection surface provided on an opposite side from the semiconductor chip mounting surface, and pads provided on the semiconductor chip mounting surface. Each pad includes a columnar section, and a tapered section, continuously formed on a first end of the columnar section, and having a cross sectional area that decreases toward a direction away from the columnar section. The tapered section of each pad projects from the semiconductor chip mounting surface. | 2020-09-17 |
20200294904 | FAN-OUT SEMICONDUCTOR PACKAGE AND ELECTRONIC DEVICE INCLUDING THE SAME - A fan-out semiconductor package includes: an interconnection member including a first insulating layer, first and second pads respectively disposed on opposite sides of the first insulating layer and a first via connecting the first and second pads to each other; a semiconductor chip disposed on the interconnection member; and an encapsulant encapsulating at least portions of the semiconductor chip. A center line of the first via is out of alignment with at least one of a center line of the first pad and a center line of the second pad. | 2020-09-17 |
20200294905 | INTEGRATED CIRCUIT INCLUDING STANDARD CELL - A standard cell of an IC includes a cell area including a transistor configured to determine a function of the standard cell; a first dummy area and a second dummy area respectively adjacent to two sides of the cell area in a first direction; and an active area extending in the first direction across the cell area, the first dummy area, and the second dummy area. The active area includes a first active area and a second active area spaced apart from each other in a second direction perpendicular to the first direction and extend parallel to each other in the first direction. At least one of the first active area and the second active area provided in the first dummy area is biased, and at least one of the first active area and the second active area provided in the second dummy area is biased. | 2020-09-17 |
20200294906 | Electronic Device Having Inverted Lead Pins - An electronic device (e.g., integrated circuit) and method of making the electronic device is provided that reduces a strength of an electric field generated outside a package of the electronic device proximate to the low voltage lead pins. The electronic device includes a low voltage side and a high voltage side. The low voltage side includes a low voltage die attached to a low voltage die attach pad. Similarly, the high voltage side includes a high voltage die attached to a high voltage die attach pad. Lead pins are attached to each of the low and high voltage attach pads and extend out from a package of the electronic device in an inverted direction. | 2020-09-17 |
20200294907 | PRINTED EXTENDABLE SENSOR SYSTEM - An extendable sensor system having a lattice topology includes a number of extendable interconnects having one or more electrically-conductive layers alternately sandwiched between two or more dielectric layers, two or more interconnect nodes, each located on the lattice topology and electrically-connected to the extendable interconnects to define a sensor array topology, and one or more sensors.. The extendable interconnects are arranged in a serpentine pattern that is configured to be expanded, thereby extending the extendable sensor system. The expanded interconnects define an extended sensor system topology, and is configured to be installed on the surface of an asset. Methods of manufacturing an extendable sensor system are also disclosed. | 2020-09-17 |
20200294908 | BONDED STRUCTURES WITH INTEGRATED PASSIVE COMPONENT - In various embodiments, a passive electronic component is disclosed. The passive electronic component can have a first surface and a second surface opposite the first surface. The passive electronic component can include a nonconductive material and a capacitor embedded within the nonconductive material. The capacitor can have a first electrode, a second electrode, and a dielectric material disposed between the first and second electrodes. The first electrode can comprise a first conductive layer and a plurality of conductive fibers extending from and electrically connected to the first conductive layer. A first conductive via can extend through the passive electronic component from the first surface to the second surface, with the first conductive via electrically connected to the first electrode. | 2020-09-17 |
20200294909 | NON-VOLATILE MEMORY WITH CAPACITORS USING METAL UNDER SIGNAL LINE OR ABOVE A DEVICE CAPACITOR - A non-volatile storage apparatus comprises a non-volatile memory structure and a plurality of I/O pads in communication with the non-volatile memory structure. The I/O pads include a power I/O pad, a ground I/O pad and data/control I/O pads. The non-volatile storage apparatus further comprises one or more capacitors connected to the power I/O pad and the ground I/O pad. The one or more capacitors are positioned in one or more metal interconnect layers below the signal lines and/or above device capacitors on the top surface of the substrate. | 2020-09-17 |
20200294910 | NON-VOLATILE MEMORY WITH CAPACITORS USING METAL UNDER SIGNAL LINE OR ABOVE A DEVICE CAPACITOR - A non-volatile storage apparatus comprises a non-volatile memory structure and a plurality of I/O pads in communication with the non-volatile memory structure. The I/O pads include a power I/O pad, a ground I/O pad and data/control I/O pads. The non-volatile storage apparatus further comprises one or more capacitors connected to the power I/O pad and the ground I/O pad. The one or more capacitors are positioned in one or more metal interconnect layers below the signal lines and/or above device capacitors on the top surface of the substrate. | 2020-09-17 |
20200294911 | Metal Interconnect Structures with Self-Forming Sidewall Barrier Layer - BEOL and MOL interconnect structures with a self-forming sidewall barrier layer are provided. In one aspect, a method of forming an interconnect structure includes: patterning a feature(s) in a dielectric; selectively forming a metal layer at a bottom of the at least one feature; depositing a liner layer lining the feature(s), wherein the conformal liner layer includes a metal alloy AB; depositing a metal onto the liner layer to form the interconnect structure; and annealing the interconnect structure under conditions sufficient to form a barrier layer including the component B along vertical sidewalls of the feature(s). A method of forming an interconnect structure including a via and a trench on top of the via is also provided, as is an interconnect structure. | 2020-09-17 |
20200294912 | PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME - A package structure includes a die, a TIV, a first encapsulant, a RDL structure, a thermal dissipation structure and a second encapsulant. The die has a first surface and a second surface opposite to each other. The TIV is laterally aside the die. The first encapsulant encapsulates sidewalls of the die and sidewalls of the TIV. The RDL structure is disposed on the first surface of the die and on the first encapsulant, electrically connected to the die and the TIV. The thermal dissipation structure is disposed over the second surface of die and electrically connected to the die through the TIV and the RDL structure. The second encapsulant encapsulates sidewalls of the thermal dissipation structure. | 2020-09-17 |
20200294913 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A device includes: a substrate; a first wiring layer above the substrate; a second wiring layer above the first wiring layer; a first insulating film on the first and second wiring layers; a second insulating film in the first insulating film, provided at a position overlapping with a part of the first wiring layer and a part of the second wiring layer in a first direction perpendicular to a surface of the substrate, and including a first portion higher than an upper surface of an end portion of the second wiring layer and a second portion lower than the upper surface of the end portion of the second wiring layer; and a plug via the second insulating film in the first insulating film, provided on the upper surface of the end portion of the second wiring layer, and electrically connected to the second wiring layer. | 2020-09-17 |
20200294914 | FAN-OUT PACKAGES WITH WARPAGE RESISTANCE - Various molded fan-out semiconductor chip devices are disclosed. In one aspect, a semiconductor chip device is provided that includes a first molding layer that has internal conductor structures, a redistribution layer (RDL) structure positioned on the first molding layer and electrically connected to the internal conductor structures, a semiconductor chip positioned on and electrically connected to the RDL structure, and a second molding layer positioned on the RDL structure and at least partially encapsulating the semiconductor chip. | 2020-09-17 |
20200294915 | PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A package structure includes a semiconductor die and a first redistribution circuit structure. The first redistribution circuit structure is disposed on and electrically connected to the semiconductor die, and includes a first build-up layer. The first build-up layer includes a first metallization layer and a first dielectric layer laterally wrapping the first metallization layer, wherein at least a portion of the first metallization layer is protruded out of the first dielectric layer. | 2020-09-17 |
20200294916 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes semiconductor dies, an encapsulant and a redistribution structure. The semiconductor dies are disposed side by side. Each semiconductor die has an active surface, a backside surface, and an inner side surface connecting the active surface and the backside surface. The encapsulant wraps the semiconductor dies and exposes the active surfaces of the semiconductor dies. The redistribution structure is disposed on the encapsulant and the active surfaces of the semiconductor dies. The inner side surfaces of most adjacent semiconductor dies face each other. The redistribution structure establishes single-ended connections between most adjacent semiconductor dies by crossing over the facing inner side surfaces of the most adjacent semiconductor dies. | 2020-09-17 |
20200294917 | PACKAGE ON PACKAGE AND PACKAGE CONNECTION SYSTEM COMPRISING THE SAME - A package-on-package includes a first semiconductor package including a first semiconductor chip and a second semiconductor package, disposed on the first semiconductor package, including a second semiconductor chip electrically connected to the first semiconductor chip. Each of the first and second semiconductor chips includes one or more units. The number of units of the first semiconductor chip is greater than the number of units of the second semiconductor chip. The one or more units of the first semiconductor chip and the one or more units of the second semiconductor chip implement a function of an application processor chip. | 2020-09-17 |
20200294918 | BONDED ASSEMBLY INCLUDING A SEMICONDUCTOR-ON-INSULATOR DIE AND METHODS FOR MAKING THE SAME - A first semiconductor die is provided, which includes a first substrate, first semiconductor devices, first interconnect-level dielectric material layers, first metal interconnect structures, and first bonding pads. A second semiconductor die is provided, which includes a semiconductor-on-insulator (SOI) substrate, second semiconductor devices, second interconnect-level dielectric material layers, second metal interconnect structures, and second bonding pads. The second bonding pads are bonded to the first bonding pads. A bulk substrate layer of the SOI substrate is removed exposing an insulating material layer of the SOI substrate, which may be retained or also removed. An external bonding pad is electrically connected to a node of the second semiconductor devices. | 2020-09-17 |
20200294919 | INTERCONNECT STRUCTURE WITH AIR-GAPS - The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first metal wire arranged within an inter-level dielectric (ILD) layer over a substrate. A second metal wire is arranged within the ILD layer and is laterally separated from the first metal wire by an air-gap. A dielectric layer is arranged over the first metal wire and the second metal wire. The dielectric layer has a curved surface along a top of the air-gap. The curved surface of the dielectric layer is a smooth curved surface that continuously extends between opposing sides of the air-gap. A via is disposed on and over the second metal wire. | 2020-09-17 |
20200294920 | SUBSTRATE PATCH RECONSTITUTION OPTIONS - Embodiments include semiconductor packages. A semiconductor package includes a first patch and a second patch on an interposer. The semiconductor package also includes a first substrate in the first patch, and a second substrate in the second patch. The semiconductor package further includes an encapsulation layer over and around the first and second patches, a plurality of build-up layers on the first patch, the second patch, and the encapsulation layer, and a plurality of dies and a bridge on the build-up layers. The bridge may be communicatively coupled with the first substrate of the first patch and the second substrate of the second patch. The bridge may be an embedded multi-die interconnect bridge (EMIB). The first and second substrates may be EMIBs and/or high-density packaging (HDP) substrates. The bridge may be positioned between two dies, and over an edge of the first patch and an edge of the second patch. | 2020-09-17 |
20200294921 | PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A package structure includes a first die, a second die, a bridge, an encapsulant and a redistribution layer (RDL) structure. The bridge is arranged side by side with the first die and the second die. The encapsulant laterally encapsulates the first die, the second die and the bridge. The RDL structure is disposed on the first die, the second die, the bridge and the encapsulant. The first die and the second die are electrically connected to each other through the bridge and the RDL structure. | 2020-09-17 |
20200294922 | Semiconductor Device - According to one embodiment, a semiconductor device includes a wiring board, a spacer board that is mounted on the wiring board and in which a power supply conductor layer and a ground conductor layer are provided, at least one first semiconductor chip that is mounted on the spacer board including a power supply layer electrically connected to the power supply conductor layer and a ground layer electrically connected to the ground conductor layer, and a second semiconductor chip that is mounted on the wiring board. | 2020-09-17 |
20200294923 | MULTI-RDL STRUCTURE PACKAGES AND METHODS OF FABRICATING THE SAME - Various arrangements of multi-RDL structure devices are disclosed. In one aspect, an apparatus is provided that includes a first redistribution layer structure and a second redistribution layer structure mounted on the first redistribution layer structure. A first semiconductor chip is mounted on the second redistribution layer structure and electrically connected to both the second redistribution layer structure and the first redistribution layer structure. | 2020-09-17 |
20200294924 | HIGH DENSITY ORGANIC BRIDGE DEVICE AND METHOD - Embodiments that allow multi-chip interconnect using organic bridges are described. In some embodiments an organic package substrate has an embedded organic bridge. The organic bridge can have interconnect structures that allow attachment of die to be interconnected by the organic bridge. In some embodiments, the organic bridge comprises a metal routing layer, a metal pad layer and interleaved organic polymer dielectric layers but without a substrate layer. Embodiments having only a few layers may be embedded into the top layer or top few layers of the organic package substrate. Methods of manufacture are also described. | 2020-09-17 |
20200294925 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor chip including a semiconductor substrate with a top surface electrode deposited on a top surface of the semiconductor substrate. An insulating film selectively covers edges of a top surface of the top surface electrode, and a plating layer covers the top surface of the top surface electrode exposed to an opening of the insulating film. A metal wiring plate includes a junction part located over the insulating film and the plating layer, and provided with a groove recessed upward from a bottom surface of the junction part. A solder part fills the groove so as to bond the plating layer and the bottom surface of the junction part together. A boundary between the insulating film and the plating layer is encompassed within the groove. | 2020-09-17 |
20200294926 | PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A package structure and the method thereof are provided. The package structure includes a conductive plate, a semiconductor die, a molding compound, and antenna elements. The conductive plate has a first surface, a second surface and a sidewall connecting the first surface and the second surface. The semiconductor die is located on the second surface of the conductive plate. The molding compound laterally encapsulates the semiconductor die and covers the sidewall and a portion of the second surface exposed by the semiconductor die, wherein the first surface of the conductive plate is coplanar with a surface of the molding compound. The antenna elements are located over the first surface of the conductive plate. | 2020-09-17 |
20200294927 | CHIP PACKAGE AND MANUFACTURING METHOD THEREOF - A chip package includes a redistribution layer, at least one first semiconductor chip, an integrated fan-out package, and an insulating encapsulation. The at least one first semiconductor chip and the integrated fan-out package are electrically connected to the redistribution layer, wherein the at least one first semiconductor chip and the integrated fan-out package are located on a surface of the redistribution layer and electrically communicated to each other through the redistribution layer, and wherein the integrated fan-out package includes at least one second semiconductor chip. The insulating encapsulation encapsulates the at least one first semiconductor chip and the integrated fan-out package. | 2020-09-17 |
20200294928 | INTERCONNECT STRUCTURE HAVING NANOCRYSTALLINE GRAPHENE CAP LAYER AND ELECTRONIC DEVICE INCLUDING THE INTERCONNECT STRUCTURE - Provided are an interconnect structure and an electronic device including the interconnect structure. The interconnect structure includes a dielectric layer including at least one trench, a conductive wiring filling an inside of the at least one trench, and a cap layer on at least one surface of the conductive wiring. The cap layer includes nanocrystalline graphene. The nanocrystalline includes nano-sized crystals. | 2020-09-17 |
20200294929 | INTERCONNECTION STRUCTURE, SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - An interconnection structure includes a first dielectric layer and a second dielectric layer. The second dielectric layer is disposed on the first dielectric layer. The second dielectric layer has a first surface and a second surface, both facing toward the first dielectric layer. The first surface of the second dielectric layer is recessed from the second surface of the second dielectric layer and defines a recess. A portion of the first dielectric layer is disposed within the recess. | 2020-09-17 |
20200294930 | PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME - A package structure includes a plurality of semiconductor die, an insulating encapsulant and a redistribution layer. Each of the plurality of semiconductor dies includes a semiconductor substrate, conductive pads disposed on the semiconductor substrate, conductive posts disposed on the conductive pads, and at least one alignment mark located on the semiconductor substrate. The insulating encapsulant is encapsulating the plurality of semiconductor dies. The redistribution layer is disposed on the insulating encapsulant and electrically connected to the plurality of semiconductor dies. | 2020-09-17 |