38th week of 2015 patent applcation highlights part 59 |
Patent application number | Title | Published |
20150263139 | SEMICONDUCTOR DEVICE - A semiconductor device includes a memory cell transistor in which a first insulation film, a first conductive layer, a second insulation film, and a second conductive layer are sequentially stacked on a semiconductor substrate, and a peripheral circuit element in which a third insulation film, a third conductive layer, a fourth insulation film, a fourth conductive layer are sequentially stacked on the semiconductor substrate and which has a contact electrically connected to the third conductive layer. In the semiconductor substrate, a recess is formed at least in a region immediately below the contact. The third conductive layer is also formed within the recess, and a film thickness of the third conductive layer in the recess is thicker than a film thickness of the first conductive layer. | 2015-09-17 |
20150263140 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - Provided is a transistor with high field-effect mobility, a transistor having stable electrical characteristics, a transistor having a low off-state current, or a semiconductor device including the transistor. A method for manufacturing a semiconductor device including a first conductor, a first insulator over the first conductor, a first semiconductor over the first insulator, a second semiconductor over the first semiconductor, a second conductor and a third conductor over the second semiconductor, a third semiconductor over the second semiconductor, the second conductor, and the third conductor, a second insulator over the third semiconductor, and a fourth conductor over the second insulator. In the method, formation of layers is performed without exposure to the air. | 2015-09-17 |
20150263141 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - Provided is a method for manufacturing a semiconductor device whose electric characteristics are prevented from being varied and whose reliability is improved. In the method, an insulating film is formed over an oxide semiconductor film, a buffer film is formed over the insulating film, oxygen is added to the buffer film and the insulating film, a conductive film is formed over the buffer film to which oxygen is added, and an impurity element is added to the oxide semiconductor film using the conductive film as a mask. An insulating film containing hydrogen and overlapping with the oxide semiconductor film may be formed after the impurity element is added to the oxide semiconductor film. | 2015-09-17 |
20150263142 | THIN-FILM TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a thin-film transistor comprises an oxide semiconductor layer formed on a part of a substrate, a first gate insulator film of a silicon dioxide film formed on the oxide semiconductor layer and by the CVD method with a silane-based source gas, a second gate insulator film of a silicon dioxide film formed on the first gate insulator film by the CVD method with a TEOS source gas, and a gate electrode formed on the second gate insulator film. | 2015-09-17 |
20150263143 | HETEROJUNCTION BIPOLAR TRANSISTORS WITH INTRINSIC INTERLAYERS - Heterojunction bipolar transistors are provided that include at least one contact (e.g., collector, emitter, and/or base) formed by a heterojunction between a crystalline semiconductor material and a doped non-crystalline semiconductor material layer. An interfacial intrinsic non-crystalline semiconductor material layer is present at the heterojunction between the crystalline semiconductor material and the doped non-crystalline semiconductor material layer. The presence of the interfacial intrinsic non-crystalline semiconductor material layer improves the surface passivation of the crystalline semiconductor material by reducing the interface defect density at the heterojunction. | 2015-09-17 |
20150263144 | SEMICONDUCTOR DEVICE AND INSULATED GATE BIPOLAR TRANSISTOR - According to one embodiment, an insulated gate bipolar transistor includes a main region, a sense region, and a semiconductor layer that is provided between the main region and the sense region, is in contact with a collector layer of a first conductivity type provided in the main region and the sense region, and has one of a dopant concentration lower than a dopant concentration of the collector layer or a second conductivity type opposite the first conductivity type. | 2015-09-17 |
20150263145 | IGBT STRUCTURE FOR WIDE BAND-GAP SEMICONDUCTOR MATERIALS - An IGBT device includes an IGBT stack, a collector contact, a gate contact, and an emitter contact. The IGBT stack includes an injector region, a drift region over the injector region, a spreading region over the drift region, and a pair of junction implants in the spreading region. The spreading region provides a first surface of the IGBT stack, which is opposite the drift region. The pair of junction implants is separated by a channel, and extends from the first surface of the IGBT stack along a lateral edge of the IGBT stack towards the drift region to a first depth, such that the thickness of the spreading region is at least one and a half times greater than the first depth. | 2015-09-17 |
20150263146 | SEMICONDUCTOR DEVICE - A semiconductor device in an embodiment includes a first region of a second conductivity type between a first electrode and a second electrode and a second region of a first conductivity type between the first region and the second electrode. a third region of the second conductivity type is between the second region and the second electrode. A fourth and fifth region of the first conductivity type are between the third semiconductor region and the second electrode. The fourth and fifth regions are adjacent to each other. A dopant concentration in the fifth region is less than a dopant concentration in the fourth region. A third electrode contacts the second region, the third region, the fourth region, and the fifth region via an insulating film. | 2015-09-17 |
20150263147 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate having an inner portion and a peripheral portion around the inner region. A recess is formed in the peripheral region inwardly of the substrate edge and extending into the substrate surface. A diffusion region and a first insulation layer is formed in the recess. The diffusion region is formed intermediate of the first insulation layer and the inner region. A first conductor extends over a portion of the diffusion region and the first insulation layer. A second insulation layer is located over the recess, the first conductor, the diffusion layer and the first insulation layer, and a second conductor layer is disposed on the second insulation layer. The distance between first and second conductor layers where the first conductor layer extends over the diffusion layer is greater than the distance therebetween where the second conductor overlies the first insulation layer. | 2015-09-17 |
20150263148 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a first semiconductor layer, a first semiconductor region, a second semiconductor region, and an insulating layer. The first semiconductor layer is provided between the first electrode and the second electrode, and contacts the first electrode. The first semiconductor region is provided between the first semiconductor layer and the second electrode, and contacts the second electrode. The second semiconductor region is provided between the first semiconductor region and the second electrode, and contacts the second electrode. An impurity concentration of the second semiconductor region is higher than an impurity concentration of the first semiconductor region. An insulating layer has one end contacting the second electrode and the other end positioned in the first semiconductor layer. The insulating layer extends along the second electrode in a first direction from the first electrode towards the second electrode. | 2015-09-17 |
20150263149 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a first semiconductor region, a second semiconductor region, an insulating region, and a third semiconductor region. The first semiconductor region is of a first conductivity type. The first semiconductor region is provided between the first electrode and the second electrode, and contacts the first electrode. The second semiconductor region is of a second conductivity type. The second conductor region is provided between the first semiconductor region and the second electrode. The insulating region extends from the second electrode to a side of the first semiconductor region. The third semiconductor region is of the first conductivity type. The third semiconductor region is provided in at least a portion of a region between the second semiconductor region and the insulating region, and contacts the first semiconductor region. | 2015-09-17 |
20150263150 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor device including: a first electrode; a second electrode having a portion extending toward the first electrode side; a first semiconductor layer; a first semiconductor region provided between the first semiconductor layer and the second electrode; a second semiconductor region provided between the first semiconductor region and the second electrode, and the second semiconductor region being in contact with the portion; a third electrode provided between the first electrode and the portion, and the third electrode being connected to the portion; a fourth electrode provided on the first semiconductor layer, the first semiconductor region, and the second semiconductor region via a second insulating film; and a third semiconductor region provided between the first semiconductor region and the second semiconductor region, and the third semiconductor region having a higher impurity concentration than the first semiconductor region. | 2015-09-17 |
20150263151 | SEMICONDUCTOR DEVICE - A semiconductor device is disclosed that comprises semiconductor regions and an insulating film. A groove extends from a top surface of a semiconductor region and reaching a semiconductor region. In plan view, a body of a bottom electrode is formed in a strip form, and extends in an extending direction of the groove, and the connection portion extends in a depth direction of the groove and is connected to an end of the body in the extending direction of the body. The body of the bottom electrode is arranged in the groove, and the connection portion of the bottom electrode is arranged in the connection groove. In plan view, a length of the groove in the extending direction of the groove is larger than a width of the groove, and the width of the groove is larger than a gap between the groove and an adjacent groove. | 2015-09-17 |
20150263152 | SEMICONDUCTOR DEVICE - A semiconductor device includes a GaN-based semiconductor layer, a source electrode on the GaN-based semiconductor layer, a drain electrode on the GaN-based semiconductor layer, and a gate electrode formed on the GaN-based semiconductor layer between the source electrode and the drain electrode. A first layer is in contact with the GaN-based semiconductor layer between the gate electrode and the drain electrode. | 2015-09-17 |
20150263153 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a first semiconductor layer; a second semiconductor layer having a larger band gap than the first semiconductor layer; a third semiconductor layer having a smaller band gap than the second semiconductor layer; a first electrode being in contact with the third semiconductor layer; a second electrode being in contact with the third semiconductor layer; and a third electrode provided between the third semiconductor layer in contact with the first electrode, the second semiconductor layer directly below the first electrode, and the first semiconductor layer directly below the first electrode, and the third semiconductor layer in contact with the second electrode, the second semiconductor layer directly below the second electrode, and the first semiconductor layer directly below the second electrode, being in contact with the third semiconductor layer, the second semiconductor layer, and the first semiconductor layer via insulating film. | 2015-09-17 |
20150263154 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first and second nitride semiconductor layer. The second nitride semiconductor layer has a band gap larger the first nitride semiconductor layer. Source and drain electrodes are formed spaced from each other on the second nitride semiconductor layer. A third nitride semiconductor layer is formed on the second nitride semiconductor layer between the source and drain electrodes. A gate electrode is formed on the third nitride semiconductor layer. The third nitride semiconductor layer comprises at least two first layers and at least one a second layer which has a lower p-type dopant concentration than the first layer. The second layer also has a band gap larger than the first layer. The lowermost layer and the uppermost layer in the third nitride semiconductor layer stack are the first layers. | 2015-09-17 |
20150263155 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first nitride semiconductor layer and a second nitride semiconductor layer having a band gap wider than the first nitride semiconductor layer. Source and drain electrodes are provided on the second nitride semiconductor layer. A third nitride semiconductor layer is provided between the source electrode and the drain electrode on the second nitride semiconductor layer. The third nitride semiconductor layer has an impurity concentration of 1×10 | 2015-09-17 |
20150263156 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes first electrode and second electrodes, first, second, third, fifth, and fourth semiconductor regions, a third electrode, and a second insulating film. The first semiconductor region is provided between the first and second electrodes. The second semiconductor region is provided between the first semiconductor region and the first electrode. The third semiconductor region is provided between the first semiconductor region and the second electrode. The fifth semiconductor region is provided between the first semiconductor region and the second electrode. The fourth semiconductor region is provided between the third semiconductor region and the second electrode and between the fifth semiconductor region and the second electrode. The third electrode contacts the first, third, and fourth semiconductor regions via a first insulating film. The second insulating film contacts the first, fifth, and fourth semiconductor regions. | 2015-09-17 |
20150263157 | SEMICONDUCTOR DEVICE - A semiconductor device of an embodiment includes: an n-type nitride semiconductor layer; an insulating layer selectively provided on the nitride semiconductor layer; an n-type first nitride semiconductor region provided on the nitride semiconductor layer and the insulating layer; an n-type second nitride semiconductor region provided on the insulating layer; a p-type third nitride semiconductor region provided between the first nitride semiconductor region and the second nitride semiconductor region; a gate insulating film provided on the third nitride semiconductor region; a gate electrode provided on the gate insulating film; a first electrode electrically connected to the second nitride semiconductor region; and a second electrode that is provided on the opposite side of the nitride semiconductor layer from the insulating layer, and is electrically connected to the nitride semiconductor layer. | 2015-09-17 |
20150263158 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes first electrode, second electrode, and third electrodes, first, second, third, fourth, and fifth semiconductor regions. The first semiconductor region is provided between the first and second electrodes. The second semiconductor region is provided between the first semiconductor region and the second electrode. The third semiconductor region is provided between the second semiconductor region and the second electrode. The third semiconductor region has an impurity concentration higher than an impurity concentration of the first semiconductor region. The third electrode contacts the third, second, and first semiconductor regions via an insulating film. The fourth semiconductor region is provided between the first semiconductor region and the second electrode. The fifth semiconductor region is provided between the fourth semiconductor region and the second electrode. The fifth semiconductor region has an impurity concentration higher than the impurity concentration of the first semiconductor region. | 2015-09-17 |
20150263159 | FINFET Structure and Method for Fabricating the Same - A device comprises a substrate comprising silicon, a fin structure comprising a lower portion formed of silicon and enclosed by an isolation region, a middle portion formed of silicon-germanium-carbon, wherein the middle portion is enclosed by an oxide layer, an upper portion formed of silicon, wherein the upper portion comprises a channel and a silicon-carbon layer formed between the middle portion and the upper portion, a first source/drain region comprising a first silicon-phosphorus region and a first silicon-carbon layer formed underlying the first silicon-phosphorus region and a second source/drain region comprising a second silicon-phosphorus region and a second silicon-carbon layer formed underlying the second silicon-phosphorus region. | 2015-09-17 |
20150263160 | SEMICONDUCTOR DEVICE WITH SELF-ALIGNED CONTACT ELEMENTS - One method disclosed herein includes forming a sacrificial etch stop material in a recess above a replacement gate structure, with the sacrificial etch stop material in position, forming a self-aligned contact that is conductively coupled to the source/drain region, after forming the self-aligned contact, performing at least one process operation to expose and remove the sacrificial etch stop material in the recess so as to thereby re-expose the recess, and forming a third layer of insulating material in at least the re-exposed recess. | 2015-09-17 |
20150263161 | SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor storage device includes a semiconductor substrate; an active region provided in the semiconductor substrate and extending in a first direction; and a plurality of gates provided above the active region and extending in a second direction. The gates are provided with a stack of a floating gate and a control gate, and an elevated portion is provided above the active region disposed between adjacent gates. | 2015-09-17 |
20150263162 | SEMICONDUCTOR DEVICE - In one embodiment, a semiconductor device includes first, second, third, fourth, fifth and sixth electrodes extending in a first direction, the third and fourth electrodes being provided to sandwich the first electrode, the fifth and sixth electrodes being provided to sandwich the second electrode, the first, second, fifth and sixth electrodes being electrically connected with one another, and the third and fourth electrodes being electrically connected with each other and electrically independent from the first, second, fifth and sixth electrodes. The device further includes a semiconductor layer provided between one of the third and fourth electrodes and one of the fifth and sixth electrodes. The device further includes a first interconnect provided on the second, fifth and sixth electrodes and on the semiconductor layer. | 2015-09-17 |
20150263163 | SEMICONDUCTOR DEVICE - A semiconductor device includes first and second semiconductor layers, first and second semiconductor regions, a source region, a drain region, and a gate electrode. The second semiconductor layer of a first conductive type is formed over the first semiconductor layer. The first semiconductor region of a second conductive type is formed on a surface of the second semiconductor layer. The source region of the first type is formed on a surface of the first semiconductor region. The drain region of the first type is formed on a surface of the first semiconductor layer having the first type, is separated from the source region. The second semiconductor region of the second type is provided between the drain region and the first semiconductor layer. The gate electrode is formed over the second semiconductor layer and is provided between the drain region and the source region. | 2015-09-17 |
20150263164 | HIGH VOLTAGE AND ULTRA-HIGH VOLTAGE SEMICONDUCTOR DEVICES WITH INCREASED BREAWKDOWN VOLTAGES - A lateral DMOS transistor is provided with a source region, a drain region, and a conductive gate. The drain region is laterally separated from the conductive gate by a field oxide that encroaches beneath the conductive gate. The lateral DMOS transistor may be formed in a racetrack-like configuration with the conductive gate including a rectilinear portion and a curved portion and surrounded by the source region. Disposed between the conductive gate and the trapped drain is one or more levels of interlevel dielectric material. One or more groups of isolated conductor leads are formed in or on the dielectric layers and may be disposed at multiple device levels. The isolated conductive leads increase the breakdown voltage of the lateral DMOS transistor particularly in the curved regions where electric field crowding can otherwise degrade breakdown voltages. | 2015-09-17 |
20150263165 | Semiconductor Device Having a Charge Compensation Region - A semiconductor device includes a semiconductor material of a first conductivity type, a body region of a second (opposite) conductivity type extending into the semiconductor material from a main surface of the semiconductor material, a source region of the first conductivity type disposed in the body region, and a channel region extending laterally in the body region from the source region along the main surface. A charge compensation region of the second conductivity type can be provided under the body region which extends in a direction parallel to the main surface and terminates prior to a pn-junction between the source and body regions at the main surface, and/or an additional region of the first conductivity type which has at least one peak doping concentration each of which occurs deeper in the semiconductor material from the main surface than a peak doping concentration of the device channel region. | 2015-09-17 |
20150263166 | ELECTRONIC DEVICE INCLUDING A TRENCH AND A CONDUCTIVE STRUCTURE THEREIN - An electronic device can include a transistor structure, including a patterned semiconductor layer overlying a substrate and having a primary surface. The electronic device can further include first conductive structures within each of a first trench and a second trench, a gate electrode within the first trench and electrically insulated from the first conductive structure, a first insulating member disposed between the gate electrode and the first conductive structure within the first trench, and a second conductive structure within the second trench. The second conductive structure can be electrically connected to the first conductive structures and is electrically insulated from the gate electrode. The electronic device can further include a second insulating member disposed between the second conductive structure and the first conductive structure within the second trench. Processing sequences can be used that simplify formation of the features within the electronic device. | 2015-09-17 |
20150263167 | MULTIGATE DUAL WORK FUNCTION DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor device includes a drain region, a source region, a channel region, a first gate insulator film provided on the channel region, a second gate insulator film provided on the channel region to be adjacent to the first gate insulator film on the source region side of the first gate insulator film, a first gate electrode provided on the first gate insulator film, and a second gate electrode provided on the second gate insulator film. An electrical thickness of the second gate insulator film is less than an electrical thickness of the first gate insulator film. A portion of the first gate electrode is provided on the second gate insulator film. A work function of the second gate electrode is higher than a work function of the first gate electrode. | 2015-09-17 |
20150263168 | Structure and Method for Semiconductor Device - A semiconductor device and a method of forming the same are disclosed. The semiconductor device includes a substrate, and a source region and a drain region formed in the substrate. The semiconductor device further includes an impurity diffusion stop layer formed in a recess of the substrate between the source region and the drain region, wherein the impurity diffusion stop layer covers bottom and sidewalls of the recess. The semiconductor device further includes a channel layer formed over the impurity diffusion stop layer and in the recess, and a gate stack formed over the channel layer. The impurity diffusion stop layer substantially prevents impurities of the substrate and the source and drain regions from diffusing into the channel layer. | 2015-09-17 |
20150263169 | SEMICONDUCTOR STRUCTURES WITH BRIDGING FILMS AND METHODS OF FABRICATION - Semiconductor structures and fabrication methods are provided having a bridging film which facilitates adherence of both an underlying layer of dielectric material and an overlying stress-inducing layer. The method includes, for instance, providing a layer of dielectric material, with at least one gate structure disposed therein, over a semiconductor substrate; providing a bridging film over the layer of dielectric material with the at least one gate structure; and providing a stress-inducing layer over the bridging film. The bridging film is selected to facilitate adherence of both the underlying layer of dielectric material and the overlying stress-inducing layer by, in part, forming a chemical bond with the layer of dielectric material, without forming a chemical bond with the stress-inducing layer. | 2015-09-17 |
20150263170 | SEMICONDUCTOR PROCESS FOR MODIFYING SHAPE OF RECESS - A semiconductor process includes the following steps. Two gates are formed on a substrate. A recess is formed in the substrate beside the gates. A surface modification process is performed on a surface of the recess to modify the shape of the recess and change the contents of the surface. | 2015-09-17 |
20150263171 | RECESS AND EPITAXIAL LAYER TO IMPROVE TRANSISTOR PERFORMANCE - Some embodiments of the present disclosure relate to a semiconductor device configured to mitigate against parasitic coupling while maintaining threshold voltage control for comparatively narrow transistors. In some embodiments, a semiconductor device formed on a semiconductor substrate. The semiconductor device comprises a channel comprising an epitaxial layer that forms an outgrowth above the surface of the semiconductor substrate, and a gate material formed over the epitaxial layer. In some embodiments, a method of forming a semiconductor device is disclosed. The method comprises etching the surface of a semiconductor substrate to form a recess between first and second isolation structures, forming an epitaxial layer within the recess that forms an outgrowth above the surface of the semiconductor substrate, and forming a gate material over the epitaxial layer. Other embodiments are also disclosed. | 2015-09-17 |
20150263172 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device is provided. A substrate includes a fin. The fin extends in a first direction. A gate structure is disposed on a first region of the fin. The gate structure extends in a second direction crossing the first direction. A source/drain is disposed on a second region of the fin. The first source/drain is disposed on at least one sidewall of the gate structure. A top surface of the first region is lower than a top surface of the second region. | 2015-09-17 |
20150263173 | HIGH VOLTAGE FIELD EFFECT TRANSISTORS AND CIRCUITS UTILIZING THE SAME - A high-voltage circuit is described that comprises a high-voltage finFET can have a semiconductor fin with an insulating cap on the fin. A gate dielectric is disposed on the first and second sides of the second. A gate overlies the gate dielectric and a channel region in the fin on the first and second sides, and over the cap. Source/drain terminals are disposed on opposing sides of the gate in the fin, and can include lightly doped regions that extend away from the edge of the gate to more highly doped contacts. The dimensions of the structures can be configured so that the transistor has a breakdown voltage of 30 V or higher. | 2015-09-17 |
20150263174 | SEMICONDUCTOR DEVICE, DISPLAY DEVICE INCLUDING THE SEMICONDUCTOR DEVICE, DISPLAY MODULE INCLUDING THE DISPLAY DEVICE, AND ELECTRONIC APPLIANCE INCLUDING THE SEMICONDUCTOR DEVICE, THE DISPLAY DEVICE, AND THE DISPLAY MODULE - In a semiconductor device including a transistor, the transistor is provided over a first insulating film, and the transistor includes an oxide semiconductor film over the first insulating film, a gate insulating film over the oxide semiconductor film, a gate electrode over the gate insulating film, a second insulating film over the oxide semiconductor film and the gate electrode, and a source and a drain electrodes electrically connected to the oxide semiconductor film. The first insulating film includes oxygen. The second insulating film includes hydrogen. The oxide semiconductor film includes a first region in contact with the gate insulating film and a second region in contact with the second insulating film. The first insulating film includes a third region overlapping with the first region and a fourth region overlapping with the second region. The impurity element concentration of the fourth region is higher than that of the third region. | 2015-09-17 |
20150263175 | SEMICONDUCTOR DEVICE - To stably control a threshold voltage of a functional circuit using an oxide semiconductor. A variable bias circuit, a monitoring oxide semiconductor transistor including a back gate, a current source, a differential amplifier, a reference voltage source, and a functional circuit which includes an oxide semiconductor transistor including a back gate are provided. The current source supplies current between a source and a drain of the monitoring oxide semiconductor transistor to generate a gate-source voltage in accordance with the current. The differential amplifier compares the voltage with a voltage of the reference voltage source, amplifies a difference, and outputs a resulting voltage to the variable bias circuit. The variable bias circuit is controlled by an output of the differential amplifier and supplies voltage to the back gate of the monitoring oxide semiconductor transistor and the back gate of the oxide semiconductor transistor included in the functional circuit. | 2015-09-17 |
20150263176 | THIN FILM TRANSISTOR AND MANUFACTURING METHOD FOR THE SAME - A thin film transistor and a manufacturing method for the same are provided. The thin film transistor comprises a substrate, a double channel semiconductor layer, a semiconductor passivation layer, a gate, a gate dielectric layer, a source and a drain. The double channel semiconductor layer comprises a first semiconductor layer and a second semiconductor layer. The first semiconductor layer is made of a metallic oxide semiconductor material and formed above the substrate. The second semiconductor layer is made of the metallic oxide semiconductor material doped by an oxygen gettering metal and formed on the first semiconductor layer. The semiconductor passivation layer is formed on the second semiconductor layer. The gate is formed above the substrate. The gate dielectric layer is formed between the gate and the double channel semiconductor layer. The source and drain are close to the double channel semiconductor layer, formed above the substrate and electrically connected to the double channel semiconductor layer. | 2015-09-17 |
20150263177 | METHOD FOR PROCESSING OXIDE SEMICONDUCTOR LAYER - A method for processing an oxide semiconductor containing indium, gallium, and zinc is provided. In the method, the oxide semiconductor layer comprises a plurality of excess oxygen, a first oxygen vacancy that is close to first indium and captures first hydrogen, and a second oxygen vacancy that is close to second indium and captures second hydrogen, the first hydrogen captured by the first oxygen vacancy is bonded to one of a plurality of excess oxygen to so that a hydroxyl is formed; the hydroxyl is bonded to the second hydrogen captured by the second oxygen vacancy to release as water; and then, the first oxygen vacancy captures one of excess oxygen and the second oxygen vacancy captures one of excess oxygen. | 2015-09-17 |
20150263178 | JFET AND METHOD OF MANUFACTURING THEREOF - A JFET has a semiconductor body with a first surface and second surface substantially parallel to the first surface. A source metallization and gate metallization are arranged on the first surface. A drain metallization is arranged on the second surface. In a sectional plane substantially perpendicular to the first surface, the semiconductor body includes: a first semiconductor region in ohmic contact with the source and drain metallizations, at least two second semiconductor regions in ohmic contact with the gate metallization, spaced apart from one another, and forming respective first pn-junctions with the first semiconductor region, and at least one body region forming a second pn-junction with the first semiconductor region. The at least one body region is in ohmic contact with the source metallization. At least a portion of the at least one body region is, in a projection onto the first surface, arranged between the two second semiconductor regions. | 2015-09-17 |
20150263179 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first electrode, a second electrode, a first conductivity-type first semiconductor region between the first electrode and the second electrode, a first conductivity-type second semiconductor region between the first electrode and the first semiconductor region, the second semiconductor region having a dopant concentration that is higher than a dopant concentration of the first semiconductor region, the second semiconductor region including a silicide layer in contact with the first electrode, and a second conductivity-type third semiconductor region between the first semiconductor region and the second electrode. | 2015-09-17 |
20150263180 | WIDE BANDGAP SEMICONDUCTOR DEVICE - A wide bandgap semiconductor device includes a wide bandgap semiconductor layer and a Schottky electrode. The wide bandgap semiconductor layer includes a first impurity region which is in contact with the Schottky electrode, is in contact with a second main surface, and has a first conductivity type, and a second impurity region which is in contact with the Schottky electrode, is in contact with the first impurity region, and has a second conductivity type, The second impurity region has a first region which is in contact with the Schottky electrode, and a second region which is connected with the first region and provided on a side of the first region closer to the second main surface, A maximum value of a width of the second region is larger than a width of a boundary portion between the first region and the Schottky electrode. | 2015-09-17 |
20150263181 | COMPACT MEMORY STRUCTURE INCLUDING TUNNELING DIODE - A resonant inter-band tunnel diode (RITD) can be fabricated using semiconductor processing similar to that used for Complementary Metal-Oxide-Semiconductor (CMOS) device fabrication, such as can include using silicon. A memory cell (e.g., a random access memory (RAM) cell) can be fabricated to include one or more negative differential resistance device, such as tunneling diodes, such as to provide a single-bit or multi-bit cell. In an example, a “hybrid” memory cell can be fabricated, such as including one or more negative resistance devices, a MOS transistor structure, and a capacitor structure, such as including an integrated capacitor configuration similar to a generally-available dynamic RAM (DRAM) structure, but such as without requiring a refresh and offering a higher area efficiency. | 2015-09-17 |
20150263182 | PHOTOVOLTAIC MODULE WITH FLEXIBLE CIRCUIT - A photovoltaic module, and method of making, is disclosed in which a flexible circuit is electrically coupled to a plurality of photovoltaic cells, where the photovoltaic cells are electrically coupled in series to form a series of cells. Each photovoltaic cell has free-standing metallic articles coupled to the top and bottom surfaces of a semiconductor substrate. A cell interconnection element of each photovoltaic cell is electrically coupled to a free-standing metallic article of an adjacent photovoltaic cell, where the interconnection elements of the initial and final cells in the series serve as contact ends for the series of cells. Contact tabs of the flexible circuit are electrically coupled to the contact ends of the series of cells, and a junction box is electrically coupled to a junction box contact region of the flexible circuit. | 2015-09-17 |
20150263183 | Solar Cell Interconnector, Solar Cell Array and Method of Interconnecting Solar Cells of a Solar Cell Array - In a solar cell interconnector ( | 2015-09-17 |
20150263184 | PHOTOCOUPLER - A photocoupler includes: an insulating substrate; an input terminal; an output terminal; a die pad part; a light emitting element; and a light receiving element. The insulating substrate includes a first layer and a second layer. The insulating substrate is provided with a plurality of through holes. The input terminal includes a first terminal and a second terminal. The first terminal includes a first conductive region, a second conductive region, a through conductive region, and a first spiral conductive region. The second terminal includes a first conductive region, a second conductive region, a through conductive region, and a second spiral conductive region. The light receiving element is bonded to the die pad part and connected to the output terminal. The light emitting element is bonded to an upper surface of the light receiving element. | 2015-09-17 |
20150263185 | PHOTOSENSOR - A photosensor includes a sensor module in which emitter and receiver leads protrude from a circuit-encapsulating portion in a direction intersecting with a direction in which an external connecting terminal extends. The photosensor includes a light emitter, a light receiver, a circuit-encapsulating portion, a connecting terminal, first and second emitter leads, and first and second receiver leads. When the connecting terminal extends in a first direction, and a first plane is parallel to the first direction, the first and second emitter leads protrude from the circuit-encapsulating portion in a direction parallel to the first plane and intersecting with the first direction, and extend opposite to the first direction. The first and second receiver leads protrude from the circuit-encapsulating portion in the direction parallel to the first plane and intersecting with the first direction and opposite to a direction in which the first and second emitter leads protrude, and extend opposite to the first direction. The first and second emitter leads and the first and second receiver leads are deformed to allow the light receiver and the light emitter to face each other. | 2015-09-17 |
20150263186 | PHOTOSENSOR - A photosensor simplifies the resin molding process for an emitter element, a receiver element, and a luminous element forming an operation indicator lamp. The photosensor includes an emitter element, an emitter-encapsulating portion, a receiver element, a receiver-encapsulating portion, a circuit portion, and a circuit-encapsulating portion. The emitter-encapsulating portion encapsulates the emitter element. The receiver-encapsulating portion encapsulates the receiver element. The circuit portion includes a luminous element for indicating an operation. The circuit-encapsulating portion encapsulates the circuit portion. The circuit-encapsulating portion includes an operation indicator portion facing the luminous element. The emitter-encapsulating portion, the receiver-encapsulating portion, and the circuit-encapsulating portion are connected to one another with a conductive leadframe. The emitter-encapsulating portion, the receiver-encapsulating portion, and the circuit-encapsulating portion are formed from the same resin material containing a light diffusing agent. | 2015-09-17 |
20150263187 | PROTECTIVE FILM FOR USE WITH SOLAR CELL AND THE SOLAR CELL - A protective film for use with a solar cell and the solar cell are introduced. The protective film is a protective coating formed on an anti-reflection layer of the solar cell. The protective film is characterized in that the protective coating is made of an organic material or a phosphor-containing organic material. Accordingly, the protective film dispenses with the need to make any change to a conventional solar cell-related semiconductor manufacturing process but only requires mixing the constituent ingredients of a material of which the protective coating on the anti-reflection layer is made, so as to enable ultraviolet to be partially converted into absorbable light and thus enhance the photovoltaic conversion efficiency. | 2015-09-17 |
20150263188 | SOLAR CELL AND METHOD FOR MANUFACTURING THE SAME - A solar cell is discussed, and includes a substrate; a first field region; a first electrode directly formed on an emitter region; and a second electrode directly formed on a second field region, wherein a second passivation layer comprises a first back passivation portion and a second back passivation portion. Furthermore, the first back passivation portion is merely positioned between the emitter region and the substrate and the second field region and the substrate, and the second back passivation portion is positioned between the emitter region and the second field region, and wherein the first back passivation portion positioned between the emitter region and the substrate is physically separated from first back passivation portion positioned between the second field region and the substrate. | 2015-09-17 |
20150263189 | THIN FILM AND METHOD FOR MANUFACTURING THE SAME - Provided embodiments are a thin film including a support material and nano particles having different density from that of the support material, and a method for manufacturing the same. Due to the density difference, the nano particles are intensively concentrated on an upper or lower part of the support material. The inventive concept also discloses a thin film capable of increasing surface roughness and a method for manufacturing the same. The thin film includes a support material, and particles contained therein. The particles may have lower density than that of the support material, and increase surface roughness at an upper part of the support material. | 2015-09-17 |
20150263190 | INTEGRATED THERMAL STABILIZATION OF A MICRORING RESONATR - Embodiments of the present disclosure provide devices and methods involving the thermal stabilization of microring resonators, such as microring modulators. Power is measured via an on-chip photodetector integrated with a drop port of the microring resonator, providing a local measurement of average power. This average power is employed as a feedback measure to actively control a heater that is integrated with the microring resonator, in order to stabilize the resonant wavelength of the microring resonator in the presence of thermal fluctuations. Employing such a system, a microring modulator can maintain error-free performance under thermal fluctuations that would normally render it inoperable. | 2015-09-17 |
20150263191 | CONE-SHAPED HOLES FOR HIGH EFFICIENCY THIN FILM SOLAR CELLS - A photovoltaic device includes a substrate having a plurality of hole shapes formed therein. The plurality of hole shapes each have a hole opening extending from a first surface and narrowing with depth into the substrate. The plurality of hole shapes form a hole pattern on the first surface, and the hole pattern includes flat areas separating the hole shapes on the first surface. A photovoltaic device stack is formed on the first surface and extends into the hole shapes. Methods are also provided. | 2015-09-17 |
20150263192 | ELECTRO-CONDUCTIVE PASTE COMPRISING AG NANO-PARTICLES AND SPHERICAL AG MICRO-PARTICLES IN THE PREPARATION OF ELECTRODES - The invention relates to an electro-conductive paste comprising Ag nano-particles and spherical Ag micro-particles in the preparation of electrodes, particularly in electrical devices, particularly in temperature sensitive electrical devices or solar cells, particularly in HIT (Heterojunction with Intrinsic Thin-layer) solar cells. In particular, the invention relates to a paste, a process for preparing a paste, a precursor, a process for preparing an electrical device and a module comprising electrical devices. The invention relates to a paste comprising the following paste constituents:
| 2015-09-17 |
20150263193 | SOLAR CELL - Discussed is a solar cell includes a semiconductor substrate, a conductive type region including a first conductive type region and a second conductive type region formed on one surface of the semiconductor substrate, an electrode including a first electrode and a second electrode, wherein the first electrode is connected to the first conductive type region and the second electrode is connected to the second conductive type region, and a passivation layer formed on the conductive type region. The passivation layer includes at least one of silicon nitride and silicon carbide. | 2015-09-17 |
20150263194 | SOLAR CELL - A solar cell has multiple busbar electrodes formed at intervals and multiple finger electrodes formed between the busbar electrodes. The finger electrodes comprise multiple finger parts connected only to one busbar electrode and multiple finger parts connected to only another busbar electrode. The adjacent multiple finger parts are connected to one another, and the adjacent multiple finger parts are connected to one another. | 2015-09-17 |
20150263195 | SOLAR CELL AND METHOD OF FABRICATING SAME - A solar cell and a method of fabricating the solar cell is described. The solar cell includes a substrate, a back contact layer over the substrate, a P1 trench on an upper portion of the back contact layer, and an insulator disposed in the P1 trench. The solar cell can also include an absorber layer over the back contact layer and insulator and a front contact layer over the absorber layer. | 2015-09-17 |
20150263196 | PHOTOVOLTAIC MODULE AND PROCESS FOR MANUFACTURE THEREOF - A photovoltaic module has a plurality of interconnected polymer sockets that have accepted and electrically connected a plurality of back-contact photovoltaic cells each having at least one set of linearly arranged back face emitter contacts and at least one set of linearly arranged back face collector contacts. A process for manufacturing such a photovoltaic module is also provided. | 2015-09-17 |
20150263197 | PHOTOVOLTAIC DEVICE INTERCONNECTION AND METHOD OF MANUFACTURING - A photovoltaic device includes a substrate and has a transparent conductive oxide layer, a conductive back layer, and at least one intermediate semiconductor layer formed thereon. An isolation scribe divides and electrically isolates the oxide layer, the back layer and the semiconductor layer to define two photovoltaic cells. A conductor extends across the isolation scribe and connects the back layer of one photovoltaic cell to the oxide layer of the other photovoltaic cell. | 2015-09-17 |
20150263198 | METHOD OF CIGS ABSORBER FORMATION - A method of forming a CIGS absorber wherein at least one source particle is selected and prepared as a powder or gel; the powder or gel is deposited on a substrate, compressed, and annealed. In some embodiments, a plurality of source particles are prepared as powders and mixed prior to deposition, compression, and annealing. In other embodiments, a plurality of source particles are individually deposited in layers, collectively compressed, and collectively annealed. In yet further embodiments, a plurality of source particles are individually deposited in layers, individually compressed, and collectively annealed. | 2015-09-17 |
20150263199 | TANDEM SOLAR CELL WITH IMPROVED ABSORPTION MATERIAL - A photosensitive device and method includes a top cell having an N-type layer, a P-type layer and a top intrinsic layer therebetween. A bottom cell includes an N-type layer, a P-type layer and a bottom intrinsic layer therebetween. The bottom intrinsic layer includes a Cu—Zn—Sn containing chalcogenide. | 2015-09-17 |
20150263200 | METHOD OF FABRICATING A SOLAR CELL WITH A TUNNEL DIELECTRIC LAYER - Methods of fabricating solar cells with tunnel dielectric layers are described. Solar cells with tunnel dielectric layers are also described. | 2015-09-17 |
20150263201 | METHODS OF GROWING HETEROEPITAXIAL SINGLE CRYSTAL OR LARGE GRAINED SEMICONDUCTOR FILMS AND DEVICES THEREON - A method is disclosed for making semiconductor films from a eutectic alloy comprising a metal and a semiconductor. Through homogeneous nucleation said film is deposited at a deposition temperature on flexible substrates, such as glass. Specifically said film is vapor deposited at a fixed temperature in said deposition temperature where said deposition temperature is above a eutectic temperature of said eutectic alloy and below a temperature at which the substrate softens. Such films could have widespread application in photovoltaic and display technologies. | 2015-09-17 |
20150263202 | Alternating Bias Hot Carrier Solar Cells - Designs of extremely high efficiency solar cells are described. A novel alternating bias scheme enhances the photovoltaic power extraction capability above the cell band-gap by enabling the extraction of hot carriers. When applied in conventional solar cells, this alternating bias scheme has the potential of more than doubling their yielded net efficiency. When applied in conjunction with solar cells incorporating quantum wells (QWs) or quantum dots (QDs) based solar cells, the described alternating bias scheme has the potential of extending such solar cell power extraction coverage, possibly across the entire solar spectrum, thus enabling unprecedented solar power extraction efficiency. Within such cells, a novel alternating bias scheme extends the cell energy conversion capability above the cell material band-gap while the quantum confinement structures are used to extend the cell energy conversion capability below the cell band-gap. Light confinement cavities are incorporated into the cell structure in order to allow the absorption of the cell internal photo emission, thus further enhancing the cell efficiency. | 2015-09-17 |
20150263203 | INTERMEDIATE BAND SEMICONDUCTORS, HETEROJUNCTIONS, AND OPTOELECTRONIC DEVICES UTILIZING SOLUTION PROCESSED QUANTUM DOTS, AND RELATED METHODS - A semiconductor includes first quantum dots and second quantum dots of a lesser amount, which are dispersed throughout the first quantum dots. The second quantum dots have a different size or composition than the first quantum dots such that the second quantum dots have a first exciton peak wavelength longer than a first exciton peak wavelength of the first quantum dots. The quantum dot layer includes a valence band, a conduction band, and an intermediate band having an energy level within a bandgap between the valence band and the conduction band. The quantum dots may be solution processed. The semiconductor may be utilized to form an electronic heterojunction, and optoelectronic devices including the electronic heterojunction. | 2015-09-17 |
20150263204 | REDUCED JUNCTION AREA BARRIER-BASED PHOTODETECTOR - A photodetector structure having a barrier layer disposed between a pair of like-conductively doped semiconductor layers, the barriers layer having a surface area smaller than the surface area of the upper one of the pair of semiconductor layers. A fill material is disposed between outer peripheral edges of the barrier layer and a region between outer peripheral edges of the first and second layers. | 2015-09-17 |
20150263205 | CYLINDRICAL SOLAR MODULE AND METHOD OF MAKING THE MODULE - A solar module comprises a cylindrical substrate, a back contact layer around the substrate, an absorber layer around the back contact layer, a buffer layer around the absorber layer, a front contact layer around the substrate to form a solar module, and a conformal polymer layer encasing the solar module. | 2015-09-17 |
20150263206 | PROTECTIVE SHEET FOR REAR SURFACE OF SOLAR CELL - This invention provides a solar cell rear surface protection sheet comprising two or more substrates laminated together by means of an adhesive, the adhesive comprising a urethane resin obtained by mixing an acrylic polyol, an isocyanate compound, 3-glycidoxypropyltriethoxysilane, and tin octylate, wherein
| 2015-09-17 |
20150263207 | SOLAR CELL INTERCONNECTS AND METHOD OF FABRICATING SAME - A solar cell device and a method of fabricating the device is described. The solar cell is fabricated by providing a substructure comprising an absorber over a back contact having a P1 line therein and scribing a P2 line in the absorber by mechanical scribing and laser scribing after the mechanical scribing. The scribing can be performed with an integrated scriber, including a scribing tip and a light source mounted adjacent the scribing tip and operable concurrently with the scribing tip. | 2015-09-17 |
20150263208 | Method of Forming an Electronic Article - An electronic article has a perimeter and includes a superstrate, an optoelectronic element disposed on the superstrate, and a silicone encapsulant that is formed from a curable silicone composition and that is disposed on the optoelectronic element sandwiching the optoelectronic element between the superstrate and the silicone encapsulant. The electronic article is formed using a method that includes the step of depositing the curable silicone composition on the optoelectronic element in a pattern defining at least one passage extending from an interior of the electronic article to a perimeter of the electronic article. The method also includes laminating the superstrate, the optoelectronic element, and the curable silicone composition. The curable silicone composition has a complex viscosity of from 10,000 to 50,000,000 cPs at 25° C. as measured at 1 radian per second at 1 to 5% strain. During lamination, the curable silicone composition cures to form the silicone encapsulant and air escapes from through the at least one passage. | 2015-09-17 |
20150263209 | BORON, BISMUTH CO-DOPING OF GALLIUM ARSENIDE AND OTHER COMPOUNDS FOR PHOTONIC AND HETEROJUNCTION BIPOLAR TRANSISTOR DEVICES - Isoelectronic co-doping of semiconductor compounds and alloys with acceptors and deep donors is used to decrease bandgap, to increase concentration of the dopant constituents in the resulting alloys, and to increase carrier mobilities lifetimes. For example, Group III-V compounds and alloys, such as GaAs and GaP, are isoelectronically co-doped with, for example, B and Bi, to customize solar cells, and other semiconductor devices. Isoelectronically co-doped Group II-VI compounds and alloys are also included. | 2015-09-17 |
20150263210 | CIS/CGS/CIGS THIN-FILM MANUFACTURING METHOD AND SOLAR CELL MANUFACTURED BY USING THE SAME - Provided are a CIS/CGS/CIGS thin-film manufacturing method and a solar cell manufactured by using the same. The CIS/CGS/CIGS thin-film manufacturing method enables CIS, CGS, and CIGS thin-films through depositing an electrode layer on a substrate and depositing a light absorber layer by sputtering a single target of each of CIS including copper (Cu), indium (In), and selenium (Se) and CGS copper (Cu), gallium (Ga) and selenium (Se). In addition, a solar cell having excellent structural, optical and electrical properties is prepared by using the same. Thus, a thin-film can be prepared by depositing a CIG, CGS, or CIGS light absorber layer with a single sputtering process by using a single target of each of CIS (CuInSe2) and CGS (CuGaSe2), to thereby enable to manufacture thin-films of various characteristics according to a control of a composition ratio of In and Ga as well as simplification of the process, and to thus provide a very favorable effect on the economics and efficiency. | 2015-09-17 |
20150263211 | OPTICAL SENSOR, AND ELECTRONIC APPARATUS - A light receiving sensor ( | 2015-09-17 |
20150263212 | SUBSTRATE FOR SEMICONDUCTOR DEVICES, METHOD OF MANUFACTURING SUBSTRATE FOR SEMICONDUCTOR DEVICES, AND SOLID-STATE IMAGING DEVICE - According to one embodiment, a substrate for semiconductor devices includes a P-type semiconductor substrate, a P-type or N-type semiconductor layer, and a P-type or N-type epitaxial layer. The P-type or N-type semiconductor layer is provided at a surface layer of the semiconductor substrate and has a resistance value lower than a resistance value of the semiconductor substrate. The P-type or N-type epitaxial layer is provided on a surface of the semiconductor layer and has a resistance value higher than the resistance value of the semiconductor layer. | 2015-09-17 |
20150263213 | FEEDBACK FOR BUFFER LAYER DEPOSITION - Improved methods and apparatus for forming thin film layers of chalcogenide on a substrate web. According to the present teachings, a feedback control system may be employed to measure one or more properties of the web and/or the chalcogenide layer, and to adjust one or more parameters of the system or buffer layer deposition method in response to the measurement. | 2015-09-17 |
20150263214 | CMOS Image Sensors and Methods for Forming the Same - A method includes forming a first implantation mask comprising a first opening, implanting a first portion of a semiconductor substrate through the first opening to form a first doped region, forming a second implantation mask comprising a second opening, and implanting a second portion of the semiconductor substrate to form a second doped region. The first portion of the semiconductor substrate is encircled by the second portion of the semiconductor substrate. A surface layer of the semiconductor substrate is implanted to form a third doped region of an opposite conductivity type than the first and the second doped regions. The third doped region forms a diode with the first and the second doped regions. | 2015-09-17 |
20150263215 | WASHING ASSEMBLY AND METHOD FOR MONITORING THE PROCESS OF FABRICATING SOLAR CELLS - A method for monitoring the process of fabricating solar cells includes delivering at least one solar cell substructure to a wash chamber having a wash solution therein, such that the solar cell substructure is at least partially immersed within the wash solution. A residual material is removed from the solar cell substructure using the wash solution. A pH value of the wash solution is detected automatically while the solar cell substructure is at least partially immersed within the wash solution, via a control apparatus. The method also includes determining whether the detected pH value is at a predefined threshold pH level or within a predefined pH range for the wash solution, via the control apparatus. The pH value of the wash solution is modified automatically if the detected pH value is different from the predefined threshold pH level or different from the predefined pH range. | 2015-09-17 |
20150263216 | DEVICE AND METHOD FOR RESTORING SILICON-BASED SOLAR CELLS USING AN ULTRASOUND TRANSDUCER - The restoration device of least one silicon-based photovoltaic solar cell includes a support of the cell, a heat source configured to heat the photovoltaic solar cell, and unit for generating charge carriers in the cell. To better accelerate the restoration kinetics of the solar cell, the device includes an ultrasonic transducer designed to generate ultrasonic waves propagating in the photovoltaic solar cell. | 2015-09-17 |
20150263217 | METHOD FOR MANUFACTURING SOLAR CELL, AND SOLAR CELL - The present invention aims to provide a method of producing a solar cell which can produce a porous inorganic oxide layer that has a high porosity and contains less impurities even by low-temperature firing. The present invention also aims to provide a solar cell produced by the method of producing a solar cell. The present invention directs to a method of producing a solar cell. The method includes: applying an inorganic oxide paste that contains inorganic oxide fine particles, a binder resin, and an organic solvent to a surface of a base to form an inorganic oxide layer on the base, the base including a conductive layer as an outermost layer thereof, the surface being a conductive layer-side surface; firing the inorganic oxide layer; irradiating the inorganic oxide layer with active energy rays or subjecting the inorganic oxide layer to ozonolysis to form a porous inorganic oxide layer; and laminating a semiconductor on the porous inorganic oxide layer. | 2015-09-17 |
20150263218 | FRONT-SIDE EMITTING MID-INFRARED LIGHT EMITTING DIODE FABRICATION METHODS - Methods for fabricating mid-infrared light emitting diodes (LEDs) based upon antimonide-arsenide semiconductor heterostructures and configured into front-side emitting high-brightness LED die and other LED die formats. | 2015-09-17 |
20150263219 | LIGHT SOURCE AND OPTICAL COHERENCE TOMOGRAPHY APPARATUS INCLUDING THE LIGHT SOURCE - A light source includes an upper electrode layer, a lower electrode layer, and an active layer interposed therebetween. At least one of the upper and lower electrode layers is divided into a plurality of electrodes separated from each other in an in-plane direction of the active layer. The separated electrodes independently inject current into a plurality of different regions in the active layer. The light source emits light by injecting current from the upper and lower electrode layers into the active layer, guide the light in the in-plane direction, and output the light. The plurality of different regions in the active layer include a first region not including a light exit end and a second region including the light exit end, and the second region is configured to emit light of at least first-order level. The active layer has an asymmetric multiple quantum well structure. | 2015-09-17 |
20150263220 | SEMICONDUCTOR LIGHT-EMITTING ELEMENT AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a light-emitting element made of a GaN-based semiconductor with an MOCVD method includes the steps of: growing an n-type semiconductor layer; growing an active layer on the n-type semiconductor layer; and growing a p-type AlGaN-based semiconductor layer on the active layer while maintaining a concavo-convex surface with a depth of 1 to 5 nm. | 2015-09-17 |
20150263221 | Semiconductor and Template for Growing Semiconductors - A template for a semiconductor device is made by providing an AGN substrate, growing a first layer of Group III nitrides on the substrate, depositing a thin metal layer on the first layer, annealing the metal such as gold so that it agglomerates to form a pattern of islands on the first layer; transferring the pattern into the first layer by etching then removing excess metal; and then depositing a second Group III nitride layer on the first layer. The second layer, through lateral overgrowth, coalesces over the gaps in the island pattern leaving a smooth surface with low defect density. A Group III semiconductor device may then be grown on the template, which may then be removed. Chlorine gas may be used for etching the pattern in the first layer and the remaining gold removed with aqua regia. | 2015-09-17 |
20150263222 | TRANSFER CHAMBER METROLOGY FOR IMPROVED DEVICE YIELD - Apparatus and method for control of epitaxial growth parameters, for example during manufacture of light emitting diodes (LEDs). Embodiments include PL measurement of a group III-V film following growth while a substrate at an elevated temperature is in a transfer chamber of a multi-chamber cluster tool. In other embodiments, a film thickness measurement, a contactless resistivity measurement, and a particle and/or roughness measure is performed while the substrate is disposed in the transfer chamber. One or more of the measurements performed in the transfer chamber are temperature corrected to room temperature by estimating the elevated temperature based on emission from a GaN base layer disposed below the group III-V film. In other embodiments, temperature correction is based on an absorbance band edge of the GaN base layer determined from collected white light reflectance spectra. Temperature corrected metrology is then used to control growth processes. | 2015-09-17 |
20150263223 | SEMICONDUCTOR LIGHT EMITTING ELEMENT - According to one embodiment, a semiconductor light emitting element includes a first electrode, a first semiconductor layer, a light emitting layer, a second semiconductor layer, a first insulating portion, and a first conductive layer. The first electrode includes first and second regions. The first semiconductor layer is separated from the first region, and includes first and second portions. The light emitting layer is provided between the second portion and the first region. The second semiconductor layer is provided between the light emitting layer and the first region. The second electrode is provided between the first region and the second semiconductor layer to contact the second semiconductor layer. The first insulating portion is provided between the first region and the second electrode. The first conductive layer is provided between the first portion and the first region, and includes a contact portion contacting the first portion. | 2015-09-17 |
20150263224 | LIGHT-EMITTING DEVICE WITH HEAVILY DOPED ACTIVE-REGION AND METHOD FOR MANUFACTURING THE SAME - A light emitting device is provided, which includes an n-type layer, a p-type layer, and an active region sandwiched between the n-type layer and the p-type layer. The active-region includes one or more quantum wells each sandwiched by quantum barriers, at least one of the quantum wells has a polarization induced electric field equal to or greater than 10 | 2015-09-17 |
20150263225 | DEVICES HAVING NITRIDE QUANTUM DOT AND METHODS OF MANUFACTURING THE SAME - Devices having nitride quantum dots and methods of manufacturing the same are provided. The device includes a nitride group material substrate, a plurality of nanorods that are formed on the nitride group material layer and are separated from each other, and a nitride quantum dot on each of the nanorods. A pyramid-shaped layer may be further formed between each of the nanorods and the nitride quantum dot. The nanorods and the nitride quantum dot are covered by an upper contact layer. A plurality of nitride quantum dots may be formed on each of the nanorods and the respective nitride quantum dots may have different sizes. | 2015-09-17 |
20150263226 | SEMICONDUCTOR STRUCTURE - A nitride semiconductor structure and a semiconductor light emitting device including the same are revealed. The nitride semiconductor structure mainly includes a stress control layer disposed between a light emitting layer and a p-type carrier blocking layer. The p-type carrier blocking layer is made from Al | 2015-09-17 |
20150263227 | SEMICONDUCTOR LIGHT-EMITTING DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor light-emitting device including a substrate, a first-type doped semiconductor structure, a light-emitting layer, and a second-type doped semiconductor layer is provided. The first-type doped semiconductor structure is located on the substrate and includes a base and multi-section rod structures extended upward from the base. Each multi-section rod structure includes rods and at least one connecting portion. The connecting portion connects adjacent rods along a first direction, wherein the first direction is perpendicular to the base and points to the connecting portion from the base. Cross-section areas of different rods on a reference plane parallel to the substrate are different, and cross-section areas of the connecting portion on the reference plane decrease along the first direction. The light-emitting layer is located on sidewalls of the rods. The second-type doped semiconductor layer is located on the light-emitting layer. A manufacturing method of the semiconductor light-emitting device is also provided. | 2015-09-17 |
20150263228 | NITRIDE SEMICONDUCTOR LIGHT-EMITTING DEVICE HAVING EXCELLENT BRIGHTNESS AND ESD PROTECTION PROPERTIES - Disclosed is a nitride semiconductor light-emitting device having excellent brightness and ESD protection properties. The nitride semiconductor light-emitting device according to the present invention includes an electron blocking layer that is disposed between a p-type nitride semiconductor layer and an active layer, wherein said electron blocking layer includes AlInGaN, and the concentration of indium increases in the electron blocking layer as said layer progressively moves away from the active layer. | 2015-09-17 |
20150263229 | SEMICONDUCTOR LIGHT-EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor light-emitting device includes a first-conductivity-type first semiconductor layer, a second-conductivity-type second semiconductor layer, a light-emitting layer provided between the first semiconductor layer and the second semiconductor layer, a nitride semiconductor layer that is provided on a side of the first semiconductor layer opposite to the light-emitting layer, has a resistance higher than a resistance of the first semiconductor layer, and includes recess portions communicating with the first semiconductor layer, and a conductive layer that comes into contact with the first semiconductor layer in the recess portions. | 2015-09-17 |
20150263230 | SEMICONDUCTOR LIGHT EMITTING DEVICE - According to one embodiment, a semiconductor light emitting device includes a stacked structure body, a first electrode, a second electrode, and a dielectric body part. The stacked structure body includes a first semiconductor layer, having a first portion and a second portion juxtaposed with the first portion, a light emitting layer provided on the second portion, a second semiconductor layer provided on the light emitting layer. The first electrode includes a contact part provided on the first portion and contacting the first layer. The second electrode includes a first part provided on the second semiconductor layer and contacting the second layer, and a second part electrically connected with the first part and including a portion overlapping with the contact part when viewed from the first layer toward the second layer. The dielectric body part is provided between the contact part and the second part. | 2015-09-17 |
20150263231 | OPTICAL SEMICONDUCTOR DEVICE, DRIVING METHOD THEREOF, AND OPTICAL COHERENCE TOMOGRAPHY APPARATUS HAVING THE OPTICAL SEMICONDUCTOR DEVICE - The present invention provides an optical semiconductor device which can make a wavelength band of emitted light wider than that of a conventional optical semiconductor device. The optical semiconductor device includes: an active layer including a multiple quantum well structure; and at least one electrode pair for injecting an electric current into the active layer, wherein the multiple quantum well structure has a first quantum well and a second quantum well which is different from the first quantum well, and the first quantum well and the second quantum well are mutually different in at least two out of a composition of a well layer, a width of the well layer, and a composition of a barrier layer. | 2015-09-17 |
20150263232 | OPTICAL SEMICONDUCTOR ELEMENT - An optical semiconductor element includes a first nitride semiconductor layer of a first conductivity type, a second nitride semiconductor layer of a second conductivity type, and an active layer provided between the first nitride semiconductor layer and the second nitride semiconductor layer. In the optical semiconductor element, a feature is provided in the active layer, and the second nitride semiconductor layer is provided within the feature of the active layer. | 2015-09-17 |
20150263233 | LED ELEMENT, AND PRODUCTION METHOD THEREFOR - Provided is an LED element which achieves high light extraction efficiency even at low operating voltages and which can be produced using a simple process. The LED element has a first semiconductor layer made of a p-type nitride semiconductor, a light-emitting layer made of a nitride semiconductor formed on the upper layer of the first semiconductor layer, a second semiconductor layer made of an n-type nitride semiconductor formed on the upper layer of the light-emitting layer, and a transparent electrode formed on the whole surface of the second semiconductor layer. The second semiconductor layer in at least a region that is in contact with the transparent electrode is made of Al | 2015-09-17 |
20150263234 | III NITRIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a high quality III nitride semiconductor device in which, not only X-shaped cracks extending from the vicinity of the corners of semiconductor structures to the center portion thereof, but also crack spots at the center portion can be prevented from being formed and can provide a method of efficiently manufacturing the III nitride semiconductor device. The III nitride semiconductor device of the present invention includes a support and two semiconductor structures having a nearly quadrangular transverse cross-sectional shape that are provided on the support. The two semiconductor structures are situated such that one side surface of one of the two semiconductor structures is placed to face one side surface of the other of them. The support covers the other three side surfaces and of the four sides of the semiconductor structures. | 2015-09-17 |
20150263235 | FLEXIBLE DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME - Provided is a flexible display apparatus having an improved light extracting efficiency and a method of manufacturing the flexible display apparatus. The flexible display apparatus includes a flexible substrate having a rippled surface, a pixel electrode on the flexible substrate and having a rippled surface, an intermediate layer on the pixel electrode and including a light emission layer, and an opposing electrode facing the pixel electrode. A method of manufacturing the flexible display apparatus includes applying a tensile force to a flexible substrate, forming a pixel electrode on the flexible substrate, removing the tensile force applied to the flexible substrate to form a rippled surface in the pixel electrode, forming an intermediate layer including an light emission layer on the pixel electrode, and forming an opposing electrode facing the pixel electrode. | 2015-09-17 |
20150263236 | SEMICONDUCTOR LIGHT EMITTING ELEMENT - A light emitting element includes a first semiconductor layer of a first conductive type, a second semiconductor layer of a second conductive type, a light emitting layer. The light emitting layer is between the first semiconductor layer and the second semiconductor layer. A first electrode layer is on a first side of the second semiconductor layer. A second electrode layer is on the first side of the first semiconductor layer. Am insulation layer is between the first electrode layer and the second electrode layer. A first metal layer is between a substrate and the insulation layer and between the substrate and the second electrode layer. The second electrode layer includes a first portion contacting the first semiconductor layer and a second portion which spaced from the first semiconductor layer. | 2015-09-17 |
20150263237 | NANOWIRE LED STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A method for ablating a first area of a light emitting diode (LED) device which includes an array of nanowires on a support with a laser is provided. The laser ablation exposes a conductive layer of the support that is electrically connected to a first conductivity type semiconductor nanowire core in the nanowires, to form a first electrode for the LED device. In embodiments, the nanowires are aligned at least 20 degrees from the plane of the support. A light emitting diode (LED) structure includes a first electrode for contacting a first conductivity type nanowire core, and a second electrode for contacting a second conductivity type shell enclosing the nanowire core, where the first electrode and/or at least a portion of the second electrode are flat. | 2015-09-17 |
20150263238 | CAP, SEMICONDUCTOR DEVICE INCLUDING THE CAP, AND MANUFACTURING METHOD THEREFOR - A cap for installing a semiconductor device that can send or receive a light having a predetermined wavelength, the cap including a recess for installing the semiconductor device, the recess being defined by a through-hole penetrating an upper surface of a silicon substrate and a lower surface of the silicon substrate, the through-hole having an upper end part of the through-hole on a side of the upper surface of the silicon substrate and a lower end part of the through-hole on a side of the lower surface of the silicon substrate, and a coating film formed to cover the upper surface of the silicon substrate and the upper end part of the through-hole, wherein the coating film that covers the upper end part of the through-hole is a window part that transmits the light having a predetermined wavelength. | 2015-09-17 |