38th week of 2015 patent applcation highlights part 54 |
Patent application number | Title | Published |
20150262639 | RESISTANCE CHANGE MEMORY - According to one embodiment, a resistance change memory comprises a memory cell array, a write and read circuit, a temperature sensor, and a memory controller. The memory cell array comprises memory cells including magnetic tunnel junction (MTJ) elements. The write and read circuit performs a write operation and a read operation for the memory cells. The temperature sensor outputs temperature information corresponding to a temperature of the memory cell array. The memory controller controls the write operation and the read operation by the write and read circuit in accordance with the temperature information. | 2015-09-17 |
20150262640 | MEMORY SYSTEM - According to one embodiment, a memory system includes a first memory cell array and a second memory cell array; and a control circuit controls data of the first and second memory cell arrays. The control circuit sets, when receiving an initialization instruction, all of the plurality of bits of the first memory cell array at a first value, and sets all of the plurality of bits of the second memory cell array at a second value which is a complementary value of the first value. | 2015-09-17 |
20150262641 | METHOD AND CIRCUIT ENABLING FERROELECTRIC MEMORY TO BE FIXED TO A STABLE STATE - A system includes a ferroelectric random access memory (FRAM) array having one or more memory elements. A cycle controller cycles data to be fixed in a subset of the one or more memory elements by reading or writing the data a predetermined number of times to fix the data to a non-volatile stable state. | 2015-09-17 |
20150262642 | SEMICONDUCTOR DEVICE - To provide a semiconductor device which includes a novel refresh circuit in a memory including an oxide semiconductor film. As circuits which operate in a refresh operation of the memory including the oxide semiconductor film, a sense amplifier circuit, a latch circuit, a first switch, and a second switch are provided. In the refresh operation, a potential which reflects a potential stored in the memory is input to the sense amplifier circuit, an output of the sense amplifier circuit is input to the latch circuit, and an output of the latch circuit is written to the memory again through the first switch and a first transistor including an oxide semiconductor in a channel. | 2015-09-17 |
20150262643 | VERTICAL TRANSISTOR, MEMORY CELL, DEVICE, SYSTEM AND METHOD OF FORMING SAME - A memory device, system and fabrication method relating to a vertical memory cell including a semiconducting pillar extending outwardly from an integrally connected semiconductor substrate are disclosed. A first source/drain region is formed in the semiconductor substrate and a body region and a second source/drain region are formed within the semiconductor pillar. A first gate is coupled to a first side of the semiconductor pillar for coupling the first and second source/drain regions together when activated. The vertical memory cell also includes a storage capacitor formed on an extended end of the semiconducting pillar and electrically coupled to the second source/drain region. | 2015-09-17 |
20150262644 | METHOD FOR DRIVING SEMICONDUCTOR MEMORY DEVICE - A method for driving a semiconductor memory device including a transistor with low leakage current between a source and a drain in an off state and capable of storing data for a long time is provided. In a matrix including a plurality of memory cells in each of which a drain of a write transistor, a gate of an element transistor, and one electrode of a capacitor are connected, a gate of the write transistor is connected to a write word line, and the other electrode of the capacitor is connected to a read word line. The amount of charge stored in the capacitor is checked by changing the potential of the read word line, and if the amount of charge has decreased beyond a predetermined amount, the memory cell is refreshed. | 2015-09-17 |
20150262645 | Semiconductor Device Including Stacked Semiconductor Chips - A semiconductor device comprising a plurality of semiconductor chips and a plurality of through-line groups is disclosed. Each of the through-line groups consists of a unique number of through-lines. The numbers associated with the through-line groups are mutually coprime to each other. When one of the through-lines is selected for the each through-line group, one of the semiconductor chip is designated by a combination of the selected through-lines of the plurality of the through-line groups. | 2015-09-17 |
20150262646 | SEMICONDUCTOR DEVICE - A semiconductor device may include a write control block configured to generate a plurality of write enable signals for controlling a write operation, and a write delay block configured to apply delay times to a plurality of write data which are transmitted through a write global input/output line. The semiconductor device may also include a plurality of banks configured to operate in response to the plurality of write enable signals and receive the plurality of write data, wherein the plurality of write data have different delay times according to physical positions of the plurality of banks. | 2015-09-17 |
20150262647 | Semiconductor Device Latching Data Signal In Response To Strobe Signal And Information Processing System Including The Same - Disclosed herein is a device including a timing control circuit that receives a strobe signal supplied from outside to generate an internal strobe signal that is used as a timing signal to latch a data signal. An operation state of the timing control circuit is changed according to temperature change so as to keep an output timing of the internal strobe signal with respect to an input timing of the strobe signal. | 2015-09-17 |
20150262648 | SEMICONDUCTOR DEVICE, ADJUSTMENT METHOD THEREOF AND DATA PROCESSING SYSTEM - A method includes resetting an output timing adjustment circuit in each of a plurality of DRAM devices to a default output timing data value, measuring a default delay from read command to read data for each of the plurality of DRAM devices, identifying a slowest DRAM device having a maximum default delay from read command to read data among the plurality of DRAM devices, writing an output timing data value to the output timing adjustment circuit in each of the plurality of DRAM devices to set the delay from read command to read data for each respective DRAM device to an amount substantially equal to the maximum default delay, and reading data from any one of the plurality of DRAM devices with a delay from read command to read data substantially equal to the maximum default delay. | 2015-09-17 |
20150262649 | MEMORY DEVICES, SYSTEMS AND METHODS EMPLOYING COMMAND/ADDRESS CALIBRATION - During a command/address calibration mode, a memory controller may transmit multiple cycles of test patterns as signals to a memory device. Each cycle of test pattern signals may be transmitted at an adjusted relative phase with respect to a clock also transmitted to the memory device. The memory device may input the test pattern signals at a timing determined by the clock, such as rising and/or falling edges of the clock. The test pattern as input by the memory device may be sent to the memory controller to determine if the test pattern was successfully transmitted to the memory device during the cycle. Multiple cycles of test pattern transmissions are evaluated to determine a relative phase of command/address signals with respect to the clock for transmission during operation of the system. | 2015-09-17 |
20150262650 | SEMICONDUCTOR MEMORY DEVICE HAVING SENSE AMPLIFIER - An apparatus includes a memory cell, a bit line coupled to the memory cell, and a sense amplifier configured to amplify a data signal on the bit line read out from the memory cell. The sense amplifier is operated in a first mode with a first power source voltage difference and operated in a second mode with a second power source voltage difference smaller than the first power source voltage difference. | 2015-09-17 |
20150262651 | GAPLESS PATTERN DETECTION CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - A semiconductor device that includes: a detection circuit suitable for detecting a gapless pattern section of a detection target signal; and an internal circuit suitable for performing a normal operation during a normal section and additionally performing the normal operation during a compensating section corresponding to the gapless pattern section in response to a detection result signal outputted from the detection circuit. | 2015-09-17 |
20150262652 | ACCESS COUNT DEVICE, MEMORY SYSTEM, AND ACCESS COUNT METHOD - An access count device and the like in a semiconductor memory are disclosed, which count accesses to row addresses in the semiconductor memory with a smaller circuit scale. An access count device includes a row-address storage unit configured to store up to a specific number n (n is an integer equal to or more than 1) of row addresses specified in accesses to memory cells, a counter configured to count an access frequency to each row address stored in the row-address storage unit, and a reset controller configured to notify the row-address storage unit to replace one of the n row addresses with a new row address or discard one of the n row addresses, and also configured to notify the counter to reset an access frequency to the row address replaced or discarded. | 2015-09-17 |
20150262653 | METHODS AND CIRCUITS FOR GENERATING PHYSICALLY UNCLONABLE FUNCTION - Various embodiments include solutions for generating a physically unclonable function. In some cases, a method includes an electronic circuit including: a static random access memory (SRAM) device having at least one memory cell with at least one transistor device therein, SRAM bias temperature instability aging circuitry coupled with the SRAM device and configured to apply aging conditions to the at least one memory cell to degrade the at least one transistor device within the at least one memory cell, and at least one computing device coupled with the SRAM device and configured to: skew a storage cell value in the at least one transistor device, measure a skewed value of the storage cell after the skewing, and create a physically unclonable function from the skewed value of the storage cell. | 2015-09-17 |
20150262654 | DIGITAL FILTERS WITH MEMORY - A memory device that, in certain embodiments, includes a memory element coupled to a bit-line and a quantizing circuit coupled to the memory element via the bit-line. In some embodiments, the quantizing circuit includes an analog-to-digital converter having an input and output and a digital filter that includes memory. The input of the analog-to-digital converter may be coupled to the bit-line, and the output of the analog-to-digital converter may be coupled to the digital filter. | 2015-09-17 |
20150262655 | NEGATIVE BITLINE BOOST SCHEME FOR SRAM WRITE-ASSIST - A device includes a transistor switch coupled between a bit line voltage node and a ground node and a boost signal circuit coupled to a gate node of the transistor switch, where the boost signal circuit providing a boost signal responsive to a write enable signal. The device also includes a first delay element and a first capacitor in series with the first delay element. The first capacitor has a first end coupled to the bit line voltage node and a second end coupled to the gate node through the first delay element. | 2015-09-17 |
20150262656 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME - A semiconductor memory device according to an embodiment comprises: a nonvolatile memory cell capable of multi-level storage; and a control circuit that performs write control on the memory cell. The control circuit executes: a first write operation to obtain a certain intermediate voltage distribution; a second write operation to obtain a final voltage distribution; and a change operation that changes a value of the first verify voltage according to the number of times of writes and the number of times of erases on the memory cell. | 2015-09-17 |
20150262657 | TWO-PART PROGRAMMING METHODS - Programming a memory in two parts to reduce cell disturb is disclosed. In at least one embodiment, data is programmed in two or more sequences of programming pulses with data requiring higher programming voltages programmed first. During each programming sequence, the data which is not being currently selected for programming is inhibited. Overlapping levels and/or voltage ranges can be used. | 2015-09-17 |
20150262658 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME - A semiconductor memory device according to an embodiment comprises: a plurality of memory cells; a word line; a plurality of first bit lines and a plurality of second bit lines; and a control circuit. The control circuit is capable of executing: a determining operation that determines whether the memory cell which is to be a write-target includes an erase-target cell whose threshold voltage is to be the erase state, or not; and an inverting operation that inverts selection or unselection of the bit line connected to one of the two memory cells adjacent to the erase-target cell, in the first write operation and the second write operation. | 2015-09-17 |
20150262659 | SETTING OPERATING PARAMETERS FOR MEMORY CELLS BASED ON WORDLINE ADDRESS AND CYCLE INFORMATION - Disclosed is an apparatus and method for adjusting operating parameters in a storage device. A controller in a solid state drive monitors current operating conditions of the drive's flash memory, and when the flash memory has been subjected to a predetermined number of program/erase cycles one or more stored bias values are retrieved from a storage location based on the wordline(s) associated with a current memory operation. Parameters of the memory operation are then adjusted based on the retrieved bias values, and the memory operation is performed using the adjusted parameters. | 2015-09-17 |
20150262660 | ASYMMETRIC LOG-LIKELIHOOD RATIO FOR FLASH CHANNEL - Disclosed is a system and method for reading flash memory cells with dynamically adjusted probability values (e.g., log-likelihood ratios). In connection with reading bit values from flash memory cells, one or more predetermined first probability values are adjusted relative to one or more predetermined second probability values. The one or more predetermined first probability values are associated with reading one or more memory cells programmed to a first binary value, and the one or more predetermined second probability values are associated with reading one or more memory cells programmed to a second binary value. The plurality of bit values read from the plurality of non-volatile memory cells and the one or more adjusted first probability values are provided to a decoder for use in decoding the plurality of bit values. | 2015-09-17 |
20150262661 | MITIGATING READ DISTURB IN A CROSS-POINT MEMORY - The present disclosure relates to mitigating read disturb in a cross-point memory. An apparatus may include a memory controller configured to select a target memory cell for a memory access operation. The memory controller includes a sense module configured to determine whether a snap back event occurs during a sensing interval; and a write back module configured to write back a logic one to the memory cell if a snap back event is detected. | 2015-09-17 |
20150262662 | NONVOLATILE LOGIC AND SECURITY CIRCUITS - In some examples, a nonvolatile storage element may be configured to store a state or value during a low power or powered down period of a circuit. For example, the nonvolatile storage element may include a bridge of resistive elements that have a resistive state that may be configured by applying voltages to multiple drive paths. A sense amplifier may be connected to the bridge in order to resolve a voltage differential associated with the bridge to ether power or ground and, thereby determine the state associated with on the nonvolatile storage element. | 2015-09-17 |
20150262663 | Methods of Manufacturing Embedded Bipolar Switching Resistive Memory - Non linear current response circuits can be used in embedded resistive memory cell for reducing power consumption, together with improving reliability of the memory array. The non linear current response circuits can include two back to back leaky PIN diodes, two parallel anti-directional PIN diodes, two back to back Zener-type metal oxide diodes, or ovonic switching elements, along with current limiting resistor for standby power reduction at the low voltage region. Also, the proposed embedded ReRAM implementation methods based upon 1T2D1R scheme can be integrated into the advanced FEOL process technologies including vertical pillar transistor and/or 3D fin-shaped field effect transistor (FinFET) for realizing a highly compact cell density. | 2015-09-17 |
20150262664 | PRESERVATION CIRCUIT AND METHODS TO MAINTAIN VALUES REPRESENTING DATA IN ONE OR MORE LAYERS OF MEMORY - Circuitry and methods for restoring data in memory are disclosed. The memory may include at least one layer of a non-volatile two-terminal cross-point array that includes a plurality of two-terminal memory elements that store data as a plurality of conductivity profiles and retain stored data in the absence of power. Over a period of time, logic values indicative of the stored data may drift such that if the logic values are not restored, the stored data may become corrupted. At least a portion of each memory may have data rewritten or restored by circuitry electrically coupled with the memory. Other circuitry may be used to determine a schedule for performing restore operations to the memory and the restore operations may be triggered by an internal or an external signal or event. The circuitry may be positioned in a logic layer and the memory may be fabricated over the logic layer. | 2015-09-17 |
20150262665 | MEMORY DEVICE - According to one embodiment, a memory controller sends a periodic control signal from a first terminal on a non-volatile memory side to the non-volatile memory, and the control signal includes a data strobe signal, a write enable signal, and a read enable signal. | 2015-09-17 |
20150262666 | Non-Volatile Semiconductor Storage Device - Provided is a non-volatile semiconductor memory device capable of reliably preventing a malfunction of a read transistor without increasing the number of bit lines. In a non-volatile semi conductor memory device ( | 2015-09-17 |
20150262667 | LOW POWER HIT BITLINE DRIVER FOR CONTENT-ADDRESSABLE MEMORY - An apparatus includes a hit bitline driver circuit and an equalization control circuit. The hit bitline driver circuit may be configured to drive a pair of hit bitlines responsive to a search bit. The equalization control circuit may be configured to transfer charge from one hit bitline of the pair to the other hit bitline of the pair in response to the search bit changing state. | 2015-09-17 |
20150262668 | TCAM PROVIDING EFFICIENT MOVE CONTENTS OPERATION - An embodiment of the invention includes a Ternary Content Addressable Memory (TCAM) that includes a group of TCAM block. Each TCAM block stores a number of match entries. Each TCAM block is ranked in priority order. The TCAM also includes a group of TCAM headpointers. There is a TCAM headpointer coupled to each TCAM block. The TCAM headpointer indicates the highest priority match in the group of match entries in a TCAM block. The match entries within a TCAM block are prioritized in circular priority order starting from the highest priority match. | 2015-09-17 |
20150262669 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes first and second memory cell transistors, first and second word lines electrically connected to the first and second memory cell transistors, respectively, first and second transfer transistors. The first and second transistors are electrically connected to the first and second word lines, respectively. The sizes of the first transistor and the second transistor are different. | 2015-09-17 |
20150262670 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes a plurality of memory cells electrically connected in series between first and second select transistors and stacked above a semiconductor substrate, a voltage generation circuit, and a controller that controls the voltage generation circuit to apply a write voltage to at least one of the memory cells before a write operation is performed on the first select transistor and, during the write operation on the first select transistor, apply a first voltage to gates of the memory cells, a second voltage that is higher than the first voltage to a gate of the second select transistor, and a third voltage that is higher than the second voltage to a gate of the first select transistor. | 2015-09-17 |
20150262671 | NON-VOLATILE MEMORY DEVICE - A nonvolatile memory device according to an embodiment includes: a semiconductor substrate; a memory cell array unit provided on an upper side of the semiconductor substrate; an integrated circuit unit provided between the memory cell array unit and the semiconductor substrate; and a peripheral circuit unit provided on the semiconductor substrate. The integrated circuit unit includes: a first contact electrode electrically connected to one of plurality of first interconnection layers; a second contact electrode connected to the peripheral circuit unit; and a first switching element connected between the first contact electrode and the second contact electrode, and conduction between the first contact electrode and the second contact electrode being controlled by a control circuit unit provided in the peripheral circuit unit. | 2015-09-17 |
20150262672 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes a first memory string including memory cell transistors and a first select transistor that are connected in series, a second memory string including memory cell transistors and a second select transistor that are connected in series, a bit line that is electrically connected to a first end of the first memory string and a first end of the second memory string, a first transistor having a gate that is connected to a second end of the first memory string, a source line that is electrically connected to a first end of the first transistor, and a second transistor having a gate that is connected to a second end of the second memory string, a first end that is electrically connected to a second end of the first transistor, and a second end that is electrically connected to the bit line. | 2015-09-17 |
20150262673 | APPARATUSES AND METHODS FOR COUPLING LOAD CURRENT TO A COMMON SOURCE - Apparatuses and methods are disclosed, including an apparatus with a string of charge storage devices coupled to a common source, a first switch coupled between the string of charge storage devices and a load current source, and a second switch coupled between the load current source and the common source. Additional apparatuses and methods are described. | 2015-09-17 |
20150262674 | SEMICONDUCTOR MEMORY DEVICE AND MEMORY CONTROLLER - A semiconductor memory device includes memory cells, word lines, and a row decoder. When program verification is performed on a memory cell that has been programmed, the row decoder transfers a first voltage to word lines that are electrically connected to gates of first memory cells. Also, when data is read, the row decoder selects a word line electrically connected to gates of selected memory cells, transfers the first voltage to non-selected word lines that are electrically connected to the first memory cells, and transfers a second voltage, which is higher than the first voltage, to non-selected word lines that are electrically connected to second memory cells. | 2015-09-17 |
20150262675 | Incremental step pulse programming (ISPP) scheme capable of determining a next starting pulse based on a current program-verify pulse for improving programming speed - A method for programming a memory including a plurality of memory cells is provided. The method comprises selecting a current cell and executing a pre-program verify operation at a first program verify level. The method comprises executing a program and program verify operation for the current cell, including applying a sequence of program pulses and performing program verify steps. The sequence includes a starting pulse having a starting magnitude. The program verify steps use a second program verify level. The method also comprises determining the starting magnitude for a next cell as a function of a magnitude of the program pulse in an instance of the program verify step in which the current cell passes verify at the second program verify level. | 2015-09-17 |
20150262676 | METHOD AND SYSTEM FOR PROGRAMMING MULTI-LEVEL CELL MEMORY - A method and a system for programming a multi-level cell (MLC) memory are provided. A first count is 1 initially. The method comprises the following steps. A first energy is set. The first energy is applied to alter a resistance of a cell of the MLC memory. The first count is increased by 1 after performing the step of applying the first energy. In the step of setting the first energy, the first energy is | 2015-09-17 |
20150262677 | DATA STORING METHOD, MEMORY CONTROL CIRCUIT UNIT AND MEMORY STORAGE APPARATUS - A data writing method, and a memory control circuit unit and a memory storage apparatus using the method are provided. The method including: programming data to several memory cells on a first word line of the rewritable non-volatile memory module of the memory storage apparatus, and a first predetermined reading voltage is initially configured for the first word line. The data storing method further includes: adjusting the first predetermined reading voltage to obtain a first available reading voltage for the first word line, and applying the first available reading voltage to the first word line to read first page data. The storing method further includes: if the difference value between the first available reading voltage and the first predetermined reading voltage is larger than a predetermined threshold value, performing a protection operation for the first page data. | 2015-09-17 |
20150262678 | SEMICONDUCTOR DEVICE AND PROGRAMMING METHOD THEREOF - A semiconductor device includes a plurality of electrically coupled memory cells in a generally vertical configuration extending in a generally perpendicular direction from a semiconductor substrate, a peripheral circuit configured to program the memory cells, and a control circuit configured to program a memory cell selected from the plurality of memory cells to trap charge in the selected memory cell, and to issue at least one command to the peripheral circuit to manage a dispersion of at least a portion of the trapped charge between memory cells adjacent to the selected memory cell. | 2015-09-17 |
20150262679 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME - A semiconductor memory device according to an embodiment comprises: a nonvolatile memory cell and a control circuit. The control circuit executes: a first write operation that performs a write on the memory cell using a first write voltage; a first verify operation that determines whether a threshold voltage of the memory cell exceeds a first threshold value due to the first write operation, or not; a second verify operation that re-determines on the memory cell that has passed the first verify operation whether the threshold voltage exceeds the first threshold value, or not; and a second write operation that performs a write on the memory cell that has not passed the second verify operation, using a second write voltage. | 2015-09-17 |
20150262680 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD THEREOF - A nonvolatile semiconductor memory device includes: a memory cell array including a memory string having plural series-connected memory transistors; plural word lines disposed to be connected to the memory transistor in the memory string; plural bit lines electrically connected to an end of the memory string; and a control circuit. When performing a write operation on the memory cell array, the control circuit applies a first voltage to a selected word line selected from the plural word lines, applies a second voltage smaller than the first voltage to an unselected word line rendered unselected from the word lines. Before lowering a voltage applied to the unselected word line from the second voltage to a third voltage smaller than the second voltage, it lowers a voltage applied to the selected word line from the first voltage to a fourth voltage smaller than the first voltage. | 2015-09-17 |
20150262681 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A non-volatile semiconductor memory device includes a memory cell array that includes a plurality of memory cells stacked on a semiconductor substrate, a voltage generating circuit that generates voltages for a memory cell selected for writing and for non-selected memory cells, and a control unit that controls the voltage generating circuit to supply the voltages to the memory cells. Normally, a write voltage is supplied to the selected memory cell, a first voltage lower than the write voltage to the memory cell adjacent to the selected memory cell, and a second voltage lower than the first voltage to the memory cell separated from the selected memory cell by one memory cell. However, if there are not enough memory cells between the selected memory cell and the semiconductor substrate, the second voltage is not supplied. | 2015-09-17 |
20150262682 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes first to fourth memory cells that are stacked above a semiconductor substrate, first to fourth word lines that are connected to gates of the first to fourth memory cells, respectively, and a row decoder that applies voltages to the first to fourth word lines. The row decoder applies a first programming voltage to the first word line during a write operation performed on the first memory cell, applies the first programming voltage to the second word line during a write operation performed on the second memory cell, applies a second programming voltage to the third word line during a write operation performed on the third memory cell, and applies the second programming voltage to the fourth word line during a write operation performed on the fourth memory cell. The second programming voltage is higher than the first programming voltage. | 2015-09-17 |
20150262683 | MEMORY DEVICE AND METHOD PROGRAMMING/READING MEMORY DEVICE - A method of programming a memory device includes generating a row selection signal according to a command type of a command received from a memory controller, loading data to page buffers corresponding to bit lines assigned by the column selection signal, and programming memory cells connected to a word line assigned by the row selection signal based on the data loaded to the page buffers. The column selection signal being generated to selectively jump a portion of the page buffers corresponding to the bit lines according to the command type. | 2015-09-17 |
20150262684 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - The voltage switching circuit comprises: an nMOS transistor having a gate connected to a first terminal that outputs an output voltage, a drain connected to a power-supply terminal, and a source connected to a second terminal; a first pMOS transistor having a source connected to the second terminal, a drain connected to the first terminal, and a gate provided with a first or second voltage, a source and a well thereof being short-circuited; and a switching circuit connected between a third terminal that supplies the input voltage and the first terminal and configured to turn on when the output voltage is supplied to the first terminal. A gate electrode of the first pMOS transistor is configured by semiconductor including p-type impurity. A concentration of p-type impurity in the gate electrode of the memory cell is different from that of the first pMOS transistor. | 2015-09-17 |
20150262685 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line. | 2015-09-17 |
20150262686 | ERASE SYSTEM AND METHOD OF NONVOLATILE MEMORY DEVICE - An erase system and method of a nonvolatile memory device includes supplying an erase voltage to a plurality of memory cells of a nonvolatile memory, performing a read operation with a read voltage to word lines of the plurality of memory cells, and performing an erase verification operation with an erase verification voltage to at least one of the word lines of the plurality of memory cells, the erase verification voltage lower than the read voltage. | 2015-09-17 |
20150262687 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory cell array, a voltage generation circuit that generates a voltage applied to the memory cell array, the voltage generation circuit including a plurality of boosting circuits connected in series between an input terminal and an output terminal, and a switching circuit configured to short-circuit one or more of the boosting circuits to the input terminal, and a control circuit that controls a conduction state of the switching circuit to vary the number of boosting circuits that are driven to generate the voltage applied to the memory cell array. | 2015-09-17 |
20150262688 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device according to one embodiment includes a control circuit. The control circuit is configured to apply, when reading data of a first selected memory cell provided in a ROM area, a first read voltage to a first selected word line, and apply a first read pass voltage lower than a second read pass voltage to a first non-selected word line, thus allowing for the ROM area reading operation of reading a threshold voltage set in the first selected memory cell. The control circuit is configured to apply, when reading data of a second selected memory cell provided in a normal storage area, a second read voltage to a second selected word line, and apply the second read pass voltage to a second non-selected word line, thus allowing for a normal storage area reading operation of reading a threshold voltage set in the second selected memory cell. | 2015-09-17 |
20150262689 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes a plurality of memory cells, a plurality of bit lines, each coupled to one of the memory cells, and a control circuit that performs a control for reading data from the first, second, and third memory cells such that when one of the first, second, and third memory cells is selected for reading, the other memory cells are not selected for reading. | 2015-09-17 |
20150262690 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory cell, a bit line that is electrically connected to the memory cell, a sense module that includes a first transistor, a sense node electrically connected to the bit line through the first transistor, a second transistor electrically connected between a power source voltage and the sense node, a voltage generating circuit capable of generating a voltage that is equal to the first voltage minus a threshold voltage of the second transistor, and a control circuit configured to turn on the first transistor for a period of time prior to performing a sense operation on the bit line through the sense module. | 2015-09-17 |
20150262691 | SEMICONDUCTOR STORAGE DEVICE - According to one embodiment, a nonvolatile semiconductor storage device includes a memory cell, a voltage generator configured to output a first voltage and a second voltage, and a controller. The controller executes a write operation, which includes a first read operation, a program operation, and a verify operation. The controller executes the first read operation before the program operation and the verify operation. The controller executes the first read operation by applying the first voltage to a gate of the memory cell. The controller executes an erase verify operation by applying the second voltage to the gate of the memory cell. The first voltage is higher than the second voltage. | 2015-09-17 |
20150262692 | READ MARGIN MEASUREMENT IN A READ-ONLY MEMORY - Read margin measurement circuitry for measuring the read margin of floating-gate programmable non-volatile memory cells. In some embodiments, the read margin of a cell with a floating-gate transistor in a non-conductive state is measured by periodically clocking a counter following initiation of a read cycle; a latch stores the counter contents upon the cell under test making a transition due to leakage of the floating-gate transistor. Logic for testing a group of cells in parallel is disclosed. In some embodiments, the read margin of a cell in which the floating-gate transistor is set to a conductive state is measured by repeatedly reading the cell, with the output developing a voltage corresponding to the duty cycle of the output of the read circuit. | 2015-09-17 |
20150262693 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device according to embodiment comprises: a memory cell array configured to include word lines and memory strings, the memory strings having memory cells connected in series, the memory cells being connected to the word lines; and a control unit configured to execute a read sequence to read data page-by-page, the control unit, during the read sequence on a first page, executing a read operation by applying a first read-pass voltage to a second word line and reading data in the first page, and executing a re-read operation by applying a second read-pass voltage different from the first read-pass voltage to the second word line and reading data in a first cell in a case where data read from a first cell group in the first page coincides with a specific first reference pattern. | 2015-09-17 |
20150262694 | NONVOLATILE MEMORY SYSTEM AND RELATED METHOD OF OPERATION - A system comprises a nonvolatile memory device comprising a memory cell array comprising a plurality of memory blocks each comprising a plurality of cell strings, each of cell strings comprises the plurality of memory cells stacked in a direction perpendicular to a substrate, a ground selection transistor disposed between the memory cells and the substrate, and a string selection transistor disposed between the memory cells and a bitline, and configured to read stored data from the memory cells using a plurality of read voltages; and a memory controller configured to read the memory cells using a reference voltage to generate on-cell data, and adjust the read voltages of the nonvolatile memory device based on the generated on-cell data. | 2015-09-17 |
20150262695 | METHODS, DEVICES, AND SYSTEMS FOR DATA SENSING - The present disclosure includes methods and devices for data sensing. One such method includes performing a number of successive sense operations on a number of memory cells using a number of different sensing voltages, determining a quantity of the number memory cells that change states between consecutive sense operations of the number of successive sense operations, and determining, based at least partially on the determined quantity of the number of memory cells that change states between consecutive sense operations, whether to output hard data corresponding to one of the number of successive sense operations. | 2015-09-17 |
20150262696 | MEMORY SYSTEM AND CONTROL METHOD OF MEMORY SYSTEM - According to one embodiment, a controller switches modes including a normal operating mode in which power resources of a volatile memory, a data storage unit, and a power control unit are all ON, a first mode in which the power resource of the volatile memory is OFF, and the power resources of the data storage unit and the power control unit are both ON, and a second mode in which the power resources of the volatile memory and the data storage unit are both OFF, and the power resource of the power control unit is ON. Upon receiving a low power consumption instruction command from a host, the controller stores management information to return to the normal operating mode into the volatile storage unit, and shifts the state of the memory system from the normal operating mode to the first mode. | 2015-09-17 |
20150262697 | STORAGE DEVICE AND RELATED METHODS USING TIMER SETTING - A storage device comprises at least one nonvolatile memory device and a memory controller configured to control the at least one nonvolatile memory device. The storage device searches for a read voltage for at least one memory cell in at least one page when power is turned on following a power-off state, calculates an off-time corresponding to the searched read voltage using a voltage-to-time lookup table, and sets a timer of the storage device using a time stamp corresponding to a page programmed before the power-off, and the off-time. | 2015-09-17 |
20150262698 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a block including a plurality of string units, each including a plurality of memory cells electrically connected in series, a bad string register in which information indicating which of the string units is a bad string is stored, and a control circuit. The control circuit controls an erase operation on the memory cells, the erase operation including a first erase operation followed by a first verify operation and as needed a subsequent erase operation followed by a subsequent verify operation. During the erase operation, the control circuit skips a verify operation for a string unit if the information in the bad string register indicates the string unit is a bad string. | 2015-09-17 |
20150262699 | SEMICONDUCTOR MEMORY DEVICE AND MEMORY CONTROLLER - A semiconductor memory device includes a plurality of string units, each of which includes a plurality of strings of memory cells connected in series, a controller configured to perform an erase operation on the string units, the erase operation including an erase verify operation that is performed per string unit, and a control circuit including a register that stores erase characteristic for at least one of the string units. The control circuit is configured to output the erase characteristic in response to a command from a memory controller. | 2015-09-17 |
20150262700 | FLASH MEMORY DEVICE USING ADAPTIVE PROGRAM VERIFICATION SCHEME AND RELATED METHOD OF OPERATION - A method of programming a flash memory device comprises programming selected memory cells, performing a verification operation to determine whether the selected memory cells have reached a target program state, and determining a start point of the verification operation based on a programming characteristic associated with a detection of a pass bit during programming of an initial program state. | 2015-09-17 |
20150262701 | NONVOLATILE MEMORY - According to one embodiment, a nonvolatile memory includes a memory area including a first magnetoresistive element, and a fuse circuit including a second magnetoresistive element serving as an anti-fuse element and configured to store correction information of the memory area when a defect exists in the memory area. The first magnetoresistive element includes a first storage layer, a first reference layer, and a first insulating film between the first storage layer and the first reference layer. The second magnetoresistive element includes a second storage layer, a second reference layer, and a second insulating film between the second storage layer and the second reference layer. | 2015-09-17 |
20150262702 | MAGNETIC MEMORY, METHOD OF RECORDING DATA TO AND REPRODUCING DATA FROM MAGNETIC MEMORY, AND METHOD OF OPERATING MAGNETIC MEMORY - A magnetic memory according to an embodiment includes: a plurality of groups of magnetic nanowires extending in a direction, each group of magnetic nanowires including at least one magnetic nanowire, each magnetic nanowire having a first terminal and a second terminal; a plurality of recording and reproducing elements corresponding to the groups of magnetic nanowires, each recording and reproducing element writing data to and reading data from magnetic nanowires of a corresponding group of magnetic nanowires, and connecting to the first terminals of the magnetic nanowires of the corresponding group of magnetic nanowires; and an electrode to which the second terminals of the magnetic nanowires of the groups of magnetic nanowires are connected. | 2015-09-17 |
20150262703 | SHIFT REGISTER, DISPLAY DEVICE PROVIDED THEREWITH, AND SHIFT-REGISTER DRIVING METHOD - Provided is a shift register capable of being driven using various clock signals, with low power consumption. A bistable circuit of a shift register is provided with first to third transistors, first to third input terminals, and an output terminal. In the first transistor, a gate terminal thereof and a first conduction terminal thereof are connected to the first input terminal. In the second transistor, a gate terminal thereof is connected to the third input terminal, and a first conduction terminal thereof is connected to the first input terminal. In the third transistor, a gate terminal thereof is connected respectively to second conduction terminals of the first and second transistors, a first conduction terminal thereof is connected to the second input terminal, and a second conduction terminal thereof is connected to the output terminal. | 2015-09-17 |
20150262704 | TRACK AND HOLD FEEDBACK CONTROL OF PULSED RF - A system and method of providing feedback control to a pulsed RF generator includes an RF generator having an RF output and a feedback input. An RF electrode is coupled to the RF output and an RF sampling circuit having a sampling input coupled to the RF electrode. The sampling circuit including a feedback signal output coupled to the feedback input of the RF generator. A method of providing feedback control to a pulse RF generator includes receiving an RF sample of an RF pulse, sampling the RF sample multiple sampling times to produce multiple feedback levels during the duration of the RF pulse and coupling the multiple feedback levels to a feedback input on an RF generator, the RF generator outputting the RF pulse. | 2015-09-17 |
20150262705 | STAGED BUFFER CACHING IN A SYSTEM FOR TESTING A DEVICE UNDER TEST - A system for testing a device under test (DUT) can include: a test controller unit that includes a first memory is operable to store a data pattern; a bridge circuit that includes a second memory that is smaller than the first memory, and a functional unit that includes a third memory that is smaller than the second memory. Portions of the data pattern can be selectively transferred from the first memory to the second memory during and for DUT testing operations. The functional circuit can interface with the DUT for testing. Portions of the data pattern can be selectively transferred from the second memory to the third memory for application to the DUT. | 2015-09-17 |
20150262706 | COMBINED RANK AND LINEAR ADDRESS INCREMENTING UTILITY FOR COMPUTER MEMORY TEST OPERATIONS - Embodiments include a combined rank and linear memory address incrementing utility. An aspect includes an address incrementing utility suitable for implementation within a memory controller as an integrated subsystem of a central processing unit (CPU) chip. In this type of on-chip embodiment, the address incrementing utility utilizes dedicated hardware, chip-resident firmware, and one or more memory address configuration maps to enhance processing speed, efficiency and accuracy. The combined rank and linear memory address incrementing utility is designed to efficiently increment through all of the individual bit addresses for a large logical memory space divided into a number of ranks on a rank-by-rank basis. The address incrementing utility sequentially generates all of the sequential memory addresses for a selected rank, and then moves to the next rank and sequentially generates all of the memory addresses for that rank, and so forth until of the ranks have been processed. | 2015-09-17 |
20150262707 | DESIGN-FOR-TEST APPARATUSES AND TECHNIQUES - Embodiments of design-for-test (DFT) apparatuses and related techniques are disclosed herein. In some embodiments, a DFT apparatus may include a static random access memory (SRAM) cell, read/write/decoder (R/W/decoder) circuitry to provide a nominal word line (WL) voltage and a nominal bit line (BL) voltage for application to the SRAM cell during accesses. The DFT apparatus may also include test circuitry having an activated state and a deactivated state. When the test circuitry is in the activated state, in some embodiments, the WL voltage and/or the BL voltage applied to the SRAM cell may be different from the nominal voltages provided by the R/W/decoder circuitry. The R/W/decoder circuitry may be operated to perform accesses to the SRAM cell while the test circuitry is in the activated state. Other embodiments may be disclosed and/or claimed. | 2015-09-17 |
20150262708 | SEMICONDUCTOR PACKAGES AND DATA STORAGE DEVICES INCLUDING THE SAME - A semiconductor package includes a package substrate having first connecting pads and second connecting pads, and a semiconductor chip mounted on the package substrate. The semiconductor chip includes a semiconductor device comprising a semiconductor substrate and electrically connected to input/output (I/O) pads, and a measuring device formed on the semiconductor device and electrically connected to measuring pads. The I/O pads are electrically connected to the first connecting pads, and the measuring pads are electrically connected to the second connecting pads. | 2015-09-17 |
20150262709 | SEMICONDUCTOR INTEGRATED CIRCUIT - According to one embodiment, there is provided a semiconductor integrated circuit including a memory, a capture register, a writing unit, and a control unit. The memory includes a plurality of memory bit cells. The capture register stores data read out from a memory bit cell selected out of the plurality of memory bit cells. The writing unit writes relevant data according to the data stored in the capture register to the memory bit cell. The control unit reads the relevant data from the written memory bit cell, compares the relevant data according to the data stored in the capture register and the read-out relevant data, controls the capture register such that a comparison result is stored by overwriting a result as a self-test result about the written memory bit cell, and controls the writing unit such that the original data according to the read-out relevant data is rewritten to the selected memory bit cell. | 2015-09-17 |
20150262710 | METHOD AND SYSTEM FOR REDUCING MEMORY TEST TIME UTILIZING A BUILT-IN SELF-TEST ARCHITECTURE - Methods and systems for reducing memory test time utilizing a serial per march element communicating architecture. A small number of slow speed signals can be configured between a BIST wrapper and a BIST controller to transfer information in accordance with a BIST sequence that includes a number of march elements. An information transfer protocol can be implemented between the BIST wrapper and the BIST controller to transfer Information with respect to each march element that includes a number of BIST operations, address sequencing information, and data pattern. A command register can be loaded utilizing the slow speed signals and slow speed clock and content of the command register can be decoded. An encoded BIST operation can then be executed once for each BIST operation per march element. The serial per march element communicating architecture reduces test time as a communication overhead and a requirement for high speed wires are eliminated. | 2015-09-17 |
20150262711 | BUILT-IN TESTING OF UNUSED ELEMENT ON CHIP - Embodiments relate to built-in testing of an unused element on a chip. An aspect includes concurrently performing on a chip comprising a plurality of chip elements comprising a plurality of active elements, each active element enabled to perform a respective function, and at least one unused element that is disabled from performing the respective function and configured to be selectively enabled as an active element, the respective functions of the respective active elements and a built-in self test (BIST) test of the at least one unused element. Another aspect includes inputting an input test pattern to the unused element. Another aspect includes receiving an output test pattern based on the input test pattern from the unused element. Another aspect includes comparing the input test pattern to the output test pattern. Another aspect includes determining whether the unused element passed or failed the testing based on the comparison. | 2015-09-17 |
20150262712 | MANUFACTURER SELF-TEST FOR SOLID-STATE DRIVES - An apparatus comprising a memory and a controller. The memory is configured to process a plurality of read/write operations. The memory comprises a plurality of memory modules each having a size less than a total size of the memory. The controller is configured to process a plurality of I/O requests to blocks of the memory that are not marked as bad on a block list. The controller is configured to track a plurality of bad blocks of the memory. The controller is configured to perform a plurality of scans on the memory. The scans are configured to (a) identify the bad blocks, and (b) mark the bad blocks as bad on the block list. | 2015-09-17 |
20150262713 | BUILT-IN TESTING OF UNUSED ELEMENT ON CHIP - Embodiments relate to built-in testing of an unused element on a chip. An aspect includes concurrently performing on a chip comprising a plurality of chip elements comprising a plurality of active elements, each active element enabled to perform a respective function, and at least one unused element that is disabled from performing the respective function and configured to be selectively enabled as an active element, the respective functions of the respective active elements and a built-in self test (BIST) test of the at least one unused element. Another aspect includes inputting an input test pattern to the unused element. Another aspect includes receiving an output test pattern based on the input test pattern from the unused element. Another aspect includes comparing the input test pattern to the output test pattern. Another aspect includes determining whether the unused element passed or failed the testing based on the comparison. | 2015-09-17 |
20150262714 | Finding Read Disturbs on Non-Volatile Memories - In non-volatile memory devices, the accessing of data on word line can degrade the data quality on a neighboring word line, in what is called a read disturb. Techniques are presented for determining word lines likely to suffer read disturbs by use of a hash tree for tracking the number of reads. Read counters are maintained for memory units at a relatively coarse granularity, such as a die or block. When the counter for one of these units reaches a certain level, it is subdivided into sub-units, each with their own read counter, in a process that be repeated to determine frequently read word lines with a fine level of granularity while only using a relatively modest amount of RAM on the controller to store the counters. | 2015-09-17 |
20150262715 | INFORMATION PROCESSING DEVICE, SEMICONDUCTOR CHIP, INFORMATION PROCESSING METHOD, AND COMPUTER PROGRAM PRODUCT - According to an embodiment, an information processing device includes a data obtaining unit and a data storage controller. The data obtaining unit is configured to obtain data measured by a sensor. The data storage controller is configured to store the data obtained by the data obtaining unit in a first memory of volatile nature when a sampling interval indicating an interval at which the data obtaining unit obtains the data is equal to or smaller than a threshold value. The data storage controller is configured to store the data obtained by the data obtaining unit and the data stored in the first memory in a second memory of nonvolatile nature when the sampling interval exceeds the threshold value. | 2015-09-17 |
20150262716 | METHODS OF OPERATING MEMORY INVOLVING IDENTIFIERS INDICATING REPAIR OF A MEMORY CELL - Method of operating memory including storing and/or using an identifier indicating repair of a memory cell. | 2015-09-17 |
20150262717 | METHODS, APPARATUS, AND SYSTEMS TO REPAIR MEMORY - Methods, apparatus and systems pertain to performing READ, WRITE functions in a memory which is coupled to a repair controller. One such repair controller could receive a row address and a column address associated with the memory and store a first plurality of tag fields indicating a type of row/column repair to be performed for at least a portion of a row/column of memory cells, and a second plurality of tag fields to indicate a location of memory cells used to perform the row/column repair. | 2015-09-17 |
20150262718 | STORAGE SYSTEM FOR PHARMACY - A storage system for a pharmacy that has a frame containing a frame with a plurality of storage carriers detachably suspended therefrom. The carriers are sized to receive filled prescription orders and the like and include individual identifiers that facilitate locating the carriers at a specific location on the frame. Preferably, the storage system includes a tracking system that detects, monitors, and displays to a worker the location of the storage carrier containing a particular customer's prescription order, thereby providing easy retrieval of the customer's prescription order. | 2015-09-17 |
20150262719 | NUCLEAR REACTOR CONTROL ROD AND MANUFACTURING METHOD THEREOF - A reactor control rod for nuclear reactor according to an embodiment has: a plurality of wing sections arranged radially around an axis extending in vertical direction in such a way as to be spaced out each other in a circumferential direction; and a central joint section bundling the plurality of wing sections together at center, wherein at least part of the central joint section and wing surface structural member is made of SiC-fiber-reinforced SiC composite material. The wing surface structural member of side of the central joint section may be sealed with the SiC-fiber-reinforced SiC composite material. Orientation directions of SiC fibers in the SiC-fiber-reinforced SiC composite material may be such that arithmetic mean of cos | 2015-09-17 |
20150262720 | ENERGY SHIELD FOR RADIATION SYSTEM - Among other things, an energy shield ( | 2015-09-17 |
20150262721 | RADIATION IMAGE ACQUIRING DEVICE - There is provided is a radiation image acquiring device which corrects a positional displacement between a collimator and a detector and obtains an image without artifacts. The device includes a detector ( | 2015-09-17 |
20150262722 | XRF SYSTEM HAVING MULTIPLE EXCITATION ENERGY BANDS IN HIGHLY ALIGNED PACKAGE - An x-ray analysis apparatus for illuminating a sample spot with an x-ray beam. An x-ray tube is provided having a source spot from which a diverging x-ray beam is produced having a characteristic first energy, and bremsstrahlung energy; a first x-ray optic receives the diverging x-ray beam and directs the beam toward the sample spot, while monochromating the beam; and a second x-ray optic receives the diverging x-ray beam and directs the beam toward the sample spot, while monochromating the beam to a second energy. The first x-ray optic may monochromate characteristic energy from the source spot, and the second x-ray optic may monochromate bremsstrahlung energy from the source spot. The x-ray optics may be curved diffracting optics, for receiving the diverging x-ray beam from the x-ray tube and focusing the beam at the sample spot. Detection is also provided to detect and measure various toxins in, e.g., manufactured products including toys and electronics. | 2015-09-17 |
20150262723 | POWDER AND PASTE FOR IMPROVING THE CONDUCTIVITY OF ELECTRICAL CONNECTIONS - An electrical connection powder comprising particles obtained by pulverising a skeleton of open cell metal foam chosen from the group consisting of iron, cobalt, nickel and the alloys of same covered with at least one coating of tin or indium or one of the alloys of same, The paste is formed from this powder dispersed in a binder such as grease. The powder or paste is particularity useful for improving the conductivity of an electrical connection consisting of a terminal ( | 2015-09-17 |
20150262724 | METHOD OF MANUFACTURING TRANSPARENT CONDUCTOR, TRANSPARENT CONDUCTOR AND DEVICE FOR MANUFACTURING THE SAME, AND DEVICE FOR MANUFACTURING TRANSPARENT CONDUCTOR PRECURSOR - According to one embodiment, a method of manufacturing a transparent conductor is provided. In the method, a silver nanowire layer including a plurality of silver nanowires and having openings is formed on a graphene film supported by a copper support. Then, a transparent resin layer insoluble in a copper-etching solution is formed on the silver nanowire layer such that the transparent resin layer contacts the graphene film through the openings. The copper support is then brought into contact with the non-acidic copper-etching solution to remove the copper support, thereby exposing the graphene film. | 2015-09-17 |
20150262725 | COMPOSITE CONDUCTOR - A composite conductor is composed of a core including a titanium or a titanium alloy, a cladding layer including a copper and being provided to clad an outer periphery of the core, and an intermetallic compound layer being formed by diffusions of the titanium or titanium alloy included in the core and the copper included in the cladding layer, and being provided between the core and the cladding layer. | 2015-09-17 |
20150262726 | GRAPHENE CONDUCTING WIRE AND METHOD OF MAKING THE SAME - A graphene conducting wire and a method of making the same are disclosed. The graphene conducting wire includes a wire core made of graphene and a copper layer encapsulating around an outer circumference of the wire core. The graphene conducting wire has an enhanced conductibility, reduced weight and improved flexibility without adverse influence on the welding characteristic thereof. By depositing graphene on a copper foil and then rolling the copper foil into the conducting wire, the technical problem that the graphene can hardly be processed into wire core is solved. | 2015-09-17 |
20150262727 | NANOPARTICLE POLYMER AND METHOD OF PREPARING A NANOPARTICLE POLYMER - Provided is a nanoparticle polymer in which a plurality of core particles that are linked to each other by a linker are surrounded by a metal-chalcogenide compound shell. The nanoparticle polymer may include a nanoparticle polymer including a core assembly including at least two nanoparticles connected to each other by a linker; and a shell that surrounds a surface of the core assembly and includes a metal-chalcogenide compound. | 2015-09-17 |
20150262728 | ELECTRICALLY CONDUCTIVE PASTE COMPOSITION AND METHOD OF FORMING AN ELECTRICAL CIRCUIT ON A POLYMER SUBSTRATE - An electrically conductive paste composition for forming an electrical circuit comprising: (a) a flake-shaped silver powder, wherein the mean particle size (D50) of the silver powder is 2.0 to 8.0 μm; and (b) a polyvinyl acetal resin, wherein the viscosity of a 10 wt % solution of the polyvinyl acetal resin in di-propylene glycol methyl ether is no less than 1 Pa·s as measured with a Brookfield viscometer (10 rpm, at 25° C.); and wherein the weight ratio of (a) to (b) is in the range from 87/13 to 95/5. | 2015-09-17 |
20150262729 | SILVER-COATED COPPER POWDER, AND METHOD FOR PRODUCING SAME - A silver-coated copper powder includes copper core particles and a silver coat layer located on the surface of the core particles. When S | 2015-09-17 |
20150262730 | TRANSPARENT CONDUCTIVE ELECTRODE AND ASSOCIATED PRODUCTION METHOD - The present invention relates to a multilayer conductive transparent electrode comprising:
| 2015-09-17 |
20150262731 | METHOD OF MAKING COPPER-CLAD GRAPHENE CONDUCTING WIRE - A method of making a copper-clad graphene conducting wire is disclosed. By filling graphene paste into inside of a hollow copper tube and then stretching the copper tube, a copper-clad graphene conducting wire is made, thereby solving the technical problem that the copper-clad graphene conducting wire can hardly be manufactured. | 2015-09-17 |
20150262732 | INSULATED WIRE AND MOTOR - An insulated wire, containing a conductor, an insulating layer that directly or indirectly coats the outer periphery of the conductor and includes a foaming thermosetting resin, and an outer non-foamed insulating layer that directly or indirectly coats the outer periphery of the insulating layer, wherein the insulating layer has a thickness deformation ratio of 15% or more and 50% or less upon applying a pressure of 1 MPa at 25° C., wherein the outer non-foamed insulating layer has pencil hardness of 4H or more, and wherein a ratio of thickness of the insulating layer to the outer non-foamed insulating layer is 20:80 to 80:20; and a motor, wherein the insulated wire is wound into a stator slot in a state in which pressure is applied in a direction for reducing the outer diameter of the insulated wire and a thickness of the insulating layer is reduced. | 2015-09-17 |
20150262733 | DURABLE FINE WIRE ELECTRICAL CONDUCTOR SUITABLE FOR EXTREME ENVIRONMENT APPLICATIONS - Durable fine wire electrical conductors are robust, durable, small in profile, and light weight, yet capable of operating under extreme environmental conditions. Formed of a glass, silica, sapphire or crystalline quartz fiber core with a metal coating and one or more polymer layers, a unipolar electrical conductor can have an outer diameter as small as about 300 microns or even smaller. The metal buffer coating may be deposited directly on the glass/silica fiber, or upon an intermediate layer between the glass/silica fiber and metal, consisting of carbon and/or polymer. The resulting metallized glass/silica fibers are extremely durable, can be bent through small radii and will not fatigue even from millions of iterations of flexing. Bipolar electrical conductors can include several insulated metallized glass/silica fibers residing side by side, or can be coaxial with two or more insulated metal conductive paths. An outer protective sheath of a flexible polymer material can be included. | 2015-09-17 |
20150262734 | SUPERCONDUCTING MEMBER AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a superconducting member includes a superconducting layer, a foundation layer, and an intermediate layer. The superconducting layer is made of an oxide including Cu and Ba. The foundation layer is made of cerium oxide. The intermediate layer is provided between the foundation layer and the superconducting layer, and is made of Ba | 2015-09-17 |
20150262735 | METHOD OF MAKING COPPER-CLAD GRAPHENE CONDUCTING WIRE - A method of making a copper-clad graphene conducting wire is disclosed. By encapsulating graphene oxide inside a copper material, stretching the copper material to form a conducting wire and then reducing the graphene oxide at a high temperature provided by an annealing or baking step, the goal of making a copper-clad graphene conducting wire in a simple way is achieved. | 2015-09-17 |
20150262736 | GRAPHENE CONDUCTING WIRE PRODUCTION METHOD - The present invention discloses a graphene conducting wire production method which involves preparing a grapheme oxide in the form of a solution, applying the solution to the surface of a metallic wire uniformly, heating the graphene oxide at a high temperature to turn it into a graphene by reduction reaction, and attaching the graphene to the surface of the metallic wire. The production method of the present invention eliminates technical difficulties in producing conventional graphene conducting wires. | 2015-09-17 |
20150262737 | SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING METHOD USING SUBSTRATE PROCESSING APPARATUS - In a substrate processing apparatus, a phosphoric acid aqueous solution is supplied to a processor, and a liquid collection from the processor is concurrently performed. Further, a silicon concentration is adjusted, to supply an adjusted processing liquid to the processor. Thus, a phosphoric acid aqueous solution film is formed on the substrate. The liquid film is heated by a heating device. The heating device has lamp heaters in a casing made of a silica glass. The phosphoric acid aqueous solution on the substrate is irradiated with infrared rays. A nitrogen gas flowing in a gas passage formed in the casing is discharged towards a position outside an outer periphery of the substrate. | 2015-09-17 |
20150262738 | Conductive Thin Film Comprising Silicon-Carbon Composite as Printable Thermistors - A method of fabricating a temperature sensing device based on printed silicon-carbon nanocomposite film is disclosed. This method includes high-crystal-quality Si nanoparticles (NPs) homogeneously mixed with carbon NPs and Si—C nanocomposites printed as negative temperature coefficient (NTC) thermistor. These mixtures of Si and C NPs are formulated into screen printing paste with acrylic polymer binder and ethylene glycol (EG) as solvent. This composite paste can be successfully printed on flexible substrates, such as paper or plastics, eventually making printable NTC thermistors quite low-cost. Si and carbon powders have size range of 10 nanometers to 100 micrometers and are mixed together with weight ratios of 100:1 to 10:1. More carbon content, higher conductivity of printed Si—C nanocomposite films keeping similar sensitivity of high-quality Si NPs. With homogeneous distribution of carbon particles in printed films, electrons can tunnel from silicon to carbon and high-conductivity carbon microclusters enhanced hopping process of electrons in printed nanocomposite film. The measured sensitivity 7.23%/° C. of printed Si—C nanocomposite NTC thermistor is approaching the reported value of 8.0-9.5%/° C. for intrinsic silicon bulk material near room temperature, with the quite low resistance of 10 kΩ-100 kΩ. This NTC thermistor is quite suitable for low-cost readout circuits and the integrated systems target to be disposable temperature sensors. | 2015-09-17 |