| 38th week of 2009 patent applcation highlights part 8 |
| Patent application number | Title | Published |
|---|
| 20090230478 | APPARATUS AND METHODS FOR IMPROVING MULTI-GATE DEVICE PERFORMACE - Embodiments of an apparatus and methods for improving multi-gate device performance are generally described herein. Other embodiments may be described and claimed. | 2009-09-17 |
| 20090230479 | Hybrid Process for Forming Metal Gates of MOS Devices - A semiconductor structure includes a first MOS device including a first gate, and a second MOS device including a second gate. The first gate includes a first high-k dielectric over a semiconductor substrate; a second high-k dielectric over the first high-k dielectric; a first metal layer over the second high-k dielectric, wherein the first metal layer dominates a work-function of the first MOS device; and a second metal layer over the first metal layer. The second gate includes a third high-k dielectric over the semiconductor substrate, wherein the first and the third high-k dielectrics are formed of same materials, and have substantially a same thickness; a third metal layer over the third high-k dielectric, wherein the third metal layer and the second metal layer are formed of same materials, and have substantially a same thickness; and a fourth metal layer over the third metal layer. | 2009-09-17 |
| 20090230480 | Epitaxial silicon germanium for reduced contact resistance in field-effect transistors - A method for selectively relieving channel stress for n-channel transistors with recessed, epitaxial SiGe source and drain regions is described. This increases the electron mobility for the n-channel transistors without affecting the strain in p-channel transistors. The SiGe provides lower resistance when a silicide is formed. | 2009-09-17 |
| 20090230481 | SEMICONDUCTOR DEVICE FORMED USING SINGLE POLYSILICON PROCESS AND METHOD OF FABRICATING THE SAME - Provided are a semiconductor device including a source/drain and a gate formed using a doped polysilicon process, and a method of fabricating the semiconductor device. The method comprises: forming a gate insulating layer on a part of an active region on a first conductivity type epitaxial layer; forming a conductive layer on the epitaxial layer; implanting high concentration impurities of a second conductivity type a first portion of the conductive layer on the gate insulating layer and second portions of the conductive layer on both sides of the first insulating layer; patterning the conductive layer; forming a second insulating layer on the epitaxial layer and high concentration impurity regions of the second conductivity type below the second conductive pattern; and implanting low-concentration impurities of the second conductivity type into the epitaxial layer between a gate structure and the high concentration impurity regions. | 2009-09-17 |
| 20090230482 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device in which an E-FET and a D-FET are integrated on the same substrate, wherein an epitaxial layer includes, in the following order from the semiconductor substrate: a first threshold adjustment layer that adjusts a threshold voltage of a gate of the E-FET and a threshold voltage of a gate of the D-FET; a first etching-stopper layer that stops etching performed from an uppermost layer to a layer abutting on the first etching-stopper layer; a second threshold adjustment layer that adjusts the threshold voltage of the gate of the D-FET; and a second etching-stopper layer that stops the etching performed from the uppermost layer to a layer abutting on the second etching-stopper layer, and at least one of the first etching-stopper layer and the second threshold adjustment layer includes an n-type doped region. | 2009-09-17 |
| 20090230483 | SEMICONDUCTOR DEVICE - Disclosed herein is a semiconductor device including: first and second transistors, each of the first and second transistors being formed with a plurality of fin transistors, and the first and second transistors being connected in parallel to electrically share a source, wherein the plurality of fin transistors each include a fin activation layer, the fin activation layer protruding from a semiconductor substrate, a source layer serving as the source being formed on one end, and a drain layer on the other end of the fin activation layer so as to form a channel region, the fin activation layers are arranged adjacent to each other in parallel, and the drain layers are disposed so that the currents flow through the plurality of fin transistors in opposite directions between the first and second transistors. | 2009-09-17 |
| 20090230484 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE - Embodiments relate to a method of fabricating a semiconductor device. In embodiments, a gate pattern may be formed on a semiconductor substrate, and sidewalls having a lower height than a height of the gate pattern may be formed at both sides of the gate pattern using a photoresist pattern. A silicide layer may be formed on exposed upper surface and side surfaces of the gate pattern and a portion of the semiconductor substrate at both sides of the sidewalls. Therefore, the silicide layer formed on a gate may be enlarged, and may reduce gate resistance. | 2009-09-17 |
| 20090230485 | ELEMENT WAFER AND METHOD FOR MANUFACTURING THE SAME - A recessed portion is provided in first and second insulating films, the first insulating film being stacked on a semiconductor wafer, the second insulating film being stacked on the first insulating film. The first and second insulating films are processed to form wiring in a formation region of the semiconductor wafer in which an acceleration sensor is to be formed. After a sacrificial film is stacked on the wiring and processed, a conductive film is stacked on the wiring and processed to form a plurality of thin film structures in the formation region. The recessed portion surrounds the formation region. | 2009-09-17 |
| 20090230486 | PIEZOELECTRIC DEVICE AND ELECTRONIC APPARATUS - A piezoelectric device includes an integrated circuit (IC) chip and a piezoelectric resonator element, a part of the piezoelectric resonator element being disposed so as to overlap with a part of the IC chip when viewed in plan. The IC chip includes: an inner pad disposed on an active face and in an area where is overlapped with the piezoelectric resonator when viewed in plan; an insulating layer formed on the active face; a relocation pad disposed on the insulating layer and in an area other than a part where is overlapped with the piezoelectric resonator element, the relocation pad being coupled to an end part of a first wire; and a second wire electrically coupling the inner pad and the relocation pad, the second wire having a relocation wire and a connector that penetrates the insulating layer, the relocation wire being disposed between the insulating layer and the active face. | 2009-09-17 |
| 20090230487 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND LID FRAME - A semiconductor device includes: a substrate; a semiconductor chip that is fixed to a first surface of the substrate; a chip covering lid body that is provided on the first surface of the substrate so as to cover the semiconductor chip and that forms a hollow first space portion that surrounds the semiconductor chip, and in which there is provided a substantially cylindrical aperture portion that extends to the outer side of the first space portion and has an aperture end at a distal end thereof and that is connected to the first space portion; and a first resin mold portion that forms the first space portion via the chip covering lid body and covers the substrate such that the aperture end is exposed, and that fixes the substrate integrally with the chip covering lid body. | 2009-09-17 |
| 20090230488 | Low dark current image sensor - Imaging sensors (CMOS image sensor, CCD) with low dark current. The disclosed embodiments employ a stacked structure directly on the sensing area. The stack structure an SiO | 2009-09-17 |
| 20090230489 | Low dark current image sensors by substrate engineering - Image sensors and the manufacture of image sensors having low dark current. A SiGe or Ge layer is selectively grown on the silicon substrate of the sensing area using an epitaxial chemical vapor deposition (CVD) method. After the SiGe or Ge growth, a silicon layer may be grown by the same epitaxial CVD method in an in-situ manner. This facilitates the formation of the hole accumulation diode and reduces the defect density of the substrate, resulting in device having a lower dark current. | 2009-09-17 |
| 20090230490 | SOLID-STATE IMAGING DEVICE AND METHOD FOR MANUFACTURING THE SAME - A solid-state imaging device includes: photoelectric transducers arranged in a matrix pattern on a substrate; and a plurality of color filter layers of different colors formed above the photoelectric transducers so as to correspond to the photoelectric transducers. One of the color filter layers of the color, which accounts for a largest area, is formed by two layers which are a bottom layer and a top layer of the color filter layers. | 2009-09-17 |
| 20090230491 | PHOTOELECTRIC CONVERSION DEVICE, IMAGING SYSTEM, AND PHOTOELECTRIC CONVERSION DEVICE MANUFACTURING METHOD - A photoelectric conversion device comprises: a plurality of photoelectric conversion units each generating charges corresponding to light; an element isolation portion which electrically isolate the plurality of photoelectric conversion units; and an antireflection portion which are arranged to prevent reflection of light, which has entered the element isolation portion from above the element isolation portion, only on a bottom face of the element isolation portion or only on the bottom face and a lower part of a side face of the element isolation portion. | 2009-09-17 |
| 20090230492 | Solid-state image pickup device and method of manufacturing the same - A solid-state image pickup device which includes a substrate carrying a plurality of photoelectric conversion elements which are two-dimensionally arranged therein the substrate having a plurality of rectangular light-receiving faces each corresponding to the photoelectric conversion element, a flattening layer having a plurality of approximately rectangular concave faces each located to correspond to the light-receiving faces, and a color filter having color layers of plural kinds of colors and buried in the concave faces of the flattening layer, the color filter exhibiting a larger refractive index than that of the flattening layer, wherein the color layers are respectively enabled to function as a convex lens. | 2009-09-17 |
| 20090230493 | SOLID-STATE IMAGING DEVICE AND METHOD OF FABRICATING SOLID-STATE IMAGING DEVICE - A solid-state imaging device includes: a solid-state imaging element having a light-receiving area; a transparent member disposed so as to oppose the light-receiving area; a supporting member configured to support the transparent member; a first mark disposed at either an upper surface of the transparent member or an upper surface of the supporting member; and a second mark disposed at an outer side of the light-receiving area, at an upper surface of the solid-state imaging element. | 2009-09-17 |
| 20090230494 | Solid-state imaging device, manufacturing method for the same, and imaging apparatus - A solid-state imaging device includes: a pixel section including, in a semiconductor substrate, plural photoelectric conversion sections that photoelectrically convert incident light to generate signal charges; metal wirings formed, on a first insulating film formed on the semiconductor substrate, above regions among the photoelectric conversion sections and above the periphery of the pixel section; a second insulating film formed on the first insulating film to cover the metal wirings; a first light shielding film formed on the second insulating film and having an opening above the pixel section; and a second light shielding film formed above the metal wirings above the pixel section and having thickness smaller than that of the first light shielding film. | 2009-09-17 |
| 20090230495 | INPUT DISPLAY - An input display is provided in the present invention. The input display includes a thin film transistor (TFT) and a light blocking layer. The TFT includes a low-field electrode, a high-field electrode connected to the low-field electrode with a connecting section, and a field-effect area positioned on the connecting section and connected to the high-field electrode, wherein a PN junction field is formed in the field-effect area when the TFT is switched off. The light blocking layer corresponds to the high-field electrode and hides the field-effect area from all incident light from the TFT. | 2009-09-17 |
| 20090230496 | SOLID-STATE IMAGING DEVICE - Disclosed herein is a solid-state imaging device including: a semiconductor substrate; a sensor of impurity diffusion layer formed on the surface layer of said semiconductor substrate; a negative charge accumulation layer formed on said sensor from an insulating material containing a first metallic substance; and an interfacial layer formed between said sensor and said negative charge accumulation layer from an insulating material containing a second metallic substance having greater electronegativity than said first metallic substance. | 2009-09-17 |
| 20090230497 | Pin Diode Structure with Zinc Diffusion Region - A PIN photodiode having a substrate, a first type electrode layer disposed on the substrate, a first layer of intrinsic material disposed over a portion of the first-type electrode layer, a first type window layer disposed over said intrinsic layer. An island shaped region of intrinsic material is disposed over the window layer and a dielectric layer disposed over the island region and at least the peripheral portion of said island shaped region whereby an opening is formed in the island shaped region. A dopant is diffused through the opening so as to form a PN junction that extends into the first layer of intrinsic material. | 2009-09-17 |
| 20090230498 | OPTICAL SEMICONDUCTOR DEVICE - An optical semiconductor device includes a semiconductor substrate; a light receiving element formed on the semiconductor substrate; a light absorbing element formed on the semiconductor substrate and located adjacent to the light receiving element; and a semiconductor element formed on the semiconductor substrate and used for signal processing. The light absorbing element includes a fifth semiconductor layer, and a light absorption region in the light receiving element has a different structure from a light absorption region in the light absorbing element. | 2009-09-17 |
| 20090230499 | Sensor device - A sensor device for sensing air flow speed at the exterior of an aircraft, comprising a substrate having an upper side on which is mounted a diaphragm over an aperture or recess in the substrate, the diaphragm being thermally and electrically insulative, and mounting on its upper surface a heating element comprising a layer of resistive material, and wherein electrical connections to the heating element are buried in the diaphragm and/or the substrate, and provide electrical terminals at the lower side of the substrate. The heating element is exposed to the environment, but the remaining electrical parts of the device are not exposed. | 2009-09-17 |
| 20090230500 | Semiconductor device - A semiconductor device equipped with a primary semiconductor element and a temperature detecting element for detecting a temperature of the primary semiconductor element. The device includes a first semiconductor layer of a first conductivity type that forms the primary semiconductor element. A second semiconductor region of a second conductivity type is provided in the first semiconductor layer. A third semiconductor region of the first conductivity type is provided in the second semiconductor region. The temperature detecting element is provided in the third semiconductor region and is separated from the first semiconductor layer by a PN junction. | 2009-09-17 |
| 20090230501 | Three dimensional structure memory - A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 μm in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques. | 2009-09-17 |
| 20090230502 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor device includes: forming a first semiconductor layer on a semiconductor substrate; forming a second semiconductor layer on the first semiconductor layer; forming a first groove which penetrates the first and the second semiconductor layers by etching the first and the second semiconductor layers; forming a support in the first groove; forming a second groove so that the first semiconductor layer is exposed by etching the second semiconductor layer; forming a cavity between the second semiconductor layer and the semiconductor substrate by etching the first semiconductor layer through the second groove; and forming an insulating film inside the cavity. In the step of forming the second groove, the second semiconductor layer is formed so as to have a first region, a second region, and a third region in a plan view. The first groove includes a plurality of first grooves. The first region is sandwiched between the first grooves in a first direction in the plan view. The second region is sandwiched between the first grooves in the first direction in the plan view and is provided parallel to the first region along a second direction which intersects with the first direction. The third region links the first and the second regions while being adjacent to the second groove. | 2009-09-17 |
| 20090230503 | METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE, AND SEMICONDUCTOR DEVICE - Methods for manufacturing a semiconductor substrate and a semiconductor device by which a high-performance semiconductor element can be formed are provided. A single crystal semiconductor substrate including an embrittlement layer and a base substrate are bonded to each other with an insulating layer interposed therebetween, and the single crystal semiconductor substrate is separated along the embrittlement layer by heat treatment to fix a single crystal semiconductor layer over the base substrate. Next, a plurality of regions of a monitor substrate are irradiated with laser light under conditions of different energy densities, and carbon concentration distribution and hydrogen concentration distribution in a depth direction of each region of the single crystal semiconductor layer which has been irradiated with the laser light is measured. Optimal irradiation intensity of laser light is irradiation intensity with which a local maximum of the carbon concentration and a shoulder peak of the hydrogen concentration are observed. A single crystal semiconductor layer is irradiated with optimal laser light at energy density detected by using the monitor substrate, whereby a semiconductor substrate is manufactured. | 2009-09-17 |
| 20090230504 | HOT process STI in SRAM device and method of manufacturing - A structure and method for forming SRAMs on HOT substrates with STI is described. Logic circuits may also be fabricated on the same chip with some devices on the SOI regions and other devices on the SOI regions. | 2009-09-17 |
| 20090230505 | Self-aligned memory cells and method for forming - The invention provides a memory cell based on variable resistance material memory element that includes an access device having a pillar structure that may also include a protective sidewall layer. The pillar access device selects and isolates the memory cell from other memory array cells and is adapted to both self-align any memory element formed thereon, and to deliver suitable programming current to the memory element. The pillar structure is formed from one or more access device layers stacked above a wordline and below the memory element. Optional resistive layers may be selectively formed within the pillar structure to minimize resistance in the access device layer and the memory element. The pillar access device may be a diode, transistor, Ovonic threshold switch or other device capable of regulating current flow to an overlying programmable memory material. | 2009-09-17 |
| 20090230506 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a fuse pattern formed as conductive polymer layer having a low melting point. The fuse pattern is easily cut at low temperature to improve repair efficiency. The semiconductor device includes first and second fuse connecting patterns that are separated from each other by a distance, a fuse pattern including a conductive polymer layer formed between the first and second fuse connection patterns and connecting the first and second fuse connection patterns, and a fuse box structure that exposes the fuse pattern. | 2009-09-17 |
| 20090230507 | MIM Capacitors in Semiconductor Components - Structures and methods of forming an ideal MIM capacitor are disclosed. The single capacitor includes a first and a second metal structure overlying a substrate, a first dielectric material disposed between a first portion of the first metal structure and a first portion of the second metal structure. A second dielectric material is disposed between a second portion of the first metal structure and a second portion of the second metal structure. No first dielectric material is disposed between the second portion of the first and second metal structures, and no second dielectric material is disposed between the first portion of the first and second metal structures. The first and second dielectric material layers include materials with opposite coefficient of capacitance. | 2009-09-17 |
| 20090230508 | SOI PROTECTION FOR BURIED PLATE IMPLANT AND DT BOTTLE ETCH - An SOI layer has an initial trench extending therethrough, prior to deep trench etch. An oxidation step, such as thermal oxidation is performed to form a band of oxide on an inner periphery of the SOI layer to protect it during a subsequent RIE step for forming a deep trench. The initial trench may stop on BOX underlying the SOI. The band of oxide may also protect the SOI during buried plate implant or gas phase doping. | 2009-09-17 |
| 20090230509 | FINGER CAPACITOR STRUCTURES - A capacitive structure formed in an Integrated Circuit (IC) includes a plurality of capacitor node conductor pairs, each including a first node conductor having a base portion and a plurality of finger portions and a second node conductor having a base portion and a plurality of finger portions that are inter digitized with the plurality of finger portions of the first node conductor. Dielectric is horizontally disposed between the first node conductor and the second node conductor. At least one dielectric layer vertically separates adjacent metal layers, each dielectric layer including dielectric disposed between the adjacent metal layers, a plurality of first node vias vertically connecting finger portions of first node conductors of the adjacent metal layers, and a plurality of second node vias vertically connecting finger portions of the second node conductors of the adjacent metal layers. The plurality of first node vias and plurality of second node vias have staggered spacing to preclude laterally adjacent first node vias and second node vias. | 2009-09-17 |
| 20090230510 | SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A rutile phase can be formed even in the case of a thin film by adding nickel or cobalt to titanium dioxide in the range of 0.5 to 10 atm %, and the use of this element-added titanium dioxide film in a capacitor dielectric film results in an increase in capacitance per unit area of a DRAM memory cell and enables a high-integration DRAM to be realized at low cost. | 2009-09-17 |
| 20090230511 | METHOD FOR FORMING CAPACITOR IN A SEMICONDUCTOR DEVICE - A method for forming a capacitor of a semiconductor device ensures charging capacity and improves leakage current characteristic. In the capacitor forming method, a semiconductor substrate formed with a storage node contact is prepared first. Next, a storage electrode is formed such that the storage electrode is connected to the storage node contact. Also, a dielectric film comprised of a composite dielectric of a SrTiO3 film and an anti-crystallization film is formed on the storage electrode. Finally, a plate electrode is formed on the dielectric film. | 2009-09-17 |
| 20090230512 | Nonvolatile Memory Devices that Use Resistance Materials and Internal Electrodes, and Related Methods and Processing Systems - A nonvolatile memory device, a method of fabricating the nonvolatile memory device and a processing system including the nonvolatile memory device. The nonvolatile memory device may include a plurality of internal electrodes that extend in a direction substantially perpendicular to a face of a substrate, a plurality of first external electrodes that extend substantially in parallel with the face of the substrate, and a plurality of second external electrodes that also extend substantially in parallel with the face of the substrate. Each first external electrode is on a first side of a respective one of the internal electrodes, and each second external electrode is on a second side of a respective one of the internal electrodes. These devices also include a plurality of variable resistors that contact the internal electrodes, the first external electrodes and the second external electrodes. | 2009-09-17 |
| 20090230513 | COMPOUND SEMICONDUCTOR SUBSTRATE AND CONTROL FOR ELECTRICAL PROPERTY THEREOF - There is provided a compound semiconductor substrate prepared by forming a point defect in an inside structure thereof by implanting an electrically-neutral impurity with energy of 0.1 to 10MeV on a surface of the substrate. When the compound semiconductor is undoped, electrical resistance increases to increase insulating properties, and when the compound semiconductor is doped with an n-type dopant, the impurity is implanted and charge concentration of the substrate increases to increase conductive properties. In accordance with the present invention, the various electrical properties needed for the compound semiconductor can be effectively controlled by increasing the insulating properties of the undoped compound semiconductor or by increasing the charge concentration of the n-type compound semiconductor, and the application range to various devices can be expanded. | 2009-09-17 |
| 20090230514 | Method of manufacturing nitride semiconductor device - A method of manufacturing a nitride semiconductor device includes the steps of: growing a group III nitride semiconductor layer on a substrate; forming a processed region in the substrate with a laser beam; and reducing the thickness of the substrate thereby spontaneously dividing the substrate from the processed region by the internal stress of the substrate. The substrate may be a sapphire substrate or an SiC substrate. | 2009-09-17 |
| 20090230515 | INSULATED GATE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A well region in which an insulated gate semiconductor element is formed is a diffusion region, and an impurity concentration of the well region is lower toward its bottom portion. This leads to a problem of increased resistance. Therefore, particularly, an insulated gate semiconductor element having an up-drain structure has a problem of increased on-resistance. A p type well region is formed by stacking two p type impurity regions on one another. The p type impurity regions are allowed to serve as the p type well region by sequentially stacking n type semiconductor layers, on one another, having p type impurities implanted into their surfaces and simultaneously diffusing the impurities by heat treatment. In this way, it is possible to obtain the p type well region in which an impurity concentration sufficient to secure a desired breakdown voltage is maintained approximately uniform up to a desired depth. | 2009-09-17 |
| 20090230516 | PIN Diode with Improved Power Limiting - A PIN diode comprising an N-type substrate comprising a cathode of the PIN diode and having an intrinsic layer disposed upon the N-type substrate and having a top surface a P-type material disposed upon the top surface of the intrinsic layer comprising an anode of the PIN diode and a N-type material disposed over the sidewall of the cathode and over the sidewall and a portion of the top surface of the intrinsic material that is not occupied by the anode, wherein a horizontal gap is defined between the anode and the cathode through the intrinsic material, the gap being variable in width and/or the horizontal gap is less than the thickness of the intrinsic layer. | 2009-09-17 |
| 20090230517 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INTEGRATION PORT - An integrated circuit package system comprising: fabricating a package base including: forming a lead frame, coupling a first integrated circuit device under the lead frame, coupling a second integrated circuit device over the first integrated circuit device, and molding an enclosure on the lead frame, the first integrated circuit device, and the second integrated circuit device for forming an integration port; and coupling a third integrated circuit device on the integration port. | 2009-09-17 |
| 20090230518 | SEMICONDUCTOR DIE PACKAGE INCLUDING IC DRIVER AND BRIDGE - A semiconductor die package. Embodiments of the semiconductor die package are usable in backlight circuitry. Systems in packages may include a bridge circuit or a part thereof, and a integrated circuit die, such as a driver die, encapsulated by a molding material or other package. The bridge circuit may be stacked on opposing surfaces of a leadframe. | 2009-09-17 |
| 20090230519 | Semiconductor Device - This application relates to a semiconductor device comprising: a carrier comprising a chip island and at least one first external contact element; only one semiconductor chip, wherein the semiconductor chip comprises a first electrode on a first surface and a second electrode on a second surface opposite to the first surface and wherein the first electrode is attached to the chip island; and a metal structure comprising a plate region attached to the second electrode and a connection region attached to the at least one first external contact element, wherein the plate region extends laterally beyond the edges of at least two sides of the second surface of the semiconductor chip. | 2009-09-17 |
| 20090230520 | Leadframe package with dual lead configurations - The invention provides a variety of leadframe packages in which signal connections and fixed voltage connections are configured differently to improve the relative performance of the connections relative to their assigned function. The signal connections incorporate one or more configurations of signal lead and corresponding signal bonding wires that tend to reduce the relative capacitance of the signal connectors and thereby improve high speed performance. The fixed voltage connections incorporate configurations of fixed voltage leads and fixed voltage bonding wires that will tend to reduce the inductance of the fixed voltage connector and reduce noise on the fixed voltage connections and improve power delivery characteristics. The configurations of the associated signal and fixed voltage connections will tend to result in signal connections that include signal leads that are shorter, narrower and/or more widely separated from the active surface of the semiconductor chip than the corresponding fixed voltage leads. | 2009-09-17 |
| 20090230521 | Stress Mitigation in Packaged Microchips - A packaged microchip has a lead frame with a die directly contacting at least a single, contiguous portion of the lead frame. The portion of the lead frame has a top surface forming a concavity and contacting the die. The packaged microchip also has mold material substantially encapsulating part of the top surface of the portion of the lead frame. | 2009-09-17 |
| 20090230522 | Method for producing a semiconductor device and the semiconductor device - In a method of manufacturing a semiconductor device which has rear electrodes extended from a front surface to a rear surface of a substrate, the rear electrodes are formed from a side of the front surface by forming a groove on the front surface, by forming a metal film on the groove, and by removing the substrate from a rear surface until the metal film is exposed on a bottom of the groove. | 2009-09-17 |
| 20090230523 | ADVANCED QUAD FLAT NO LEAD CHIP PACKAGE HAVING A CAVITY STRUCTURE AND MANUFACTURING METHODS THEREOF - A semiconductor package and related methods are described. In one embodiment, the package includes a die pad, a plurality of leads, a chip, and a package body. The die pad includes: (1) a peripheral edge region defining, a cavity with a cavity bottom including a central portion; (2) an upper sloped portion; and (3) a lower sloped portion. Each lead includes an upper sloped portion and a lower sloped portion. The chip is disposed on the central portion of the cavity bottom and is coupled to the leads. The package body is formed over the chip and the leads, substantially fills the cavity, and substantially covers the upper sloped portions of the die pad and the leads. The lower sloped portions of the die pad and the leads at least partially extend outwardly from a lower surface of the package body. | 2009-09-17 |
| 20090230524 | SEMICONDUCTOR CHIP PACKAGE HAVING GROUND AND POWER REGIONS AND MANUFACTURING METHODS THEREOF - A semiconductor package and related methods are described. In one embodiment the semiconductor package includes a die pad, a plurality of leads, a semiconductor chip, and a package body. The die pad includes a first part that includes a lower surface and a first peripheral edge region comprising a ground region. The die pad further includes a second part that is spaced apart from the first part and that includes a lower surface and a second peripheral edge region comprising a power region. The plurality of leads is disposed around the die pad. The semiconductor chip is disposed on the die pad and is electrically coupled to the ground region, the power region, and the plurality of leads. The package body is formed over the semiconductor chip and the plurality of leads. | 2009-09-17 |
| 20090230525 | ADVANCED QUAD FLAT NO LEAD CHIP PACKAGE HAVING MARKING AND CORNER LEAD FEATURES AND MANUFACTURING METHODS THEREOF - A semiconductor package and related methods are described. In one embodiment, the package includes a die pad, a first plurality of leads disposed in a lead placement area around the die pad, a second plurality of leads disposed in corner regions of the lead placement area, a semiconductor chip on the die pad and coupled to each lead, and a package body. Each lead includes an upper sloped portion and a lower sloped portion. An average of surface areas of lower surfaces of each of the second plurality of leads is at least twice as large as an average of surface areas of lower surfaces of each of the first plurality of leads. The package body substantially covers the upper sloped portions of the leads. The lower sloped portions of the leads at least partially extend outwardly from a lower surface of the package body. | 2009-09-17 |
| 20090230526 | ADVANCED QUAD FLAT NO LEAD CHIP PACKAGE HAVING A PROTECTIVE LAYER TO ENHANCE SURFACE MOUNTING AND MANUFACTURING METHODS THEREOF - A semiconductor package and related methods are described. In one embodiment, the package includes a die pad, multiple leads, a chip, a package body, and a protective layer. The die pad includes an upper sloped portion, a lower sloped portion, and a peripheral edge region defining a cavity with a cavity bottom. Each lead includes an upper sloped portion and a lower sloped portion. The chip is disposed on the cavity bottom and is coupled to the leads. The package body is formed over the chip and the leads, substantially fills the cavity, and substantially covers the upper sloped portions of the die pad and the leads. The lower sloped portions of the die pad and the leads at least partially extend outwardly from a lower surface of the package body. The protective layer substantially covers the lower sloped portion and the lower surface of at least one lead. | 2009-09-17 |
| 20090230527 | Multi-chips package structure and the method thereof - A multi-chips package structure is provided, which includes a chip-placed frame having a plurality of chip-placed areas thereon, and two adjacent chip-placed areas is connected by a plurality of leads; a plurality of chips, each chip has a plurality of pads on an active surface thereon, and is provided on the chip-placed area; a package body is covered around the four sides of the chip-placed frame, and the pads of the chip is to be exposed; one end of a plurality of patterned metal traces is electrically connected to the plurality of pads, another end is extended to cover the surface of the patterned first protection layer; a patterned second protective layer is covered on the patterned metal traces and another end of the patterned metal traces is to be exposed; a plurality of patterned UMB layer is formed on the extended surface of the patterned metal traces; and a plurality of conductive elements is formed on the patterned UMB layer and is electrically connected to one end of the exposed portion of the patterned metal traces. | 2009-09-17 |
| 20090230528 | Support Mounted Electrically Interconnected Die Assembly - Stacked die assemblies are electrically connected to connection sites on any support, without electrical connection to any interposed substrate or leadframe, and without solder. | 2009-09-17 |
| 20090230529 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ETCHED RING AND DIE PADDLE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system is provided including: forming a D-ring includes half etching a paddle, etching a ring, and etching a tie bar. The tie bar is between the paddle and the ring. The system further includes mounting an integrated circuit die on a central portion of the D-ring, connecting the integrated circuit die and the D-ring, and encapsulating the integrated circuit die and a portion of the D-ring. | 2009-09-17 |
| 20090230530 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE - A back side of the silicon semiconductor substrate is roughly ground and is finishing-ground by using a whetstone having a copper content of less than 1 ppm, the back side being an opposite side of a side on which the semiconductor element is formed. The back side of the silicon semiconductor substrate is cleaned by the silicon chemical etching. A part up to depth of 3 nm from the back side of the silicon semiconductor substrate comprises copper of 1×10 | 2009-09-17 |
| 20090230531 | Semiconductor Package with Penetrable Encapsulant Joining Semiconductor Die and Method Thereof - A semiconductor device is made by mounting a first semiconductor die to a first substrate, forming a first encapsulant over the first semiconductor die, and forming a second encapsulant over the first encapsulant. The second encapsulant is penetrable, thermally conductive material. A second semiconductor die is mounted to the second substrate. A bond wire electrically connects the second semiconductor die to the second substrate. A passive circuit element is mounted to the second substrate. Leading with the second encapsulant, the first substrate is pressed onto the second substrate so that the second encapsulant completely covers the second semiconductor die, bond wire, and passive circuit element. The second encapsulant is then cured. A third encapsulant is formed over the first and second substrates. A shield can be disposed over the second semiconductor die with openings for the second encapsulant to flow through when pressed onto the second substrate. | 2009-09-17 |
| 20090230532 | SYSTEM FOR SOLDER BALL INNER STACKING MODULE CONNECTION - An integrated circuit package-in-package system including: providing a substrate; mounting a structure over the substrate; supporting an inner stacking module cantilevered over the substrate by an electrical interconnect connected to the substrate, the electrical interconnect forming a gap between the inner stacking module and the structure controlled by the size of the electrical interconnect; and encapsulating the structure and inner stacking module with an encapsulation. | 2009-09-17 |
| 20090230533 | MANUFACTURING STACKED SEMICONDUCTOR DEVICE - A method in accordance with an embodiment of the invention can include forming fan-out wirings on an insulating layer formed on a wafer. Additionally, electrodes of a plurality of semiconductor chips stacked on the fan-out wirings can be electrically coupled with the fan-out wirings. The wafer can be removed. | 2009-09-17 |
| 20090230534 | SEMICONDUCTOR MEMORY APPARATUS - The semiconductor memory apparatus related to an embodiment of the present invention includes a wiring substrate arranged with a device mounting part and connection pads aligned along one exterior side of the wiring substrate, a plurality of semiconductor memory devices including electrode pads which are arranged along one external side of the wiring substrate, a semiconductor memory device group in which the plurality of semiconductor memory devices are stacked on the device mounting part of the wiring substrate so that pad arrangement sides all face in the same direction, and a controller device including the electrode pads arranged along at least one external side of the wiring substrate, wherein the electrode pads of the plurality of semiconductor memory devices and the electrode pads of the controller device are arranged parallel to an arrangement position of the connection pads of the wiring substrate. | 2009-09-17 |
| 20090230535 | SEMICONDUCTOR MODULE - A semiconductor module. In one embodiment, at least two semiconductor chips are placed on a carrier. The at least two semiconductor chips are then covered with a molding material. An exposed portion of the at least two semiconductor chips is provided. A first layer of conductive material is applied over the exposed portion of the at least two semiconductor chips to electrically connect to a contact pad on the exposed portion of the at least two semiconductor chips. The at least two semiconductor chips are singulated. | 2009-09-17 |
| 20090230536 | SEMICONDUCTOR DIE PACKAGE INCLUDING MULTIPLE SEMICONDUCTOR DICE - A semiconductor die package. The semiconductor die package includes a leadframe structure comprising a first die attach pad, and a second die attach pad laterally spaced from the first die attach pad, a first side and a second side opposite to the first side. The semiconductor die package further includes a first semiconductor die attached the first die attach pad at the first side of the leadframe structure, and a second semiconductor die attached to the second die attach pad at the second side of the leadframe structure. The semiconductor die package further includes a housing material covering at least a portion of the leadframe structure, the first semiconductor die, and the second semiconductor die. | 2009-09-17 |
| 20090230537 | SEMICONDUCTOR DIE PACKAGE INCLUDING EMBEDDED FLIP CHIP - A semiconductor die package. The semiconductor die package includes a leadframe structure, a first semiconductor die comprising a first surface attached to a first side of the leadframe structure, and a second semiconductor die attached to a second side of the leadframe structure. The second semiconductor die comprises an integrated circuit die. A housing material is formed over at least a portion of the leadframe structure, the first semiconductor die, and the second semiconductor die. An exterior surface of the molding material is substantially coplanar with the first surface of the semiconductor die. | 2009-09-17 |
| 20090230538 | SEMICONDUCTOR CHIP PACKAGE STRUCTURE FOR ACHIEVING FACE-UP ELECTRICAL CONNECTION WITHOUT USING A WIRE-BONDING PROCESS AND METHOD FOR MAKING THE SAME - A semiconductor chip package structure for achieving face-up electrical connection without using a wire-bonding process includes a package unit, a semiconductor chip, a substrate unit, a first insulative unit, a first conductive unit, a second conductive unit, and a second insulative unit. The package unit has a central receiving groove and an outer receiving groove formed around the central receiving groove. The semiconductor chip has a plurality of conductive pads. The first insulative unit has a first insulative layer formed between the conductive pads. The first conductive unit has a plurality of first conductive layers. The second conductive unit has a plurality of second conductive layers formed on the first conductive layers. The second insulative unit is formed between the first conductive layers and between the second conductive layers. | 2009-09-17 |
| 20090230539 | SEMICONDUCTOR DEVICE - In recent years, as electronic equipment becomes thinner, an area for mounting a semiconductor device used in the electronic equipment is required to be smaller, and a thickness of an encapsulating resin for encapsulating a semiconductor substrate having a circuit formed thereon and the like also becomes smaller. The encapsulating resin is marked with a product number, a manufacturer name, or the like. There arises a problem in that, in the marking, an infrared laser beam applied to the encapsulating resin passes through the encapsulating resin, generates heat in the semiconductor substrate, and destructs the formed circuit. By providing a thin film for refracting the infrared laser beam on a rear surface of the semiconductor substrate, the optical path of the infrared laser beam is made longer to reduce heat generated in the semiconductor substrate. | 2009-09-17 |
| 20090230540 | HIGH PERFORMANCE MULTI-CHIP FLIP CHIP PACKAGE - A structure and method of manufacture for an improved multi-chip semiconductor package that reduces package resistance to a negligible level, and offers superior thermal performance. Housing of multiple dies is facilitated by providing electrically isolated lead frames that are separated from a common base carrier by a non-conductive layer of laminating material. A silicon die is attached inside a cavity formed in each lead frame. Direct connection of the active surface of the silicon die to the printed circuit board is then made by an array of solder bumps that is distributed across the surface of each die as well as the edges of the lead frame adjacent to each die. | 2009-09-17 |
| 20090230541 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor device in which a chip is embedded in a wiring board and bump electrodes formed over the front surface of the semiconductor chip are flip-chip coupled to wiring formed in the wiring board and the entire back surface of the semiconductor chip functions well as a back electrode and a method of manufacturing the semiconductor device. A semiconductor chip is embedded inside a wiring board. The semiconductor chip is flip-chip coupled (face down) to a base substrate as the core layer of the wiring board through bump electrodes. A conductive film is formed over the semiconductor chip's surface reverse to the surface over which bump electrodes are formed. The conductive film functions as a back electrode which supplies a reference voltage to the integrated circuit in the semiconductor chip. The conductive film is electrically coupled to third-layer wiring through vias. | 2009-09-17 |
| 20090230542 | Semiconductor Device With Integrated Passive Circuit and Method of Making the Same Using Sacrificial Substrate - A semiconductor device is made by providing a sacrificial substrate, forming a first insulating layer over the sacrificial substrate, forming a first passivation layer over the first insulating layer, forming a second insulating layer over the first passivation layer, forming an integrated passive device over the second insulating layer, forming a wafer support structure over the integrated passive device, removing the sacrificial substrate to expose the first insulating layer after forming the wafer support structure, and forming an interconnect structure over the first insulating layer in electrical contact with the integrated passive device. The integrated passive device includes an inductor, capacitor, or resistor. The sacrificial substrate is removed by mechanical grinding and wet etching. The wafer support structure can be glass, ceramic, silicon, or molding compound. The interconnect structure can include a solder bump, wire bond, and intermediate conduction layer formed on a backside of the semiconductor device. | 2009-09-17 |
| 20090230543 | Semiconductor package structure with heat sink - A semiconductor package structure with a heat sink is disclosed herein. The semiconductor package structure includes a substrate having a chip mounting area and a plurality of through holes surrounding the chip mounting area; a chip set on the chip mounting area and electrically connected to the substrate; a heat sink covering the chip, wherein the heat sink has a plurality of support portions extending from the upper surface to the lower surface of the substrate via those through holes; and a molding compound covering the chip, a portion of the substrate and the heat sink. Those support portions of the heat sink are utilized to improve the heat dissipation efficiency and the warpage issue of the package. | 2009-09-17 |
| 20090230544 | HEAT SINK STRUCTURE AND SEMICONDUCTOR PACKAGE AS WELL AS METHOD FOR CONFIGURING HEAT SINKS ON A SEMICONDUCTOR PACKAGE - A heat sink structure according to the present invention is provided. The heat sink has a through opening extending from the upper surface through to the lower surface. A solder is disposed in the through opening and on the upper and lower surfaces of the heat sink, wherein the portion of the solder in the through opening is connected with the portions of the solder on the upper and lower surfaces. | 2009-09-17 |
| 20090230545 | ELECTRONIC DEVICE CONTACT STRUCTURES - Electronic device contact structures are disclosed. | 2009-09-17 |
| 20090230546 | MOUNTED BODY AND METHOD FOR MANUFACTURING THE SAME - A mounted body of the present invention includes: a multilayer semiconductor chip | 2009-09-17 |
| 20090230547 | DESIGN STRUCTURE, SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING A SEMICONDUCTOR STRUCTURE AND PACKAGING THEREOF - A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a dielectric material formed between a design sensitive structure and a passivation layer. The design sensitive structure comprising a lower wiring layer electrically and mechanically connected to a higher wiring level by a via farm. A method and structure is also provided. | 2009-09-17 |
| 20090230548 | SEMICONDUCTOR PACKAGE AND MULTI-CHIP PACKAGE USING THE SAME - A semiconductor package may have a semiconductor chip that includes a chip pad formed on a substrate including an integrated circuit, and a passivation layer exposing the chip pad, a first redistribution wiring layer that is connected to the chip pad and extends on the semiconductor chip and includes a wire bonding pad to provide wire bonding and a first solder pad to connect the first redistribution wiring layer to a second semiconductor chip, and a second redistribution wiring layer that is connected to the first redistribution wiring layer on the first redistribution wiring layer and includes a second solder pad to connect the second redistribution wiring layer to a third semiconductor chip. | 2009-09-17 |
| 20090230549 | FLIP CHIP PACKAGE - A flip chip package may include a substrate, a semiconductor chip, main bump structures and auxiliary bump structures. The substrate has a circuit pattern. The semiconductor chip is arranged over the substrate. The semiconductor chip includes a body having semiconductor structures, main pads electrically connected to the semiconductor structures to mainly control the semiconductor structures, and auxiliary pads electrically connected to the semiconductor structures to provide auxiliary control of the semiconductor structures. The main bump structures are interposed between the semiconductor chip and the substrate to electrically connect the circuit pattern with the main pads. The auxiliary bump structures can be interposed between the semiconductor chip and the substrate to electrically connect the circuit pattern with the auxiliary pads. | 2009-09-17 |
| 20090230550 | Method and system for the modular design and layout of integrated circuits - An integrated circuit (IC) and fabrication method thereof is provided that include the steps of specifying a plurality of required tile modules suitable for a particular end application, each of the modular tiles being configured to perform a predetermined function and constructed to have approximately the same length and width dimensions. The modular tiles are used to form the IC in a standard IC fabrication process. In many implementations, physical layout of the IC does not include the step of routing. Capabilities also include configuring the modular tiles to have programmable performance parameters and configuring the modular tiles to cooperate usefully with one another based on a programmable parameter. | 2009-09-17 |
| 20090230551 | SEMICONDUCTOR DEVICE - The reliability of a semiconductor device which has the semiconductor components which were mounted on the same surface of the same substrate via the bump electrodes with which height differs, and with which package structure differs is improved. | 2009-09-17 |
| 20090230552 | Bump-on-Lead Flip Chip Interconnection - A flip chip interconnect is made by mating the interconnect bump directly onto a lead, rather than onto a capture pad. Also, a flip chip package includes a die having solder bumps attached to interconnect pads in an active surface, and a substrate having electrically conductive traces in a die attach surface, in which the bumps are mated directly onto the traces. In some embodiments the interconnection is formed without employing a solder mask. In some methods a curable adhesive is dispensed either onto the bumps on the die or onto the traces on the substrate; the adhesive is partly cured during the mating process, and the partly cured adhesive serves to confine the molten solder during a reflow process. | 2009-09-17 |
| 20090230553 | SEMICONDUCTOR DEVICE INCLUDING ADHESIVE COVERED ELEMENT - A semiconductor device includes a chip, at least one element electrically coupled to the chip, an adhesive at least partially covering the at least one element, and a mold material at least partially covering the chip and the adhesive. | 2009-09-17 |
| 20090230554 | WAFER-LEVEL REDISTRIBUTION PACKAGING WITH DIE-CONTAINING OPENINGS - Methods, systems, and apparatuses for integrated circuit packages, and processes for forming the same, are provided. In one example, an integrated circuit (IC) package includes a thick film material that forms a opening, a die, an insulating material, a redistribution interconnect on the insulating material, and a ball interconnect. The die is positioned in the opening. The insulating material covers the die and a surface of the thick film material, and fills a space adjacent to the die in the opening. The redistribution interconnect is formed on the insulating material. The redistribution interconnect has a first portion coupled to a terminal of the die through the layer of the insulating material, and a second portion that extends away from the first portion over the insulating material filling the space adjacent to the die in the opening. The ball interconnect is coupled to the second portion of the redistribution interconnect. | 2009-09-17 |
| 20090230555 | TUNGSTEN LINER FOR ALUMINUM-BASED ELECTROMIGRATION RESISTANT INTERCONNECT STRUCTURE - An underlying interconnect level containing underlying W vias embedded in a dielectric material layer are formed on a semiconductor substrate. A metallic layer stack comprising, from bottom to top, a low-oxygen-reactivity metal layer, a bottom transition metal layer, a bottom transition metal nitride layer, an aluminum-copper layer, an optional top transition metal layer, and a top transition metal nitride layer. The metallic layer stack is lithographically patterned to form at least one aluminum-based metal line, which constitutes a metal interconnect structure. The low-oxygen-reactivity metal layer enhances electromigration resistance of the at least one aluminum-based metal line since formation of compound between the bottom transition metal layer and the dielectric material layer is prevented by the low-oxygen-reactivity metal layer, which does not interact with the dielectric material layer. | 2009-09-17 |
| 20090230556 | NONVOLATILE SEMICONDUCTOR MEMORY APPARATUS AND MANUFACTURING METHOD THEREOF - A nonvolatile semiconductor memory apparatus | 2009-09-17 |
| 20090230557 | Semiconductor Device and Method for Making Same - One or more embodiments are related to a semiconductor device, comprising: a metallic layer having a top surface and a sidewall surface; an intermediate layer disposed on a sidewall surface of the metallic layer; a dielectric layer disposed over the metallic layer, the dielectric layer having an opening formed therethrough; and a conductive material disposed within the opening, the conductive material at least partially overlying the top surface of the metallic layer, the conductive material being electrically coupled to the metallic layer. | 2009-09-17 |
| 20090230558 | Semiconductor device and method for manufacturing the same - The present invention is a method for manufacturing a semiconductor device having a conductor and an insulating film on a substrate, the method including the steps of forming the conductor on the substrate, forming the insulating film on the conductor, removing the insulating film on the conductor, and blowing an organosilane gas and a hydrogen gas to reduce an oxidized region on the conductor, wherein the oxidized region on the conductor is formed when the insulating film is removed. | 2009-09-17 |
| 20090230559 | Semiconductor device - A semiconductor device having macro circuit including a plurality of fine interconnections, an extension interconnection wider than the fine interconnections, having a first end connected to one or more of the fine interconnections and a second end located in an area of the semiconductor device external to the macro circuit, and one or more of the fine interconnections widened towards the connection to the extension wiring interconnection. The extension interconnection is formed in the same layer as one or more of the interconnections connected to the extension interconnection. | 2009-09-17 |
| 20090230560 | Semiconductor device and manufacturing method thereof - A semiconductor device and manufacturing method thereof improving moisture resistance of a FeRAM. After a probe test using a pad, a metal film is formed to cover the pad in an opening of a protective film and a region from the pad to an opening outer periphery of the protective film. On the metal film, a metal bump is formed. The metal film is formed to have a two-layer structure of the first and second metal films. Materials of the lower and upper layers are selected mainly in consideration of adhesion to the protective film and adhesion to the metal bump, respectively. Film formation conditions thereof are set to provide metal films with a desired quality and thickness. Thus, penetration of moisture from the pad or the periphery into a ferroelectric capacitor can be prevented and therefore, occurrence of potential inversion abnormalities due to penetrated moisture can be effectively suppressed. | 2009-09-17 |
| 20090230561 | SEMICONDUCTOR DEVICE - A semiconductor device includes an active area having a source and a gate. A gate metal contact is deposited above and forms an electrical contact with the gate and a source metal contact is deposited above and forms an electrical contact with the source. The source metal contact includes a plurality of metal through contacts positioned adjacent a side of the active area, the plurality of metal through contacts being spaced at intervals from one another and arranged in two or more rows. | 2009-09-17 |
| 20090230562 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device including a dummy via is disclosed. In the semiconductor integrated circuit device, problems such as reduction in the designability and increase in fabrication cost which result from the existence of a dummy wire connected to the dummy via are suppressed. The semiconductor integrated circuit device includes a substrate and three or more wiring layers formed on the substrate. The dummy via connects between a first wiring layer and a second wiring layer. The dummy wire connected to the dummy via exists in the second wiring layer. A protrusion amount of the dummy wire is smaller than a protrusion amount of an intermediate wire included in a stacked via structure. | 2009-09-17 |
| 20090230563 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device capable of preventing a crack from occurring in an electrode layer exposed through a through hole which is formed in a semiconductor substrate and a method of manufacturing the semiconductor device. In exemplary embodiments, a through via and an opening in a passivation film are disposed so that an opening diameter of the through via is larger than an opening diameter of the opening of the passivation film, and an opening edge of the through via is located outside an opening edge of the opening of the passivation film. In other embodiments, the through via and the opening of the passivation film are disposed so that the opening edge of the through via is disposed at a location which does not overlap with the opening edge (opening edge of a portion in contact with a pad electrode) of the opening of the passivation film. | 2009-09-17 |
| 20090230564 | CHIP STRUCTURE AND STACKED CHIP PACKAGE AS WELL AS METHOD FOR MANUFACTURING CHIP STRUCTURES - A chip structure according to the present invention is provided. A plurality of pedestals extends from the back surface of the chip structure. Each of the pedestals is located at a position away from the edge of the back surface for a non-zero distance so that the pedestals of an upper chip structure will not damage the bonding pads positioned on the edge of the active surface of a lower chip structure when the upper chip structure is stacked on the active surface of the lower chip structure with the pedestals. | 2009-09-17 |
| 20090230565 | SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A stacked semiconductor package and a method for manufacturing the same are presented which exhibit a reduced electrical resistance and an increased junction force. The semiconductor package includes at least two semiconductor chips stacked upon each other. Each semiconductor chip has a plurality of bonding pads formed on upper surfaces and has via-holes. First wiring lines are located on the upper surfaces of the semiconductor chips, on the surfaces of the via-holes, and respectively connected onto their respective bonding pads. Second wiring lines are located on lower surfaces of the semiconductor chips and on the surfaces of the respective via-holes which connect to their respective first wiring lines. The semiconductor chips are stacked so that the first wiring lines on an upper surface of an upwardly positioned semiconductor chip are respectively joined with corresponding second wiring lines formed on a lower surface of a downwardly positioned semiconductor chip. | 2009-09-17 |
| 20090230566 | Method of underfill air vent for flipchip BGA - This invention relates to ejecting an underfill resin at multiple semiconductor die edges such that vacuum suction provided at a laminate through hole located beneath a stage enables spread of underfill resin from each edge simultaneously for quicker spread and reduction of voids. The excess underfill resin intentionally suctioned through the through hole air vent on the underside of the laminate is attracted to re-usable tape. The attracted underfill resin is cleaned from a rotating head mechanism by a cleaning pad positioned beneath a lower surface of the head. | 2009-09-17 |
| 20090230567 | METHOD OF POST-MOLD GRINDING A SEMICONDUCTOR PACKAGE - A method of grinding a molded semiconductor package to a desired ultra thin thickness without damage to the package is disclosed. Prior to grinding a molded package to a desired package thickness, the package may be protected from excessive mechanical stress generated during grinding by applying a protective tape to enclose interconnects formed on the package. This way, the protective tape provides support to the semiconductor package during package grinding involving the mold material as well as the die. In the post-grind package, the grinded die surface may be exposed and substantially flush with the mold material. The protective tape may then be removed to prepare the post-grind package for connection with an external device or PCB. | 2009-09-17 |
| 20090230568 | Adhesive Film for Semiconductor and Semiconductor Device Therewith - There is provided an adhesive film for a semiconductor, comprising a thermoplastic resin (A), an epoxy resin (B) and a curing agent (C), wherein a minimum melt viscosity of said adhesive film for a semiconductor is 0.1 Pa·s to 500 Pa·s both inclusive in a temperature range of 50° C. to 180° C. both inclusive at a temperature-rise rate of 10° C./min from room temperature and a content of volatile component is 5.0% or less. | 2009-09-17 |
| 20090230569 | DEVICE COMPRISING A SEMICONDUCTOR CMPONENT, AND A MANUFACTURING METHOD - A device having at least one semiconductor component, which is covered by a protective material on its outer surface. The invention provides for the outer surface to be provided with a surface structure so as to enlarge the heat transfer area to the protective material. The invention furthermore relates to a manufacturing method. | 2009-09-17 |
| 20090230570 | RESIN COMPOSITION AND SEMICONDUCTOR DEVICE EMPOLYING THE SAME - The present invention provides a resin composition for sealing a semiconductor device. The resin composition is in liquid state at room temperature, and can be supplied from a dispenser. The composition is advantageous in regard to molding time, viscosity, moldability and adhesion. This resin composition indispensably comprises a bisphenol type epoxy resin having a polymerization degree of 3 or less, a particular phenol resin or a particular acid anhydride, a catalyst (A) such as 1-cyanoethyl-2-undecylimidazolium trimellitate, a catalyst (B) such as 1-cyanoethyl-2-ethyl-4-methylimidazol, and spherical fused silica particles. The weight ratio (A/B) between the catalysts (A) and (B) is in the range of 9/1 to 4/6. | 2009-09-17 |
| 20090230571 | MASKING OF REPEATED OVERLAY AND ALIGNMENT MARKS TO ALLOW REUSE OF PHOTOMASKS IN A VERTICAL STRUCTURE - A monolithic three dimensional semiconductor device structure includes a first layer including a first occurrence of a first reference mark at a first location, and a second layer including a second occurrence of the first reference mark at a second location, wherein the second location is substantially directly above the first location. The device structure also includes an intermediate layer between the first layer and the second layer, the intermediate layer including a blocking structure, wherein the blocking structure is vertically interposed between the first occurrence of the first reference mark and the second occurrence of the first reference mark. Other aspects are also described. | 2009-09-17 |
| 20090230572 | DRUM HUMIDIFIER WITH PIVOTING FLOOR - A drum humidifier is designed for use with a forced air furnace and includes a housing including a base, a first side wall, a second side wall and a top. A removable water pan is positioned to be supported by the base. Water is maintained in the water pan by a watering means, the watering means comprising a float. A movable water pan floor, the water pan floor having an operating position and a maintenance position. The water pan floor is substantially coplanar with the base and is positioned under at least a portion of the water pan in the operating position. The water pan floor is moved to a maintenance position to allow removal of the water pan around a float while the water pan remains in a substantially horizontal position. | 2009-09-17 |
| 20090230573 | Gas Dissolving Apparatus - A dissolving apparatus has a cylindrical tubular container closed at both ends with its center axis being inclined to the horizon. A center of an interface between a gas and a liquid in the container is positioned at a center in a lengthwise direction of a side wall of the container. Two inner spaces of the container above and below the interface are referred to as a gas section and a liquid section. An injection inlet for injecting a gas-liquid mixed fluid into the container is provided at a level corresponding to, or lower than, the interface. A liquid outlet for discharging the liquid is provided near a bottom of the liquid section of the container. Since the container is inclined, the interface can have an area large enough to promote dissolution of the gas into the liquid. Since the depth of the liquid in the liquid section is sufficiently deep, the liquid can be prevented from being discharged through the liquid outlet with large gas bubbles being present therein. | 2009-09-17 |
| 20090230574 | HUMIDIFIER WITH LOUVERED AIR INTAKE - A humidification system includes a housing mountable into an air duct, that includes a base frame, a cover and at least one open end panel. The base frame is mountable to an opening in the air duct that is shaped and configured to align with the base frame. The cover attaches to the base frame with the open end panel between the base frame and cover. The air outlet is through the open end panel. An evaporative element is positioned between the air inlet and air outlet. Controlling humidity output provides moisture to the evaporative element when needed. | 2009-09-17 |
| 20090230575 | Method for cast molding contact lenses - The invention provide a method for cast-molding hydrogel contact lenses, especially silicone hydrogel contact lenses by using plastic molds of a poly(cycloalkylene-dialkylene terephthalate) copolymer. These plastic molds do not need to be degassed and stored in an oxygen-free atmosphere (e.g., N | 2009-09-17 |
| 20090230576 | Method for Manufacturing Optical Film - A method for manufacturing an optical film comprising the steps of: 1) casting a dope (a solution), prepared by dissolving thermoplastic resin film raw materials in a solvent, from a casting die onto an at least 1.8 m wide belt support, and 2) drying a cast web (a cast film) peeled from the belt support, wherein the belt support has a thickness (Te) at both right and left end portions, of 5-20% less than a thickness (T) of the remaining portion including the transverse center portion of the belt support, provided that the Te indicates a thickness at both right and left end portions, each having a width (We) of 2-25% of a total width (W) of the belt support when viewed from both right and left side edges thereof. | 2009-09-17 |
| 20090230577 | METHOD OF PRODUCING INDENTED SHEET - The present invention provides a sheet-shaped object on which surface a regular, fine indented pattern is formed, without a decrease in accuracy of the formed pattern structure or defects caused by peeling faults. The present invention also provides a method of producing an indented sheet on which indents on an indented roller surface are transferred onto a surface of a sheet-shaped object. In order to solve the problems above, the method comprises the steps of: continuously running a band-shaped flexible sheet-shaped object; coating a radiation curable resin solution on a surface of the continuously running sheet-shaped object to form a coated layer; transferring indents on the indented roller surface onto the coated layer with the continuously running sheet-shaped object being wound onto the rotating indented roller; curing the coated layer by irradiating radiation with the continuously running sheet-shaped object being wound onto the indented roller; and peeling the continuously running sheet-shaped object from the indented roller, wherein the transferring step, curing step, and peeling step are carried out inside a casing, and temperature and humidity in the casing are each controlled to be within a certain variation range with respect to a target value. | 2009-09-17 |
