37th week of 2021 patent applcation highlights part 58 |
Patent application number | Title | Published |
20210288015 | DISPLAY DEVICE - A display device includes a display panel including a first signal pad and a second signal pad, a circuit board overlapped with the first and second signal pads, and an adhesive film overlapped with the first and second signal pads and disposed between the circuit board and the display panel. The adhesive film includes a base resin and a plurality of conductive balls dispersed in the base resin. The circuit board includes a first driving pad and a second driving pad. The first and second driving pads protrude toward the adhesive film and are arranged in a first direction. The first and second driving pads overlap with the first and second signal pads, respectively. The display device may be configured to satisfy the inequality: | 2021-09-16 |
20210288016 | WIRING STRUCTURE AND SEMICONDUCTOR MODULE - A lead frame structure for connecting a semiconductor chip to a connection target includes a conductive member electrically connecting the semiconductor chip and the connection target. The conductive member includes a first bonding part having a main surface, disposed on one side of the conductive member and being bonded to the semiconductor chip, a second bonding part having a main surface, being disposed on another side of the conductive member that is spaced from the one side in one direction and being bonded to the connection target, and a joining part having a wall section intersecting the main surface of the first bonding part and the main surface of the second bonding part, the wall section joining a portion of the first bonding part to a portion of the second bonding part. | 2021-09-16 |
20210288017 | WIRING FABRICATION METHOD, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - According to one embodiment, a wiring fabrication method includes pressing a first template including a first recessed portion and a second recessed portion provided at a bottom of the first recessed portion against a first film to form a first pattern including a first raised portion, corresponding to the first recessed portion, and a second raised portion, corresponding to the second recessed portion. The second raised portion protrudes from the first raised portion once formed. After forming the first pattern, a first wiring, corresponding to the first raised portion, and a via, corresponding to the second raised portion, is formed using the first pattern. | 2021-09-16 |
20210288018 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first terminal, a second terminal, and a plurality of third terminals on a substrate. Memory chips are stacked on the substrate in an offset manner. Each memory chip has first pads, second pads, and third pads thereon. A first bonding wire is electrically connected to the first terminal and physically connected to a first pad of each memory chip. A second bonding wire is electrically connected to the second terminal and physically connected to a second pad of each memory chip. A third bonding wire electrically connects one third terminal to a third pad on each memory chip. A fourth bonding wire is connected to the first bonding wire at a first pad on a first memory chip of the stack and another first pad on the first memory chip. The fourth bonding wire straddles over the second bonding wire and the third bonding wire. | 2021-09-16 |
20210288019 | SEMICONDUCTOR DEVICE AND WIRE BONDING METHOD - A semiconductor device includes a semiconductor chip having an electrode pad, a terminal having a terminal pad, and a bonding wire. The bonding wire includes a first end portion, a first bonded portion bonded to the electrode pad, a loop portion extending between the semiconductor chip and the terminal, and a second bonded portion bonded to the terminal pad. The second bonded portion is a wedge bonded portion comprising a second end portion of the bonding wire opposite to the first end portion. A length of the first bonded portion in the first direction is greater than a length of the second bonded portion in the first direction. | 2021-09-16 |
20210288020 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor chip including an output electrode portion on a front surface thereof, the output electrode portion including a plurality of electrode regions, each of which is provided at a respective position of the output electrode portion, and a plurality of wires, each electrode region being connected to a different one or more wires among the plurality of wires, through which a respective amount of output current is output. A total number of the different one or more wires connected to each electrode region is set depending on the respective position of the electrode region of the output electrode portion, so that the electrode region has a respective current amount per wire that is equal to or less than a respective predetermined value. | 2021-09-16 |
20210288021 | THERMAL COMPRESSION BONDER NOZZLE WITH VACUUM RELIEF FEATURES - An apparatus comprising a bonding nozzle that has one or more channels in a bonding surface. The one or more channels comprise a first channel portion in an inner region of the bonding surface and a second channel portion along an outer periphery of the bonding surface. The one or more channels are in fluid communication with a vacuum port. A vacuum relief conduit within the bonding nozzle comprises a first opening into the second channel portion along the outer periphery of the bonding surface, and a second opening along an exterior wall of the bonding nozzle. | 2021-09-16 |
20210288022 | Silicon Interposer Sandwich Structure for ESD, EMC, and EMC Shielding and Protection - An interposer sandwich structure includes a top interposer and a bottom interposer enclosing an integrated circuit electronic device that includes an attachment for attaching the device to the bottom interposer, and an interconnection structure connecting the top interposer to the bottom interposer. The top interposer may also be directly connected to a chip carrier in addition to the bottom interposer. The structure provides shielding and protection of the device against Electrostatic Discharge (ESD), Electromagnetic Interference (EMI), and Electromagnetic Conductivity (EMC) in miniaturized 3D packaging. | 2021-09-16 |
20210288023 | SEMICONDUCTOR DEVICE, ENDOSCOPE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - An image pickup apparatus includes: an image pickup member having a first surface and a second surface, an external electrode being disposed on the second surface; a terminal where a core wire terminal is disposed on a first upper surface and a core wire electrode is disposed on a lower surface; a wiring layer including an insulation layer and a wiring, the wiring being in contact with the external electrode and the core wire electrode, a third surface being in contact with the second surface and the lower surface; a resin layer disposed on the third surface, an outer dimension of the resin layer being equal to an outer dimension of the wiring layer, the resin layer fixing the image pickup member and the terminal; and an electric cable including a core wire bonded to the core wire terminal. | 2021-09-16 |
20210288024 | SEMICONDUCTOR DEVICE PACKAGES AND METHODS OF MANUFACTURING THE SAME - A semiconductor device package includes a first conductive layer, a second conductive layer and a third conductive layer. The first conductive layer has a first pitch. The second conductive layer has a second pitch and is arranged at two different sides of the first conductive layer. The third conductive layer has a third pitch and is disposed above the first conductive layer and the second conductive layer. The third conductive layer is electrically connected to the first conductive layer. The first pitch is smaller than the third pitch, and the third pitch is smaller than the second pitch. | 2021-09-16 |
20210288025 | HIGH BANDWIDTH MODULE - A module includes a substrate having a plurality of contact regions, and a spacer-chip assembly. The spacer-chip assembly in turn includes at least first and second semiconductor dies, each having a plurality of electrical interconnect pillars and a plurality of contact pads, and a spacer wafer. The at least first and second semiconductor dies are secured to the spacer wafer, and the spacer wafer includes at least first and second semiconductor circuit features coupled to a first portion of the contact pads of the at least first and second semiconductor dies. The spacer wafer includes wiring electrically coupling the at least first and second semiconductor dies via a second portion of the contact pads. The spacer wafer has a plurality of holes formed therethrough. The plurality of electrical interconnect pillars extend through the holes and are secured to the contact regions on the substrate. | 2021-09-16 |
20210288026 | SEMICONDUCTOR PACKAGES - A semiconductor package includes a first chip, a first chip and a molding compound. The first chip has a first via protruding from the first chip. The second chip has a second via protruding from the second chip, wherein a thickness of the first chip is different from a thickness of the second chip. The molding compound encapsulates the first chip, the second chip, the first via and the second via, wherein surfaces of the first via, the second via and the molding compound are substantially coplanar. | 2021-09-16 |
20210288027 | HIGH CONNECTIVITY DEVICE STACKING - The present disclosure generally relates to stacked miniaturized electronic devices and methods of forming the same. More specifically, embodiments described herein relate to semiconductor device spacers and methods of forming the same. The semiconductor device spacers described herein may be utilized to form stacked semiconductor package assemblies, stacked PCB assemblies, and the like. | 2021-09-16 |
20210288028 | STACKED TYPE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE STACKED TYPE SEMICONDUCTOR DEVICE - There are provided a stacked type semiconductor device and a manufacturing method of the stacked type semiconductor device. The stacked type semiconductor device includes: semiconductor chips stacked to overlap with each other; through electrodes respectively protruding the semiconductor chips, the through electrodes being bonded to each other; and empty gaps respectively buried in the through electrodes. | 2021-09-16 |
20210288029 | HYBRID BOND PAD STRUCTURE - In some embodiments, the present disclosure relates to an integrated chip structure. The integrated chip structure includes a first plurality of interconnects arranged within a first inter-level dielectric (ILD) structure on a first substrate, and a second plurality of interconnects arranged within a second ILD structure between the first ILD structure and a second substrate. A bonding structure is disposed within a recess extending through the second substrate. A connector structure is vertically between the first plurality of interconnects and the second plurality of interconnects. The second plurality of interconnects include a first interconnect directly contacting the bonding structure. The second plurality of interconnects also include one or more extensions extending from directly below the first interconnect to laterally outside of the first interconnect and directly above the connector structure, as viewed along a cross-sectional view. | 2021-09-16 |
20210288030 | Integrated Circuit Package and Method - In an embodiment, a device includes: a bottom integrated circuit die having a first front side and a first back side; a top integrated circuit die having a second front side and a second back side, the second back side being bonded to the first front side, the top integrated circuit die being free from through substrate vias (TSVs); a dielectric layer surrounding the top integrated circuit die, the dielectric layer being disposed on the first front side, the dielectric layer and the bottom integrated circuit die being laterally coterminous; and a through via extending through the dielectric layer, the through via being electrically coupled to the bottom integrated circuit die, surfaces of the through via, the dielectric layer, and the top integrated circuit die being planar. | 2021-09-16 |
20210288031 | DEVICE FOR TRANSFER OF LIGHT EMITTING ELEMENTS, METHOD FOR TRANSFERRING LIGHT EMITTING ELEMENTS, AND METHOD OF MANUFACTURING THE TRANSFER DEVICE - A device for collecting and transferring light emitting elements of microscale size includes a non-magnetic plate, a plurality of magnetic probes, and a magnetic plate. The non-magnetic plate defines through holes. Each of the probes is fixed in one through holes. The magnetic plate is on a surface of the non-magnetic plate and closes one opening of each of the through holes. The magnetic plate generates a magnetic field, so that each of the probes magnetically attracts one light emitting element. A method for making the transfer device and a method for transferring light emitting elements using the transfer device are also disclosed. | 2021-09-16 |
20210288032 | INTEGRATING CONTROL CIRCUITS WITH LIGHT EMISSIVE CIRCUITS WITH DISSIMILAR WAFER SIZES - In some examples, an article comprises a semiconductor including at least one integrated circuit and an inorganic semiconductor layer bonded to a first surface of the semiconductor. The inorganic semiconductor layer comprises a μLED array, and the first surface of the semiconductor extends beyond a first edge of the inorganic semiconductor layer. The first edge of the inorganic semiconductor layer is oriented substantially perpendicular to the first surface of the semiconductor. | 2021-09-16 |
20210288033 | LIGHT EMITTING DEVICE AND DISPLAY DEVICE HAVING SAME - A light emitting device may include; a substrate including a plurality of unit light emitting regions; at least one first light emitting element having a first end portion and a second end portion in a first direction; at least one second light emitting element having a first end portion and a second end portion in a second direction intersecting the first direction; a first electrode connected to any one of the first and second end portions of each of the first and second light emitting elements and a second electrode connected to the other of the first and second end portions of each of the first and second light emitting elements; a first alignment line extending along the second direction on the substrate, the first alignment line being connected to the first electrode; and a second alignment line connected to the second electrode. | 2021-09-16 |
20210288034 | MULTI-DIE, VERTICAL-WIRE PACKAGE-IN-PACKAGE APPARATUS, AND METHODS OF MAKING SAME - A vertical-wire package-in-package includes at least two memory-die stacks that form respective memory modules that are stacked vertically on a bond-wire board. Each memory die in the memory-die stack includes a vertical bond wire that emerges from a matrix for connection. The matrix encloses the memory-die stack, the spacer, and a redistribution layer. At least two memory modules are assembled in a vertical-wire package-in-package. | 2021-09-16 |
20210288035 | ACTIVE BRIDGE ENABLED CO-PACKAGED PHOTONIC TRANSCEIVER - Embodiments may relate to a microelectronic package that includes a package substrate with an active bridge positioned therein. An active die may be coupled with the package substrate, and communicatively coupled with the active bridge. A photonic integrated circuit (PIC) may also be coupled with the package substrate and communicatively coupled with the active bridge. Other embodiments may be described or claimed. | 2021-09-16 |
20210288036 | INTEGRATING CONTROL CIRCUITS WITH LIGHT EMISSIVE CIRCUITS WITH DISSIMILAR WAFER SIZES - In some examples, an article comprises a semiconductor including at least one integrated circuit, a μLED array on a first surface of the semiconductor, and a fill material disposed on a first edge of the semiconductor. The first edge of the μLED array or the semiconductor is oriented substantially perpendicular to the first surface of the semiconductor. | 2021-09-16 |
20210288037 | DIRECT-BONDED LED ARRAYS AND APPLICATIONS - Direct-bonded LED arrays and applications are provided. An example process fabricates a LED structure that includes coplanar electrical contacts for p-type and n-type semiconductors of the LED structure on a flat bonding interface surface of the LED structure. The coplanar electrical contacts of the flat bonding interface surface are direct-bonded to electrical contacts of a driver circuit for the LED structure. In a wafer-level process, micro-LED structures are fabricated on a first wafer, including coplanar electrical contacts for p-type and n-type semiconductors of the LED structures on the flat bonding interface surfaces of the wafer. At least the coplanar electrical contacts of the flat bonding interface are direct-bonded to electrical contacts of CMOS driver circuits on a second wafer. The process provides a transparent and flexible micro-LED array display, with each micro-LED structure having an illumination area approximately the size of a pixel or a smallest controllable element of an image represented on a high-resolution video display. | 2021-09-16 |
20210288038 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a first chip and a second chip. The first chip includes a semiconductor substrate and a plurality of transistors disposed on a surface of the semiconductor substrate. The second chip includes a plurality of first conductive layers, a plurality of first semiconductor layers, and a plurality of memory cells disposed in intersection portions of the plurality of first conductive layers and the plurality of first semiconductor layers. The second chip includes a second semiconductor layer farther from the semiconductor substrate than the plurality of first conductive layers and connected to the plurality of first semiconductor layers and a first insulating layer that includes a part farther from the semiconductor substrate than a surface on aside opposite to the semiconductor substrate of the second semiconductor layer and a part closer to the semiconductor substrate than the surface. | 2021-09-16 |
20210288039 | RF CIRCUIT MODULE AND MANUFACTURING METHOD THEREFOR - An RF circuit module includes a module substrate, a first substrate in which a first circuit is implemented, and a second substrate in which a second circuit is implemented. The first circuit includes a control circuit that controls an operation of the second circuit. The second circuit includes a radio-frequency amplifier circuit that amplifies an RF signal. The second substrate is mounted on the first substrate. The first substrate is disposed on the module substrate such that a circuit forming surface faces the module substrate. The first substrate and the second substrate have a circuit-to-circuit connection wire that electrically connects the first circuit and the second circuit without intervening the module substrate. | 2021-09-16 |
20210288040 | Die Stacking Structure and Method Forming Same - A method includes bonding a first device die to a second device die, encapsulating the first device die in a first encapsulant, performing a backside grinding process on the second device die to reveal through-vias in the second device die, and forming first electrical connectors on the second device die to form a package. The package includes the first device die and the second device die. The method further includes encapsulating the first package in a second encapsulant, and forming an interconnect structure overlapping the first package and the second encapsulant. The interconnect structure comprises second electrical connectors. | 2021-09-16 |
20210288041 | BACK-TO-BACK SOLID STATE LIGHTING DEVICES AND ASSOCIATED METHODS - Solid state lights (SSLs) including a back-to-back solid state emitters (SSEs) and associated methods are disclosed herein. In various embodiments, an SSL can include a carrier substrate having a first surface and a second surface different from the first surface. First and second through substrate interconnects (TSIs) can extend from the first surface of the carrier substrate to the second surface. The SSL can further include a first and a second SSE, each having a front side and a back side opposite the front side. The back side of the first SSE faces the first surface of the carrier substrate and the first SSE is electrically coupled to the first and second TSIs. The back side of the second SSE faces the second surface of the carrier substrate and the second SSE is electrically coupled to the first and second TSIs. | 2021-09-16 |
20210288042 | INTEGRATED CIRCUITS AND METHODS OF FORMING INTEGRATED CIRCUITS - According to various embodiments, an integrated circuit may include an upper inter-level dielectric (ILD) layer, a lower ILD layer, and an interlayer arranged between the upper ILD layer and the lower ILD layer. The integrated circuit may further include a capacitor device and a resistor device. The capacitor device may include a top plate disposed in a first region of the interlayer and a bottom plate disposed in the lower ILD layer. The resistor device may include a resistive element and a plurality of vias disposed in a second region of the interlayer. The plurality of vias may extend from the resistive element to the lower ILD layer. A distance between the top plate and the lower ILD layer may be at least substantially equal to a height of each via of the plurality of vias. | 2021-09-16 |
20210288043 | SEMICONDUCTOR DEVICE - A method, includes: in a strap cell disposed between a memory cell and a logic cell, arranging a first gate across an active region; arranging a second gate next to and in parallel with the first gate and at an end of the active region; and when at least one conductive segment has a first length, arranging the at least one conductive segment across the first gate, the second gate, and no dummy gate in the strap cell. A semiconductor device is also disclosed herein. | 2021-09-16 |
20210288044 | FLOATING BASE SILICON CONTROLLED RECTIFIER - A floating base silicon controlled rectifier is provided, which at least comprises a first conductivity type layer; a second conductivity type well formed in the first conductivity type layer; a first conductivity type heavily doped region coupled to a first node and formed in the second conductivity type well; and a second conductivity type heavily doped region coupled to a second node and formed in the first conductivity type layer. The first conductivity type and the second conductivity type are opposite. When the first conductivity type is N type, the second conductivity type is P type. Alternatively, when the first conductivity type is P type, the second conductivity type is N type. By employing the proposed present invention, the floating base silicon controlled rectifier acts as a forward diode, and an input capacitance can be greatly reduced. | 2021-09-16 |
20210288045 | Systems and Methods for Protecting a Semiconductor Device - Circuits and methods for protecting a device are provided. A first device to be protected includes a gate dielectric of a first thickness. A second device includes a gate dielectric of a second thickness that is less than the first thickness. A gate is shared by the first device and the second device. | 2021-09-16 |
20210288046 | ON-CHIP DECOUPLING CAPACITOR - A semiconductor device including a decoupling capacitor disposed between adjacent device source-drain regions, the decoupling capacitor comprising an outer metal liner, a dielectric disposed adjacent to the outer metal liner, and an inner metal liner disposed adjacent to the dielectric, a single diffusion break isolation region disposed between the adjacent device source-drain regions. The outer metal liner is disposed in electrical contact with the adjacent device source-drain regions. | 2021-09-16 |
20210288047 | TRENCH CAPACITOR WITH LATERAL PROTRUSION STRUCUTRE - Various embodiments of the present application are directed towards a semiconductor device comprising a trench capacitor, the trench capacitor comprising a plurality of lateral protrusions. In some embodiments, the trench capacitor comprises a dielectric structure over a substrate. The dielectric structure may comprise a plurality of dielectric layers overlying the substrate. The dielectric structure may comprise a plurality of lateral recesses. In some embodiments, the plurality of lateral protrusions extend toward and fill the plurality of lateral recesses. By forming the trench capacitor with the plurality of lateral protrusions filling the plurality of lateral recesses, the surface area of the capacitor is increased without increasing the depth of the trench. As a result, greater capacitance values may be achieved without necessarily increasing the depth of the trench and thus, without necessarily increasing the size of the semiconductor device. | 2021-09-16 |
20210288048 | METHOD TO EMBED PLANAR FETS WITH FINFETS - Various embodiments of the present disclosure are directed towards a method to embed planar field-effect transistor (FETs) with fin field-effect transistors (finFETs). A semiconductor substrate is patterned to define a mesa and a fin. A trench isolation structure is formed overlying the semiconductor substrate and surrounding the mesa and the fin. A first gate dielectric layer is formed on the mesa, but not the fin. The trench isolation structure recessed around the fin, but not the mesa, after the forming the first gate dielectric layer. A second gate dielectric layer is deposited overlying the first gate dielectric layer at the mesa and further overlying the fin. A first gate electrode is formed overlying the first and second gate dielectric layers at the mesa and partially defining a planar FET. A second gate electrode is formed overlying the second gate dielectric layer at the fin and partially defining a finFET. | 2021-09-16 |
20210288049 | TECHNIQUES AND MECHANISMS FOR OPERATION OF STACKED TRANSISTORS - Techniques and mechanisms for operating transistors that are in a stacked configuration. In an embodiment, an integrated circuit (IC) device includes transistors arranged along a line of direction which is orthogonal to a surface of a semiconductor substrate. A first epitaxial structure and a second epitaxial structure are coupled, respectively, to a first channel structure of a first transistor and a second channel structure of a second transistor. The first epitaxial structure and the second epitaxial structure are at different respective levels relative to the surface of the semiconductor substrate. A dielectric material is disposed between the first epitaxial structure and the second epitaxial structure to facilitate electrical insulation of the channels from each other. In another embodiment, the stacked transistors are coupled to provide a complementary metal-oxide-semiconductor (CMOS) inverter circuit. | 2021-09-16 |
20210288050 | THIN FILM TRANSISTORS AND RELATED FABRICATION TECHNIQUES - Methods and apparatuses for thin film transistors and related fabrication techniques are described. The thin film transistors may access two or more decks of memory cells disposed in a cross-point architecture. The fabrication techniques may use one or more patterns of vias formed at a top layer of a composite stack, which may facilitate building the thin film transistors within the composite stack while using a reduced number of processing steps. Different configurations of the thin film transistors may be built using the fabrication techniques by utilizing different groups of the vias. Further, circuits and components of a memory device (e.g., decoder circuitry, interconnects between aspects of one or more memory arrays) may be constructed using the thin film transistors as described herein along with related via-based fabrication techniques. | 2021-09-16 |
20210288051 | MEMORY DEVICE COMPRISING ELECTRICALLY FLOATING BODY TRANSISTOR - A semiconductor memory cell comprising an electrically floating body. A method of operating the memory cell is provided. | 2021-09-16 |
20210288052 | METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE AND THE SAME - The present application discloses a method for fabricating a semiconductor device with a pad structure. The method includes providing a substrate, forming a capacitor structure above the substrate, forming a plurality of passivation layers above the capacitor structure, forming a pad opening in the plurality of passivation layers, performing a passivation process comprising soaking the pad opening in a precursor, and forming a pad structure in the pad opening. The precursor is dimethylaminotrimethylsilane or tetramethylsilane. Forming the pad structure in the pad opening comprises forming a pad bottom conductive layer comprising nickel in the pad opening and forming a pad top conductive layer on the pad bottom conductive layer. The pad top conductive layer comprises palladium, cobalt, or a combination thereof. | 2021-09-16 |
20210288053 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes an active region in a substrate, an isolation film defining the active region in the substrate, a gate trench extending across the active region and the isolation film and including a first trench in the active region and a second trench in the isolation film, a gate electrode including a main gate electrode and a pass gate electrode, the main gate electrode filling a lower part of the first trench, and the pass gate electrode filling a lower part of the second trench, a support structure on the pass gate electrode, the support structure filling an upper part of the second trench, a gate insulating film interposed between the isolation film and the pass gate electrode and between the support structure and the pass gate electrode. | 2021-09-16 |
20210288054 | SEMICONDUCTOR DEVICE HAVING SELECTION LINE STUD CONNECTED TO STRING SELECTION LINE - A semiconductor device includes; a memory stack disposed on a substrate and including a lower gate electrode, an upper gate stack including a string selection line, a vertically extending memory gate contact disposed on the lower gate electrode, and a vertically extending selection line stud disposed on the string selection line. The string selection line includes a material different from that of the lower gate electrode, and the selection line stud includes a material different from that of the memory gate contact. | 2021-09-16 |
20210288055 | Antifuse OTP structures with hybrid low-voltage devices - An antifuse One-Time-Programmable memory cell includes a substrate, and a hybrid select transistor and a hybrid antifuse capacitor formed on the substrate. The hybrid select transistor includes a first gate dielectric layer formed on the substrate, wherein the first gate dielectric layer is thinner than 40 nm, a first high-voltage junction formed in the substrate, and a low-voltage junction formed in the substrate. The hybrid antifuse capacitor includes a second gate dielectric layer, wherein the second gate dielectric layer is thinner than 40 nm, which enables a low-voltage antifuse capacitor device, a second gate formed on the gate dielectric layer, a second high-voltage junction formed in the substrate, and a third high-voltage junction formed in the substrate. | 2021-09-16 |
20210288056 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device according to one embodiment includes a semiconductor substrate, first transistors including a first diffusion layer provided on a surface of the semiconductor substrate and including impurities and carbon, and first contact plugs provided on the first diffusion layer. The first diffusion layer includes a first region being in contact with the first contact plugs and a second region covering the first region. A concentration of the carbon is higher than that of the impurities in the first region as a depth from the surface is larger. | 2021-09-16 |
20210288057 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device according to an embodiment, includes a plurality of semiconductor pillars extending in a first direction and being arranged along a second direction crossing the first direction, two interconnects extending in the second direction and being provided on two sides of the plurality of semiconductor pillars in a third direction crossing the first direction and the second direction, and an electrode film disposed between each of the semiconductor pillars and each of the interconnects. The two interconnects are drivable independently from each other. | 2021-09-16 |
20210288058 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device according to an embodiment includes a substrate, first members, first conductive layers, and first and second pillars. The substrate includes first and second areas, and block areas. The first conductive layers are split by the first members. The first pillars are provided in an area in which the first area and the block areas overlap. The second pillars are provided in an area in which the second area and the block areas overlap. The second area includes a first sub-area in which the second pillars are periodically arranged in an area that overlaps at least one block area in the block areas. In the first sub-area, at least one second pillar is omitted from the second pillars that are periodically arranged. | 2021-09-16 |
20210288059 | EMBEDDED MEMORY USING SOI STRUCTURES AND METHODS - An integrated circuit (IC) includes a semiconductor-on-insulator (SOI) substrate comprising a handle substrate, an insulator layer over the handle substrate, and a semiconductor device layer over the insulator layer. A logic device includes a logic gate arranged over the semiconductor device layer. The logic gate is arranged within a high κ dielectric layer. A memory cell includes a control gate and a select gate laterally adjacent to one another and arranged over the semiconductor device layer. A charge-trapping layer underlies the control gate. | 2021-09-16 |
20210288060 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a first conductive layer, and a first structure that extends in a first direction orthogonal to a stacking direction of a stacked body and the stacking direction, and reaches a position deeper than an upper surface of the first conductive layer. The first structure has a first width at a bottom of the stacked body, and a second width narrower than the first width, in a first depth region from a position of the upper surface of the first conductive layer to a first depth position. A third conductive layer is connected to a side surface of the first conductive layer in the first depth region in a second direction orthogonal to the stacking direction and the first direction. | 2021-09-16 |
20210288061 | SEMICONDUCTOR STORAGE DEVICE - According to one embodiment, a semiconductor storage device includes a stacked body that includes a plurality of first conductive layers stacked with a first insulating layer interposed therebetween and has a stair portion and a memory portion; and a first structure that extends in the stacked body in a predetermined direction and divides the stacked body, the first structure including a projection extending in the stacking direction across the plurality of first conductive layers, on a side surface thereof in the stair portion wherein the first structure includes: a second insulating layer that is provided in the projection; and a third insulating layer that covers end surfaces of the plurality of first conductive layers and the first insulating layer facing toward the first structure and continuously extends in the first structure over the memory portion and the stair portion. | 2021-09-16 |
20210288062 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises: a semiconductor substrate comprising a first and a second surface; a first and a second electrode provided on a first surface side; a third and a fourth electrode provided on a second surface side; a first through-electrode connected to the first and the third electrode; a second through-electrode connected to the second and the fourth electrode; and a first insulating layer comprising a first and a second portion. The semiconductor substrate comprises: a first impurity region of N type facing a surface of the first through-electrode via the first portion; a second impurity region of N type facing a surface of the second through-electrode via the second portion; and a third impurity region of P type provided between the first and the second impurity region. | 2021-09-16 |
20210288063 | MEMORY DEVICE AND METHOD FOR FORMING THE SAME - A method for fabricating a memory device includes providing an initial semiconductor structure, including a base substrate, a stack structure of interlayer dielectric layers and first sacrificial layers; a channel trench formed through the stack structure. The method includes removing a portion of each first sacrificial layer from the channel trench to form a trapping-layer trench; forming a second sacrificial layer in the trapping-layer trench; forming a charge trapping film to fill the trapping-layer trench; and removing a portion of the charge trapping film from the channel trench to form a charge trapping layer; forming a tunneling layer and a channel layer on the sidewalls of the channel trench; removing the first sacrificial layers and the second sacrificial layer; forming a blocking layer on the charge trapping layer; and forming gate structures, in contact with the tunneling layer, between adjacent interlayer dielectric layers. | 2021-09-16 |
20210288064 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a substrate, insulating members, first conductive layers, first pillars, and second pillars. The substrate includes a first area, a second area, block regions, and a first dummy block region. The insulating members are arranged at respective boundary portions of the block regions and the first dummy block region. The first conductive layers are partitioned by the insulating members. The first pillars penetrates the first conductive layers in a region where the first area and the block regions overlap. The second pillars penetrates at least one of the first conductive layers in a region where the first area and the first dummy block region overlap. | 2021-09-16 |
20210288065 | SEMICONDUCTOR STORAGE DEVICE AND SEMICONDUCTOR STORAGE DEVICE MANUFACTURING METHOD - A semiconductor storage device of an embodiment includes: a stacked body in which each of a plurality of first conductive layers and each of a plurality of first insulating layers are alternately stacked; a pillar extending in the stacked body in a stacking direction of the stacked body; a plurality of memory cells individually formed at intersections of the plurality of first conductive layers and the pillar; a lower layer structure arranged below the stacked body; a lower receiver that opens on an upper surface of the lower layer structure, the lower receiver having a metal layer filled in a groove extending in a first direction along a surface direction of the upper surface of the lower layer structure; and a strip extending in the first direction and extending in the stacking direction in the stacked body, having a lower end of the strip being arranged in the lower receiver. | 2021-09-16 |
20210288066 | THREE-DIMENSIONAL MEMORY DEVICES HAVING TWO-DIMENSIONAL MATERIALS - Methods and structures of a three-dimensional memory device are disclosed. A 3D NAND memory structure includes a substrate and a vertical insulating layer. The 3D NAND memory structure also includes a channel layer surrounding the vertical insulating layer. The channel layer is formed of a two-dimensional material. The 3D NAND memory structure further includes a plurality of vertical dielectric layers surrounding the channel layer and an alternating conductor/dielectric stack in contact with the plurality of vertical dielectric layers. | 2021-09-16 |
20210288067 | 3D SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING SAME - A semiconductor memory device includes; a lower stacked structure including lower metallic lines stacked in a first direction on a substrate, an upper stacked structure including a first upper metallic line and a second upper metallic line sequentially stacked on the lower stacked structure, a vertical structure penetrating the upper stacked structure and lower stacked structure and including a channel film, a connection pad disposed on the vertical structure, contacted with the channel film and doped with N-type impurities, a first cutting line cutting the lower metallic lines, the first upper metallic line and the second upper metallic line, a second cutting line spaced apart from the first cutting line in a second direction different from the first direction, and cutting the lower metallic lines, the first upper metallic line and the second upper metallic line, and sub-cutting lines cutting the first upper metallic line and the second upper metallic line between the first cutting line and the second cutting line. The channel film includes an undoped channel region and a doping channel region, and the doping channel region contacts the connection pad and overlaps a part of the second upper metallic line in the second direction. | 2021-09-16 |
20210288068 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor memory device and a method for fabricating a semiconductor memory device, the device including a peripheral logic structure on a substrate; a horizontal conductive substrate on the peripheral logic structure; a stacked structure including a plurality of electrode pads stacked in a vertical direction; a plate contact plug connected to the horizontal conductive substrate; and a first penetration electrode connected to the lower connection wiring body, wherein upper surfaces of the plate contact plug and the first penetration electrode are on a same plane, the plate contact plug includes an upper part and a lower part directly connected to each other, the first penetration electrode includes an upper part and a lower part directly connected to each other, moving away from upper surfaces of the first penetration electrode and the plate contact plug, widths of the upper parts increase and widths of the lower parts decrease. | 2021-09-16 |
20210288069 | THREE-DIMENSIONAL STRUCTURES FOR MICROELECTRONIC WORKPIECES - In certain embodiments, a 3D structure for a microelectronic workpiece includes a multilayer stack that includes polysilicon layers separated by other layers, holes formed within the multilayer stack, recesses formed within the polysilicon layers at edges of the holes, conductive material deposited within the recesses to form outer layers within the holes, and plugs formed adjacent the outer layers within the holes. | 2021-09-16 |
20210288070 | 3-DIMENSIONAL NAND FLASH MEMORY DEVICE, METHOD OF FABRICATING THE SAME, AND METHOD OF DRIVING THE SAME - A 3-dimensional flash memory device and methods of fabricating and driving the same are provided. The device includes: a channel layer extending over a substrate in a first direction perpendicular to a surface of the substrate; an information storing layer extending along a sidewall of the channel layer in the first direction; control gates each surrounding, the channel layer, with the information storing layer between the channel layer and the control gates; an insulating layer being between the control gates in the first direction and separating the control gates from each other; a fixed charge region disposed at an interface of the insulating layer and the information storing layer or in a portion of the information storing layer between the control gates in the first direction; and a doped region induced by the fixed charge region and disposed at a surface of the channel layer facing the fixed charge region. | 2021-09-16 |
20210288071 | BLOCK-ON-BLOCK MEMORY ARRAY ARCHITECTURE USING BI-DIRECTIONAL STAIRCASES - A memory device stores data in non-volatile memory. The memory device includes a non-volatile memory array. The memory array includes tiers for accessing data stored in blocks of the memory array, including a block having a left block portion and a right block portion. A first staircase is positioned between the left block portion and the right block portion, and a bottom portion of the first staircase includes steps corresponding to first tiers of the left block portion. A second staircase is positioned between the left block portion and the right block portion, and a top portion of the second staircase includes steps corresponding to second tiers of the right block portion. The steps of the first staircase and the steps of the second staircase descend in opposite directions. | 2021-09-16 |
20210288072 | SEMICONDUCTOR DEVICE INCLUDING MULTI-STACK STRUCTURE - A semiconductor device includes a substrate having a cell region and a connection region adjacent to the cell region. A lower stack structure and an upper stack structure are disposed on the substrate. A channel structure is provided to pass through the upper stack structure and the lower stack structure. A distance between a lower extension line portion included in an uppermost one of a plurality of lower interconnection layers and an upper extension line portion included in a lowermost one of a plurality of upper interconnection layers is less than a distance between a lower gate electrode portion included in the uppermost one of the plurality of lower interconnection layers and an upper gate electrode portion included in the lowermost one of the plurality of upper interconnection layers. | 2021-09-16 |
20210288073 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor memory device includes a connecting member including a semiconductor material, a first electrode film, a first insulating film, a stacked body and three or more semiconductor pillars. The stacked body includes second electrode films and second insulating films that alternately stacked. The semiconductor pillars are arrayed along two or more directions, extend in a stacking direction, pierce through the stacked body and the first insulating film, and are connected to the connecting member. The device includes a third insulating film provided between the semiconductor pillars and the stacked body and between the connecting member and the first electrode film. A charge storage layer is provided at least between one of the second electrode films and the third insulating film. | 2021-09-16 |
20210288074 | SEMICONDUCTOR MEMORY - A semiconductor memory according to an embodiment includes a first conductor, a first insulator and memory pillars. The first conductor and the first insulator are alternately stacked along a first direction. The memory pillars penetrates through the stacked first conductor and first insulator. Each of the memory pillars include a semiconductor, a tunnel insulating film, a second insulator, and a block insulating film. The memory pillars include a first memory pillar. The stacked first insulator includes a first layer and a second layer that are adjacent to each other in the first direction. The first conductor between the first layer and the second layer includes a first conductive part, a second conductive part, and a first dissimilar conductive part. | 2021-09-16 |
20210288075 | LIQUID CRYSTAL DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME - Provided is a method to manufacture a liquid crystal display device in which a contact hole for the electrical connection of the pixel electrode and one of the source and drain electrode of a transistor and a contact hole for the processing of a semiconductor layer are formed simultaneously. The method contributes to the reduction of a photography step. The transistor includes an oxide semiconductor layer where a channel formation region is formed. | 2021-09-16 |
20210288076 | FINFET DEVICE AND A METHOD FOR FABRICATING THE SAME - A finFET device that includes a substrate and at least one semiconductor fin extending from the substrate. The fin may include a plurality of wide portions comprising a first semiconductor material and one or more narrow portions. The one or more narrow portions have a second width less than the first width of the wide portions. Each of the one or more narrow portions separates two of the plurality of wide portions from one another such that the plurality of wide portions and the one or more narrow portions are arranged alternatingly in a substantially vertical direction that is substantially perpendicular with a surface of the substrate. The fin may also include a channel layer covering sidewalls of the plurality of wide portions and a sidewall of the one or more narrow portions. | 2021-09-16 |
20210288077 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE - First to third insulators are successively formed in this order over a first conductor over a semiconductor substrate; a hard mask with a first opening is formed thereover; a resist mask with a second opening is formed thereover; a third opening is formed in the third insulator; a fourth opening is formed in the second insulator; the resist mask is removed; a fifth opening is formed in the first to third insulators; a second conductor is formed to cover an inner wall and a bottom surface of the fifth opening; a third conductor is formed thereover; polishing treatment is performed so that the hard mask is removed, and that levels of top surfaces of the second and third conductors and the third insulator are substantially equal to each other; and an oxide semiconductor is formed thereover. The second insulator is less permeable to hydrogen than the first and third insulators, the second conductor is less permeable to hydrogen than the third conductor. | 2021-09-16 |
20210288078 | DISPLAY DEVICE - The object of the present invention is to make it possible to form an LTPS TFT and an oxide semiconductor TFT on the same substrate. A display device includes a substrate having a display region in which pixels are formed. The pixel includes a first TFT using an oxide semiconductor | 2021-09-16 |
20210288079 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - An object of an embodiment of the present invention is to manufacture a semiconductor device with high display quality and high reliability, which includes a pixel portion and a driver circuit portion capable of high-speed operation over one substrate, using transistors having favorable electric characteristics and high reliability as switching elements. Two kinds of transistors, in each of which an oxide semiconductor layer including a crystalline region on one surface side is used as an active layer, are formed in a driver circuit portion and a pixel portion. Electric characteristics of the transistors can be selected by choosing the position of the gate electrode layer which determines the position of the channel. Thus, a semiconductor device including a driver circuit portion capable of high-speed operation and a pixel portion over one substrate can be manufactured. | 2021-09-16 |
20210288080 | DISPLAY PANEL AND METHOD OF FABRICATING SAME - A display panel and a method for fabricating the same are provided, the display panel including a substrate, a first insulating layer on the substrate, a source-drain layer on the first insulating layer, and a flexible layer pattern. The source-drain layer includes sources and drains. The flexible layer pattern includes at least one opening, the sources and the drains of the display panel are arranged in the openings, and the at least one opening corresponds to at least one of the sources and at least one of the drains. | 2021-09-16 |
20210288081 | DISPLAY PANEL AND DISPLAY DEVICE - A display panel and a display device are provided that relate to the field of display technology. The display panel includes a first signal line having a first and a second sub-portions; at least one insulating layer disposed on the first signal line; and a second signal line having a third and a fourth sub-portions disposed on the insulating layer. The second sub-portion and the fourth sub-portion have an overlapping part therebetween, the first sub-portion and the third sub-portion do not overlap each other, the second sub-portion has a varying line width, and at least one edge of the second sub-portion is extended away from a straight line connecting two vertices of the edge so that a distance D between and the straight line and a first point of the edge extending farthest from the straight line is in the range of 0.05 μm to 0.8 μm. | 2021-09-16 |
20210288082 | ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREFOR, AND DISPLAY DEVICE - An array substrate, a manufacturing method thereof, and a display device are provided. The array substrate includes a base substrate and a thin film transistor on the base substrate; a light shielding layer is disposed between the thin film transistor and the base substrate, and the light shielding layer includes a light shielding metal layer and, a light reflection adjusting layer which are stacked on the base substrate, the light reflection adjusting layer covers the light shielding metal layer, and a reflectance of the light reflection adjusting layer is lower than a reflectance of the light shielding metal layer. | 2021-09-16 |
20210288083 | DISPLAY APPARATUS HAVING A SILICON NITRIDE BUFFER LAYER AND METHOD OF MANUFACTURING THE SAME - A display apparatus includes a substrate. A first buffer layer is disposed over the substrate. The first buffer layer includes silicon nitride and has an atomic percentage of hydrogen bonded to silicon of about 0.36 to about 1.01. A thin film transistor is disposed over the first buffer layer. The thin film transistor includes an active layer. A display element is electrically connected to the thin film transistor. | 2021-09-16 |
20210288084 | LAYER STACK FOR DISPLAY APPLICATIONS - Embodiments of the present disclosure generally relate to a layer stack including a high K dielectric layer formed over a first dielectric layer and a metal electrode. The high K dielectric layer has a K value of 20 or higher and may be formed as a part of a capacitor, a gate insulating layer, or any suitable insulating layer in electronic devices, such as display devices. The layer stack includes a second dielectric layer disposed on the first dielectric layer and the metal layer, and the high K dielectric layer containing zirconium dioxide or hafnium dioxide disposed on the second dielectric layer. The second dielectric layer provides a homogenous surface on which the high K dielectric layer is formed. The homogeneous surface enables the high K dielectric material to be deposited uniformly thereover, resulting in a uniform thickness profile. | 2021-09-16 |
20210288085 | PHOTODETECTOR AND MANUFACTURE METHOD THEREOF, TOUCH SUBSTRATE AND DISPLAY PANEL - A photodetector and a manufacture method thereof, a touch substrate and a display panel are provided. The photodetector includes: a substrate; a polysilicon layer on the substrate including a first doped region and a second doped region; a transparent conductive film covering the first doped region of the polysilicon layer; and a metal electrode on the second doped region of the polysilicon layer. The conductive film, the metal electrode and the polysilicon layer constitute a photosensitive device. | 2021-09-16 |
20210288086 | METHODS FOR REFLECTOR FILM GROWTH - Methods and apparatus for forming reflector films are described A liner is formed on a substrate surface followed by formation of the reflector layer so that there is no oxygen exposure between liner and reflector layer formation. In some embodiments, a high aspect ratio structure is filled with a reflector material by partially filling the structure with the reflector material while growth is inhibited at a top portion of the structure, reactivating the top portion of the substrate and then filling the structure with the reflector material. | 2021-09-16 |
20210288087 | MULTISPECTRAL IMAGING SENSOR PROVIDED WITH MEANS FOR LIMITING CROSSTALK - A hybrid multispectral imaging sensor, characterized in that it comprises a photosensitive backside-illumination detector (DET) that is made on a substrate ( | 2021-09-16 |
20210288088 | IMAGE SENSOR - An image sensor includes a detection region, a first transistor region, and a second transistor region. The detection region including a first demodulation node and a second demodulation node generates a hole current in a substrate, and captures photocharges that are generated by incident light and move by the hole current. The first pixel transistor region including a plurality of transistors is disposed at one side of the detection region, and processes photocharges captured by the first demodulation node. The second pixel transistor region including a plurality of transistors is disposed at other side of the detection region, and processes photocharges captured by the second demodulation node. | 2021-09-16 |
20210288089 | IMAGE CAPTURING DEVICE UNIT INCLUDING MULTILAYER SUBSTRATE, MULTILAYER SUBSTRATE, AND IMAGE CAPTURING APPARATUS - An image capturing device unit includes a multilayer substrate, an image capturing device mounted on one face of the multilayer substrate, and components mounted on the other face of the multilayer substrate. The multilayer substrate includes electrodes to electrically connect the image capturing device and the multilayer substrate, vias that electrically connect the electrodes and the components, first wiring electrically connected to the vias, second wiring on layers of the multilayer substrate, and a non-wired region that insulates the vias and the first wiring from the second wiring on each of the layers. The vias are located in the multilayer substrate so that, on a projection plane given when the multilayer substrate is viewed in a layering direction of the multilayer substrate, there is no area in which the non-wired region overlaps with a region where the image capturing device is arranged throughout the layers. | 2021-09-16 |
20210288090 | SOLID-STATE IMAGE SENSOR - A solid-state image sensor is provided. The solid-state image sensor includes a plurality of photoelectric conversion elements. The solid-state image sensor also includes a first color filter layer disposed above the photoelectric conversion elements and having a plurality of first color filter segments. The solid-state image sensor further includes a second color filter layer disposed adjacent to the first color filter layer and having a plurality of second color filter segments. The solid-state image sensor includes a first grid structure disposed between the first color filter layer and the second color filter layer. The first grid structure has a first grid height. The solid-state image sensor also includes a second grid structure disposed between the first color filter segments and between the second color filter segments. The second grid structure has a second grid height that is lower than or equal to the first grid height. | 2021-09-16 |
20210288091 | IMAGING ELEMENT, MANUFACTURING METHOD OF IMAGING ELEMENT, METAL THIN FILM FILTER, AND ELECTRONIC DEVICE - According to some aspects, an imaging device is provided comprising a photoelectric conversion layer configured to receive light and to produce an electric charge in response to the received light, including a first filter region corresponding to a first pixel of the imaging device, the first filter region having a first thickness and a plurality of through holes formed therein, wherein the first filter region transmits light incident on the first filter region with a first peak transmission wavelength, and a second filter region corresponding to a second pixel of the imaging device, the second filter region having a second thickness greater than the first thickness and having a plurality of through holes formed therein, wherein the second filter region transmits light incident on the second filter region with a second peak transmission wavelength that is greater than the first peak transmission wavelength. | 2021-09-16 |
20210288092 | IMAGING ELEMENT, STACKED IMAGING ELEMENT, AND SOLID-STATE IMAGING APPARATUS - An imaging element includes a photoelectric conversion unit including a first electrode | 2021-09-16 |
20210288093 | SEMICONDUCTOR DEVICE, MANUFACTURING METHOD FOR SAME, AND EQUIPMENT - A semiconductor device includes a semiconductor layer, a metal layer disposed above a surface of the semiconductor layer, a first barrier portion that covers a first portion of a surface of the metal layer, a second barrier portion that covers a second portion of the surface of the metal layer, an insulating film that covers the metal layer and the first and second barrier portions; and a metal member that is disposed in an opening portion provided in the insulating film, the metal member positioned on a third portion of the surface of the metal layer that is between the first portion and the second portion. A part of the insulating film is disposed between the metal member and the first barrier portion and between the metal member and the second barrier portion. | 2021-09-16 |
20210288094 | Solid-State Image Sensor with Pillar Surface Microstructure and Method of Fabricating the Same - A solid-state image sensor with pixels each including a photoelectric conversion portion made of a second type doped semiconductor layer and a semiconductor material layer, and the second type doped semiconductor layer contacts a first type doped semiconductor substrate. An anti-reflective portion is provided with multiple micro pillars on the semiconductor material layer, wherein micro pillars are isolated by recesses extending into the photoelectric conversion portion, and the refractive index of the micro pillar gradually decreases from bottom to top and is smaller than the refractive index of the light-receiving portion of the semiconductor material layer. | 2021-09-16 |
20210288095 | IMPROVED BI-SPECTRAL DETECTOR - An optical detector that is sensitive in at least two infrared wavelength ranges: first spectral band and second spectral band; and having a set of pixels, comprising: an absorbent structure disposed on a lower face of a substrate and comprising a stack of at least one absorbent layer made of semi-conductor material; the detector further comprising a plurality of dielectric resonators on the upper surface of said substrate forming an upper surface metasurface, the metasurface configured to diffuse, deflect and focus in the pixels of the detector in a resonant manner, when illuminated by the incident light, a first beam having at least one first wavelength included in the first spectral band and a second beam having at least one second wavelength included in the second band, the metasurface also being configured so that said first and second beams are focused on different pixels of the detector. | 2021-09-16 |
20210288096 | IMAGING APPARATUS AND IMAGE SENSOR INCLUDING THE SAME - An image sensor includes a substrate, thin lenses disposed on a first surface of the substrate and configured to concentrate lights incident on the first surface, and light-sensing cells disposed on a second surface of the substrate, the second surface facing the first surface, and the light-sensing cells being configured to sense lights passing through the thin lenses, and generate electrical signals based on the sensed lights. A first thin lens and second thin lens of the thin lenses are configured to concentrate a first light and a second light, respectively, of the incident lights onto the light-sensing cells, the first light having a different wavelength than the second light. | 2021-09-16 |
20210288097 | DUAL IMAGE SENSOR - Provided are a dual image sensor including an image sensor including a first area and a second area, the first area and the second area including a plurality of pixels, respectively, a band-pass filter layer provided on the first area, the band-pass filter layer configured to transmit light emitted by an object and having a specific wavelength corresponding to physical property information of the object to the image sensor, and a planarization layer provided on the second area and on the same plane as the band-pass filter layer. | 2021-09-16 |
20210288098 | SOLID-STATE IMAGING ELEMENT, METHOD FOR PRODUCING SOLID-STATE IMAGING ELEMENT, AND ELECTRONIC DEVICE - To reduce the probability of lowering an image quality in a solid-state imaging element such as a rear surface irradiation type CMOS image sensor. | 2021-09-16 |
20210288099 | IMAGING ELEMENT, LAMINATED IMAGING ELEMENT, AND SOLID-STATE IMAGING DEVICE - An imaging element includes a photoelectric conversion unit formed by laminating a first electrode, a photoelectric conversion layer, and a second electrode. An inorganic oxide semiconductor material layer is formed between the first electrode and the photoelectric conversion layer. The inorganic oxide semiconductor material layer contains a gallium (Ga) atom and a tin (Sn) atom, or a gallium (Ga) atom and an indium (In) atom. | 2021-09-16 |
20210288100 | LOW CAPACITANCE PHOTO DETECTORS - A system includes a pixel having a diffusion layer within a cap layer. The diffusion layer defines a front side and an illumination side opposite the front side with an absorption layer operatively connected to the illumination side as well as the diffusion and cap layers. A set of alternating oxide and nitride layers are deposited on the front side of the cap and diffusion layers. | 2021-09-16 |
20210288101 | FLAT PANEL DETECTOR AND MANUFACTURING METHOD THEREOF - A flat panel detector is provided, which includes a substrate and a plurality of photodiodes on the substrate. The flat panel detector further includes a first transparent conductive layer disposed on a side of the photodiodes away from the substrate. An orthographic projection of the first transparent conductive layer on the substrate at least partially overlaps the orthographic projection of each photodiode of the plurality of photodiodes on the substrate. The flat panel detector can mitigate or reduce the influence of external static electricity and improve the working stability. | 2021-09-16 |
20210288102 | BACK-SIDE ILLUMINATED IMAGE SENSOR - Image sensors and methods of manufacturing image sensors are provided herein. In an embodiment, a method of manufacturing an image sensor includes forming a structure having a front side and a back side. The structure includes a semiconductor layer extending between the front side and the back side of the structure, and a capacitive insulation wall extending through the semiconductor layer between the front side and the back side of the structure. The capacitive insulation wall includes first and second insulating walls separated by a region of a conductive or semiconductor material. The method further includes selectively etching, from the back side of the structure, portions of the semiconductor layer and the region of conductive or semiconductor material, while retaining adjacent portions of the first and second insulating walls. | 2021-09-16 |
20210288103 | LIGHT EMITTING DIODE UNIT - A light emitting diode unit including a blue light emitting diode package disposed on a substrate and configured to emit blue light to the outside, a red light emitting diode package disposed on the substrate and configured to emit red light to the outside, and a green light emitting diode package disposed on the substrate and configured to emit green light to the outside, in which each of the blue light emitting diode package, the red light emitting diode package, and the green light emitting diode package includes a wall to prevent light from being emitted to the sides thereof. | 2021-09-16 |
20210288104 | DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF - A display device includes a substrate, a first bank pattern and a second bank pattern on the substrate and spaced apart from each other, a first electrode on the first bank pattern, and a second electrode on the second bank pattern, a light emitting element between the first bank pattern and the second bank pattern, an insulation pattern on the light emitting element, and exposing a first end and a second end of the light emitting element respectively adjacent to the first bank pattern and the second bank pattern, a third electrode contacting the first electrode and the first end of the light emitting element, and a fourth electrode contacting the second electrode and the second end of the light emitting element, wherein a thickness of the insulation pattern is within a range of about 50% to about 150% of a thickness of the first bank pattern. | 2021-09-16 |
20210288105 | IMAGE DISPLAY DEVICE - An image display device comprises a drive circuit substrate including a drive circuit that supplies currents to micro light-emitting elements to emit light; and the micro light-emitting elements arranged in an array shape on the drive circuit substrate, wherein a light-distribution control unit that increases forward light emission of the micro light-emitting elements is disposed on a light-emitting surface of each of the micro light-emitting elements, and a partition wall that does not transmit the light emitted by the micro light-emitting elements is disposed around the light-distribution control unit. | 2021-09-16 |
20210288106 | LIGHT-EMITTING DEVICE - A light-emitting device including a substrate, an insulating layer, an inner circuit structure, a plurality of light-emitting elements, an insulating encapsulation layer, and a transparent conductive layer is provided. The insulating layer is disposed on the substrate. The inner circuit structure is disposed on the insulating layer. The light-emitting elements are correspondingly disposed on the inner circuit structure. The insulating encapsulation layer is disposed on the inner circuit structure. The insulating encapsulating layer covers a portion of the inner circuit structure and encapsulates the light-emitting elements. The transparent conductive layer is disposed on the insulating encapsulating layer. The transparent conductive layer electrically connects the light-emitting elements, and serially connects the light-emitting elements. | 2021-09-16 |
20210288107 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, a first top electrode on the first MTJ and a second top electrode on the second MTJ, a passivation layer between the first MTJ and the second MTJ, and an ultra low-k (ULK) dielectric layer on and directly contacting the passivation layer and around the first MTJ and the second MTJ. Preferably, a top surface of the passivation layer includes a V-shape and a valley point of the V-shape is higher than a bottom surface of the first top electrode. | 2021-09-16 |
20210288108 | THRESHOLD SWITCHING SELECTOR BASED MEMORY - Embodiments include a threshold switching selector. The threshold switching selector may include a threshold switching layer and a semiconductor layer between two electrodes. A memory cell may include the threshold switching selector coupled to a storage cell. The storage cell may be a PCRAM storage cell, a MRAM storage cell, or a RRAM storage cell. In addition, a RRAM device may include a RRAM storage cell, coupled to a threshold switching selector, where the threshold switching selector may include a threshold switching layer and a semiconductor layer, and the semiconductor layer of the threshold switching selector may be shared with the semiconductor layer of the RRAM storage cell. | 2021-09-16 |
20210288109 | RESISTIVE RANDOM ACCESS MEMORY INTEGRATED WITH STACKED VERTICAL TRANSISTORS - A method may include forming two vertical transport field effect transistors stacked one atop the other and separated by a resistive random access memory structure. The two vertical transport field effect transistors may include a source, a channel, and a drain, wherein a contact layer of the resistive random access memory structure functions as the drain of the two vertical transport field effect transistors. Forming the two vertical transport field effect transistors may further include forming a first source and a second source. The first source is a bottom source and the second source is a top source. The method may include forming a gate conductor layer surrounding the channel. The resistive random access memory structures may include faceted epitaxy defined by pointed tips. The pointed tips of the faceted epitaxy may extend vertically toward each other. The faceted epitaxy may be between the two vertical transport field effect transistors. | 2021-09-16 |
20210288110 | METAL-INSULATOR-SEMICONDUCTOR-INSULATOR-METAL (MISIM) DEVICE, METHOD OF OPERATION, AND MEMORY DEVICE INCLUDING THE SAME - A metal-insulator-semiconductor-insulator-metal (MISIM) device includes a semiconductor layer, an insulating layer disposed over an upper surface of the semiconductor layer, a back electrode disposed over a lower surface of the semiconductor layer opposing the upper surface, and first and second electrodes disposed over the insulating layer and spaced-apart from each other. | 2021-09-16 |
20210288111 | IMAGE PICKUP ELEMENT, STACKED IMAGE PICKUP ELEMENT, AND SOLID IMAGE PICKUP APPARATUS - An image pickup element includes a photoelectric conversion section including a first electrode, a photoelectric conversion layer including an organic material, and a second electrode stacked on one another. Between the first electrode and the photoelectric conversion layer, an oxide semiconductor layer and an oxide film are formed from the first electrode side. | 2021-09-16 |
20210288112 | ORGANIC COMPONENT FOR CONVERTING LIGHT INTO ELECTRICAL ENERGY WITH IMPROVED EFFICIENCY AND SERVICE LIFE IN THE CASE OF PARTIAL SHADING - The invention relates to organic components for converting light into electrical energy, comprising integrated bypass diodes, which are integrated into the optoelectronic stack, in order to increase the efficiency and the service life of the optoelectronic component in the case of partial shading/shading of individual cells or cell segments. Said components can also be produced for large-area applications in the roll-to-roll method. | 2021-09-16 |
20210288113 | IMAGING ELEMENT AND ELECTRONIC APPARATUS - The present technology relates to an imaging element and an electronic apparatus which make it possible to acquire a variety of information regarding a subject including polarization information. Included are an organic photoelectric conversion film that has a light-transmitting property, is oriented in a predetermined axial direction, and includes a step; an upper electrode arranged on a light incident surface side of the organic photoelectric conversion film; and a lower electrode arranged on a side of the organic photoelectric conversion film facing the upper electrode. Protrusions and recesses are formed on the light incident surface side of the organic photoelectric conversion film. An accumulation layer that accumulates an electric charge converted by the organic photoelectric conversion film is included between the organic photoelectric conversion film and the lower electrode, and the step is formed depending on the presence or absence of the accumulation layer. The present technology can be applied, for example, to an imaging element that detects a polarization component in a predetermined direction. | 2021-09-16 |
20210288114 | ORGANIC PHOTOELECTRONIC DEVICE AND IMAGE SENSOR - An organic photoelectronic device includes a first electrode and a second electrode facing each other and a light-absorption layer between the first electrode and the second electrode and including a first region closest to the first electrode, the first region having a first composition ratio (p | 2021-09-16 |