37th week of 2022 patent applcation highlights part 63 |
Patent application number | Title | Published |
20220293425 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND APPARATUS FOR MANUFACTURING SEMICONDUCTOR DEVICE - There is provided a method for manufacturing a semiconductor device, including: attracting a semiconductor device wafer by a chuck mechanism and rotating the semiconductor device wafer horizontally; rotating a rotary blade horizontally by a vertical spindle to which ultrasonic waves are applied; trimming an outer peripheral end portion of the semiconductor device wafer that is horizontally rotating by the rotary blade that is horizontally rotating, to form a groove in the outer peripheral end portion; correcting a tip shape of the rotary blade that is horizontally rotating by a blade-forming grinding wheel during the trimming; and grinding one main surface of the semiconductor device wafer that is horizontally rotating by a cup grinding wheel that is horizontally rotating after the trimming. | 2022-09-15 |
20220293426 | METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES - A method of manufacturing a semiconductor device includes forming an interlayer insulating layer on a substrate, forming a first mask layer on the interlayer insulating layer, forming a second mask layer and a first spacer on the first mask layer, forming a photoresist pattern on the second mask layer, forming a second mask pattern by patterning the second mask layer through a first etching process, forming a first mask pattern by patterning the first mask layer through a second etching process, forming a trench by etching a portion of the interlayer insulating layer through a third etching process, and forming an interconnection pattern within the trench. A width of the first mask pattern after the second etching process is less than a width of the photoresist pattern. | 2022-09-15 |
20220293427 | SYSTEM AND METHOD FOR FABRICATING PHOTONIC DEVICE ELEMENTS - Elements of photonic devices with high aspect ratio patterns are fabricated. A stabilizing catalyst that forms a stable metal-semiconductor alloy allows to etch a substrate in vertical direction even at very low oxidant concentration without external bias or magnetic field. A metal layer on the substrate reacts with the oxidant contained in air and catalyzes the semiconductor etching by the etchant. Air in continuous flow at the metal layer allows to maintain constant the oxidant concentration in proximity of the metal layer. The process can continue for a long time in order to form very high aspect ratio structures in the order of 10,000:1. Once the etched semiconductor structure is formed, the continuous air flow supports the reactant species diffusing through the etched semiconductor structure to maintain a uniform etching rate. The continuous air flow supports the diffusion of reaction by-products to avoid poisoning of the etching reaction. | 2022-09-15 |
20220293428 | APPARATUS FOR PROCESSING SUBSTRATE - An apparatus for processing a substrate is provided. The apparatus includes a chamber having at least one gas inlet and at least one gas outlet, a substrate support in the chamber, a plasma generator and a controller configured to cause (a) placing a substrate on the substrate support, the substrate including a target layer having a recess, (b) exposing the substrate to a silicon-containing precursor, thereby forming an adsorption layer on a sidewall of the recess, (c) generating a plasma from a gas mixture in the chamber, the gas mixture including an oxygen-containing gas and a halogen-containing gas, (d) exposing the substrate to the plasma, thereby forming a protection layer on the adsorption layer while etching a bottom of the recess and (e) repeating (b) to (d) in sequence. | 2022-09-15 |
20220293429 | ANTI-OXIDATION LAYER TO PREVENT DIELECTRIC LOSS FROM PLANARIZATION PROCESS - In some embodiments, the present disclosure relates to a method that includes forming a dielectric layer over a substrate and patterning the dielectric to form an opening in the dielectric layer. Further, a conductive material is formed within the opening of the dielectric layer. A planarization process is performed to remove portions of the conductive material arranged over the dielectric layer thereby forming a conductive feature within the opening of the dielectric layer. An anti-oxidation layer is formed on upper surfaces of the conductive feature, and then, the anti-oxidation layer is removed. | 2022-09-15 |
20220293430 | ISOTROPIC SILICON NITRIDE REMOVAL - Exemplary methods of etching a silicon-containing material may include flowing a fluorine-containing precursor into a remote plasma region of a semiconductor processing chamber. The methods may include forming a plasma within the remote plasma region to generate plasma effluents of the fluorine-containing precursor. The methods may include flowing the plasma effluents into a processing region of the semiconductor processing chamber. A substrate may be positioned within the processing region. The substrate may include a trench formed through stacked layers including alternating layers of silicon nitride and silicon oxide. The methods may include isotropically etching the layers of silicon nitride while substantially maintaining the silicon oxide. | 2022-09-15 |
20220293431 | THERMAL ATOMIC LAYER ETCH WITH RAPID TEMPERATURE CYCLING - Disclosed are apparatuses and methods for performing atomic layer etching. A method may include supporting and thermally floating a substrate in a processing chamber, modifying one or more surface layers of material on the substrate by chemical adsorption, without using a plasma, while the substrate is maintained at a first temperature, and removing the one or more modified surface layers by desorption, without using a plasma, while the substrate is maintained at a second temperature, the first temperature being different than the second temperature. An apparatus may include a processing chamber and support features configured to support and thermally float a substrate in the chamber, a process gas unit configured to flow a first process gas onto the substrate, a substrate heating unit configured to heat the substrate, and a substrate cooling unit configured to actively cool the substrate. | 2022-09-15 |
20220293432 | SEMICONDUCTOR PACKAGE, ELECTRONIC APPARATUS AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE - A semiconductor package includes an interposer having a separation layer on a rear surface of which a plurality of first recesses is arranged. A plurality of wiring structures is stacked on the separation layer alternately with a plurality of insulation interlayers. A plurality of semiconductor devices is arranged, side by side, on the interposer side and connected to a plurality of the wiring structures. A plurality of contact terminals on the rear surface of the separation layer is connected to the plurality of the wiring structures through the separation layer. A flatness deterioration of the interposer is minimized and the contact surface between the interposer and under fill resin is enlarged. | 2022-09-15 |
20220293433 | Seal Ring Designs Supporting Efficient Die to Die Routing - Chip sealing designs to accommodate die-to-die communication are described. In an embodiment, a chip structure includes a split metallic seal structure including a lower metallic seal and an upper metallic seal with overlapping metallization layers, and a through seal interconnect navigating through the split metallic seal structure. | 2022-09-15 |
20220293434 | SEMICONDUCTOR MANUFACTURING APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME, AND SEMICONDUCTOR DEVICE - A mold die includes a resin injection gate through which fluid resin serving as mold resin is injected toward a cavity, a resin reservoir to store the fluid resin flowing through the cavity, and a resin reservoir gate. The resin reservoir is provided on the side opposite to the side on which the resin injection gate is arranged with the cavity interposed. The resin reservoir gate communicatively connects the cavity and the resin reservoir. The opening cross-sectional area of the resin reservoir gate is smaller than the opening cross-sectional area of the resin injection gate. | 2022-09-15 |
20220293435 | SYSTEMS AND METHODS FOR FABRICATION OF MICRO-LED DISPLAYS - A LED display fabrication tool includes first and second dispensing chambers to deliver first and second color conversion precursors onto a workpiece for fabrication of a light emitting diode (LED) displays, first and second curing stations to cure the workpiece to form first and second color conversion layers over a first and second set of LEDs on the workpiece, and first and second washing/drying chambers to remove uncured portions of the first and second color conversion precursors from the workpiece and then dry the workpiece. Each of the chambers is independently sealable. A controller controls a workpiece transport system to move the workpiece sequentially between the chambers. | 2022-09-15 |
20220293436 | SEMICONDUCTOR SUBSTRATE BONDING TOOL AND METHODS OF OPERATION - A bonding tool includes a gas supply line that may extend directly between valves associated with one or more gas supply tanks and a processing chamber such that gas supply line is uninterrupted without any intervening valves or other types of structures that might otherwise cause a pressure buildup in the gas supply line between the processing chamber and the valves associated with the one or more gas supply tanks. The pressure in the gas supply line may be maintained at or near the pressure in the processing chamber so that gas provided to the processing chamber through the gas supply line does not cause a pressure imbalance in the processing chamber, which might otherwise cause early or premature contact between semiconductor substrates that are to be bonded in the processing chamber. | 2022-09-15 |
20220293437 | CLAMPING JIG AND CLEANING DEVICE - A clamping jig according to the present disclosure includes a supporting portion extending in a vertical direction, and a bent portion connected to a top side of the supporting portion and configured to come into contact with an outer peripheral portion of a substrate. The bent portion includes a base end portion located on a side of the supporting portion and a tip portion connected to the base end portion. At least the tip portion contains a ceramic containing silicon carbide or aluminum oxide as a main component. | 2022-09-15 |
20220293438 | PROCESSING APPARATUS AND PROCESSING METHOD - A processing trajectory at the time of processing a peripheral part of a workpiece is set such that a processing width of the peripheral part of the workpiece is narrowed as spaced more from the position of a notch in a predetermined range centered at the position of the notch and that the processing width of the peripheral part of the workpiece is equal to a reference width (lower limit of the processing width) outside the predetermined range. As a result, the processing width at a position far from the position of the notch is narrow, and therefore, the proportion of devices damaged by edge trimming can be reduced or set to zero. In addition, since the processing width at the position of the notch is widened most, the probability that cracks are generated in the workpiece after the back surface side of the workpiece is ground can be lowered. | 2022-09-15 |
20220293439 | SUBSTRATE PROCESSING APPARATUS - A substrate processing apparatus includes: a rotary table provided in a processing container; a stage provided on the rotary table to place a substrate thereon, and configured to revolve by a rotation of the rotary table; a heater configured to heat the substrate placed on the stage; and a rotation shaft configured to rotate together with the rotary table and support the stage to be rotatable; and a deflector configured to deflect heating light emitted from the heater toward the rotation shaft. | 2022-09-15 |
20220293440 | LOAD PORT AND METHODS OF OPERATION - A load port is capable of monitoring various environmental parameters associated with a transport carrier to minimize and/or prevent exposure of the semiconductor substrates therein to increased humidity, increased oxygen, increased vibration, and/or one or more other elevated environmental conditions that might otherwise contaminate the semiconductor substrates, damage the semiconductor substrates, and/or cause processing defects. For example, the load port may monitor the environmental parameters as indicators of a potential blockage of a diffuser of the transport carrier, and a relief valve may be used to divert a gas away from the transport carrier based on a determination that a diffuser blockage has occurred. In this way, the gas may be diverted through the relief valve and away from the transport carrier to prevent increased humidity, contaminants, and/or vibration from contaminating and/or damaging the semiconductor substrates. | 2022-09-15 |
20220293441 | FABRICATION OF MICRO-LED DISPLAYS WITH REWORK OR TRANSFER LINE - A LED display fabrication tool includes a plurality of chambers including an initial chamber, a final chamber, and a plurality of intermediate chambers, and the plurality of chambers are arranged to form a transfer line from the initial chamber to the final chamber with each intermediate chamber coupled by a first sealable port to a prior chamber in the transfer line and by a second sealable port to a subsequent chamber in the transfer line. The plurality of chambers include first and second dispensing chambers to deliver first and second color conversion precursors onto a workpiece for fabrication of a light emitting diode (LED) displays, and first and second washing/drying chambers to remove uncured portions of the first and second color conversion precursors. First and second curing stations cure the precursors. | 2022-09-15 |
20220293442 | DYNAMIC PROCESS CONTROL IN SEMICONDUCTOR MANUFACTURING - Methods and system are provided for dynamic process control in substrate processing, for example in semiconductor manufacturing applications. Some example systems and methods are provided for advanced monitoring and machine learning in atomic layer deposition (ALD) processes. Some examples also relate to dynamic process control and monitoring for chamber parameter matching and gas line charge times. | 2022-09-15 |
20220293443 | NOZZLE HAVING REAL TIME INSPECTION FUNCTIONS - A method of manufacturing a semiconductor device includes: receiving a workpiece on which the semiconductor device is manufactured; causing a nozzle to dispense a fluid toward a surface of the workpiece external to the nozzle, wherein the nozzle includes a first channel and a second channel that allow the fluid to flow through; emitting light, by a light source, from within the nozzle toward the surface while the nozzle is dispensing the fluid; receiving light reflected from the surface by a light sensor, the light source and the light sensor being disposed within the nozzle and opposite to each other, and the emitted light and the reflected light adapted to be contained within the fluid; and examining a status of the reflected light. The emitted light and the reflected light propagate in a direction parallel to a longitudinal axis of each of the first channel and the second channel. | 2022-09-15 |
20220293444 | FRONT-DUCTED EQUIPMENT FRONT END MODULES, SIDE STORAGE PODS, AND METHODS OF OPERATING THE SAME - An equipment front end module, including: an equipment front end module chamber. An upper plenum at a top of the equipment front end module and including an opening into the equipment front end module chamber. A plurality of return ducts that are coupled between a bottom of the equipment front end module chamber and the upper plenum, the plurality of return ducts providing a return gas flow path enabling recirculation of gas from the equipment front end module chamber to the upper plenum. | 2022-09-15 |
20220293445 | TRANSFER SYSTEM, TRANSFER DEVICE, AND TRANSFER METHOD - A transfer system has a storage device including a plurality of shelves, each of the shelves including a placement portion in which an opening region is formed and on which the article is placed and an attaching portion provided according to a position of the placement portion; and a transfer device used for transferring the article, from the one side with respect to the transfer target shelf. The transfer device has a main unit portion attached to the attaching portion of the transfer target shelf from the one side, a moving portion including a grip portion and being capable of supporting the article and configured to move along the one direction, and an elevating portion configured to elevate the moving portion through the opening region of the transfer target shelf. | 2022-09-15 |
20220293446 | SEMICONDUCTOR SUBSTRATE CARRYING CONTAINER WITH FRONT AND REAR OPENINGS - A semiconductor substrate carrying container, such as a front opening unified pod, is configured such that a semiconductor substrate can be accessed and removed from or inserted into an interior space of the container via a rear opening that is located opposite a front opening that also permits removal and insertion therethrough. The removal and insertion via the rear opening can be achieved in any suitable manner including, but not limited to, using an automated mechanism, such as a robot arm, or manually. | 2022-09-15 |
20220293447 | SYSTEMS, DEVICES, AND METHODS FOR AIR FLOW OPTIMIZATION INCLUDING ADJACENT A FOUP - A system comprises a front opening universal pod (FOUP) configured to hold one or more semiconductor wafers and a load dock having a stage and a receiving portion extending above the stage. The FOUP is positioned on the stage. A fan filter unit (FFU) positioned above the load dock. An air flow optimizer device is disposed on the receiving portion and under the FFU. The air flow optimizer device has an inlet opening and an outlet opening and a channel extends between the inlet opening and the outlet opening. | 2022-09-15 |
20220293448 | Wafer Positioning Method and Apparatus - A method of correcting a misalignment of a wafer on a wafer holder and an apparatus for performing the same are disclosed. In an embodiment, a semiconductor alignment apparatus includes a wafer stage; a wafer holder over the wafer stage; a first position detector configured to detect an alignment of a wafer over the wafer holder in a first direction; a second position detector configured to detect an alignment of the wafer over the wafer holder in a second direction; and a rotational detector configured to detect a rotational alignment of the wafer over the wafer holder. | 2022-09-15 |
20220293449 | MOUNTING FIXTURE OF BEARING RING FOR WAFER - The present disclosure provides a mounting fixture of a bearing ring for a wafer. The bearing ring includes a circular ring portion, screw elements, and multiple permanent seats, wherein the circular ring portion includes a ring body and multiple lugs provided with light holes, each of the permanent seats is provided with a threaded hole, and one of the screw elements can be in threaded connection with the threaded hole after passing through a light hole. The mounting fixture includes a first clamp body and a second clamp body, where the first clamp body is provided with a first circular hole portion and first groove portions; a diameter of the first circular hole portion is greater than or equal to an external diameter of the ring body; the second clamp body is provided with second groove portions penetrating through the second clamp body. | 2022-09-15 |
20220293450 | SEMICONDUCTOR MANUFACTURING APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor manufacturing apparatus includes a stage configured to mount a wafer on a mounting surface. A blade is configured to cut an outer circumference portion of the wafer toward the mounting surface. The stage includes a protrusion portion provided at a position corresponding to a first region where a material film is not formed on a first surface of the outer circumference portion of the wafer facing the mounting surface. | 2022-09-15 |
20220293451 | LIFT PIN ASSEMBLY - Methods and apparatus for lift pin assemblies for substrate processing chambers are provided. In some embodiments, a lift pin assembly includes a lift pin comprising a shaft, a head, and a coupling end, the head configured to rest against an electrostatic chuck; an upper guide comprising a top end, a bottom end, and a first opening extending from the top end to the bottom end, wherein the shaft is disposed and axially movable through the first opening; a lower guide comprising a top end, a bottom end, and a second opening and a third opening extending from the top end to the bottom end, wherein the third opening is larger than the second opening, and wherein the shaft is disposed and axially movable through the second opening and the third opening; and a biasing mechanism coupled to the shaft and configured to bias the lift pin against the electrostatic chuck. | 2022-09-15 |
20220293452 | LIFT PIN MECHANISM - Methods and apparatus for a lift pin mechanism for substrate processing chambers are provided herein. In some embodiments, the lift pin mechanism includes a lift pin comprising a shaft with a top end, a bottom end, and a coupling end at the bottom end; a bellows assembly disposed about the shaft. The bellows assembly includes an upper bellows flange having an opening for axial movement of the shaft; a bellows having a first end coupled to a lower surface of the upper bellows flange such that the shaft extends into a central volume surrounded by the bellows; and a bellows guide assembly coupled to a second end of the bellows to seal the central volume. The shaft is coupled to the bellows guide assembly at the coupling end. The bellows guide assembly is axially movable to move the lift pin with respect to the upper bellows flange. | 2022-09-15 |
20220293453 | MULTI-ZONE SEMICONDUCTOR SUBSTRATE SUPPORTS - Exemplary support assemblies may include a top puck characterized by a first surface and a second surface opposite the first surface. The top puck may define a recessed ledge at an outer edge of the first surface of the top puck. The assemblies may include a cooling plate coupled with the top puck adjacent the second surface of the top puck. The assemblies may include a back plate coupled with the top puck about an exterior of the top puck. The back plate may at least partially define a volume with the top puck. The cooling plate may be housed within the volume. The assemblies may include a heater disposed on the recessed ledge of the top puck. The assemblies may include an edge ring seated on the heater and extending about the top puck. The edge ring may be maintained free of contact with the top puck. | 2022-09-15 |
20220293454 | SHALLOW TRENCH ISOLATION FILLING STRUCTURE IN SEMICONDUCTOR DEVICE - Disclosed herein are apparatuses and methods that include a shallow trench isolation filling structure. An example method includes: etching a semiconductor substrate to form a plurality of pillars and a trench therebetween; providing rinse solution in the trench; adding a plurality of insulating particles into the rinse solution; and removing the rinse solution such that the insulating particles and an air gap remains in the trench. | 2022-09-15 |
20220293455 | WAFER SCALE PACKAGING - A method of wafer scale packaging acoustic resonator devices and an apparatus therefor. The method including providing a partially completed semiconductor substrate comprising a plurality of single crystal acoustic resonator devices, each having a first electrode member, a second electrode member, and an overlying passivation material. At least one of the devices to be configured with an external connection, a repassivation material overlying the passivation material, an under metal material overlying the repassivation material. Copper pillar interconnect structures are then configured overlying the electrode members, and solder bump structures are form overlying the copper pillar interconnect structures. | 2022-09-15 |
20220293456 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE - A semiconductor structure and a method for manufacturing the semiconductor structure are provided. The semiconductor structure includes a base and a conductive portion that is arranged in the base and includes a via portion and a first conductive layer, where the first conductive layer is connected with the via portion and arranged above the via portion, an air gap is arranged in the base and one end of the air gap is configured to expose the conductive portion. | 2022-09-15 |
20220293457 | IMAGE SENSOR WITH DUAL TRENCH ISOLATION STRUCTURE - In some embodiments, the present disclosure relates to an image sensor. The image sensor comprises a substrate. A photodetector is in the substrate and includes a semiconductor guard ring extending into a first side of the substrate. A shallow trench isolation (STI) structure extends into the first side of the substrate. An outer isolation structure extends into a second side of the substrate, opposite the first side of the substrate, to the STI structure. The STI structure and the outer isolation structure laterally surround the photodetector. An inner isolation structure extends into the second side of the substrate and overlies the photodetector. The inner isolation structure is vertically separated from the photodetector by the substrate. Further, the outer isolation structure laterally surrounds the inner isolation structure. | 2022-09-15 |
20220293458 | LOW THERMAL BUDGET DIELECTRIC FOR SEMICONDUCTOR DEVICES - The present disclosure describes a method of forming low thermal budget dielectrics in semiconductor devices. The method includes forming, on a substrate, first and second fin structures with an opening in between, filling the opening with a flowable isolation material, treating the flowable isolation material with a plasma, and removing a portion of the plasma-treated flowable isolation material between the first and second fin structures | 2022-09-15 |
20220293459 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A method includes forming a gate stack over a substrate and a gate spacer on a sidewall of the gate stack; forming a source/drain region in the substrate and adjacent to the gate spacer; forming a first interlayer dielectric layer over the source/drain region; forming a protective layer over the gate stack and in contact with a top surface of the gate spacer; removing the first interlayer dielectric layer after forming the protective layer; forming an etch stop layer over the protective layer; forming a second interlayer dielectric layer over the etch stop layer; etching the second interlayer dielectric layer and the etch stop layer to form an opening that exposes a top surface of the protective layer; and forming a contact plug in the opening. | 2022-09-15 |
20220293460 | Patterning Methods for Semiconductor Devices and Structures Resulting Therefrom - Semiconductor devices and methods of forming semiconductor devices are provided. A method includes forming a first mask layer over a target layer, forming a plurality of spacers over the first mask layer, and forming a second mask layer over the plurality of spacers and patterning the second mask layer to form a first opening, where in a plan view a major axis of the opening extends in a direction that is perpendicular to a major axis of a spacer of the plurality of spacers. The method also includes depositing a sacrificial material in the opening, patterning the sacrificial material, etching the first mask layer using the plurality of spacers and the patterned sacrificial material, etching the target layer using the etched first mask layer to form second openings in the target layer, and filling the second openings in the target layer with a conductive material. | 2022-09-15 |
20220293461 | Method of Forming Trenches with Different Depths - A semiconductor device includes a gate structure disposed over a substrate, and a first dielectric layer disposed over the substrate, including and over the gate structure. A first metal feature is disposed in the first dielectric layer, including an upper portion having a first width and a lower portion having a second width that is different than the first width. A dielectric spacer is disposed along the lower portion of the first metal feature, wherein the upper portion of the first metal feature is disposed over the dielectric spacer. A second dielectric layer is disposed over the first dielectric layer, including over the first metal feature and a second metal feature extends through the second dielectric layer to physically contact with the first metal feature. A third metal feature extends through the second dielectric layer and the first dielectric layer to physically contact the gate structure. | 2022-09-15 |
20220293462 | INTERCONNECT STRUCUTRE WITH PROTECTIVE ETCH-STOP - In some embodiments, the present disclosure relates to an integrated chip. The integrated chip may comprise a first metal line disposed over a substrate. A via may be disposed directly over a top of the first metal line and the via may comprise a first lower surface and a second lower surface above the first lower surface. A first dielectric structure may be disposed laterally adjacent to the first metal line and may be disposed along a sidewall of the first metal line. A first protective etch-stop structure may be disposed directly over a top of the first dielectric structure and the first protective etch-stop structure may vertically separate the second lower surface of the via from the top of the first dielectric structure. | 2022-09-15 |
20220293463 | METHODS AND SYSTEMS FOR FILLING A GAP - Disclosed are methods and systems for filling a gap. An exemplary method comprises providing a substrate to a reaction chamber. The substrate comprises the gap. The method further comprises at least partially filling the gap with a gap filling fluid. The method then comprises subjecting the gap filling fluid to a transformation treatment, thus forming a transformed material in the gap. The methods and systems are useful, for example, in the field of integrated circuit manufacture. | 2022-09-15 |
20220293464 | SEMICONDUCTOR MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE - A semiconductor manufacturing method includes forming a concave portion in a layer provided above a substrate from a top surface of the layer downwards, the layer including an insulation layer at least partially. The method includes forming a silicon film on an inner surface of the concave portion. The method includes exposing the silicon film to a raw material gas of metal and an inhibitor gas that inhibits growth of the metal at a first temperature, to replace a first portion of the silicon film located in an upper-end side portion of the concave portion with a first conductive film containing the metal. The method includes exposing the silicon film to the raw material gas and the inhibitor gas at a second temperature lower than the first temperature, to replace a second portion of the silicon film with a second conductive film containing the metal. | 2022-09-15 |
20220293465 | METHOD FOR MANUFACTURING INTERCONNECTION STRUCTURE - A method includes providing a semiconductor structure including a dielectric layer having an opening exposing a top surface of a metal layer. A bottom via is selectively deposited in the opening and over the metal layer. A barrier layer is deposited over the bottom via and in contact with the dielectric layer at a sidewall of the opening. A top via is formed in the opening, in contact with the barrier layer, and over the bottom via. The top via is separated from the dielectric layer by the barrier layer. | 2022-09-15 |
20220293466 | Method for Forming Semiconductor Structure and Semiconductor Structure - The present disclosure relates to a field of semiconductor manufacturing technology, and in particular to a method for forming a semiconductor structure and a semiconductor structure. The method for forming the semiconductor structure includes: a substrate is placed in a reaction chamber, and the substrate includes at least one first conductive structure, a surface of the substrate is covered with an isolation layer, a surface of the isolation layer is covered with a first mask layer, and the first mask layer includes at least one etching window exposing the isolation layer; the isolation layer, a part of the substrate and a part of each of the at least one first conductive structure are etched along the at least one etching window according to preset etching parameters to form at least one trench; a barrier layer is formed; and at least one second conductive structure is formed. | 2022-09-15 |
20220293467 | METHOD FOR MICROSTRUCTURE MODIFICATION OF CONDUCTING LINES - A method for microstructure modification of conducting lines is provided. An electroplating process is performed to deposit the metal thin film/conducting line(s) with a face-centered cubic (FCC) structure and a preferred crystallographic orientation over a surface of a substrate. The metal thin film/ conducting line(s) is subsequently subjected to a thermal annealing process to modify its microstructure with the grain sizes in a range of 5 μm to 100 μm. The thermal annealing process is conducted at the temperature of above 25 degrees Celsius and below 240 degrees Celsius. | 2022-09-15 |
20220293468 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - An adhesive layer ( | 2022-09-15 |
20220293469 | SEMICONDUCTOR DEVICE AND INTEGRATED CIRCUIT IN HYBRID ROW HEIGHT STRUCTURE - A semiconductor device includes several first cell row an several second cell rows. The first cell rows extend in a first direction. Each of the first cell rows has a first row height. A first row of the first cell rows is configured for a first cell to be arranged. The second cell rows extend in the first direction. Each of the second cell rows has a second row height that is different from the first row height. At least one row of the second cell rows includes a portion for at least one second cell to be arranged. The portion has a third row height that is different from the first row height and the second row height. | 2022-09-15 |
20220293470 | INTEGRATED CIRCUIT IN HYBRID ROW HEIGHT STRUCTURE - A system includes a non-transitory storage medium encoded with a set of instructions and a processor. The processor is configured to execute the set of instructions. The set of instructions is configured to cause the processor to: obtain, based on a netlist of a circuit, values each corresponding to one of transistors included in the circuit; compare the values with a threshold value; in response to a comparison, generate an adjusted netlist of the circuit by adding redundant transistors; and determine, based on the adjusted netlist, one of layout configurations for the circuit. The layout configurations include first cell rows each having a first row height and second cell rows each having a second row height different from the first row height. | 2022-09-15 |
20220293471 | Fin Field-Effect Transistor Device and Method - A method of forming a semiconductor device includes: forming a metal gate structure over a fin that protrudes above a substrate, the metal gate structure being surrounded by an interlayer dielectric (ILD) layer; recessing the metal gate structure below an upper surface of the ILD layer distal from the substrate; after the recessing, forming a first dielectric layer over the recessed metal gate structure; forming an etch stop layer (ESL) over the first dielectric layer and the ILD layer; forming a second dielectric layer over the ESL; performing a first dry etch process to form an opening that extends through the second dielectric layer, through the ESL, and into the first dielectric layer; after the first dry etch process, performing a wet etch process to clean the opening; and after the wet etch process, performing a second dry etch process to extend the opening through the first dielectric layer. | 2022-09-15 |
20220293472 | METHOD FOR MANUFACTURING FIN FIELD EFFECT TRANSISTOR - The present application discloses a method for manufacturing fin field effect transistors, comprising: step | 2022-09-15 |
20220293473 | Semiconductor Device and Method - A method includes forming a gate structure over fins protruding from a semiconductor substrate; forming an isolation region surrounding the fins; depositing a spacer layer over the gate structure and over the fins, wherein the spacer layer fills the regions extending between pairs of adjacent fins; performing a first etch on the spacer layer, wherein after performing the first etch, first remaining portions of the spacer layer that are within inner regions extending between pairs of adjacent fins have a first thickness and second remaining portions of the spacer layer that are not within the inner regions have a second thickness less than the first thickness; and forming an epitaxial source/drain region adjacent the gate structure and extending over the fins, wherein portions of the epitaxial source/drain region within the inner regions are separated from the first remaining portions of the spacer layer. | 2022-09-15 |
20220293474 | Method of Manufacturing Semiconductor Devices with Multiple Silicide Regions - A semiconductor device with multiple silicide regions is provided. In embodiments a first silicide precursor and a second silicide precursor are deposited on a source/drain region. A first silicide with a first phase is formed, and the second silicide precursor is insoluble within the first phase of the first silicide. The first phase of the first silicide is modified to a second phase of the first silicide, and the second silicide precursor being soluble within the second phase of the first silicide. A second silicide is formed with the second silicide precursor and the second phase of the first silicide. | 2022-09-15 |
20220293475 | METHOD FOR MANUFACTURING FIN FIELD EFFECT TRANSISTOR - The present application discloses a method for manufacturing a fin field effect transistor, comprising: step | 2022-09-15 |
20220293476 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE, SEMICONDUCTOR MANUFACTURING SYSTEM, AND SEMICONDUCTOR DEVICE - According to one embodiment, there is provided a manufacturing method of a semiconductor device. The method includes inspecting each of plural chip regions of a substrate and determining the inspected chip region as a non-defective chip region or a defective chip region, the substrate including the plural chip regions formed as one system, the plural chip regions arranged in a planar direction on the substrate. The method includes forming a wiring, the wiring being connected to an electrode of the non-defective chip region among the plural chip regions, the wiring being not connected to an electrode of the defective chip region among the plural chip regions. | 2022-09-15 |
20220293477 | TEST STRUCTURE AND TESTING METHOD THEREOF - A method includes: providing a substrate defining a scribe line region and a device region adjacent to the scribe line region; depositing a first mask layer over the device region and the scribe line region; patterning the first mask layer to define a plurality of first areas in the device region and a plurality of second areas in the scribe line region, wherein the first areas and the second areas are parallel and extending in a first direction from a top-view perspective; performing a first ion implantation to form first well regions in the first areas and second well regions in the second areas; coupling conductive pads to the second well regions; and performing a test on the second well regions through the conductive pads. | 2022-09-15 |
20220293478 | REGISTRATION MARK, POSITIONAL DEVIATION DETECTION METHOD AND DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a registration mark includes a first step portion and a second step portion. The first step portion includes a plurality of first steps which descend step by step in a first direction from a surface of a substrate or a layer formed on the substrate. The second step portion includes a plurality of second steps which descend step by step from the surface in a second direction different from the first direction and have the same number as the number of the plurality of first steps, is spaced apart from the first step portion, and is disposed rotationally symmetrically to the first step portion. | 2022-09-15 |
20220293479 | SEMICONDUCTOR MODULE CASE AND METHOD FOR PRODUCING SEMICONDUCTOR MODULE CASE - A semiconductor module case formed by injection molding into a box shape using a mold open on a bottom thereof, includes an external terminal disposed on a top face or a side face of the case, the external terminal penetrating through the case from an inside to an outside thereof and being electrically connectable to a semiconductor element inside of the case, and a single first gate for a resin to enter the case. The case has a rectangular shape in a plan view of the case and has first and second short sides and first and second long sides, and the first gate is disposed at a side face of the first short side and has a flat surface area having a first width that extends along the first short side in a width direction of the case. | 2022-09-15 |
20220293480 | WELDING METHOD OF DEMETALLIZED CERAMIC SUBSTRATE HAVING SURFACE CAPILLARY MICROGROOVE STRUCTURE - The present invention discloses a welding method of a demetallized ceramic substrate having a surface capillary microgroove structure. The demetallized ceramic substrate includes a ceramic substrate main body and surface capillary microstructures. The surface capillary microstructures are arranged on two lateral sides of the ceramic substrate main body and the surface capillary microstructures specifically are capillary microgrooves. The welding method includes the following steps: fixing a chip to an upper surface of the demetallized ceramic substrate having the surface capillary microgroove structure, fixing the ceramic substrate with the chip to a printed circuit board having a bonding pad, and placing melted solder on the bonding pad, and driving the solder to ascend to an electrode of the chip from the bonding pad in a lower layer by means of a capillary force, thereby realizing an electrical connection between the chip and the printed circuit board. | 2022-09-15 |
20220293481 | SEMICONDUCTOR MODULE AND MANUFACTURING METHOD OF SEMICONDUCTOR MODULE - Provided is a semiconductor module, including: a semiconductor chip; a terminal, configured to extend in a extending direction, and be connected electrically with the semiconductor chip; a sealing resin, configured to seal the semiconductor chip, and cover at least a part of an upper surface of the terminal and at least a part of a lower surface of the terminal; and a lower side resin, configured to extend in the extending direction from the sealing resin, and cover at least a part of the lower surface of the terminal, wherein in the extending direction, a length at which the sealing resin and the lower side resin cover the lower surface of the terminal is greater than a length at which the sealing resin covers the upper surface of the terminal in the extending direction; and wherein the sealing resin and the lower side resin are formed of a same material. | 2022-09-15 |
20220293482 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a stackable semiconductor device with small size and fine pitch and a method of manufacturing thereof. | 2022-09-15 |
20220293483 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A semiconductor package provided herein includes a first semiconductor die, a second semiconductor die and an insulating encapsulation. The second semiconductor die is stacked on the first semiconductor die. The insulating encapsulation laterally surrounds the first semiconductor die and the second semiconductor die in a one-piece form, and has a first sidewall and a second sidewall respectively adjacent to the first semiconductor die and the second semiconductor die. The first sidewall keeps a lateral distance from the second sidewall. | 2022-09-15 |
20220293484 | INTEGRATED CIRCUIT PACKAGE SYSTEM - An integrated circuit package system includes a substrate, a plurality of leads, N semiconductor devices, N first heat sinks, an encapsulating body, a second heat sink and a plurality of heat-dissipating fins protruding upward from the second heat sink, where N is a natural number. The leads are formed on a lower surface of the substrate. Each of the semiconductor devices is attached on an upper surface of the substrate, and includes a plurality of bonding pads which each is electrically connected to the corresponding lead. Each first heat sink is thermally coupled to a first top surface of the corresponding semiconductor device. The encapsulating body is formed to cover the substrate, the N semiconductor devices and the N first heat sinks such that the leads are exposed. The second heat sink is mounted on the encapsulating body, and is thermally coupled to the N first heat sinks. | 2022-09-15 |
20220293485 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor chip, a heat sink, a resin package, heat transfer material and multiple spacers. The heat sink absorbs heat of the semiconductor chip. The resin package accommodates the semiconductor chip, and the resin package has a surface at which the heat sink is disposed. The heat transfer material has fluidity, and the heat transfer material is filled between the heat sink and the cooling plate. The spacers are dispersedly arranged in the heat transfer material, and the spacers are in contact with the heat sink and the cooling plate. | 2022-09-15 |
20220293486 | LIDDED MICROELECTRONIC DEVICE PACKAGES AND RELATED SYSTEMS, APPARATUS, AND METHODS OF MANUFACTURE - A microelectronic device package may include one or more semiconductor dice coupled to a substrate. The microelectronic device package may further include a lid coupled to the substrate, the lid defining a volume over and around the one or more semiconductor die. The microelectronic device package may further include a thermally conductive dielectric filler material substantially filling the volume defined around the semiconductor die. | 2022-09-15 |
20220293487 | ELECTRICAL DEVICE AND ELECTRONIC CONTROL DEVICE - An electrical device includes a first housing which has therein a first circuit board on which a first electronic component is mounted, a second housing which has therein a second circuit board on which a second electronic component is mounted, and fans which send air passing between the first housing and the second housing. The first housing has a plurality of fins facing the second housing. The second housing has a plurality of fins facing the first housing. In at least one of cross sections of the first circuit board in a thickness direction, the electrical device has a structure having a region in which the fin of the first housing is longer than the fin of the second housing and a region in which the fin of the first housing is shorter than the fin of the second housing. | 2022-09-15 |
20220293488 | HEAT SINK FOR IC COMPONENT AND IC HEAT SINK ASSEMBLY - A heat sink for an IC component and an IC heat sink assembly are provided. The heat sink for an IC component has a contact surface suitable for thermally contacting with the IC component. A groove is provided in the contact surface. The IC heat sink assembly includes: a heat sink for an IC component; an IC component thermally connected to the heat sink; and a thermally conductive interface material provided between the heat sink and the IC component. | 2022-09-15 |
20220293489 | COMPACT POWER ELECTRONICS MODULE WITH INCREASED COOLING SURFACE - The invention relates to a power electronics module including a first circuit carrier ( | 2022-09-15 |
20220293490 | COOLING SYSTEM - A cooling system for a semiconductor device. The system includes a first heat sink containing a ceramic material as a main component and a semiconductor device having a first contact surface. The first heat sink serves for cooling the semiconductor device and as an electrical insulator with respect to the semiconductor device. Furthermore, a first metal-containing layer is provided on at least one outer surface of the first heat sink, the first metal-containing layer having a size at least equal to the area of the first contact surface of the semiconductor device. The semiconductor device is attached to the first metal-containing layer via the contact surface by a first bonding layer formed by soldering or sintering. | 2022-09-15 |
20220293491 | COOLING APPARATUS, SEMICONDUCTOR MODULE, AND VEHICLE - The flow speed distribution of a refrigerant in a cooling apparatus is made uniform. A cooling apparatus provided includes: a top plate; a casing portion having a base plate facing the top plate, and a refrigerant delivery portion arranged between the top plate and the base plate, the casing portion provided with two opening portions to function as an inlet port through which a refrigerant is let into the refrigerant delivery portion and an outlet port through which the refrigerant is let out; a cooling fin portion arranged in the refrigerant delivery portion of the casing portion and between the two opening portions; and a loss adding portion arranged in the refrigerant delivery portion of the casing portion and between the cooling fin portion and at least one of the two opening portions, the loss adding portion generating pressure loss in the refrigerant passing therethrough. | 2022-09-15 |
20220293492 | MEMORY MACRO INCLUDING THROUGH-SILICON VIA - A memory macro structure includes a first memory array, a second memory array, a cell activation circuit coupled to the first and second memory arrays and positioned between the first and second memory arrays, a control circuit coupled to the cell activation circuit and positioned adjacent to the cell activation circuit, and a through-silicon via (TSV) extending through one of the cell activation circuit or the control circuit. | 2022-09-15 |
20220293493 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - The present disclosure relates to the technical field of semiconductors, and proposes a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a base and a communication portion, the communication portion being located in the base and including a first connection layer, a second connection layer, and a third connection layer, the second connection layer being located on the first connection layer, and the third connection layer being located on the second connection layer; wherein the first connection layer, the second connection layer, and the third connection layer include different conductive materials, and thermal expansion coefficients of the second connection layer and the third connection layer are both less than a thermal expansion coefficient of the first connection layer. | 2022-09-15 |
20220293494 | METHOD OF FORMING SEMICONDUCTOR DEVICE - A method of forming a semiconductor device includes following steps. A first organic layer is formed to cover a first conductive layer. A first opening is formed in the first organic layer to expose a first surface of the first conductive layer. A first silicon layer is formed on a sidewall of the first opening and the first surface of the first conductive layer. A first dielectric layer is formed on the sidewall of the first opening and the first surface of the first conductive layer over the first silicon layer. By using a first mask, portions of the first silicon layer and the first dielectric layer on the first surface are simultaneously removed to expose the first surface, wherein after removing the portions of the first silicon layer and the first dielectric layer, the first dielectric layer covers a top surface of the first silicon layer. | 2022-09-15 |
20220293495 | SYSTEM IN PACKAGE - The present application describes a system in package which features no printed circuit board inside an encapsulation structure and comprises: a copper holder with a silicon layer at a top face; a plurality of dies mounted on the silicon layer and electrically connected to a plurality of data pins of the copper holder; a passive element mounted on the silicon layer and electrically connected to the dies wherein the dies are electrically connected to the ground pin of the copper holder; a molding compound encasing the dies and the passive element on the top face of the copper holder. | 2022-09-15 |
20220293496 | SEMICONDUCTOR PACKAGE WITH PLURALITY OF LEADS AND SEALING RESIN - A semiconductor device includes a semiconductor chip, a plurality of leads that each includes a lead body portion which has a mounting portion which includes an upper surface whereon a semiconductor chip is bonded, and a lead connecting portion for external connection which projects downward from a lower surface of the lead body portion, a first sealing resin that seals a space that is defined by each lead body portion and each lead connecting portion of the plurality of leads in a region below the upper surface of each lead body portion of the plurality of leads, and a second sealing resin that seals the semiconductor chip in a region above the upper surface of each lead body portion of the plurality of leads. | 2022-09-15 |
20220293497 | CIRCUIT MODULE - In a circuit module, lead frames include top surfaces facing a main surface of a substrate and bottom surfaces exposed from an insulating seal. The lead frames include pad portions including portions of the top surfaces and connected to metal posts, and lead portions including the bottom surfaces. The pad portions completely overlap the metal posts. | 2022-09-15 |
20220293498 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND CORRESPONDING SEMICONDUCTOR DEVICE - A semiconductor device, such as a Quad-Flat No-lead (QFN) package, includes a semiconductor chip arranged on a die pad of a leadframe. The leadframe has an array of electrically-conductive leads around the die pad. The leads in the array have distal ends facing away from the die pad as well as recessed portions at an upper surface of the leads. Resilient material, such as low elasticity modulus material, is present at the upper surface of the leads and filling the recessed portions. An insulating encapsulation is molded onto the semiconductor chip. The resilient material is sandwiched between the insulating encapsulation and the distal ends of the leads. This resilient material facilitates flexibility of the leads, making them suited for reliable soldering to an insulated metal substrate. | 2022-09-15 |
20220293499 | POWER MODULES AND RELATED METHODS - Implementations of power modules may include: a substrate having a first side and a second side. The power module may include a plurality of leads coupled to a second side of the substrate and a molding compound over a portion of five or more surfaces of the substrate. The power module may also include an opening extending from a first side of the substrate to an outer edge of the molding compound. The opening may be configured to receive a coupling device and the coupling device may be configured to couple with a heat sink or a package support. | 2022-09-15 |
20220293500 | BALL GRID ARRAY PATTERN FOR AN INTEGRATED CIRCUIT - Embodiments are disclosed for providing a ball grid array pattern for an integrated circuit. An example integrated circuit apparatus includes an integrated circuit and a ball grid array. The integrated circuit includes at least a package substrate and a silicon chip. The ball grid array is disposed on the package substrate of the integrated circuit. The ball grid array includes a first set of solder balls that is configured to provide electrical connections for communication channels and a second set of the solder balls associated with an electrical ground. The first set of solder balls includes a first subset of solder balls configured in a first orientation and a second subset of solder balls configured in a second orientation. Furthermore, at least one solder ball from the second set of the solder balls is disposed between the first subset of solder balls and the second subset of solder balls. | 2022-09-15 |
20220293501 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a redistribution substrate and a semiconductor chip on a top surface of the redistribution substrate. The redistribution substrate includes an insulating layer, and first, second, and third redistribution patterns disposed in the insulating layer. The first to third redistribution patterns are sequentially stacked in an upward direction and are electrically connected to each other. Each of the first to third redistribution patterns includes a wire portion that extends parallel to the top surface of the redistribution substrate. Each of the first and third redistribution patterns further includes a via portion that extends from the wire portion in a direction perpendicular to the top surface of the redistribution substrate. The second redistribution pattern furthers include first fine wire patterns that are less wide than the wire portion of the second redistribution pattern. | 2022-09-15 |
20220293502 | INTERCONNECTION SUBSTRATE, SEMICONDUCTOR PACKAGE, AND METHOD OF MANUFACTURING INTERCONNECTION SUBSTRATE - According to one embodiment, an interconnection substrate includes an insulating layer. A first interconnection layer is on a first side of the insulating layer. A second interconnection layer is on a second side of the insulating layer, which is opposite the first side. A first film comprising carbon covers at least part of the first and second interconnection layers. | 2022-09-15 |
20220293503 | INTERCONNECT STRUCTURES AND MANUFACTURING METHOD THEREOF - In some implementations, one or more semiconductor processing tools may form a metal cap on a metal gate. The one or more semiconductor processing tools may form one or more dielectric layers on the metal cap. The one or more semiconductor processing tools may form a recess to the metal cap within the one or more dielectric layers. The one or more semiconductor processing tools may perform a bottom-up deposition of metal material on the metal cap to form a metal plug within the recess and directly on the metal cap. | 2022-09-15 |
20220293504 | SEMICONDUCTOR PACKAGING STRUCTURE, METHOD, DEVICE AND ELECTRONIC PRODUCT - The application provides a semiconductor packaging structure, a semiconductor packaging method, a semiconductor packaging device and an electronic product. The semiconductor packaging structure comprises a substrate, at least one packaged component, a redistribution layer and a passivation layer. The substrate has at least one groove and the at least one packaged component is fixed in the at least one groove in one-to-one correspondence. Each packaged component is separated from a corresponding groove, in which the package component is disposed, by insulating materials. The at least one packaged component has first bonding pads on at least one active surface facing away from the substrate and are flush. The redistribution layer is formed over the at least one active surface. The substrate includes a semiconductor material or insulating material with a thermal expansion coefficient that is the same as or similar to that of a base semiconductor material in the packaged component. | 2022-09-15 |
20220293505 | PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A package structure includes a carrier substrate, a die, and a first redistribution structure. The carrier substrate has a first surface and a second surface opposite to the first surface. The carrier substrate includes an insulating body and through carrier vias (TCV) embedded in the insulating body. The die is disposed over the firs surface of the carrier substrate. The die is electrically connected to the TCVs. The first redistribution structure is disposed on the second surface of the carrier substrate. | 2022-09-15 |
20220293506 | PACKAGE-ON-PACKAGE SEMICONDUCTOR ASSEMBLIES AND METHODS OF MANUFACTURING THE SAME - Package-on-package systems for packaging semiconductor devices. In one embodiment, a package-on-package system comprises a first semiconductor package device and a second semiconductor package device. The first package device includes a base substrate including a first side having a die-attach region and a peripheral region, a first semiconductor die attached to the base substrate at the die-attach region, wherein the first semiconductor die has a front side facing the first side of the base substrate and a backside spaced apart from the first side of the base substrate by a first distance, and a high density interconnect array in the perimeter region of the base substrate outside of the die-attach region. The interconnect array has a plurality of interconnects that extend from the first side of the base substrate by a second distance greater than the first distance. The second semiconductor device package is electrically coupled corresponding individual interconnects. | 2022-09-15 |
20220293507 | FINGERPRINT SENSOR PACKAGE AND SMART CARD INCLUDING THE SAME - A fingerprint sensor package includes a first substrate including a core insulating layer; a first bonding pad on the core insulating layer; and an external connection pad between an edge of the second surface of the core insulating layer and the first bonding pad, a second substrate on the core insulating layer, the second substrate including: a plurality of first sensing patterns spaced apart in a first direction and extending in a second direction intersecting with the first direction; a plurality of second sensing patterns spaced apart from each other in the second direction and extending in the first direction; and a second bonding pad, a conductive wire connecting the first bonding pad to the second bonding pad; a controller chip on the second substrate; and a molding layer covering the second substrate and the first bonding pad and spaced apart from the external connection pad. | 2022-09-15 |
20220293508 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least one semiconductor die, an interposer, a molding compound and connectors. The interposer has a first surface, a second surface opposite to the first surface and sidewalls connecting the first and second surfaces. The at least one semiconductor die is disposed on the first surface of interposer and electrically connected with the interposer. The molding compound is disposed over the interposer and laterally encapsulates the at least one semiconductor die. The molding compound laterally wraps around the interposer and the molding compound at least physically contacts a portion of the sidewalls of the interposer. The connectors are disposed on the second surface of the interposer, and are electrically connected with the at least one semiconductor die through the interposer. | 2022-09-15 |
20220293509 | DIELECTRIC-TO-METAL ADHESION PROMOTION MATERIAL - An electronic substrate may be formed having at least one metal-to-dielectric adhesion promotion material layer therein. The electronic substrate may comprise a conductive metal trace, a dielectric material layer on the conductive metal trace, and the adhesion promotion material layer between the conductive metal trace and the dielectric material layer, wherein the adhesion promotion material layer comprises an organic adhesion material and a metal constituent dispersed within the organic adhesion material, wherein a metal within the metal constituent has a standard reduction potential greater than a standard reduction potential of the conductive metal trace. | 2022-09-15 |
20220293510 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE STRUCTURE OF WORD-LINE AVOIDING SHORT CIRCUIT THEREOF - A semiconductor device includes: a substrate; a memory cell region provided over the substrate; a peripheral region provided over the substrate and adjacent to the memory cell region; a plurality of word-lines extending across the memory cell region and the peripheral region; and a plurality of contacts connected to edge portions of even numbered ones of the plurality of word-lines in the peripheral region, respectively; wherein a side of each of the edge portions of the even numbered ones of the plurality of word-lines is adjacent a portion missing an odd numbered word-line; and wherein another side of each of the edge portions of the even numbered ones of the plurality of word-lines is adjacent an offcut of another odd numbered word-line. | 2022-09-15 |
20220293511 | SEMICONDUCTOR DEVICE AND POWER AMPLIFIER - A semiconductor device includes a gate wiring line connected to an input wiring line, a first and second transistors disposed on both sides of the gate wiring line, and a signal combining wiring line. The signal combining wiring line includes a first output wiring line that extends on or above the first transistor over at least one source wiring line and at least one gate electrode and that is connected to drain wiring lines of the first transistor, a second output wiring line that extends on or above the second transistor over at least one source wiring line and at least one gate electrode and that is connected to drain wiring lines of the second transistor, a third output wiring line that connects the first and the second output wiring lines, and a fourth output wiring line that connects the third output wiring line to the output terminal. | 2022-09-15 |
20220293512 | CAPPING LAYER OVERLYING DIELECTRIC STRUCTURE TO INCREASE RELIABILITY - Some embodiments relate to a method for forming an integrated chip, the method includes forming a first conductive wire and a second conductive wire over a substrate. A dielectric structure is formed laterally between the first conductive wire and the second conductive wire. The dielectric structure comprises a first dielectric liner, a dielectric layer disposed between opposing sidewalls of the first dielectric liner, and a void between an upper surface of the first dielectric liner and a lower surface of the dielectric layer. A dielectric capping layer is formed along an upper surface of the dielectric structure. Sidewalls of the dielectric capping layer are aligned with sidewalls of the dielectric structure. | 2022-09-15 |
20220293513 | POWER DECOUPLING METAL-INSULATOR-METAL CAPACITOR - Disclosed are examples of a device including a front side metallization portion having a front side BEOL. The device also includes a backside BEOL. The device also includes a substrate, where the substrate is disposed between the backside BEOL and the front side metallization portion. The device also includes a metal-insulator-metal (MIM) capacitor embedded in the backside BEOL. | 2022-09-15 |
20220293514 | SYSTEM ON CHIP AND ELECTRONIC SYSTEM INCLUDING THE SAME - A system on chip includes a processing unit including the first processing circuit and a second processing circuit, a connection circuit configured to form a path connecting one of the first processing circuit and the second processing circuit to an external capacitor, and a controller configured to control the connection circuit based on a state of at least one of the first processing circuit and the second processing circuit. | 2022-09-15 |
20220293515 | VIA LANDING ON FIRST AND SECOND BARRIER LAYERS TO REDUCE CLEANING TIME OF CONDUCTIVE STRUCTURE - In some embodiments, the present disclosure relates to an integrated chip that includes a conductive structure arranged within a substrate or a first dielectric layer. A first barrier layer is arranged on outermost sidewalls and a bottom surface of the conductive structure. A second barrier layer is arranged on outer surfaces of the first barrier layer. The second barrier layer separates the first barrier layer from the substrate or the first dielectric layer. A second dielectric layer is arranged over the substrate or the first dielectric layer. A via structure extends through the second dielectric layer, is arranged directly over topmost surfaces of the first and second barrier layers, and is electrically coupled to the conductive structure through the first and second barrier layers. | 2022-09-15 |
20220293516 | STACKED VIAS WITH BOTTOM PORTIONS FORMED USING SUBTRACTIVE PATTERNING - Disclosed herein are methods for fabricating IC structures that include stacked vias providing electrical connectivity between metal lines of different layers of a metallization stack, as well as resulting IC structures. An example IC structure includes a first and a second metallization layers, including, respectively, a bottom metal line and a top metal line. The IC structure further includes a via that has a bottom via portion and a top via portion, where the top via portion is stacked over the bottom via portion (hence, the via may be referred to as a “stacked via”). The bottom via portion is coupled and self-aligned to the bottom electrically conductive line, while the top via portion is coupled and self-aligned to the top electrically conductive line. The bottom via portion is formed using subtractive patterning, while the top via portion may be formed using a different fabrication technique, such as Damascene fabrication. | 2022-09-15 |
20220293517 | STACKED VIAS WITH BOTTOM PORTIONS FORMED USING SELECTIVE GROWTH - Disclosed herein are methods for fabricating IC structures that include stacked vias providing electrical connectivity between metal lines of different layers of a metallization stack, as well as resulting IC structures. An example IC structure includes a first and a second metallization layers, including, respectively, a bottom metal line and a top metal line. The IC structure further includes a via that has a bottom via portion and a top via portion, where the top via portion is stacked over the bottom via portion (hence, the via may be referred to as a “stacked via”). The bottom via portion is coupled and self-aligned to the bottom electrically conductive line, while the top via portion is coupled and self-aligned to the top electrically conductive line. The bottom via portion is formed using selective growth, e.g., assisted by a self-assembled monolayer (SAM) material. | 2022-09-15 |
20220293518 | INTERCONNECTION STRUCTURE AND MANUFACTURE METHOD THEREOF - An interconnection structure includes a first dielectric layer, a first conduction layer, a conductor pillar, an upper dielectric layer and an upper conduction layer. The first dielectric layer is disposed over a first terminal of a device. The first conduction layer is disposed over the first dielectric layer. The conductor pillar is connected to the first terminal. The upper dielectric layer is disposed over the first conduction layer. The upper conduction layer is disposed over the upper dielectric layer. The conductor pillar connects to the upper conduction layer but disconnects from the first conduction layer. | 2022-09-15 |
20220293519 | SEMICONDUCTOR DEVICE STRUCTURE WITH SERPENTINE CONDUCTIVE FEATURE AND METHOD FOR FORMING THE SAME - The present disclosure relates to a semiconductor device structure with a serpentine conductive feature and a method for forming the semiconductor device structure. The semiconductor device structure includes a conductive pad disposed in a semiconductor substrate, and a first mask layer disposed over the semiconductor substrate. The semiconductor device structure also includes a second mask layer disposed over the first mask layer. The first mask layer and the second mask layer are made of different materials. The semiconductor device structure further includes a conductive feature penetrating through the first mask layer and the second mask layer to connect to the conductive pad. The conductive feature has a serpentine pattern in a top view. | 2022-09-15 |
20220293520 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THEREOF - A method includes forming a first etch stop layer (ESL) over a conductive feature, forming a first dielectric layer on the first ESL, forming a second ESL on the first dielectric layer, forming a second dielectric layer on the second ESL, forming a trench in the second dielectric layer, forming a first opening in a bottom surface of the trench extending through the second dielectric layer, and forming a second opening in a bottom surface of the first opening. The second opening extends through the first dielectric layer and the first ESL. The second opening exposes a top surface of the conductive feature. The method further includes widening the first opening to a second width, filling the trench with a conductive material to form a conductive line, and filling the second opening and the first opening with the conductive material to form a conductive via. | 2022-09-15 |
20220293521 | CONTACT VIA FORMATION - Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes an active region including a channel region and a source/drain region and extending along a first direction, and a source/drain contact structure over the source/drain region. The source/drain contact structure includes a base portion extending lengthwise along a second direction perpendicular to the first direction, and a via portion over the base portion. The via portion tapers away from the base portion. | 2022-09-15 |
20220293522 | Buried Power Rail Architecture - Various implementations described herein are directed to a method for routing buried power rails underneath a memory instance. The method may identify first rails of the buried power rails disposed in a first layer and second rails of the buried power rails disposed perpendicular to the first rails in a second layer. The method may identify long rails of the first rails with a first length and short rails of the first rails with a second length that is less than the first length. The method may separately couple the long rails and the short rails to the second rails with vias that extend between the first layer and the second layer. | 2022-09-15 |
20220293523 | THREE-DIMENSIONAL DEVICE WITH VERTICAL CORE AND BUNDLED WIRING - A semiconductor device includes a buried power rail (BPR) over a substrate and a semiconductor structure over the BPR. The semiconductor structure is tube-shaped and extends along a vertical direction. The semiconductor structure includes a first source/drain (S/D) region over the BPR, a gate region over the first S/D region, and a second S/D region over the gate region. The semiconductor device includes a first S/D interconnect structure extending from the BPR and further into the semiconductor structure such that a top portion of the first S/D interconnect structure is surrounded by the first S/D region. The semiconductor device includes a gate structure that includes (i) a gate oxide formed along an inner surface of the gate region and (ii) a gate electrode formed along sidewalls of the gate oxide in the gate region. The semiconductor device includes a second S/D interconnect structure positioned over the second S/D region. | 2022-09-15 |
20220293524 | STRUCTURE WITH INTERCONNECTION DIE AND METHOD OF MAKING SAME - A structure including a first die, a second die, a first insulating encapsulant, an interconnection die, and a second insulating encapsulant is provided. The first die includes a first bonding structure. The first bonding structure includes a first dielectric layer and a first conductive pad embedded in the first dielectric layer. The second die includes a second bonding structure. The second bonding structure includes a second dielectric layer and a second conductive pad embedded in the second dielectric layer. The first insulating encapsulant laterally encapsulates the first die and the second die. The interconnection die includes a third bonding structure. The third bonding structure includes a third dielectric layer and third conductive pads embedded in the third dielectric layer. The second insulating encapsulant laterally encapsulates the interconnection die. The third bonding structure is in contact with the first bonding structure and the second bonding structure. | 2022-09-15 |