37th week of 2022 patent applcation highlights part 60 |
Patent application number | Title | Published |
20220293125 | MULTIPLE STATE DIGITAL ASSISTANT FOR CONTINUOUS DIALOG - Systems and processes for operating an intelligent automated assistant are provided. For example, a first speech input is received from a user. In response to receiving the first speech input, a response is provided. A first output is provided corresponding to a digital assistant in a first state, and a second speech input is received from the user. A first plurality of values is obtained. Based on the first plurality of values, a first confidence level corresponding to the second speech input is obtained. In accordance with a determination that the first confidence level exceeds a first threshold confidence level, a second output is provided corresponding to the digital assistant in a second state. The second speech input continues to be received. | 2022-09-15 |
20220293126 | INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND PROGRAM - The present technology relates to an information processing apparatus, an information processing method, and a program which can curb occurrence of howling at the time of outputting vibration in response to an input sound. The information processing apparatus of one aspect of the present technology is an apparatus that generates, at the time of outputting vibration in response to an input sound from the outside, a vibration signal representing the vibration having a frequency different from a frequency of the input sound. The present technology can be applied to, for example, smartphones, smart watches, wearable apparatuses, cushions, and music experience apparatuses that vibrate in response to input sounds. | 2022-09-15 |
20220293127 | METHOD OF DETECTING SPEECH AND SPEECH DETECTOR FOR LOW SIGNAL-TO-NOISE RATIOS - The present disclosure relates in a first aspect to a method of detecting speech of incoming sound at a portable communication device. A microphone signal is divided into a plurality of separate frequency band signals from which respective power envelope signals are derived. Onsets of voiced speech of a first frequency band signal are determined based on a first stationary noise power signal and a first clean power signal and onsets of unvoiced speech in a second frequency band signal are determined based on a second stationary noise power signal and second clean power signal. | 2022-09-15 |
20220293128 | SYSTEMS AND METHODS FOR IMPROVED SPEECH AND COMMAND DETECTION - Provided herein are systems and methods for improved speech and command detection. For example, a user utterance may be received by a voice-enabled device. The voice-enabled device and associated system may determine that a first portion of the utterance comprises a complete command, and begin processing the command for execution. Thereafter, the device may receive an additional utterance and determine the additional utterance to be a second portion, related to the first portion, and together with the first portion comprise a different command. The device and associated system can then adjust and process the intended command. | 2022-09-15 |
20220293129 | MAGNETIC DISK DEVICE AND READ/WRITE PROCESSING METHOD - According to one embodiment, a magnetic disk device includes a disk, a head, and a controller setting a rewrite threshold value for executing a rewrite process of different tracks in a first sector group including at least one first sector continuous from a first parity sector in which error correction processing in units of tracks is executable based on the first parity sector and including the first parity sector, and a second sector group including at least one second sector continuous in which the error correction processing in units of tracks is unexecutable, and rewriting the first sector group and the second sector group with different frequencies. | 2022-09-15 |
20220293130 | MAGNETIC DISK DEVICE AND REORDERING METHOD - According to one embodiment, a magnetic disk device includes a first head which writes and reads to the first disk, a second head which writes data and reads data to the second disk, a first actuator including the first head, a second actuator including the second head, and a controller which performs a first reordering process for a command scored in a first queue corresponding to the first actuator and performs a second reordering process for a command stored in a second queue corresponding to the second actuator, wherein the controller selects a first command to be executed next by the first actuator based on current and future operating states of the second actuator, and executes the first command. | 2022-09-15 |
20220293131 | ROTATING RAMP WITH RETRACTION CAPABILITY FOR A DISK DRIVE - A data storage system include a disk drive having a rotating ramp assembly that may be moved between an engaged and disengaged position. The rotating ramp assembly may include a ramp extension that is not disposed in overlapping relation to a data storage disk location in the drive when in the disengaged position. However, in the engaged position, the ramp extension may overhang a portion of the data storage disk location. In turn, the head extension may include a ramp surface that allows a head assembly to move to a head parking surface when the rotating ramp assembly is in the engaged position. IN turn, the rotating ramp assembly may be rotated while maintaining the head assembly on the head parking surface, which may be arcuate and extend about at least a portion of the rotating ramp assembly. | 2022-09-15 |
20220293132 | SCALABLE STORAGE DEVICE - Implementations described and claimed herein provide a high-capacity, high-bandwidth scalable storage device. The scalable storage device includes a layer stack including at least one memory layer and at least one optical control layer positioned adjacent to the memory layer. The memory layer includes a plurality of memory cells and the optical control layer is adapted to receive optically-encoded read/write signals and to effect read and write operations to the plurality of memory cells through an electrical interface. | 2022-09-15 |
20220293133 | AUTOMATED VIDEO EDITING - A method of generating a modified video file using one or more processors is disclosed. The method comprises detecting objects that are represented in an original video file using computer vision object-detection techniques, determining object motion characteristics for the detected objects, based on a specific object motion characteristic for a specific detected object meeting certain requirements, selecting a corresponding audio or visual effect, and applying the corresponding visual effect to the original video file to create the modified video file. | 2022-09-15 |
20220293134 | METHOD AND SYSTEM FOR REALIZING INTELLIGENT MATCHING AND ADDING OF RHYTHMIC TRACKS - The present disclosure provides a method and a system for realizing intelligent matching and adding of rhythmic tracks. In one example, a method is provided, including: pre-storing a plurality of music elements; generating a rhythmic track library according to the plurality of music elements, the rhythmic track library including a plurality of rhythmic tracks based on the plurality of music elements; detecting a BPM of original music, and calculating a time interval between every two beats based on the detected BPM of the original music; selecting one or more rhythmic tracks from the rhythmic track library, and assigning a time parameter to the one or more rhythmic tracks based on the time interval so as to match the rhythm of the original music; and adding the one or more rhythmic tracks assigned with the time parameter into the original music so as to combine with the original music and play. | 2022-09-15 |
20220293135 | USER-GENERATED TEMPLATES FOR SEGMENTED MULTIMEDIA PERFORMANCE - Disclosed herein are computer-implemented method, system, and computer-readable storage-medium embodiments for implementing user-generated templates for segmented multimedia performances. An embodiment includes at least one computer processor configured to transmit a first version of a content instance and corresponding metadata. The first version of the content instance may include a plurality of structural elements, with at least one structural element corresponding to at least part of the metadata. The first content instance may be transformed by a rendering engine triggered by the at least one computer processor. | 2022-09-15 |
20220293136 | METHOD AND APPARATUS FOR DISPLAYING MUSIC POINTS, AND ELECTRONIC DEVICE AND MEDIUM - Disclosed are a method and apparatus for displaying music points, and an electronic device and a medium. One specific embodiment of the method includes: acquiring audio material; analyzing initial music points in the audio material, wherein the initial music points include beat points and/or note starting points in the audio material; and on an operation interface of video clipping, displaying, according to the position of the audio material on a clip timeline and the positions of target music points in the audio material, identifiers of the target music points on the clip timeline, wherein the target music points are some of or all of the initial music points. According to the embodiment, the time for a user to process audio material and to make music points is reduced, and the flexibility of tools is also guaranteed. | 2022-09-15 |
20220293137 | SEMICONDUCTOR MEMORY PACKAGE STRUCTURE AND SEMICONDUCTOR MEMORY SYSTEM - A semiconductor memory package structure includes at least one semiconductor die and a lead group. The at least one semiconductor die includes a chip enable terminal. The lead group is configured to electrically connect the chip enable terminal to an external circuit board and includes a first pin and a second pin coupled to the chip enable terminal. The at least one semiconductor die and the lead group are formed as an integral entity using an insulating material. | 2022-09-15 |
20220293138 | SEMICONDUCTOR DEVICE - A semiconductor device of an embodiment includes: a wiring board having a first surface and a second surface on a side opposite to the first surface; a first semiconductor element on the first surface of the wiring board; a second semiconductor element on the first surface of the wiring board; and a first sealing material that seals at least the second semiconductor element. A slit is formed in the first sealing material between the first semiconductor element and the second semiconductor element. When a thickness of the first sealing material on the first semiconductor element is t | 2022-09-15 |
20220293139 | MEMORY DEVICE WITH SPLIT POWER SUPPLY CAPABILITY - A memory device includes a printed circuit board having a plurality of conductive layers; memory chips mounted over the printed circuit board, wherein the memory chips comprise at least a first number of memory chips and a second number of memory chips; a first power module mounted over the printed circuit board and for providing a first set of power supplies to the first number of memory chips through the plurality of conductive layers; and a second power module mounted over the printed circuit board and for providing a second set of power supplies to the second number of memory chips through the plurality of conductive layers. | 2022-09-15 |
20220293140 | HEATER DEVICES FOR MICROELECTRONIC DEVICES AND RELATED MICROELECTRONIC DEVICES, MODULES, SYSTEMS AND METHODS - A memory device includes at least one die and a heater device. The heater device includes a first switch element electrically connected to a power supply connection and the at least one die, a second switch element electrically connected to the first switch element, and a resistive element electrically connected to the second switch element and a ground connection. A method includes configuring the first switching element of the heater device to electrically connect the second switching element of the heater device to a power supply connection, configuring the second switching element to electrically connect one of a first resistor or a second resistor of the resistive element to the first switching element, and applying an voltage across the first resistor or the second resistor that is electrically connected to the first switching element. | 2022-09-15 |
20220293141 | SENSE AMPLIFIER AND OPERATING METHOD FOR NON-VOLATILE MEMORY WITH REDUCED NEED ON ADJUSTING OFFSET TO COMPENSATE THE MISMATCH - A sense amplifier includes a voltage comparator with offset compensation, a first clamping device and a second clamping device. The voltage comparator is coupled to a bit line and a reference bit line respectively, and configured to compare a first input voltage and a second input voltage to output a sensing signal. The first clamping circuit and the second clamping circuit trim a voltage corresponding to the bit line and a voltage corresponding to the reference bit line respectively to match the voltage corresponding to the reference bit line with the voltage corresponding to the bit line. | 2022-09-15 |
20220293142 | CALIBRATION DEVICE - A calibration device which is configured for calibrating a memory is provided. The calibration device includes an input terminal, a first pull-up circuit, and a first comparator. The input terminal is coupled to an external resistor. The first pull-up circuit is coupled to the input terminal, and configured to receive a power supply voltage. The first pull-up circuit includes a plurality of first pull-up units. The first pull-up units are coupled to each other in parallel. The first comparator is coupled to the input terminal. The first comparator is configured to receive a proportion voltage which is corresponding to the power supply voltage, and output a first control signal to the first pull-up units, such that a resistance of each of the first pull-up units is equal to a resistance of the external resistor. | 2022-09-15 |
20220293143 | APPARATUSES AND METHODS INCLUDING MULTILEVEL COMMAND AND ADDRESS SIGNALS - Multilevel command and address (CA) signals are used to provide commands and memory addresses from a controller to a memory system. Using multilevel signals CA signals may allow for using fewer signals compared to binary signals to represent a same number of commands and/or address space, or using a same number of multilevel CA signals to represent a larger number of commands and/or address space. A number of external command/address terminals may be reduced without reducing a set of commands and/or address space. Alternatively, a number of external terminals may be maintained, but provide for an expanded set of commands and/or address space. | 2022-09-15 |
20220293144 | APPARATUSES AND METHODS INCLUDING MULTILEVEL COMMAND AND ADDRESS SIGNALS - Multilevel command and address (CA) signals are used to provide commands and memory addresses from a controller to a memory system. Using multilevel signals CA signals may allow for using fewer signals compared to binary signals to represent a same number of commands and/or address space, or using a same number of multilevel CA signals to represent a larger number of commands and/or address space. A number of external command/address terminals may be reduced without reducing a set of commands and/or address space. Alternatively, a number of external terminals may be maintained, but provide for an expanded set of commands and/or address space. | 2022-09-15 |
20220293145 | APPARATUSES AND METHODS INCLUDING MULTILEVEL COMMAND AND ADDRESS SIGNALS - Multilevel command and address (CA) signals are used to provide commands and memory addresses from a controller to a memory system. Using multilevel signals CA signals may allow for using fewer signals compared to binary signals to represent a same number of commands and/or address space, or using a same number of multilevel CA signals to represent a larger number of commands and/or address space. A number of external command/address terminals may be reduced without reducing a set of commands and/or address space. Alternatively, a number of external terminals may be maintained, but provide for an expanded set of commands and/or address space. | 2022-09-15 |
20220293146 | APPARATUSES AND METHODS INCLUDING MULTILEVEL COMMAND AND ADDRESS SIGNALS - Multilevel command and address (CA) signals are used to provide commands and memory addresses from a controller to a memory system. Using multilevel signals CA signals may allow for using fewer signals compared to binary signals to represent a same number of commands and/or address space, or using a same number of multilevel CA signals to represent a larger number of commands and/or address space. A number of external command/address terminals may be reduced without reducing a set of commands and/or address space. Alternatively, a number of external terminals may be maintained, but provide for an expanded set of commands and/or address space. | 2022-09-15 |
20220293147 | APPARATUSES AND METHODS INCLUDING MULTILEVEL COMMAND AND ADDRESS SIGNALS - Multilevel command and address (CA) signals are used to provide commands and memory addresses from a controller to a memory system. Using multilevel signals CA signals may allow for using fewer signals compared to binary signals to represent a same number of commands and/or address space, or using a same number of multilevel CA signals to represent a larger number of commands and/or address space. A number of external command/address terminals may be reduced without reducing a set of commands and/or address space. Alternatively, a number of external terminals may be maintained, but provide for an expanded set of commands and/or address space. | 2022-09-15 |
20220293148 | Low Power and Robust Level-Shifting Pulse Latch for Dual-Power Memories - A level-shifting pulse latch is provided for a self-timed memory clock signal for a memory. The level-shifting pulse latch includes a system-power-domain-to-memory-power-domain level-shifter that inverts and level-shifts a system clock signal into an inverted version of the system clock signal. A pass transistor controls whether the inverted version of the system clock signal drives a memory-power-domain latch to produce the self-timed memory clock signal. | 2022-09-15 |
20220293149 | MEMORY SYSTEM - According to one embodiment, there is provided a memory system including a controller, a plurality of memory chips, and a channel. The controller outputs a clock signal, a timing control signal and a data signal. Each of the plurality of memory chips includes at least a clock input terminal, a timing control input terminal, a timing control output terminal, a data input terminal and a data output terminal. The channel includes a loop bus which connects the controller and the plurality of memory chips in a ring shape. The controller is able to control operation timings of the memory chips by transmitting the clock signal and the timing control signal to the plurality of memory chips via the channel. | 2022-09-15 |
20220293150 | MONOTONIC COUNTER - A monotonic counter stores N binary words representing a value in N memory cells. When i memory cells of consecutive ranks between k modulo N and k+i modulo N each represent a value complementary to a null value, the counter is incremented by erasing a value of a memory cell of rank k+i+1 modulo N. When i+1 memory cells of consecutive ranks between k+1 modulo N and k+i+1 modulo N each represent the value complementary to the null value, the counter is incremented by incrementing a value of a memory cell of rank k modulo N by two step sizes and storing a result in a memory cell of rank k+1 modulo N, wherein, N is an integer greater than or equal to five, k is an integer, and i is an integer between 2 and N−3. | 2022-09-15 |
20220293151 | MONOTONIC COUNTER - The present disclosure relates to a monotonic counter whose value is represented by a number N of binary words of N memory cells of a non-volatile memory, and being able to implement a step increment operation wherein if only one first memory cell represents a first value different from zero, then a second value equal to the said first value incremented by two times the said step is written into a second memory cell of rank directly higher than the rank of the first memory cell; and if a third and a fourth memory cell of consecutive ranks represent, respectively, a third value and a fourth value different from zero, then the third value of the third memory cell of lower rank is erased. | 2022-09-15 |
20220293152 | RANDOM ACCESSING - A random number generator selects addresses while a ‘scoreboard’ bank of registers (or bits) tracks which addresses have already been output (e.g., for storing or retrieval of a portion of the data.) When the scoreboard detects an address has already been output, a second address which has not been used yet is output rather than the randomly selected one. The second address may be selected from nearby addresses that have not already been output. | 2022-09-15 |
20220293153 | SYSTEMS AND METHODS FOR ADAPTIVE WRITE TRAINING OF THREE DIMENSIONAL MEMORY - A memory system is provided. The memory system includes a memory controller and a data bus electrically coupled to the memory controller. The memory system further includes one or more memory devices communicatively coupled to the memory controller via the data bus, wherein each of the one or more memory devices comprises a write training setting configured to adjust a write timing of data being sent by the memory controller to the one or more memory devices during write operations of the memory system. | 2022-09-15 |
20220293154 | OPERATING METHOD OF MEMORY DEVICE FOR EXTENDING SYNCHRONIZATION OF DATA CLOCK SIGNAL, AND OPERATING METHOD OF ELECTRONIC DEVICE INCLUDING THE SAME - Disclosed is an operating method of a memory device communicating with a memory controller, which includes receiving a first command from the memory controller, the first command indicating initiation of synchronization of a data clock signal and defining a clock section corresponding to the synchronization, preparing a toggling of the data clock signal during a preparation time period, processing a first data stream based on the data clock signal toggling at a reference frequency, and processing a second data stream based on the data clock toggling at the reference frequency and extended for a period of the defined first clock section. | 2022-09-15 |
20220293155 | STORAGE DEVICE - A storage device includes a first interconnection, a second interconnection, a memory cell connected between the first and second interconnections and including a variable resistance element and a switching element that is connected in series to the variable resistance element, and a control circuit configured to exercise control of a read operation to read data stored in the memory cell. The control circuit exercises control in such a manner as to set the first interconnection which has been charged with a first voltage and the second interconnection which has been charged with a second voltage into floating states, to set the switching element into an on-state by discharging the second interconnection set into the floating state to thereby increase a voltage applied to the memory cell, and to read the data stored in the memory cell in a state in which the switching element is set into the on-state. | 2022-09-15 |
20220293156 | SIGNAL AMPLIFICATION IN MRAM DURING READING - A control circuit is configured to connect to a cross-point memory array in which each conductive line, such as a bit line or word line, is connected to a transistor pair comprising a pMOSFET in parallel with an nMOSFET. When selecting a memory cell to be read, a voltage of a first conductive line may be pulled up using the pMOSFET in a conductive state while the nMOSFET is in a non-conductive state. Further, when reading the selected memory cell, the parallel nMOSFET of the first conductive line may be in a conductive state. | 2022-09-15 |
20220293157 | MEMRISTOR ELEMENT, SYNAPSE ELEMENT AND NEUROMORPHIC PROCESSOR INCLUDING THE SAME - Disclosed are a memristor element, a synapse element and a neuromorphic processor including the same. The memristor element includes a free layer including a domain wall; and a fixed layer including a material of which a magnetization direction is fixed, wherein a position of the domain wall in the free layer is changeable based on a spin orbit torque (SOT) generated by a current introduced from an outside, and wherein a resistance value, measured through both ends of the fixed layer, is based on the position of the domain wall and on a Hall voltage. | 2022-09-15 |
20220293158 | SEMICONDUCTOR MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF - A semiconductor device comprises a first conductive structure extending along a vertical direction and a second conductive structure extending along the vertical direction. The second conductive structure is spaced apart from the first conductive structure along a lateral direction. The semiconductor device further comprises a plurality of third conductive structures each extending along the lateral direction. The plurality of third conductive structures are disposed across the first and second conductive structures. The first and second conductive structures each have a varying width along the lateral direction. The plurality of third conductive structures are configured to be applied with respective different voltages in accordance with the varying width of the first and second conductive structures. | 2022-09-15 |
20220293159 | SEMICONDUCTOR DEVICE - A semiconductor device in which a memory region at each level of a memory device can be changed is provided. The semiconductor device includes a memory device including a first and a second memory circuit and a control circuit. The first memory circuit includes a first capacitor and a first transistor which has a function of holding charges held in the first capacitor. The second memory circuit includes a second transistor, a second capacitor which is electrically connected to a gate of the second transistor, and a third transistor which has a function of holding charges held in the second capacitor. The first and the third transistors each have a semiconductor layer including an oxide semiconductor, a gate, and a back gate. The voltage applied to the back gate of the first or the third transistor is adjusted, whereby the memory region of each of the first and the second memory circuit is changed. | 2022-09-15 |
20220293160 | REFRESH CIRCUIT AND MEMORY - Embodiments of the present disclosure provide a refresh circuit and a memory. The refresh circuit includes: a row hammer address generation module, configured to receive a row activate command, a precharge command, and a single row address corresponding to the row activate command, and output a row hammer address corresponding to the single row address, where each of the single row addresses corresponds to a word line, the row activate command is configured to activate a word line pointed to by the single row address, and the precharge command is configured to inactivate the word line; and output the row hammer address if a single activation time of the word line is greater than a preset time; and a signal selector, configured to receive the row hammer address and a regular refresh address, and at least output the row hammer address. | 2022-09-15 |
20220293161 | REFRESH CONTROL CIRCUIT AND MEMORY - The present disclosure provides a refresh control circuit and a memory. The refresh control circuit includes: a random capture module, configured to sequentially receive n single row addresses and randomly output m single row addresses among the n single row addresses, wherein the n>the m>1; a row hammer address generation module, connected to an output terminal of the random capture module, configured to analyze a single row address with highest frequency of occurrence among the m single row addresses, and configured to output a row hammer address corresponding to the single row address with highest frequency of occurrence; and a signal selector, configured to receive a conventional refresh address and the row hammer address and output address information, the address information being the row hammer address and the conventional refresh address, or the address information being the row hammer address. | 2022-09-15 |
20220293162 | RANDOMIZATION OF DIRECTED REFRESH MANAGEMENT (DRFM) PSEUDO TARGET ROW REFRESH (PTRR) COMMANDS - In a memory subsystem, a controller can randomize the sending of directed refresh management (DRFM) commands for DRFM commands that hit multiple banks at a time. The controller can generate commands to indicate the memory device should capture addresses for various banks to use for pseudo target row refresh (pTRR) operations based on addresses associated with activate commands. The controller can randomize the indication of address capture for the memory device. With captured addresses and DRFM commands generated at random, the system can make better use of DRFM commands because the multiple banks are more likely to have addresses for pTRR, and randomization can reduce the ability for a row hammer attack to avoid the DRFM. | 2022-09-15 |
20220293163 | COLUMN SELECTOR ARCHITECTURE WITH EDGE MAT OPTIMIZATION - A memory mat architecture is presented where a column decoder is disposed within the memory array. The location of the column decoder reduces a distance between the column decoder and a target memory cell and thus reduces a distance that a column select signal travels from the column decoder to the target memory cell. A single predecoder is disposed in a bank controller for the memory array. The column decoder may be disposed in the middle of the memory array or offset from the middle near the far edge of the memory array opposite the bank controller. The location of the column decoder enables a reduced array access time to obtain data from the target memory cell. | 2022-09-15 |
20220293164 | Semiconductor Device and Method for Driving Semiconductor Device - The semiconductor device includes a first memory cell, and a second memory cell thereover. The first memory cell includes first and second transistors, and a first capacitor. The second memory cell includes third and fourth transistors, and a second capacitor. A gate of the first transistor is electrically connected to one of a source and a drain of the second transistor and the first capacitor. A gate of the third transistor is electrically connected to one of a source and a drain of the fourth transistor and the second capacitor. One of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the third transistor. The second and fourth transistors include an oxide semiconductor. A channel length direction of the first and third transistors is substantially perpendicular to a channel length direction of the second and fourth transistors. | 2022-09-15 |
20220293165 | Memory Device Having Variable Impedance Memory Cells and Time-To-Transition Sensing of Data Stored Therein - The present disclosure relates to circuits, systems, and methods of operation for a memory device. In an example, a memory device includes a plurality of memory cells, each memory cell having a variable impedance that varies in accordance with a respective data value stored therein; and a read circuit configured to read the data value stored within a selected memory cell based upon a variable time delay determination of a signal node voltage change corresponding to the variable impedance of the selected memory cell. | 2022-09-15 |
20220293166 | APPARATUSES AND METHODS FOR SKETCH CIRCUITS FOR REFRESH BINNING - Apparatuses, systems, and methods for sketch circuits for refresh binning. The rows of a memory may have different information retention times. The row addresses may be sorted into different bins based on these information retention times. In order to store information about which row addresses are associated with which bins a sketch circuit may be used. When an address is generated as part of a refresh operation, it may be used to generate a number of different hash values, which may be used to index entries in a storage structure. The entries may indicate which bin the address is associated with. Based on the binning information, the memory may refresh the address at different rates (e.g., by determining whether to provide the address as a refresh address or not). | 2022-09-15 |
20220293167 | REFRESH CONTROL CIRCUIT AND MEMORY - A refresh control circuit includes: a random output sub-circuit for sequentially receiving n single-row addresses and m single-row addresses in L single-row addresses, a single enabling duration of word lines pointed to by the n single-row addresses being greater than a preset duration, the m single-row addresses ranking top m in occurrence frequency, the L single-row addresses corresponding to word lines turned on between adjacent refresh commands, n being a natural number, and m being a positive integer; and for receiving a first random number which is a positive integer less than or equal to n+m, and then outputting an i-th received single-row address, i being equal to the first random number; and a row hammer address generation sub-circuit for outputting a row hammer address corresponding to the received single-row address acting as a refresh object corresponding to the refresh command. | 2022-09-15 |
20220293168 | ELECTRONIC DEVICE FOR CONTROLLING COMMAND INPUT - An electronic device includes a command generation circuit configured to generate a refresh command and a driving control signal, which are enabled during an all-bank refresh operation, according to a logic level combination of an internal chip selection signal and an internal command address. The electronic device also includes a buffer control circuit configured to generate, from the refresh command and the driving control signal, a first buffer enable signal for enabling a first group of buffers and a second buffer enable signal for enabling a second group of buffers. | 2022-09-15 |
20220293169 | APPARATUSES, SYSTEMS, AND METHODS FOR CONTROLLER DIRECTED TARGETED REFRESH OPERATIONS - Apparatuses, systems, and methods for controller directed targeted refresh operations. A memory may be coupled to a controller. The memory may identify aggressor addresses based on sampled addresses. The addresses may be sampled based on internal timing logic of the memory and also based on a sampling command received from the controller. The memory may also receive a controller identified aggressor address from the controller. The memory may refresh one or more victim word lines of the identified (either by the memory or the controller) aggressor addresses as part of a targeted refresh operation. Victims of controller identified aggressor addresses may be refreshed before memory identified aggressor addresses. | 2022-09-15 |
20220293170 | INTEGRATED SCALING AND STRETCHING PLATFORM FOR OPTIMIZING MONOLITHIC INTEGRATION AND/OR HETEROGENEOUS INTEGRATION IN A SINGLE SEMICONDUCTOR DIE - The present invention provides a single monolithic the comprising a first schematic circuit manufactured based on a first technology node. A die area of the single monolithic die is smaller than a die area of another monolithic die with a second schematic circuit made based on the first technology node, wherein the first schematic circuit is the same as the second schematic circuit, and the first schematic circuit is a SRAM circuit, a logic circuit, a combination of SRAM and logic circuit, or a major function block circuit. | 2022-09-15 |
20220293171 | STORAGE DEVICE - According to one embodiment, a storage device includes first wirings extending in a first direction and second wirings extending in a second direction. A memory cells are connected between the first wirings and the second wirings and include a variable resistance memory element. A first drive circuit is provided for supplying voltages to the first wirings, and a second drive circuit is provided for supplying voltages to the second wirings. The first drive circuit applies a first voltage to a selected first wiring, the second drive circuit applies a second voltage to a selected second wiring. A voltage between the second voltage and one-half of the sum of the first and second voltages is applied to a non-selected first wiring, and a voltage between the first voltage and one-half of the sum of the first and second voltages is applied to a non-selected second wiring. | 2022-09-15 |
20220293172 | RESISTIVE MEMORY DEVICE WITH BOUNDARY AND EDGE TRANSISTORS COUPLED TO EDGE BIT LINES - A resistive memory device includes a first bit line group including a first edge bit line, a second bit line group including a second edge bit line, and a first boundary transistor configured to apply a non-selection voltage to the second edge bit line according to a selection of the first edge bit line. The first edge bit line of the first bit line group is disposed closest to the second bit line group, and the second edge bit line of the second bit line group is disposed closest to the first bit line group. | 2022-09-15 |
20220293173 | AUTO-CALIBRATING CROSSBAR-BASED APPARATUSES - Aspects of the present disclosure provide a method for calibrating crossbar-based apparatuses. The method includes obtaining output data of a crossbar-based apparatus may include a plurality of cross-point devices with tunable conductance, where the output data of the crossbar-based apparatus represents computing results of at least one operation performed by the crossbar-based apparatus, and where the output data corresponding to a plurality of settings of a plurality of analog components of the crossbar-based apparatus. The method also includes obtaining, by a processing device, one or more calibration parameters based on the output data of the crossbar-based apparatus, where the one or more calibration parameters correspond to one or more errors associated with one or more of the analog components of the crossbar-based apparatus. The method further includes calibrating the crossbar-based apparatus using the one or more calibration parameters. | 2022-09-15 |
20220293174 | RESISTIVE MEMORY DEVICE FOR MATRIX-VECTOR MULTIPLICATIONS - A device for performing a matrix-vector multiplication of a matrix with a vector. The device comprising a memory crossbar array comprising a plurality of row lines, a plurality of column lines and a plurality of junctions arranged between the plurality of row lines and the plurality of column lines. Each junction comprises a programmable resistive element and an access element for accessing the programmable resistive element. The memory crossbar array further comprises one or more write-assist wires and one or more corresponding arrays of switching elements. The write-assist wires are connectable via the switching elements to the plurality of column lines. | 2022-09-15 |
20220293175 | METHOD FOR PROGRAMMING MEMORY - A method includes setting a current level of a write signal to a first non-zero value for a first period of time. The write signal is provided to a memory element during the first period of time. The current level of the write signal is adjusted from the first non-zero value to a second non-zero value, different from the first non-zero value, for a second period of time. The write signal is provided to the memory element during the second period of time. The current level of the write signal is adjusted from the second non-zero value to a third value, different from the first non-zero value and different from the second non-zero value, for a third period of time. The write signal is provided to the memory element during the third period of time. | 2022-09-15 |
20220293176 | MEMORY DEVICE - According to one embodiment, a memory device includes: a memory cell including a memory element and a switching element; and a circuit that applies a first write pulse having a first polarity to the memory cell at the time of writing first data in the memory cell and applies a second write pulse having a second polarity different from the first polarity to the memory cell at the time of writing second data in the memory cell. The switching element has polarity dependence according to the first and second polarities. | 2022-09-15 |
20220293177 | RESISTIVE MEMORY DEVICE AND METHOD OF PROGRAMMING THE SAME - A method of programming a resistive memory device, and a corresponding resistive memory device, which includes the resistive memory device, in response to a write command, applying a write pulse to a selected memory cell arranged in a region where a selected word line intersects with a selected bit line; and after the applying the write pulse, applying a dummy pulse to at least one unselected memory cell. The at least one unselected memory cell is connected to at least one of the selected word line, the selected bit line, a first word line adjacent to the selected word line, and a first bit line adjacent to the selected bit line. | 2022-09-15 |
20220293178 | RESISTANCE CHANGE MEMORY CELL CIRCUITS AND METHODS - The gate of the access transistor of a 1 transistor 1 resistor (1T1R) type RRAM cell is biased relative to the source of the access transistor using a current mirror. Under the influence of a voltage applied across the 1T1R cell (e.g., via the bit line), the RRAM memory element switches from a higher resistance to a lower resistance. As the RRAM memory element switches from the higher resistance to the lower resistance, the current through the RRAM cell switches from being substantially determined by the higher resistance of the RRAM device (while the access transistor is operating in the linear region) to being substantially determined by the saturation region operating point of the access transistor. | 2022-09-15 |
20220293179 | Masking circuit and pre-charge circuit applicable to content addressable memory - A masking circuit of a content addressable memory (CAM) includes a masking control circuit and a level control circuit. The masking control circuit generates a masking signal according to a word line (WL) signal and a write enablement (WE) signal. When both the WL and WE signals are at a first level, the masking signal is a first masking signal; when they are at different levels respectively, the masking signal is a second masking signal. The level control circuit generates a level control signal according to the masking signal for determining whether to pull a voltage level of a match line of the CAM to a predetermined level. When the masking signal is the first masking signal, the level control circuit pulls the voltage level to the predetermined level; and when the masking signal is the second masking signal, the level control circuit does not interfere in the voltage level. | 2022-09-15 |
20220293180 | SEMICONDUCTOR DEVICES AND DATA STORAGE SYSTEMS INCLUDING THE SAME - Provided are semiconductor devices and data storage systems including the same. The semiconductor devices may include first and second separation structures parallel to each other, a block between the first and second separation structures, and bit lines on the block. The block includes strings, the bit lines include a first bit line electrically connected to first and second strings, each of the strings includes a lower select transistor, memory cell transistors, and upper select transistors connected in series, the upper select transistors in each of the strings include a first upper select transistor and a second upper select transistor below the first upper select transistor. The first upper select transistors of the first and second strings may share a single first upper select gate electrode. Gate electrodes of the lower select transistors of the first and second strings may include surfaces coplanar with each other. | 2022-09-15 |
20220293181 | TRACKING OPERATIONS PERFORMED AT A MEMORY DEVICE - A system includes a memory device and a processing device coupled to the memory device. The processing device is to perform operations including maintaining a counter to track a number of memory access operations performed on a range of consecutive wordlines in a block of the memory device. The operations further include determining that the number of memory access operations performed on the range of consecutive wordlines satisfies a threshold criterion. The operations further include, responsive to the number of memory access operations performed on the range of consecutive wordlines satisfying the threshold criterion, causing a memory management operation to be performed at each wordline of the range of consecutive wordlines in the block of the memory device. | 2022-09-15 |
20220293182 | ESTIMATING RESISTANCE-CAPACITANCE TIME CONSTANT OF ELECTRICAL CIRCUIT - Described are systems and methods for estimating the resistance-capacitance time constant of an electrical circuit (e.g., of a wordline of a memory device). An example system comprises: a memory device comprising a plurality of memory cells electrically coupled to a plurality of wordlines; a resistance-capacitance (RC) measurement circuit to measure a voltage at a specified wordline of the plurality of wordlines; and a processing device coupled to the memory device. The processing device is configured to: apply an initial voltage to a selected wordline of the plurality of wordlines; discharge the selected wordline for a discharge period of time; float the selected wordline until a voltage at the selected wordline is stabilized; determine, by the RC measurement circuit, a stabilized voltage at the selected wordline; and estimate, based on the stabilized voltage, an RC time constant of the wordline. | 2022-09-15 |
20220293183 | ADAPTIVE TEMPERATURE COMPENSATION FOR MEMORY DEVICES - In one embodiment, a memory system receives a request to perform a memory access operation, the request identifying a memory cell in a segment of the memory system comprising at least a portion of the memory device. The system determines that an operating temperature of the memory device satisfies a threshold criterion. Responsive to determining that the operating temperature of the memory device satisfies the threshold criterion, the system determines a temperature compensation value corresponding to an access control voltage adjustment value specific to the segment of the memory system. The system adjusts, based on an amount represented by the temperature compensation value, an access control voltage applied to the memory cell during the memory access operation. | 2022-09-15 |
20220293184 | TEMPERATURE-DEPENDENT OPERATIONS IN A MEMORY DEVICE - A method and system for temperature-dependent operations in a memory device are described. Temperature measurements of a memory device are recorded. A determination that a temperature measurement of the memory device satisfies a threshold temperature value is performed. In response to the determination, execution of a background operation in the memory device is delayed, and host system operation(s) continue to be executed in the memory device while execution of the background operation is delayed. | 2022-09-15 |
20220293185 | MEMORY CONTROL METHOD, MEMORY STORAGE DEVICE, AND MEMORY CONTROL CIRCUIT UNIT - A memory control method, a memory storage device, and a memory control circuit unit are provided. The memory control method includes: programming multiple first memory cells in a first physical erasing unit in a rewritable non-volatile memory module; and applying an electronic pulse to at least one word line in the rewritable non-volatile memory module. The at least one word line is coupled to multiple second memory cells in the first physical erasing unit. The second memory cells include the first memory cells. The electronic pulse is not configured to read, program, or erase the second memory cells. | 2022-09-15 |
20220293186 | MEMORY CONTROLLER AND METHOD OF OPERATING THE MEMORY CONTROLLER - A memory controller that controls a memory device including a memory block includes an initial program controller configured to control the memory device to program at least one or more monitoring memory cells from among memory cells respectively connected to monitoring word lines from among a plurality of word lines connected to the memory block, a pre-read controller configured to generate a shifting information of a threshold voltage distribution of the monitoring memory cells based on a result of reading the monitoring memory cells before a read operation is performed on the memory block, and a pre-program controller configured to control the memory device to perform the read operation after applying a pre-program voltage having a voltage level determined according to the shifting information to the plurality of word lines. | 2022-09-15 |
20220293187 | OPEN BLOCK-BASED READ OFFSET COMPENSATION IN READ OPERATION OF MEMORY DEVICE - Open block-based read offset compensation in read operation of memory device is disclosed. For example, a memory device includes an array of memory cells arranged in a plurality of blocks and a peripheral circuit coupled to the array of memory cells. The peripheral circuit is configured to, in response to a block of the plurality of blocks being an open block, perform a read operation on a memory cell of the array of memory cells in the block using a compensated read voltage. The compensated read voltage has an offset from a default read voltage of the block. | 2022-09-15 |
20220293188 | SEMICONDUCTOR MEMORY DEVICE WITH WRITE DISTURB REDUCTION - A semiconductor memory device implements a write disturb reduction method to reduce write disturb on unselected memory cells by alternating the order of the write logical “1” step and write logical “0” step in the write operations of selected memory cells associated with the same group of bit lines. In one embodiment, a method in an array of memory cells includes performing write operation on the memory cells in one of the memory pages to store write data into the memory cells where the write operation includes a first write step of writing a data of a first logical state and a second write step of writing data of a second logical state; and performing the write operation for each row of memory cells by alternately performing the first write step followed by the second write step and performing the second write step followed by the first write step. | 2022-09-15 |
20220293189 | WEAK ERASE PULSE - Systems, apparatuses and methods may provide for technology that biases a word line of a block in NAND memory to a first voltage level, biases a source-side select gate and a drain-side select gate of the block to a second voltage level, and issues a discharge erase pulse to bitlines and a source of the block, wherein the discharge erase pulse is issued at a third voltage level, wherein the third voltage level is greater than the first voltage level and the second voltage level, and wherein the third voltage level is less than a fourth voltage level of a standard erase pulse. In one example, the discharge erase pulse injects holes into pillars of the block and bypasses an erase of cells in the pillars of the block. | 2022-09-15 |
20220293190 | MEMORY DEVICE AND METHOD OF READING DATA - A non-volatile memory includes a memory cell region including an outer region proximate a first end of the memory cell region and an inner region separated from the first end by the outer region, first and second bit lines, an outer memory cell string including memory cells connected to an outer pillar extending vertically upward through the outer region, and an inner memory cell string including memory cells connected to an inner pillar extending vertically upward through the inner region, and a data input/output (I/O). The data I/O circuit includes a page buffer circuit that connects the first bit line during a first read operation directed to memory cells of the outer memory cell string, and connects the second bit line during a second read operation directed to memory cells of the inner memory cell string, and a read voltage determination unit that selects a first optimal read voltage used during the first read operation, and a second optimal read voltage used during the second read operation. | 2022-09-15 |
20220293191 | Dynamic Valley Searching in Solid State Drives - A storage device can reorganize a sequentially performed calibration task and delegate various steps of the task to multiple memory planes. By utilizing a characteristic that provides for similar memory device responses across multiple planes, the calibration task processed on one memory plane can be applied to another memory plane within the device. In this way, partial calibration data may be generated across a plurality of memory planes, and subsequently pooled together to generate a unified calibration data that can be utilized on each of the plurality of planes to do a full calibrated read on memory devices, thus reducing the amount of time needed to perform a calibrated read. Reduced times for calibrated reads allows for increased resolution of threshold valley scans, increased lifespan of the storage device, improved read times, and also provides for data write methods to use less memory during intermediate multi-pass programming steps. | 2022-09-15 |
20220293192 | DE-NOISING USING MULTIPLE THRESHOLD-EXPERT MACHINE LEARNING MODELS - Systems and methods of the present disclosure may be used to improve equalization module architectures for NAND cell read information. For example, embodiments of the present disclosure may provide for de-noising of NAND cell read information using a Multiple Shallow Threshold-Expert Machine Learning Models (MTM) equalizer. An MTM equalizer may include multiple shallow machine learning models, where each machine learning model is trained to specifically solve a classification task (e.g., a binary classification task) corresponding to a weak decision range between two possible read information values for a given NAND cell read operation. Accordingly, during inference, each read sample with a read value within a weak decision range is passed through a corresponding shallow machine learning model (e.g., a corresponding threshold expert) that is associated with (e.g., trained for) the particular weak decision range. | 2022-09-15 |
20220293193 | NAND SENSING CIRCUIT AND TECHNIQUE FOR READ-DISTURB MITIGATION - Sensing circuits and techniques for NAND memory that can enable improved read disturb on the selected SGS are described herein. In one example, a reverse sensing circuit includes circuitry coupled with a bitline of the string of NAND memory cells to perform a sensing operation. The circuitry charges the bitline of the string of NAND memory cells to a target bitline voltage and applies a voltage to the source line that is higher than the bitline voltage. The sense current flows through the string from the source line to the bitline. The voltage at a sensing node that is indicative of a threshold voltage of a memory cell can then be detected. | 2022-09-15 |
20220293194 | MODULATION OF SOURCE VOLTAGE IN NAND-FLASH ARRAY READ - Modulation of the source voltage in a NAND-flash array read waveform can enable improved read-disturb mitigation. For example, increasing the source line voltage to a voltage with a magnitude greater than the non-idle source voltage during the read operation when the array is idle (e.g., not during sensing) enables a reduction in read disturb without the complexity arising from the consideration of multiple read types. Additional improvement in FN disturb may also be obtained on the sub-blocks in the selected SGS by increasing the source line voltage during the selected wordline ramp when the array is idle. | 2022-09-15 |
20220293195 | POWER REALLOCATION FOR MEMORY DEVICE - A data storage device including, in one implementation, a number of memory die packages disposed on a substrate within the data storage device. Each memory die package has a die density that includes one or more memory dies. The die density of each memory die package is configured to provide an even thermal distribution across the number of memory die packages. The respective die densities of two memory of the die packages are different from each other. | 2022-09-15 |
20220293196 | FREQUENCY-VOLTAGE CONVERSION CIRCUIT, SEMICONDUCTOR DEVICE, AND MEMORY SYSTEM - A frequency-voltage conversion circuit includes a constant current source, a first switch connected to an output of the constant current source, a first capacitor connected between the first switch and ground, a second switch connected between a first node that is between the first switch and the first capacitor, and an output node, a third switch connected between the first node and the ground, a fourth switch connected to the output of the constant current source, a second capacitor connected between the fourth switch and the ground, a fifth switch connected between a second node that is between the fourth switch and the second capacitor, and the output node, and a sixth switch connected between the second node and the ground. | 2022-09-15 |
20220293197 | COUNTERMEASURES FOR PERIODIC OVER PROGRAMMING FOR NON-VOLATILE MEMORY - A non-volatile memory apparatus and method of operation are provided. The apparatus includes storage elements connected to a word line. Each of the storage elements is configured to be programmed to a respective target data state. The apparatus also includes a respective bit line associated with each of the storage elements and a control circuit configured to apply a plurality of program pulses to the word line that progressively increase by a program step voltage. The control circuit counts an over programming number of the storage elements having a threshold voltage exceeding an over programming verify level of the respective target data state that is less than a default verify level and based on the program step voltage. The control circuit adjusts a voltage of the respective bit line to one or more adjusted levels in response to the over programming number being greater than a predetermined over programming number. | 2022-09-15 |
20220293198 | REVERSE VT-STATE OPERATION AND OPTIMIZED BICS DEVICE STRUCTURE - Systems and methods for improving the reliability of non-volatile memory by reducing the number of memory cell transistors that experience excessive hole injection are described. The excessive hole injection may occur when the threshold voltage for a memory cell transistor is being set below a particular negative threshold voltage. To reduce the number of memory cell transistors with threshold voltages less than the particular negative threshold voltage, the programmed data states of the memory cell transistors may be reversed such that the erased state comprises the highest data state corresponding with the highest threshold voltage distribution. To facilitate programming of the memory cell transistors with reversed programmed data states, a non-volatile memory device structure may be used in which the bit line connections to NAND strings comprise direct poly-channel contact to P+ silicon and the source line connections to the NAND strings comprise direct poly-channel contact to N+ silicon. | 2022-09-15 |
20220293199 | ELEMENT SUBSTRATE - A switch is configured to switch connection between a second terminal to which a data signal is input and a memory control signal of a memory element in accordance with a switching signal included in a data signal. In write to a memory element, the switching signal switches such that the switch connects the second terminal and the memory control signal of the memory element, and a pulse signal for the write to the memory element is input via the second terminal. | 2022-09-15 |
20220293200 | SUBSTRATE, PRINTING APPARATUS, AND MANUFACTURING METHOD - A substrate includes a plurality of memory units each including an anti-fuse element and a switching element configured to switch application of a predetermined voltage to the anti-fuse element, a wiring to which the plurality of memory units are connected, a first electrode pad to which a voltage for supplying the predetermined voltage to the wiring is applied, and a second electrode pad to which a voltage for supplying the predetermined voltage to the wiring is applied. | 2022-09-15 |
20220293201 | SEMICONDUCTOR DEVICE, LIQUID DISCHARGE HEAD, AND LIQUID DISCHARGE APPARATUS - A device, comprising a plurality of units arrayed in a predetermined direction, a first terminal configured to supply a voltage to the plurality of units, and a second terminal configured to supply a voltage to the plurality of units, wherein the plurality of units include a first unit including a memory element arranged between the first terminal and the second terminal, and a first transistor configured to perform write to the memory element, and a second unit including a second transistor arranged between the first terminal and the second terminal in correspondence with the first transistor of the first unit. | 2022-09-15 |
20220293202 | VEHICLE MEMORY SYSTEM BASED ON 3D MEMORY AND METHOD OPERATING THEREOF - A vehicle memory system and a driving method thereof are provided. The vehicle memory system includes a first function device that is configured to perform a safety function of a vehicle and a second function device that is configured to perform a convenience specification function of the vehicle. A first memory layer is shared by the first function device and the second function device and a second memory layer is used solely by the second function device. A vehicle memory device has a stacked structure including a through-silicon electrode connecting the first function device, the first memory layer, the second function device, and the second memory layer. | 2022-09-15 |
20220293203 | MEMORY DEVICE WITH ANALOG MEASUREMENT MODE FEATURES - The present disclosure relates to an apparatus, and a method for memory management and more a memory device structured with internal analogic measurement mode features. The memory device includes memory component having a memory array, a memory controller coupled to the memory component, a JTAG interface in the memory controller, voltage and current reference generators, and an analogic measurement block driven by the JTAG interface. | 2022-09-15 |
20220293204 | MEMORY SYSTEM - According to one embodiment, a non-volatile memory includes a plurality of groups and a memory controller configured to execute a first operation. Each of the plurality of groups includes a plurality of cell units. Each of the plurality of cell units includes a plurality of memory cells. The first operation includes: based on a first correction amount associated with a target group, reading data from the target group; and updating the first correction amount to a second correction amount based on the data. The memory controller is configured to: select a first group as the target group; and when a condition is satisfied, select a second group as the target group after performing the first operation related to the first group. | 2022-09-15 |
20220293205 | BUILT-IN-SELF-TEST LOGIC, MEMORY DEVICE WITH SAME, AND MEMORY MODULE TESTING METHOD - A memory device includes a memory module and a BIST logic circuit. The BIST logic circuit includes; a pattern generator configured to generate first main data including a first portion, an error correction code (ECC) encoder configured to generate first parity data based on the first main data, and a parity control circuit configured to generate mask data based on the first parity data and the first main data, and generate first substituted parity data based on the mask data and the first parity data, wherein a pattern of the first substituted parity data is the same as a pattern of the first portion of the first main data. | 2022-09-15 |
20220293206 | TEST METHOD FOR MEMORY DEVICE, OPERATION METHOD OF TEST DEVICE TESTING MEMORY DEVICE, AND MEMORY DEVICE WITH SELF-TEST FUNCTION - A test method for a memory device including a plurality of memory cells includes generating a first test pattern, performing a first pattern write operation of writing the first test pattern in the plurality of memory cells, reading first data from the plurality of memory cells in which the first test pattern was written, generating a second test pattern based on the first data, and performing a second pattern write operation of writing the second test pattern in the plurality of memory cells. The second test pattern is generated such that a write operation is skipped with regard to failure cells from among the plurality of memory cells at which a write failure occurs, during the second pattern write operation. | 2022-09-15 |
20220293207 | SYSTEM AND METHOD FOR DETECTING AND REPAIRING DEFECTIVE MEMORY CELLS - One embodiment provides a memory module that enables online repair of defective memory cells. The memory module includes a memory array storing data, a self-test controller coupled to the memory array and configured to perform a self-test on a region within the memory array without interrupting operations of the memory module, and a memory-repair module configured to repair a defective memory cell identified by the self-test controller. | 2022-09-15 |
20220293208 | VOLTAGE CALIBRATION SCANS TO REDUCE MEMORY DEVICE OVERHEAD - A voltage calibration scan is initiated. A first value of a data state metric measured for a sample block of a memory device based on associated with a first bin of blocks designated as a current is received. The first value is designated as a minimum value. A second value of the data state metric for the sample block is measured based on a set of read voltage offsets associated with a second bin of blocks having an index value higher than the current bin. In response to determining that the second value exceeds the first value, the first bin is maintained as the current bin and the voltage calibration scan is stopped. | 2022-09-15 |
20220293209 | GENOMIC AND EPIGENOMIC COMPARATIVE, INTEGRATIVE PATHWAY DISCOVERY - Disclosed herein are systems and methods for identifying biomarkers. Biomarker identification can be achieved while increasing efficiency and decreasing data and computation complexity but maintaining accuracy. Such biomarker identification can be achieved by applying pathway enrichment analysis associated with differential gene expression and epigenomic regulation, such as DNA methylation. | 2022-09-15 |
20220293210 | SINGLE-CELL MODELING OF CLINICAL DATA TO DETERMINE RED BLOOD CELL REGULATION - A method includes receiving data representing a first complete blood count (CBC) measured from a first sample of red blood cells (RBCs) from a subject and data representing a second CBC measured from a second sample of RBCs from the subject, each of the first and second CBCs including a volume and a hemoglobin content of each of the RBCs in the respective sample, the first and second samples being different samples corresponding to different times. Parameters representing RBC population dynamics for the subject are calculated based on the volume and the hemoglobin content for the RBCs in each of the first and second samples and a time between the first and second samples. A pathophysiological state of the subject is determined based on the one or more parameters representing the RBC population dynamics. | 2022-09-15 |
20220293211 | Automated Interpretation of Protein Capillary Electrophoresis Data - Serum protein electrophoresis (SPEP) analysis systems and methods for automatically generating appropriate clinical interpretations of SPEP data are disclosed. | 2022-09-15 |
20220293212 | METHOD FOR AUTOMATICALLY PREDICTING TREATMENT MANAGEMENT FACTOR CHARACTERISTICS OF DISEASE AND ELECTRONIC APPARATUS - The present application disclosed a method for automatically predicting treatment management factor characteristics and an electronic apparatus, the method includes: acquiring, by the electronic apparatus, concerted effect burden parameter data of several mutant genes of a tested sample of a target object on expression activity of each gene in a predetermined genome, wherein the predetermined genome corresponds to the disease; and outputting, by the electronic apparatus, predictive data of at least one treatment management factor characteristic of the target object relative to the disease based on the concerted effect burden parameter data. | 2022-09-15 |
20220293213 | METHOD FOR ACQUIRING INTRACELLULAR DETERMINISTIC EVENTS AND ELECTRONIC APPARATUS - A method for obtaining an intracellular deterministic event, and an electronic device. The method includes: an electronic device obtaining several pieces of mutant gene information of a tested sample extracted from a target object; and the electronic device obtaining, according to the several pieces of mutant gene information, comprehensive influence parameter data of several mutant genes regarding the expression activity of each gene in a predetermined genome. | 2022-09-15 |
20220293214 | METHODS OF ANALYZING GENETIC VARIANTS BASED ON GENETIC MATERIAL - Provided are methods for identifying gene variants associated with a phenotype, for example by inferring and scoring of structural variants from whole-genome or exome data or processing a set of genes against a known set of genes having known variants associated with a set of phenotypes, and optionally determining how likely each of the genes are to cause the phenotype. | 2022-09-15 |
20220293215 | SYSTEMS AND METHODS FOR MHC CLASS II EPITOPE PREDICTION - A system and method for prediction of immunodominant epitopes is provided herein. MHCII peptidomics was used to discover complex bacterial epitopes and host antigen processing pathways. Novel insights into the features of antigenicity are leveraged to build an algorithm for prediction of immunodominant epitopes. Use of immunodominant epitopes is described. | 2022-09-15 |
20220293216 | MATERIAL REPRESENTATION IN COMPUTATIONAL SYSTEMS - A computational system, which may be an artificial intelligence (AI) system, allows for the electronic representation, modeling, generation, rendering, simulating, and querying of polymeric materials by encoding architectural features as nodes and embedding a directed graph of the polymeric materials within a database system. The embedding of chemical data from multiple nodes within the directed graph data structure enables a scalable data model for containing materials data within computational systems. The computational system may be used for predictive modeling of new polymeric materials and for rendering and/or simulating stochastic polymeric ensembles. | 2022-09-15 |
20220293217 | SYSTEM AND METHOD FOR RISK ASSESSMENT OF MULTIPLE SCLEROSIS - Multiple sclerosis (MS) is a neurodegenerative autoimmune disease affecting brain and the spinal cord which results in distorted communication between brain and rest of the body. It is necessary to assess the risk of MS at the earliest. A system and method for diagnosis and risk assessment of an individual for multiple sclerosis has been provided. The system is using a non-invasive method for risk assessment through prediction of metabolic potential of the bacteria residing in gastrointestinal tract of the individual. The system is configured to calculate a score, which is evaluated from the gut bacterial taxonomic abundance profile, indicative of its metabolic potential for production of a particular neuroactive compound. The score is subsequently used to predict the risk of the individual for MS. The present disclosure also provides microbiome based therapeutic approaches that can potentially minimize the side effects through maintaining the healthy cohort of bacteria in gut. | 2022-09-15 |
20220293218 | PREDICTING TOTAL NUCLEIC ACID YIELD AND DISSECTION BOUNDARIES FOR HISTOLOGY SLIDES - A method for qualifying a specimen prepared on one or more hematoxylin and eosin (H&E) slides by assessing an expected yield of nucleic acids for tumor cells and providing associated unstained slides for subsequent nucleic acid analysis is provided. | 2022-09-15 |
20220293219 | SYSTEM AND METHOD FOR DFI-BASED GAMETE SELECTION - In variants, a method for DFI-based gamete selection can include: sampling a video of a scene having a plurality of gametes, tracking each gamete across successive images, and determining attribute values for a gamete, and selecting the gamete. The attribute values can be determined using a model trained to predict the attribute values for the gamete based on a video. | 2022-09-15 |
20220293220 | Biological information inference apparatus and method utilizing biological species identification - Disclosed are a biological information inference apparatus and method utilizing biological species identification. According to an embodiment of the present invention, provided is a biological information inference apparatus in which a biological species is recommended with respect to a user's query by a recommendation system, and at this time pieces of information stored in a biological system information causal model are utilized to infer biological information by combining factors having a connection with a biological species identification key. | 2022-09-15 |
20220293221 | DATA STRUCTURE FOR GENOMIC INFORMATION - A method, comprising: obtaining data to be stored in a data structure comprising a first part and a second part, determining from the data a first data part that is to be stored in the first part of the data structure, wherein the first data part comprises a binary representation of a reference sequence and existence indicators for one or more variants, the said reference sequence comprising a plurality of base pairs, determining from the data a second data part that is to be stored in the second part of the data structure, wherein the second data part comprises a description of the said one or more variants, and storing the obtained data in the data structure such that the first data part is stored in the first data structure part and the second data part is stored in the second data structure part. | 2022-09-15 |
20220293222 | METHODS FOR ENABLING SECURED AND PERSONALISED GENOMIC SEQUENCE ANALYSIS - Described herein is a secure integrated storage and analysis solution for personal genomic applications. The method guarantees data privacy whilst enabling access and ongoing analysis of genomic data when required. Described is a computer implemented homomorphic encryption method for securely producing natively encrypted sequencing data in a way that allows subsequent analysis on the encrypted data without requiring the file to be decrypted. | 2022-09-15 |
20220293223 | SYSTEMS AND METHODS FOR PREDICTION OF PROTEIN FORMULATION PROPERTIES - In a method for predicting a property of potential protein formulations, a set of formulation descriptors is classified as belonging to a specific one of a plurality of predetermined groups that each correspond to a different value range for a protein formulation property. Classifying the set of descriptors includes applying at least a first portion of the set of descriptors as inputs to a first machine learning model. The method also includes selecting, based on the classification, a second machine learning model from among multiple models corresponding to different groups. The method also includes predicting a value of the protein formulation property that corresponds to the set of descriptors, by applying at least a second portion of the set of formulation descriptors as inputs to the selected model. The method further includes causing the value of the protein formulation property to be displayed to a user and/or stored in a memory. | 2022-09-15 |
20220293224 | MODULAR SYNTHON-BASED SCREENING APPROACH FOR USE IN DRUG DISCOVERY FOR DISEASES - This disclosure provides for modular synthon-based screening for rapid drug discovery. Such screening includes initially docking a pre-built set of fragment-like compounds representing library reaction scaffolds and corresponding synthons. Best selected scaffold and synthon combinations from the initial docking are used to enumerate a further library, which is screened again to produce fully enumerated compounds. Such an iterative approach focuses on a subset of synthons at each screening, thereby reducing the combinatorial chemical space for docking and facilitating more rapid drug discovery. | 2022-09-15 |