37th week of 2017 patent applcation highlights part 58 |
Patent application number | Title | Published |
20170263722 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first gate electrode on a substrate, a first trench on a first side of the first gate electrode, a second trench on a second side of the first gate electrode, a depth of the second trench being greater than a depth of the first trench, a first source/drain filling the first trench, and a second source/drain filling the second trench, a height of an upper surface of the second source/drain being greater than a height of the first source/drain. | 2017-09-14 |
20170263723 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - A semiconductor device may include a linear gate trench that crosses an active region of a substrate of the semiconductor device. The active region may include a plurality of gate areas at a bottom of the gate trench and junction areas at a surface of the substrate in a central portion and opposite end portions of the active region. A conductive line may be in a lower portion of the gate trench. The conductive line may include a gate line and a capping layer that at least partially isolates the gate line from an upper surface of the conductive line. A sealing line may be in an upper portion of the gate trench. The sealing line may cover the conductive line and a surface of the sealing line may be coplanar with the junction areas. | 2017-09-14 |
20170263724 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor layer, a first electrode above and electrically connected to the first semiconductor layer, a second electrode above the first semiconductor layer and electrically connected to the first semiconductor layer, a first insulating layer above the first semiconductor layer between the first and second electrodes, and a third electrode. The second electrode is spaced from the first electrode along the first semiconductor layer. The third electrode includes a first portion above the first insulating layer between the first and second electrodes, and a second portion between the first portion and the second electrode and extending from the first portion in the direction of, and spaced from, the second electrode. The distance between the first semiconductor layer and an adjacent curved surface of the second portion gradually increases from the first portion to the end of the second portion distal the first portion. | 2017-09-14 |
20170263725 | SEMICONDUCTOR DEVICE - A technique of reducing the complication in manufacture is provided. There is provided a semiconductor device comprising an n-type semiconductor region made of a nitride semiconductor containing gallium; a p-type semiconductor region arranged to be adjacent to and in contact with the n-type semiconductor region and made of the nitride semiconductor; a first electrode arranged to be in ohmic contact with the n-type semiconductor region; and a second electrode arranged to be in ohmic contact with the p-type semiconductor region. The first electrode and the second electrode are mainly made of one identical metal. The identical metal is at least one metal selected from the group consisting of palladium, nickel and platinum. A concentration of a p-type impurity in the n-type semiconductor region is approximately equal to a concentration of the p-type impurity in the p-type semiconductor region. A difference between a concentration of an n-type impurity and the concentration of the p-type impurity in the n-type semiconductor region is not less than 1.0×10 | 2017-09-14 |
20170263726 | THIN FILM TRANSISTOR, METHOD FOR PRODUCING THE SAME, ARRAY SUBSTRATE AND DISPLAY APPARATUS - The present disclosure provides a thin film transistor, a method for producing the same, an array substrate and a display apparatus. An electrode of the thin film transistor is made of Cu or Cu alloy, and an anti-oxidization layer is used to prevent oxidization of Cu. The thin film transistor includes a gate electrode, a gate insulation layer, a semiconductor active layer, a source electrode and a drain electrode provided on a base substrate, wherein the gate electrode and/or the drain and source electrodes is/are made of Cu or Cu alloy. The thin film transistor further includes an anti-oxidization layer made of a topological insulator material, the anti-oxidization layer being provided above and in contact with the gate electrode and/or the source and drain electrodes made of Cu or Cu alloy. | 2017-09-14 |
20170263727 | LATERAL PNP BIPOLAR TRANSISTOR WITH NARROW TRENCH EMITTER - A lateral bipolar transistor includes trench emitter and trench collector regions to form ultra-narrow emitter regions, thereby improving emitter efficiency. The same trench process is used to form the emitter/collector trenches as well as the trench isolation structures so that no additional processing steps are needed to form the trench emitter and collector. In embodiments of the present invention, the trench emitter and trench collector regions may be formed using ion implantation into trenches formed in a semiconductor layer. In other embodiments, the trench emitter and trench collector regions may be formed by out-diffusion of dopants from heavily doped polysilicon filled trenches. | 2017-09-14 |
20170263728 | STRUCTURE AND METHOD TO ACHIEVE COMPRESSIVELY STRAINED SI NS - A stack for a semiconductor device and a method for making the stack are disclosed. The stack includes a plurality of sacrificial layers in which each sacrificial layer has a first lattice parameter; and at least one channel layer that has a second lattice parameter in which the first lattice parameter is less than or equal to the second lattice parameter, and each channel layer is disposed between and in contact with two sacrificial layers and includes a compressive strain or a neutral strain based on a difference between the first lattice parameter and the second lattice parameter. | 2017-09-14 |
20170263729 | Surface Treatment and Passivation for High Electron Mobility Transistors - A High Electron Mobility Transistor (HEMT) and a method of forming the same are disclosed. The HEMT includes a first III-V compound layer having a first band gap and a second III-V compound layer having a second band gap over the first III-V compound layer, wherein the second band gap is greater than the first band gap. The HEMT further includes a first oxide layer over the second III-V compound layer; a first interfacial layer over the first oxide layer; and a passivation layer over the first interfacial layer. | 2017-09-14 |
20170263730 | SEMICONDUCTOR PROCESS - A semiconductor process including the following steps is provided. An epitaxial layer is formed on a substrate. An oxide layer is formed on the epitaxial layer, wherein the oxide layer includes a chemical oxide layer, a high-temperature oxide (HTO) layer or a surface modification oxide layer. An ion implant process is performed to the epitaxial layer to form a doped region in the epitaxial layer. The oxide layer is removed by using a diluted hydrofluoric acid (DHF) solution after performing the ion implant process, wherein a volume ratio of water to a hydrofluoric acid (HF) in the DHF solution is 200:1 to 1000:1. | 2017-09-14 |
20170263731 | SEMICONDUCTOR DEVICE STRAIN RELAXATION BUFFER LAYER - A method for forming a semiconductor device comprises forming a first buffer layer with a first melting point on a substrate. A second buffer layer is formed on the first buffer layer. The second buffer layer has a second melting point that is greater than the first melting point. Annealing process is performed that increases a temperature of the first buffer layer such that the first buffer layer partially liquefies and causes a strain in the second buffer layer to be substantially reduced. | 2017-09-14 |
20170263732 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device preferably includes a substrate, a fin-shaped structure on the substrate, a buffer layer on the fin-shaped structure, and an epitaxial layer on the buffer layer. Preferably, the buffer layer is made of silicon germanium and including three or more than three elements. The buffer layer also includes dopants selected from the group consisting of P, As, Sb, Bi, C, and F. | 2017-09-14 |
20170263733 | FINFET SEMICONDUCTOR STRUCTURES AND METHODS OF FABRICATING SAME - The invention provides a method of forming a semiconductor structure, which include: providing an intermediate semiconductor structure having semiconductor substrate, a fin having an EG oxide layer in contact with at least a portion of the fin, and a gate stack disposed over a portion of the fin; forming a silicon nitride layer over portions of the fin that are not located under the gate stack; and after forming the silicon nitride layer, performing one or more ion implantation steps on the intermediate semiconductor structure. The invention also provides a method of forming a semiconductor structure including: providing an intermediate semiconductor structure having a semiconductor substrate, a fin having an EG oxide layer in contact with at least a portion of the fin, and a gate material disposed over the fin; forming, over the fin and gate material of the intermediate semiconductor structure, a gate stack hardmask including an oxide layer; forming a silicon nitride barrier layer on the oxide layer of the gate stack hardmask; performing one or more gate stack hardmask patterning steps; removing the EG oxide layer from portions of the fin that are not located under the gate; and subsequent to removing the EG oxide layer from portions of the fin that are not located under the gate, performing one or more ion implantation steps. | 2017-09-14 |
20170263734 | THIN FILM TRANSISTOR (TFT) ARRAY SUBSTRATE AND FABRICATION METHOD THEREOF, AND DISPLAY DEVICE - The present disclosure provides a thin film transistor array substrate and a fabrication method thereof, and a display device. The thin film transistor array substrate includes an active layer. The active layer is formed using a zinc target under an environment of oxygen and nitrogen in a sputtering chamber. A source/drain buffer layer is formed on the active layer using the zinc target by a sputtering process in the sputtering chamber under an environment containing one of oxygen and nitrogen. | 2017-09-14 |
20170263735 | Method of Manufacturing Thin Film Transistor (TFT) and TFT - A method of manufacturing a thin-film transistor (TFT) and a TFT are provided. The method of manufacturing the TFT includes, after depositing a semiconductor layer, oxidizing regions of the semiconductor layer corresponding to sputtering target gaps, so that oxygen vacancies at the regions corresponding to the sputtering target gaps can be decreased and oxygen vacancies on the semiconductor layer can be more uniform. | 2017-09-14 |
20170263736 | ADVANCED HETEROJUNCTION DEVICES AND METHODS OF MANUFACTURE OF ADVANCED HETEROJUNCTION DEVICES - Methods of manufacture of advanced electronic and photonic structures including heterojunction transistors, transistor lasers and solar cells and their related structures, are described herein. Other embodiments are also disclosed herein. | 2017-09-14 |
20170263737 | SEMICONDUCTOR DEVICES WITH CAVITIES - A semiconductor device comprises a first semiconductor wafer including a cavity formed in the first semiconductor die. A second semiconductor die is bonded to the first semiconductor die over the cavity. A first transistor includes a portion of the first transistor formed over the cavity. | 2017-09-14 |
20170263738 | SWITCHING DEVICE - A switching device includes a semiconductor substrate having a first element range and an ineffective range. First trenches extend in a first direction across the first element range and the ineffective range. Second trenches are provided in each inter-trench region within the first element range and are not provided within the ineffective range. A gate electrode is disposed in the trenches. No contact hole is provided in an interlayer insulating film within the ineffective range. The first metal layer covers the interlayer insulating film. The insulating protective film covers a portion of the first metal layer on its outer peripheral side within the ineffective range. The second metal region is in contact with the first metal layer within an opening of the insulating protective film, and is in contact with a side surface of the opening. | 2017-09-14 |
20170263739 | SWITCHING DEVICE - A switching device includes a semiconductor substrate having a first element range including first trenches for gates, and an ineffective range not including the first trenches. In an interlayer insulating film, a contact hole is provided within the first element range, and a wide contact hole is provided within the inactive range. The first metal layer contacts the semiconductor substrate within the contact hole and the wide contact hole. The insulating protective film covers an outer peripheral side portion of a bottom surface of a second recess which is provided in a surface of the first metal layer above the wide contact hole. A side surface of an opening provided in a portion of the insulating protective film that includes the first element range is disposed in the second recess. The second metal layer contacts the first metal layer and the side surface of the opening. | 2017-09-14 |
20170263740 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device comprising: a semiconductor substrate; a plurality of first trench portions formed at a front surface side of the semiconductor substrate and extending in a predetermined extending direction in a planar view; an emitter region of a first conductivity type formed between adjacent trenches of the plurality of first trench portions at the front surface side of the semiconductor substrate; a first contact region of a second conductivity type formed between the adjacent trenches of the plurality of first trench portions, the first contact region and the emitter region being arranged alternately in the extending direction; and a second contact region of a second conductivity type formed above the first contact region to be apart from the emitter region and having a higher doping concentration than the first contact region. | 2017-09-14 |
20170263741 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first stacked portion above a substrate, the first stacked portion comprising a first nitride semiconductor layer containing aluminum and a second nitride semiconductor layer containing carbon, a third nitride semiconductor layer on the first stacked portion, the third nitride semiconductor layer containing carbon and having a greater thickness than each of the first and second nitride semiconductor layers, the third nitride semiconductor layer having a lower carbon concentration than the second nitride semiconductor layer, a second stacked portion on the third nitride semiconductor, the second stacked portion comprising a fourth nitride semiconductor layer containing aluminum and a fifth nitride semiconductor layer containing carbon, a sixth nitride semiconductor layer on the second stacked portion, a seventh nitride semiconductor layer on the sixth nitride semiconductor layer and containing aluminum, and a first electrode on the seventh nitride layer. | 2017-09-14 |
20170263742 | COMPOUND SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A compound semiconductor device includes a compound semiconductor layer, a gate electrode disposed above the compound semiconductor layer, and source and drain electrodes disposed above the compound semiconductor layer with the gate electrode between the source and drain electrodes, wherein the compound semiconductor layer has a groove in a surface thereof at least between the source electrode and the gate electrode in a region between the source electrode and the drain electrode, the groove gradually deepened toward the source electrode. | 2017-09-14 |
20170263743 | HIGH ELECTRON MOBILITY TRANSISTOR (HEMT) AND PROCESS OF FORMING THE SAME - A High Electron Mobility Transistor (HEMT) and a process of forming the same are disclosed. The HEMT includes a substrate, a channel layer, a barrier layer, and heavily doped regions made of metal oxide. The channel layer and the barrier layer provide recesses and a mesa therebetween. The heavily doped regions are formed by partially removing in a portion thereof on the mesa and have slant surfaces facing the gate electrode. The slant surfaces make angle of 135° to 160° against the top horizontal level of the mesa. | 2017-09-14 |
20170263744 | METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE HAVING GATE STRUCTURE WITH DOPED HARD MASK - A method for fabricating semiconductor device includes the steps of: providing a substrate having at least a gate structure thereon and an interlayer dielectric (ILD) layer surrounding the gate structure, wherein the gate structure comprises a hard mask thereon; forming a dielectric layer on the gate structure and the ILD layer; removing part of the dielectric layer to expose the hard mask and the ILD layer; and performing a surface treatment to form a doped region in the hard mask and the ILD layer. | 2017-09-14 |
20170263745 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes: an n | 2017-09-14 |
20170263746 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD - To restrict alloy formation between a hydrogen-absorbing layer of titanium or the like and an electrode of aluminum or the like, provided is a semiconductor device. The semiconductor device may include a semiconductor substrate. The semiconductor device may include a first layer that is formed above the semiconductor substrate. The first layer may contain a hydrogen-absorbing first metal. The semiconductor device may include a second layer that is formed above the first layer. The second layer may contain a second metal differing from the first metal. The semiconductor device may include an Si-containing layer that is formed between the first layer and the second layer and contains silicon. The second layer may further include silicon. The Si-containing layer may have a higher silicon concentration than the second layer. The second metal may be aluminum. The first metal may be titanium. | 2017-09-14 |
20170263747 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first conductivity type first semiconductor region, a second conductivity type second semiconductor region, a second conductivity type third semiconductor region, a first conductivity type fourth semiconductor region, a gate insulating portion, a gate electrode, and first and second electrodes. The first semiconductor region includes first and second portions. The second semiconductor region includes third and fourth portions. The gate electrode is on the gate insulating portion and over the first semiconductor region and a portion of the third semiconductor region. The first electrode is on, and electrically connected to, the fourth semiconductor region. The second electrode is over the first portion, the third portion, and the gate electrode, and spaced from the first electrode. | 2017-09-14 |
20170263748 | METHODS TO ACHIEVE STRAINED CHANNEL FINFET DEVICES - Methods to achieve strained channel finFET devices and resulting finFET devices are presented. In an embodiment, a method for processing a field effect transistor (FET) device may include forming a fin structure comprising a fin channel on a substrate. The method may also include forming a sacrificial epitaxial layer on a side of the fin structure. Additionally, the method may include forming a deep recess in a region that includes at least a portion of the fin structure, wherein the fin structure and sacrificial layer relax to form a strain on the fin channel. The method may also include depositing source/drain (SD) material in the deep recess to preserve the strain on the fin channel. | 2017-09-14 |
20170263749 | Integrated Circuit Transistor Structure with High Germanium Concentration SiGe Stressor - An embodiment of a method for forming a transistor that includes providing a semiconductor substrate having a source/drain region is provided where a first SiGe layer is formed over the source/drain region. A thermal oxidation is performed to convert a top portion of the first SiGe layer to an oxide layer and a bottom portion of the first SiGe layer to a second SiGe layer. A thermal diffusion process is performed after the thermal oxidation is performed to form a SiGe area from the second SiGe layer. The SiGe area has a higher Ge concentration than the first SiGe layer. | 2017-09-14 |
20170263750 | FINFET TRANSISTOR - A semiconductor device includes a semiconductor substrate having isolation regions formed therein and a fin-shaped semiconductor structure protruding vertically above the isolation regions and extending laterally in a first direction. The device additionally includes a gate dielectric wrapping a channel region of the fin-shaped semiconductor structure and a gate electrode wrapping the gate dielectric. The channel region is interposed in the first direction between a source region and a drain region and has sloped sidewalls and a width that continuously decreases from a base towards a peak of the channel region. The channel region comprises a volume inversion region having a height greater than about 25% of a total height of the channel region. | 2017-09-14 |
20170263751 | Method of Forming FinFET Gate Oxide - A semiconductor device includes a semiconductor fin, a first silicon nitride based layer, a lining oxide layer, a second silicon nitride based layer and a gate oxide layer. The semiconductor fin has a top surface, a first side surface adjacent to the top surface, and a second side surface which is disposed under and adjacent to the first side surface. The first silicon nitride based layer peripherally encloses the second side surface of the semiconductor fin. The lining oxide layer is disposed conformal to the first silicon nitride based layer. The second silicon nitride based layer is disposed conformal to the lining oxide layer. The gate oxide layer is disposed conformal to the top surface and the first side surface of the semiconductor fin. | 2017-09-14 |
20170263752 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type on the first semiconductor region, a first electrode surrounded by the first semiconductor region and including a first electrode portion and a second electrode portion provided on the first electrode portion, and a first insulating section including first and second insulating portions. The second insulating portion is arranged side by side with the second electrode portion in a second direction perpendicular to a first direction from the first semiconductor region to the second semiconductor region. The first insulating portion is arranged side by side with the first electrode portion in the second direction. A length and a thickness of the first insulating portion in the first direction are greater than a length and a thickness of the second insulating portion in the first direction, respectively. | 2017-09-14 |
20170263753 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - To provide a semiconductor device less affected by noise without making a manufacturing process more complicated and increasing a chip area. The device has a semiconductor substrate having first and second surfaces, a first-conductivity-type drain region on the second surface side in the semiconductor substrate, a first-conductivity-type drift region on the first surface side of a substrate region, a second-conductivity-type base region on the first surface side of the drift region, a first-conductivity-type source region on the first surface of the semiconductor substrate sandwiching a base region between the source and drift regions, a gate electrode opposite to and insulated from the base region, a wiring on the first main surface electrically coupled to the source region, and a first conductive film on the first main surface, opposite to and insulated from the wiring, and electrically coupled to the substrate region. | 2017-09-14 |
20170263754 | SWITCHING DEVICE - A switching device including a semiconductor substrate including a trench (gate electrode) extending in a mesh shape is provided, and the upper surface of the semiconductor substrate is covered by the interlayer insulating film. Within an element range a contact hole is provided in an interlayer insulating film above each cell region while within a surrounding range an entire upper surface of each cell region is covered by the interlayer insulating film. The first metal layer covers the interlayer insulating film, and has recesses above the contact holes. The insulating protective film covers an outer peripheral side portion of the first metal layer within the surrounding range. The second metal layer covers the first metal layer within an opening of the insulating protective film. Within the surrounding range, a second conductivity-type region extending to below lower ends of the trench and is electrically connected to the body region, is provided. | 2017-09-14 |
20170263755 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - An n-channel power MOS transistor having a gate electrode is formed in an element formation region defined in a semiconductor substrate. A p-type guard ring region is formed in a terminal region. A plurality of p-type column regions are formed from the bottom of the p-type base region to a further deeper position. The column region located in the outermost periphery and the p | 2017-09-14 |
20170263756 | Semiconductor Devices and a Method for Forming a Semiconductor Device - A semiconductor device includes a plurality of striped-shaped trenches extending into a semiconductor substrate. At least one trench of a first group of trenches of the plurality of striped-shaped trenches is located between two trenches of a second group of trenches of the plurality of striped-shaped trenches. A gate of a transistor structure is located in each trench of the second group of trenches and a gate insulation layer is located between the gate and the semiconductor substrate in each trench of the second group of trenches. Trench insulation material is located in each trench of the first group of trenches. A thickness of the trench insulation material throughout each trench of the first group of trenches is at least two times larger than a thickness of the gate insulation layer in each trench of the second group of trenches. | 2017-09-14 |
20170263757 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A silicon carbide semiconductor device includes: a substrate; a drift layer over the substrate; a base region over the drift layer; multiple source regions over an upper layer portion of the base region; a contact region over the upper layer portion of the base region between opposing source regions; multiple trenches from a surface of each source region to a depth deeper than the base region; a gate electrode on a gate insulating film in each trench; a source electrode electrically connected to the source regions and the contact region; a drain electrode over a rear surface of the substrate; and multiple electric field relaxation layers in the drift layer between adjacent trenches. Each electric field relaxation layer includes: a first region at a position deeper than the trenches; and a second region from a surface of the drift layer to the first region. | 2017-09-14 |
20170263758 | VERTICAL CONDUCTION INTEGRATED ELECTRONIC DEVICE PROTECTED AGAINST THE LATCH-UP AND RELATING MANUFACTURING PROCESS - A vertical conduction integrated electronic device including: a semiconductor body; a trench that extends through part of the semiconductor body and delimits a portion of the semiconductor body, which forms a first conduction region having a first type of conductivity and a body region having a second type of conductivity, which overlies the first conduction region; a gate region of conductive material, which extends within the trench; an insulation region of dielectric material, which extends within the trench and is arranged between the gate region and the body region; and a second conduction region, which overlies the body region. The second conduction region is formed by a conductor. | 2017-09-14 |
20170263759 | LDMOS TRANSISTOR WITH LIGHTLY-DOPED ANNULAR RESURF PERIPHERY - Apparatus and associated methods relate to controlling an electric field profile within a drift region of an LDMOS device using first and second RESURF regions. The first RESURF region extends from a source end toward a drain end of the LDMOS device. The first RESURF region is adjacent to a forms a metallurgical junction with the drift region. The second RESURF layer extends from the drain end toward the source end of the LDMOS device. The second RESURF layer has an end that is longitudinally between the body contact and the source end of the first RESURF layer. A distance between the end of the second RESURF layer and the body contact is greater than a vertical distance between the end of the second RESURF layer and the body contact. A maximum electric field between the second RESURF layer and the body contact can be advantageously reduced with this geometry. | 2017-09-14 |
20170263760 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a semiconductor device includes a first semiconductor region, a second semiconductor region, a third semiconductor region, an insulating unit, a void, a gate insulating film and a gate electrode. The second semiconductor region provides on a part of the first semiconductor region. The third semiconductor region provides on one other part of the first semiconductor region. The insulating unit provides on a part of the second semiconductor region. The void provides at a lower part of the insulating unit. The gate insulating film provides on a part of the first semiconductor region between the second semiconductor region and the third semiconductor region. The gate electrode provides on the gate insulating film. A position in a first direction of at least a part of the void is between the insulating unit and the third semiconductor region. | 2017-09-14 |
20170263761 | SEMICONDUCTOR DEVICE CAPABLE OF HIGH-VOLTAGE OPERATION - A semiconductor device capable of high-voltage operation includes a semiconductor substrate having a first conductivity type. A first well doped region is formed in the semiconductor substrate, having a second conductivity type that is the opposite of the first conductivity type. A first doped region and a second doped region are formed on the first well doped region, having the second conductivity type. A first gate structure is formed over the first well doped region and adjacent to the first doped region. A second gate structure overlaps the first gate structure and the first well doped region. A third gate structure is formed beside the second gate structure and close to the second doped region. The top surface of the first well doped region between the second gate structure and the third gate structure avoids having any gate structure and silicide formed thereon. | 2017-09-14 |
20170263762 | LOW-COST SEMICONDUCTOR DEVICE MANUFACTURING METHOD - Provided are a low-cost semiconductor device manufacturing method and a semiconductor device made using the method. The method includes forming multiple body regions in a semiconductor substrate, forming multiple gate insulating layers and multiple gate electrodes in the body region; implementing a blanket ion implantation in an entire surface of the substrate to form a low concentration doping region (LDD region) in the body region without a mask, forming a spacer at a side wall of the gate electrode, and implementing a high concentration ion implantation to form a high concentration source region and a high concentration drain region around the LDD region. According to the examples, devices have favorable electrical characteristics and at the same time, manufacturing costs are reduced. Since, when forming high concentration source region and drain regions, tilt and rotation co-implants are applied, an LDD masking step is potentially omitted. | 2017-09-14 |
20170263763 | SEMICONDUCTOR DEVICE - The present examples relate to a semiconductor device used in an electric device or high voltage device. The present examples improve R | 2017-09-14 |
20170263764 | SEMICONDUCTOR DEVICE CAPABLE OF HIGH-VOLTAGE OPERATION - A semiconductor device capable of high-voltage operation includes a semiconductor substrate, a first well region, a second well region, a first gate structure, a first doped region, a second doped region, and a second gate structure. The first well region is formed in a portion of the semiconductor substrate. The second well region is formed in a portion of the first well region. The first gate structure is formed over a portion of the second well region and a portion of the first well region. The first doped region is formed in a portion of the second well region. The second doped region is formed in a portion of the first well region. The second gate structure is formed over a portion of the first gate structure, a portion of the first well region, and a portion of the second doped region. | 2017-09-14 |
20170263765 | DRIFT-REGION FIELD CONTROL OF AN LDMOS TRANSISTOR USING BIASED SHALLOW-TRENCH FIELD PLATES - Apparatus and associated methods relate to controlling an electric field profile within a drift region of an LDMOS device using biased field plates to deplete majority carriers from a drift region between a body/drift-region metallurgical junction and a drain contact. Such field plates are located in trenches that longitudinally extend within the drift region. Field plates are laterally spaced apart from each other at a distance that permits substantial depletion of majority carriers between adjacent field plates. Trenches have trench bottoms located within a drift-region/substrate metallurgical junction so as to permit substantial depletion of majority carriers between trench bottoms and the drift-region/substrate metallurgical junction. Between adjacent trenches, dopant concentrations can be increased up to a threshold that can be substantially depleted under specified bias conditions. Such control of the electric field profile within the drift region may advantageously optimize a breakdown-voltage/on-resistance characteristic of the LDMOS device. | 2017-09-14 |
20170263766 | LDMOS TRANSISTORS INCLUDING RESURF LAYERS AND STEPPED-GATES, AND ASSOCIATED SYSTEMS AND METHODS - A lateral double-diffused metal-oxide-semiconductor field effect (LDMOS) transistor includes a silicon semiconductor structure including (a) a base layer, (b) a p-type reduced surface field effect (RESURF) layer disposed over the base layer in a thickness direction, (c) a p-body disposed over the p-type RESURF layer in the thickness direction, (d) a source p+ region and a source n+ region each disposed in the p-body, (e) a high-voltage n-type laterally-diffused drain (HVNLDD) disposed adjacent to the p-body in a lateral direction orthogonal to the thickness direction, the HVNLDD contacting the p-type RESURF layer, and (f) a drain n+ region disposed in the HVNLDD. The LDMOS transistor further includes (a) a first dielectric layer disposed on the silicon semiconductor structure in the thickness direction over at least part of the p-body and the HVNLDD and (b) a first gate conductor disposed on the first dielectric layer in the thickness direction. | 2017-09-14 |
20170263767 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type on the first semiconductor region, a third semiconductor region of the first conductivity type on the second semiconductor region, a first electrode surrounded by the first semiconductor region, a first insulating portion between a first part of the first electrode and the first semiconductor region, a second insulating portion having a higher dielectric constant than the first insulating portion, between a second part of the first electrode and the first semiconductor region, a gate electrode above the first electrode, and a gate insulating portion between the second semiconductor region and the gate electrode. | 2017-09-14 |
20170263768 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first conductivity type first semiconductor region, a second semiconductor region on the first semiconductor region, a third semiconductor region on the second semiconductor region, a first insulating portion extending inwardly of, and surrounded by, the first semiconductor region, a gate electrode extending inwardly of the first insulating portion and spaced from the second semiconductor region in a second direction that intersects a first direction extending from the first semiconductor region to the second semiconductor region, by the first insulating portion, and a first electrode including a portion spaced from the first semiconductor region in the second direction by the first insulating portion, and surrounded by the first insulating portion and the gate electrode. | 2017-09-14 |
20170263769 | III-NITRIDE TRANSISTOR WITH ENHANCED DOPING IN BASE LAYER - A vertical trench MOSFET comprising: a N-doped substrate of a III-N material; and an epitaxial layer of the III-N material grown on a top surface of the substrate, a N-doped drift region being formed in said epitaxial layer; a P-doped base layer of said III-N material, formed on top of at least a portion of the drift region; a N-doped source region of said III-N material; formed on at least a portion of the base layer; and a gate trench having at least one vertical wall extending along at least a portion of the source region and at least a portion of the base layer; wherein at least a portion of the P-doped base layer along the gate trench is a layer of said P-doped III-N material that additionally comprises a percentage of aluminum. | 2017-09-14 |
20170263770 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor device includes a first source region, a second source region, and a drain region. The first source region includes a first conductivity type that is formed in a semiconductor layer. The second source region includes a second conductivity type that is adjacent to a gate region and formed in the first source region, the second source region being electrically connected to the first source region, and configured such that one end of a first face of the second source region abuts a gate insulating film formed in the gate region and at least a portion of a second face opposite to the first face abuts the first source region. The drain region includes the first conductivity type that is formed adjacent to the gate region in the semiconductor layer with the gate region interposed with the second source region and the drain region. | 2017-09-14 |
20170263771 | MOS Devices Having Epitaxy Regions with Reduced Facets - An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is over the first silicon germanium region. The second silicon germanium region comprises a portion in the opening. The second silicon germanium region has a second germanium percentage greater than the first germanium percentage. A silicon cap substantially free from germanium is over the second silicon germanium region. | 2017-09-14 |
20170263772 | SEMICONDUCTOR DEVICE STRAIN RELAXATION BUFFER LAYER - A method for forming a semiconductor device comprises forming a first buffer layer with a first melting point on a substrate. A second buffer layer is formed on the first buffer layer. The second buffer layer has a second melting point that is greater than the first melting point. Annealing process is performed that increases a temperature of the first buffer layer such that the first buffer layer partially liquefies and causes a strain in the second buffer layer to be substantially reduced. | 2017-09-14 |
20170263773 | COMPOSITE AND TRANSISTOR - A novel material is provided. A composite oxide semiconductor in which a first region and a plurality of second regions are mixed is provided. Note that the first region contains at least indium, an element M (the element M is one or more of Al, Ga, Y, and Sn), and zinc, and the plurality of second regions contain indium and zinc. Since the plurality of second regions have a higher concentration of indium than the first region, the plurality of second regions have a higher conductivity than the first region. An end portion of one of the plurality of second regions overlaps with an end portion of another one of the plurality of second regions. The plurality of second regions are three-dimensionally surrounded with the first region. | 2017-09-14 |
20170263774 | SEMICONDUCTOR DEVICE - A transistor having favorable electrical characteristics. A transistor suitable for miniaturization. A transistor having a high switching speed. One embodiment of the present invention is a semiconductor device that includes a transistor. The transistor includes an oxide semiconductor, a gate electrode, and a gate insulator. The oxide semiconductor includes a first region in which the oxide semiconductor and the gate electrode overlap with each other with the gate insulator positioned therebetween. The transistor has a threshold voltage higher than 0 V and a switching speed lower than 100 nanoseconds. | 2017-09-14 |
20170263775 | SEMICONDUCTOR DEVICE - High field-effect mobility is provided for a semiconductor device including an oxide semiconductor. Further, a highly reliable semiconductor device including the transistor is provided. In a transistor in which a stack of oxide semiconductor layers is provided over a gate electrode layer with a gate insulating layer provided therebetween, an oxide semiconductor layer functioning as a current path (channel) of the transistor and containing an n-type impurity is sandwiched between oxide semiconductor layers having lower conductivity than the oxide semiconductor layer. In the oxide semiconductor layer functioning as the channel, a region on the gate insulating layer side contains the n-type impurity at a higher concentration than a region on the back channel side. With such a structure, the channel can be separated from the interface between the oxide semiconductor stack and the insulating layer in contact with the oxide semiconductor stack, so that a buried channel can be formed. | 2017-09-14 |
20170263776 | SEMICONDUCTOR DEVICE AND DISPLAY DEVICE INCLUDING THE SAME - A change in electrical characteristics in a semiconductor device including an oxide semiconductor film is inhibited, and the reliability is improved. The semiconductor device includes a gate electrode, a first insulating film over the gate electrode, an oxide semiconductor film over the first insulating film, a source electrode electrically connected to the oxide semiconductor film, a drain electrode electrically connected to the oxide semiconductor film, a second insulating film over the oxide semiconductor film, the source electrode, and the drain electrode, a first metal oxide film over the second insulating film, and a second metal oxide film over the first metal oxide film. The first metal oxide film contains at least one metal element that is the same as a metal element contained in the oxide semiconductor film. The second metal oxide film includes a region where the second metal oxide film and the first metal oxide film are mixed. | 2017-09-14 |
20170263777 | SEMICONDUCTOR DEVICE - An object is to reduce leakage current and parasitic capacitance of a transistor used for an LSI, a CPU, or a memory. A semiconductor integrated circuit included in an LSI, a CPU, or a memory is manufactured using the transistor which is formed using an oxide semiconductor which is an intrinsic or substantially intrinsic semiconductor obtained by removal of impurities which serve as electron donors (donors) from the oxide semiconductor and has larger energy gap than a silicon semiconductor, and is formed over a semiconductor substrate. With the transistor which is formed over the semiconductor substrate and includes the highly purified oxide semiconductor layer with sufficiently reduced hydrogen concentration, a semiconductor device whose power consumption due to leakage current is low can be realized. | 2017-09-14 |
20170263778 | FLASH MEMORY STRUCTURE AND FABRICATION METHOD THEREOF - A method is provided for fabricating a flash memory structure. The method includes providing a substrate; and forming a gate structure and a hard mask layer. The method also includes forming a sidewall structure on side walls of the gate structure and the hard mask layer; and forming an etching barrier layer covering the sidewall structure. In addition, the method includes forming a first dielectric layer; and removing the sidewall structure and the etching barrier layer higher than the first dielectric layer. Moreover, the method includes forming a sacrificial sidewall layer on the side wall of the hard mask layer and above the sidewall structure and the etching barrier layer; and forming a second dielectric layer on the first dielectric layer. Further, the method includes forming a contact hole penetrating through the second dielectric layer and the first dielectric layer; and forming a contact-hole plug in the contact hole. | 2017-09-14 |
20170263779 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a non-volatile semiconductor memory device includes: a tunnel insulation film provided on a semiconductor substrate; a floating gate electrode provided on the tunnel insulation film; an inter-electrode insulation film provided on the floating gate electrode; and a control gate electrode provided on the inter-electrode insulation film. The inter-electrode insulation film includes: a lower insulation film provided on the floating gate electrode side; and an upper insulation film provided on the control gate electrode side. The lower insulation film includes: N (N is an integer of 2 or larger) electric charge accumulation layers; and boundary insulation films provided between the electric charge accumulation layers. | 2017-09-14 |
20170263780 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a nonvolatile semiconductor memory device includes first and second gate electrode layers, an inter-layer insulating layer, a channel layer, a tunneling insulating layer, first and second charge storage portions, and a blocking insulating layer. The channel layer is separated from the first and second gate electrode layers, and the inter-layer insulating layer. The tunneling insulating layer is provided between the first gate electrode layer and the channel layer. The first charge storage portion is provided between the first gate electrode layer and the tunneling insulating layer. The second charge storage portion is provided the second gate electrode layer and the tunneling insulating layer. The blocking insulating layer is provided between the inter-layer insulating layer and the tunneling insulating layer, between the first gate electrode layer and the first charge storage portion, between the inter-layer insulating layer and the first charge storage portion. | 2017-09-14 |
20170263781 | VERTICAL TRANSISTOR FABRICATION AND DEVICES - A method of fabricating a vertical field effect transistor including forming a first recess in a substrate; epitaxially growing a first drain from the first bottom surface of the first recess; epitaxially growing a second drain from the second bottom surface of a second recess formed in the substrate; growing a channel material epitaxially on the first drain and the second drain; forming troughs in the channel material to form one or more fin channels on the first drain and one or more fin channels on the second drain, wherein the troughs over the first drain extend to the surface of the first drain, and the troughs over the second drain extend to the surface of the second drain; forming a gate structure on each of the one or more fin channels; and growing sources on each of the fin channels associated with the first and second drains. | 2017-09-14 |
20170263782 | TRANSISTOR AND ELECTRONIC DEVICE - A transistor capable of high-speed operation is provided. In a transistor including a back gate electrode, the back gate electrode is provided over a back gate wiring. A gate wiring and the back gate wiring are apart from each other; thus, the parasitic capacitance between the gate wiring and the back gate wiring is reduced and withstand voltage is improved. In addition, the width of the back gate electrode is smaller than a channel width; thus, the parasitic capacitance between the gate wiring and the back gate electrode is reduced and withstand voltage is improved. | 2017-09-14 |
20170263783 | SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE INCLUDING THE SEMICONDUCTOR DEVICE - To improve field-effect mobility and reliability of a transistor including an oxide semiconductor film. Provided is a semiconductor device including an oxide semiconductor film. The semiconductor device includes a first insulating film, the oxide semiconductor film over the first insulating film, a second insulating film and a third insulating film over the oxide semiconductor film, and a gate electrode over the second insulating film. The oxide semiconductor film includes a first oxide semiconductor film, a second oxide semiconductor film over the first oxide semiconductor film, and a third oxide semiconductor film over the second oxide semiconductor film. The first to third oxide semiconductor films contain the same element. The second oxide semiconductor film includes a region where the crystallinity is lower than the crystallinity of one or both of the first oxide semiconductor film and the third oxide semiconductor film. | 2017-09-14 |
20170263784 | DIODE WITH REDUCED RECOVERY TIME FOR APPLICATIONS SUBJECT TO THE CURRENT RECIRCULATION PHENOMENON AND/OR TO FAST VOLTAGE VARIATIONS - A diode comprising a semiconductor body delimited by a front surface and including: a first semiconductor region having a first type of conductivity, facing at least in part the front surface; and a second semiconductor region having a second type of conductivity, the second semiconductor region facing at least in part the front surface and surrounding, at a distance, at least part of the first semiconductor region. The diode further includes: a trench, which extends in the semiconductor body starting from the front surface, for surrounding at least part of the second semiconductor region; and a lateral insulation region, which is arranged within the trench, is formed by dielectric material and contacts at least in part the second semiconductor region. | 2017-09-14 |
20170263785 | SEMICONDUCTOR DEVICE - A p type anode layer is formed on a front surface of an n type drift layer in an active region. An n type buffer layer is formed on a rear surface of the n | 2017-09-14 |
20170263786 | OXIDE SEMICONDUCTOR SUBSTRATE AND SCHOTTKY BARRIER DIODE - A schottky barrier diode element having a silicon (Si) substrate, an oxide semiconductor layer and a schottky electrode layer, wherein the oxide semiconductor layer includes a polycrystalline and/or amorphous oxide semiconductor having a band gap of 3.0 eV or more and 5.6 eV or less. | 2017-09-14 |
20170263787 | PHOTOVOLTAIC MODULE WITH FLEXIBLE CIRCUIT - A photovoltaic module, and method of making, is disclosed in which a flexible circuit is electrically coupled to a plurality of photovoltaic cells, where the photovoltaic cells are electrically coupled in series to form a series of cells. Each photovoltaic cell has free-standing metallic articles coupled to the top and bottom surfaces of a semiconductor substrate. A cell interconnection element of each photovoltaic cell is electrically coupled to a free-standing metallic article of an adjacent photovoltaic cell, where the interconnection elements of the initial and final cells in the series serve as contact ends for the series of cells. Contact tabs of the flexible circuit are electrically coupled to the contact ends of the series of cells, and a junction box is electrically coupled to a junction box contact region of the flexible circuit. | 2017-09-14 |
20170263788 | HIGHLY RESPONSIVE III-V PHOTODETECTORS USING ZnO:Al AS N-TYPE EMITTER - A photodiode includes a p-type ohmic contact and a p-type substrate in contact with the p-type ohmic contact. An intrinsic layer is formed over the substrate and including a III-V material. A transparent II-VI n-type layer is formed on the intrinsic layer and functions as an emitter and an n-type ohmic contact. | 2017-09-14 |
20170263789 | DESICCANT-BASED COOLING OF PHOTOVOLTAIC MODULES - An example device includes a photovoltaic (PV) unit and a desiccant-based passive cooling component that is thermally coupled to the PV unit. The desiccant-based passive cooling component is configured to sorb, under first conditions, moisture from an environment that surrounds the device, via at least one of adsorption or absorption, and evaporate, under second conditions that are different from the first conditions, at least a portion of the moisture. | 2017-09-14 |
20170263790 | NANO-ELECTRODE MULTI-WELL HIGH-GAIN AVALANCHE RUSHING PHOTOCONDUCTOR - Provided is a detector that includes a scintillator, a common electrode, a pixel electrode, and a plurality of insulating layers, with a plurality of nano-pillars formed in the plurality of insulating layers, a nano-scale well structure between adjacent nano-pillars, with a-Se separating the adjacent nano-pillars, and a method for operation thereof. | 2017-09-14 |
20170263791 | SOLAR CELL AND MANUFACTURING METHOD OF SOLAR CELL - The present invention is a solar cell comprising a gallium-doped silicon substrate having a p-n junction formed therein, wherein the silicon substrate is provided with a silicon thermal oxide film at least on the first main surface of main surfaces of the silicon substrate, the first main surface being a main surface having a p-type region, and the silicon substrate is further doped with boron. This provides a solar cell that can possess high conversion efficiency while suppressing the photo-degradation even though having a silicon thermal oxide film as a passivation film of the substrate surface, and a method for manufacturing such a solar cell. | 2017-09-14 |
20170263792 | SOLAR CELLS PROVIDED WITH COLOR MODULATION AND METHOD FOR FABRICATING THE SAME - Solar cells provided with color modulation and a method for fabricating the same are disclosed. The solar cell includes a photoelectric conversion layer and a color-modulating layer provided over the photoelectric conversion layer. The photoelectric conversion layer is employed for generating electrical energy from incident light and the color-modulating layer is used to modulate colorful appearance. The color-modulating layer is composed of at least one dielectric layer which is free of granules. | 2017-09-14 |
20170263793 | PHOTODETECTOR AND OBJECT DETECTION SYSTEM USING THE SAME - A photodetector according to an embodiment includes: a semiconductor substrate including a first region and a second region adjacent to the first region; at least one light detection cell including a first semiconductor layer disposed in the first region, a second semiconductor layer disposed between the first semiconductor layer and the semiconductor substrate and including a junction portion with the first semiconductor layer, a third semiconductor layer disposed in the semiconductor substrate separately from the second semiconductor layer, a first electrode on the semiconductor substrate and applying a voltage to the first semiconductor layer, and a second electrode on the semiconductor substrate and applying a voltage to the third semiconductor layer; and a light guide disposed in the second region and guiding incident light to be propagated in a first direction to the junction portion between the first semiconductor layer and the second semiconductor layer. | 2017-09-14 |
20170263794 | MATERIALS, STRUCTURES, AND METHODS FOR OPTICAL AND ELECTRICAL III-NITRIDE SEMICONDUCTOR DEVICES - The present invention provides materials, structures, and methods for III-nitride-based devices, including epitaxial and non-epitaxial structures useful for III-nitride devices including light emitting devices, laser diodes, transistors, detectors, sensors, and the like. In some embodiments, the present invention provides metallo-semiconductor and/or metallo-dielectric devices, structures, materials and methods of forming metallo-semiconductor and/or metallo-dielectric material structures for use in semiconductor devices, and more particularly for use in III-nitride based semiconductor devices. In some embodiments, the present invention includes materials, structures, and methods for improving the crystal quality of epitaxial materials grown on non-native substrates. In some embodiments, the present invention provides materials, structures, devices, and methods for acoustic wave devices and technology, including epitaxial and non-epitaxial piezoelectric materials and structures useful for acoustic wave devices. In some embodiments, the present invention provides metal-base transistor devices, structures, materials and methods of forming metal-base transistor material structures for use in semiconductor devices. | 2017-09-14 |
20170263795 | METHOD OF FABRICATING AN EMITTER REGION OF A SOLAR CELL - Methods of fabricating emitter regions of solar cells are described. Methods of forming layers on substrates of solar cells, and the resulting solar cells, are also described. | 2017-09-14 |
20170263796 | Encapsulated Solar Cells that Incorporate Structures that Totally Internally Reflect Light Away from Front Contacts and Related Manufacturing Methods - Solar cells in accordance with a number of embodiments of the invention are encapsulated by a material that can render the front contacts of the solar cells effectively invisible at certain angles of incidence. Front contacts of a solar cell provide a way for current to escape from the solar cell. However, these front contacts cover portions of the photoabsorbing substrate, blocking incident light that could otherwise be utilized by the photoabsorbing substrate for electrical power generation. By encapsulating the solar cell and using encapsulated volumes above the front contact that define interfaces, light reaching the interface can be refracted due to the different refractive indices of the two media. Depending on the refractive index ratio, total internal reflection can occur at certain angles of incidence. Totally internally reflected light can be redirected away from the front contacts and onto the photoabsorbing substrate, thereby reducing optical waste. | 2017-09-14 |
20170263797 | CHALCOGENIDE-BASED MATERIALS AND IMPROVED METHODS OF MAKING SUCH MATERIALS - The present invention provides strategies for making high quality CIGS photoabsorbing materials from precursor films that incorporate a sub-stoichiometric amount of chalcogen(s). Chalcogen(s) are incorporated into the CIGS precursor film via co-sputtering with one or more other constituents of the precursor. Optional annealing also may be practiced to convert precursor into more desirable chalcopyrite crystalline form in event all or a portion of the precursor has another constitution. The resultant precursors generally are sub-stoichiometric with respect to chalcogen and have very poor electronic characteristics. The conversion of these precursors into CIGS photoabsorbing material via chalcogenizing treatment occurs with dramatically reduced interfacial void content. The resultant CIGS material displays excellent adhesion to other layers in the resultant photovoltaic devices. Ga migration also is dramatically reduced, and the resultant films have optimized Ga profiles in the top or bottom portion of the film that improve the quality of photovoltaic devices made using the films. | 2017-09-14 |
20170263798 | PHOTODETECTOR AND LIDAR DEVICE USING THE SAME - A photodetector according to an embodiment includes: a first semiconductor layer; a porous semiconductor layer disposed on the first semiconductor layer; and at least one photo-sensing element including a second semiconductor layer of a first conductivity type disposed in a region of the porous semiconductor layer and a third semiconductor layer of a second conductivity type disposed on the second semiconductor layer. | 2017-09-14 |
20170263799 | ACTIVE BLUE LIGHT LEAKAGE PREVENTING LED STRUCTURES - The present invention discloses active blue light leakage preventing LED structures. Each of the structure includes a circuit board, at least one blue light LED die, a photo detector and a wavelength transformation layer, wherein the electric circuit on the circuit board receives detection signal from the photo detector and turns off the said blue light LED die accordingly. With the implementation of the present invention, the active blue light leakage preventing LED structure turns off the blue light LED die when it reaches its usage life span limit thus avoiding damage to human from the massive release of blue light. | 2017-09-14 |
20170263800 | SOLAR BATTERY MODULE AND MANUFACTURING METHOD THEREFOR - A solar battery module and manufacturing method for a solar battery module having improved output are provided. The solar battery module | 2017-09-14 |
20170263801 | INTEGRATED ON CHIP DETECTOR AND ZERO WAVEGUIDE MODULE STRUCTURE FOR USE IN DNA SEQUENCING - A semiconductor structure for use in single molecule real time DNA sequencing technology is provided. The structure includes a semiconductor substrate including a first region and an adjoining second region. A photodetector is present in the first region and a plurality of semiconductor devices is present in the second region. A contact wire is located on a surface of a dielectric material that surrounds the photodetector and contacts a topmost surface of the photodetector and a portion of one of the semiconductor devices. An interconnect structure is located above the first region and the second region, and a metal layer is located atop the interconnect structure. The metal layer has a zero waveguide module located above the first region of the semiconductor substrate. A DNA polymerase can be present at the bottom of the zero waveguide module. | 2017-09-14 |
20170263802 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor substrate, an insulating layer made of silicon oxide formed on the semiconductor substrate and a semiconductor layer made of silicon formed on the insulating layer are provided, and the semiconductor layer constitutes an optical waveguide in an optical signal transmission line section and an optical modulator in an optical modulation section. Also, the insulating layer is removed except for a part thereof to have a hollow structure with a cavity, and both side surfaces and a lower surface of each of the semiconductor layers constituting the optical waveguide and the optical modulator are exposed and covered with air. | 2017-09-14 |
20170263803 | Edgelit Multi-Panel Lighting System - A lighting system can include a lightguide having an edge and two major surfaces. The lightguide can be mounted in a frame so that one of the major surfaces faces towards an area to be illuminated, while the other major surface faces away from the area. LEDs can couple light into the lightguide edge, with the coupled light emitting from both major surfaces. Light emitted from the major surface that faces away from the area to be illuminated can be reflected back into the lightguide by a reflective surface. The reflective surface can be separated from the lightguide by an air gap. The air gap can promote internal reflection at the major surface facing away from the area to be illuminated, thereby enhancing homogeneity and output of light towards the area to be illuminated. The frame can include integral wireways, reflector retention clips, and grounding circuitry. | 2017-09-14 |
20170263804 | INTEGRATED PHOTOSENSITIVE FILM AND THIN LED DISPLAY - A system to configure a conductive pathway and a method of forming a system of configurable conductivity pathways include a photosensitive layer that becomes conductive based on photoexcitation, and a light source layer deposited over the photosensitive layer, the light source layer selectively providing the photoexcitation to the photosensitive layer. The system further includes a controller to control the light source layer, the controller illuminating a portion of the light source layer corresponding with a user input image to photoexcite the photosensitive layer and configure the conductive pathway in the photosensitive layer according to the image. | 2017-09-14 |
20170263805 | Optoelectronic Device with Modulation Doping - An improved heterostructure for an optoelectronic device is provided. The heterostructure includes an active region, an electron blocking layer, and a p-type contact layer. The p-type contact layer and electron blocking layer can be doped with a p-type dopant. The dopant concentration for the electron blocking layer can be at most ten percent the dopant concentration of the p-type contact layer. A method of designing such a heterostructure is also described. | 2017-09-14 |
20170263806 | METHOD OF MANUFACTURING DISPLAY DEVICE - To provide a method of manufacturing a display device having an excellent impact resistance property with high yield, in particular, a method of manufacturing a display device having an optical film that is formed using a plastic substrate. The method of manufacturing a display device includes the steps of: laminating a metal film, an oxide film, and an optical filter on a first substrate; separating the optical filter from the first substrate; attaching the optical filter to a second substrate; forming a layer including a pixel on a third substrate; and attaching the layer including the pixel to the optical filter. | 2017-09-14 |
20170263807 | METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR TEMPLATE - There is provided a method for manufacturing a nitride semiconductor template, including the steps of: growing and forming a buffer layer in a thickness of not more than a peak width of a projection and in a thickness of not less than 10 nm and not more than 330 nm on a sapphire substrate formed by arranging conical or pyramidal projections on its surface in a lattice pattern; and growing and forming a nitride semiconductor layer on the buffer layer. | 2017-09-14 |
20170263808 | LIGHT-EMITTING DEVICES AND METHODS OF MANUFACTURING THE SAME - A light-emitting device that may be manufactured includes an n-type semiconductor layer including a first dopant on a substrate, an active layer on the n-type semiconductor layer, and a p-type semiconductor layer including a second dopant on the active layer. The light-emitting device may be formed according to at least one of a first layering process and a second layering process. The first layering process may include implanting the first dopant into the n-type semiconductor layer into the n-type semiconductor layer according to an ion-implantation process, and the second layering process may include implanting the second dopant into the p-type semiconductor layer according to an ion-implantation process. Forming a semiconductor layer that includes an ion-implanted dopant may include thermally annealing the semiconductor layer subsequent to the ion implantation. The p-type semiconductor layer may include magnesium-hydrogen (Mg—H) complexes at a concentration of about 1×10 | 2017-09-14 |
20170263809 | Electronic Devices Comprising N-Type and P-Type Superlattices - A superlattice and method for forming that superlattice are disclosed. In particular, an engineered layered single crystal structure forming a superlattice is disclosed. The superlattice provides p-type or n-type conductivity, and comprises alternating host layers and impurity layers, wherein: the host layers consist essentially of a semiconductor material; and the impurity layers consist of a donor or acceptor material. | 2017-09-14 |
20170263810 | Method for Separating Group 13 Element Nitride Layer, and Composite Substrate - A composite substrate includes a sapphire substrate and a layer of a nitride of a group 13 element provided on the sapphire substrate. The layer of the nitride of the group 13 element is composed of gallium nitride, aluminum nitride or gallium aluminum nitride. The composite substrate satisfies the following formulas (1), (2) and (3). A laser light is irradiated to the composite substrate from the side of the sapphire substrate to decompose crystal lattice structure at an interface between the sapphire substrate and the layer of the nitride of the group 13 element. 5.0≦(an average thickness (μm) of the layer of the nitride of the group 13 element/a diameter (mm) of the sapphire substrate)≦10.0 . . . (1); 0.1≦ a warpage (mm) of said composite substrate×(50/a diameter (mm) of said composite substrate) | 2017-09-14 |
20170263811 | REPAIRING METHOD, MANUFACTURING METHOD, DEVICE AND ELECTRONIC APPARATUS OF MICRO-LED - A repairing method, manufacturing method, device and electronic apparatus of micro-LED are disclosed. The method for repairing micro-LED defects comprises: obtaining a micro-LED defect pattern on a receiving substrate; forming micro-LEDs ( | 2017-09-14 |
20170263812 | Light Emitting Diode and Fabrication Method Thereof - An LED fabrication method includes forming impurity release holes by focusing a laser at the substrate back surface, and forming invisible explosion points by focusing a laser inside the substrate on positions corresponding to the impurity release holes; communicating the impurity release holes with the invisible explosion points to release impurities generated during forming of the invisible explosion points from the substrate through the impurity release holes, thereby avoiding low external quantum efficiency resulting from adherence of impurities to the side wall of the invisible explosion points. By focusing on a position with 10 μm˜40 ˜m inward from the substrate back side, adjusting laser energy and frequency to burn holes inside the substrate to penetrate and expose the substrate back surface, thereby effectively removing by-products, and reducing light absorption by such by-products, light extraction from a side wall of the LED can also be improved and light extraction efficiency is enhanced. | 2017-09-14 |
20170263813 | Advanced Electronic Device Structures Using Semiconductor Structures and Superlattices - Semiconductor structures and methods for forming those semiconductor structures are disclosed. For example, a p-type or n-type semiconductor structure is disclosed. The semiconductor structure has a polar crystal structure with a growth axis that is substantially parallel to a spontaneous polarization axis of the polar crystal structure. The semiconductor structure changes in composition from a wider band gap (WBG) material to a narrower band gap (NBG) material or from a NBG material to a WBG material along the growth axis to induce p-type or n-type conductivity. | 2017-09-14 |
20170263814 | SEMICONDUCTOR STRUCTURE - A semiconductor structure includes a first-type semiconductor layer, a second-type semiconductor layer, a light emitting layer and a hole supply layer. The light emitting layer is disposed between the first-type semiconductor layer and the second-type semiconductor layer. The hole supply layer is disposed between the light emitting layer and the second-type semiconductor layer, and the hole supply layer includes a first hole supply layer and a second hole supply layer. The first hole supply layer is disposed between the light emitting layer and the second hole supply layer, and a chemical formula of the first hole supply layer is Al | 2017-09-14 |
20170263815 | Group 13 Element Nitride Crystal Substrate and Function Element - A crystal substrate is composed of a crystal of a nitride of a group 13 element and has a first main face and a second main face. The crystal substrate includes a low carrier concentration region and a high carrier concentration region both extending between the first main face and second main face. The low carrier concentration region has a carrier concentration of 10 | 2017-09-14 |
20170263816 | LIGHT-EMITTING DEVICE - A light-emitting device includes an emission structure, a current block layer on the emission structure, a reflective layer on the current block layer, a protection layer that covers the reflective layer, and an electrode layer on the protection layer. | 2017-09-14 |
20170263817 | Nitride Semiconductor Ultraviolet Light-Emitting Element and Nitride Semiconductor Ultraviolet Light-Emitting Device - There is provided a nitride semiconductor ultraviolet light-emitting element capable of efficiently releasing a waste heat generated in an ultraviolet light emitting operation. The nitride semiconductor ultraviolet light-emitting element includes a semiconductor laminated portion | 2017-09-14 |
20170263818 | LIGHT-EMITTING DEVICE - A light-emitting device, includes: a substrate; a light-emitting structure formed on the substrate and including a first portion, and a second portion where no optoelectronic conversion occurs therein; and a first electrode located on both the first portion and the second portion. | 2017-09-14 |
20170263819 | Semiconductor Element and Fabrication Method Thereof - A semiconductor element has a metal protective layer and a metal oxide protective layer formed on the substrate to prevent the Si substrate surface from forming an amorphous layer; and a transition layer to reduce lattice difference between the metal oxide protective layer and the III-IV-group buffer layer, thus improving crystal quality of the III-IV-group buffer layer. A fabrication method can avoid formation of amorphous layers and cracks surrounding the Si substrate surface. A light-emitting diode (LED) element or a transistor element can be formed by depositing a high-quality multi-layer buffer structure via PVD and forming a GaN, InGaN or AlGaN epitaxial layer thereon. | 2017-09-14 |
20170263820 | LIGHT-EMITTING DEVICE - A light-emitting device is provided. The light-emitting device comprises: a light-emitting stack having an active layer emitting first light having a peak wavelength λ nm; and an adjusting element stacked electrically connected to the active layer in series for tuning a forward voltage of the light-emitting device; wherein the forward voltage of the light-emitting device is between (1240/0.8λ) volt and (1240/0.5λ) volt. | 2017-09-14 |
20170263821 | LIGHT-EMITTING DIODE - The present invention relates to a light-emitting diode having enhanced liability. More particularly, a light-emitting diode has enhanced liability in a high-temperature and/or high humidity environment as well as in a room-temperature environment and can have decrease in light-emitting characteristics prevented. In addition, the present invention relates to a light-emitting diode comprising a structure which enables enhancing of light reflection and having enhanced light extraction efficiency by means of light reflection through the structure. | 2017-09-14 |