37th week of 2017 patent applcation highlights part 57 |
Patent application number | Title | Published |
20170263622 | Embedded SONOS Based Memory Cells - Memory devices and methods for forming the same are disclosed. In one embodiment, the device includes a non-volatile memory (NVM) transistor formed in a first region of a substrate, the NVM transistor comprising a channel and a gate stack on the substrate overlying the channel. The gate stack includes a dielectric layer on the substrate, a charge-trapping layer on the dielectric layer, an oxide layer overlying the charge-trapping layer, a first gate overlying the oxide layer, and a first silicide region overlying the first gate. The device includes a metal-oxide-semiconductor transistor formed in a second region of the substrate comprising a gate oxide overlying the substrate in the second region, a second gate overlying the gate oxide, and second silicide region overlying the second gate. A strain inducing structure overlies at least the NVM transistor and a surface of the substrate in the first region of the substrate. | 2017-09-14 |
20170263623 | Memory Device with Multi-Layer Channel and Charge Trapping Layer - A 3-D/vertical non-volatile (NV) memory device such as 3-D NAND flash memory and fabrication method thereof, the NV memory device includes vertical openings disposed in a stack of alternating stack layers of first stack layers and second stack layers over a wafer, a multi-layer dielectric disposed over an inner sidewall of each opening, a first channel layer disposed over the multi-layer dielectric, and a second channel layer disposed over the first channel layer, in which at least one of the first or second channel layers includes polycrystalline germanium or silicon-germanium. | 2017-09-14 |
20170263624 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device according to an embodiment comprises: a semiconductor substrate; a semiconductor layer provided extending in a first direction above the semiconductor substrate, on the semiconductor substrate; a first insulating layer provided on a side surface of the semiconductor layer; a charge accumulation layer provided on a side surface of the first insulating layer; a block insulating layer provided on a side surface of the charge accumulation layer; and a plurality of conductive layers stacked in the first direction via an insulating layer, in a periphery of the block insulating layer. The block insulating layer includes: a first block insulating layer; and a second block insulating layer that has a permittivity which is higher than that of the first block insulating layer. A lower end of the second block insulating layer is positioned more upwardly than a lower end of the first insulating layer. | 2017-09-14 |
20170263625 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to an embodiment, a semiconductor memory device includes a substrate, at least one stacked body, and a first insulating film. The stacked body includes a first end portion positioned at an end in at least one of a first direction and a second direction that crosses the first direction along a surface of the substrate, the plurality of electrode layers being formed into stairs in the first end portion, each of the plurality of electrode layers having a step in the first end portion. The first insulating film is provided on the substrate and includes first and second surfaces, the first and second surfaces surrounding the first end portion, the first surface being crossing a direction that the steps are formed, the second surface being positioned along the direction that the steps are formed. | 2017-09-14 |
20170263626 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to an embodiment, a semiconductor memory device comprises: a plurality of control gate electrodes stacked above a substrate; a first semiconductor layer extending in a first direction above the substrate and facing the plurality of control gate electrodes; a gate insulating layer extending in the first direction and provided between the control gate electrode and first semiconductor layer; and a second semiconductor layer positioned downwardly of the first semiconductor layer and gate insulating layer, and connected to a lower end of the first semiconductor layer and the substrate. Moreover, the first semiconductor layer comprises: a first portion contacting an upper surface of the second semiconductor layer at a position more downward than a lower end of the gate insulating layer; and a second portion connected to an upper end of the first portion, extending in the first direction, and having a different crystalline structure from the first portion. | 2017-09-14 |
20170263627 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor memory device includes a semiconductor layer, a stacked body on the semiconductor layer, the stacked body including a first insulating layer and an electrode layer, a channel layer within and extending through the stacked body and electrically connected to the semiconductor layer, a second insulating layer between the channel layer and the electrode layer, a charge storage layer between the second insulating layer and the electrode layer, and a third insulating layer between the charge storage layer and the electrode layer. The third insulating layer includes an insulating film on a side of the charge storage layer and a first dielectric layer on a side of the electrode layer. The first dielectric layer includes a first material, a second material, and oxygen. The first material has a dielectric constant higher than a dielectric constant of aluminum oxide when the first material is converted into an oxide, and an oxide of the second material has a dielectric constant lower than the dielectric constant of the oxide of the first material. | 2017-09-14 |
20170263628 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to the embodiment, the semiconductor device includes: a stacked body; first interconnect and a second interconnect; a first columnar portion, a second columnar portion, a third columnar portion, and a fourth columnar portion; a first intermediate interconnect; a first connection portion; a second connection portion; and a second intermediate interconnect. The stacked body includes a plurality of electrode layers. The first interconnect and the second interconnect are provided on the stacked body, and extend in a first direction crossing a stacking direction of the stacked body. The first intermediate interconnect is electrically connected to the first interconnect, the first columnar portion, and the second columnar portion. The second intermediate interconnect is provided at a height different from a height of the first intermediate interconnect, and is electrically connected to the second interconnect, the third columnar portion, and the fourth columnar portion. | 2017-09-14 |
20170263629 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a substrate; a stacked body; a first columnar portion; a second columnar portion; and a plurality of first interconnects. The stacked body is provided on the substrate and includes a plurality of electrode layers separately stacked each other. A distance between the first columnar portion and one end of the plurality of electrode layers in the first direction is smaller than a distance between the second columnar portion and the other end of the plurality of electrode layers in the first direction. In the same electrode layer, a first width of a first charge storage film of the first columnar portion is smaller than a second width of a second charge storage film of the second columnar portion. | 2017-09-14 |
20170263630 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a columnar section and an interconnection section. The stacked body includes a first insulating layer, a first electrode layer, a second insulating layer, and a second electrode layer. The first insulating layer includes a first surface facing the substrate, and a second surface facing the first electrode layer and opposite to the first surface. The second insulating layer includes a third surface facing the first electrode layer, and a fourth surface facing the second electrode layer and opposite to the third surface. A width of the interconnection section located between the first surface and the second surface in a second direction perpendicular to a stacking direction and a first direction is larger than a width of the interconnection section located between the third surface and the fourth surface in the second direction. | 2017-09-14 |
20170263631 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a first semiconductor region of a first conductivity type; a stacked body; a plurality of columnar portions; a plurality of first insulating portions having a wall configuration; and a plurality of second insulating portions having a columnar configuration. The columnar portions extend in a stacking direction of the stacked body. The columnar portions include a semiconductor body and a charge storage film. The first insulating portions extend in the stacking direction and in a first direction crossing the stacking direction. The second insulating portions extend in the stacking direction. A wide of the second insulating portions along a second direction crossing the first direction in a plane is wider than a wide of the first insulating portions along the second direction. The second insulating portions are disposed in a staggered lattice configuration. | 2017-09-14 |
20170263632 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, columnar portions, and first and second interconnection portions. The stacked body includes insulating layers and electrode layers alternately stacked one layer by one layer on the substrate. The columnar portions are provided between the first and second interconnection portions and include a first row having a first columnar portion and a second row having a second columnar portion, the first columnar portion being positioned closest to the first interconnection portion, and the second columnar portion being positioned closest to the second interconnection portion. A distance between the first interconnection portion and the first columnar portion is smaller than a distance between the second interconnection portion and the second columnar portion, and the distance between the second interconnection portion and the second columnar portion is greater than 20 nanometers. | 2017-09-14 |
20170263633 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to the embodiment, a semiconductor device includes: a substrate; a stacked body provided on the substrate and including a plurality of electrode layers stacked with an insulator interposed; a semiconductor pillar provided on the substrate and in the stacked body; a semiconductor body provided in the stacked body; and an insulating film including a charge storage film provided between the plurality of electrode layers and the semiconductor body, and extending in the stacking direction. The semiconductor body includes a first portion and a second portion. The first portion is surrounded with the plurality of electrode layers and extends in a stacking direction of the stacked body. The second portion is in contact with an upper surface of the semiconductor pillar. | 2017-09-14 |
20170263634 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor memory device according to the embodiment includes a substrate, electrodes, at least one pillar structure, at least one charge storage film, and at least one insulating member. The electrodes are provided on the substrate, are separately stacked each other, and constitute a stacked body. The electrodes have a first width in a first direction along a surface of the substrate and include a portion extending in a second direction crossing the first direction along the surface. The pillar structure is provided in the stacked body and includes a semiconductor layer extending in a stacking direction of the stacked body. The charge storage film is provided between the semiconductor layer and the electrodes. The insulating member has a width in the first direction smaller than the first width, pierces the electrodes, and is provided to extend in the stacking direction. | 2017-09-14 |
20170263635 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor device includes a substrate; a stacked body provided on the substrate, the stacked body including a plurality of electrode layers stacked with an insulator interposed; a semiconductor body provided in the stacked body; and an insulating film. The semiconductor body includes a channel portion extending in a stacking direction of the stacked body, and a lower end portion of the semiconductor body provided between the channel portion and the substrate. The insulating film includes a charge storage film provided between the stacked body and the semiconductor body. A lower end portion of the insulating film surrounds the lower end portion of the semiconductor body. An upper surface of the lower end portion of the insulating film is provided at a lower height than an upper surface of the lower end portion of the semiconductor body in the stacking direction. | 2017-09-14 |
20170263636 | STACKED NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE WITH BURIED SOURCE LINE AND METHOD OF MANUFACTURE - According to one embodiment, a semiconductor device includes a first interconnection, a first semiconductor region, a stacked body, a columnar portion, first insulators, and arrays. The first interconnection is provided on a substrate via a first insulating film interposed. The first semiconductor region is provided on the first interconnection via a second insulating film. The stacked body is provided on the first semiconductor region. The columnar portion is provided in the stacked body. The first insulators are provided in the stacked body. The first insulators extend in the stacking direction and a first direction crossing the stacking direction. The arrays are provided in the first semiconductor region. The arrays each include second semiconductor regions. The second semiconductor regions are separated from each other. The second semiconductor regions are provided under the first insulators. The second semiconductor regions are electrically connected to the first interconnection. | 2017-09-14 |
20170263637 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor memory device according to one embodiment, includes a first electrode film, a plurality of semiconductor members, and a charge storage member. The first electrode film includes three or more first portions and a second portion connecting the first portions to each other. The first portions extend in a first direction and are arranged along a second direction that intersects with the first direction. The plurality of semiconductor members are arranged along the first direction between the first portions and extending in a third direction. The third direction intersects with a plane containing the first direction and the second direction. The charge storage member is disposed between each of the semiconductor members and each of the first portions. The second portion is disposed between the semiconductor members. | 2017-09-14 |
20170263638 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a first region including first memory cells and first wiring layers, and a second region including second memory cells and second wiring layers, the first and second wiring layers each including a first level wiring layer and a second level wiring layer. End portions of the first and second wiring layers extend in a first direction into a wiring pullout region, such that each of the first and second level wiring layers has an exposed upper surface. The exposed upper surfaces of the first and second level wiring layers are adjacent in a second direction crossing the first direction. First and second contacts are arranged respectively on the exposed surfaces of the first and second level wiring layers, such that the first contacts and the second contacts are arranged respectively along first and second lines extending in the first direction | 2017-09-14 |
20170263639 | SEMICONDUCTOR STORAGE DEVICE - According to one embodiment, a semiconductor storage device includes a substrate including an insulating region and a semiconductor region, an insulating film disposed on upper surfaces of the semiconductor region and the insulating region, a first conductive film disposed on an upper surface of the insulating film, and including a terrace region, and a first contact plug disposed on an upper surface of the terrace region of the first conductive film. The insulating region includes an upper surface positioned directly under the first contact plug. A lower surface of the insulating film is in contact with the upper surfaces of the semiconductor region and the insulating region, in the region directly under the terrace region. | 2017-09-14 |
20170263640 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a nonvolatile semiconductor memory device includes a semiconductor layer, a first electrode, first to third layers, and nitride portions of nitride molecules. The first layer is provided between the semiconductor layer and the first electrode. The second layer is provided between the first layer and the first electrode. The second energy of a conduction band edge of the second layer is lower than a first energy of a conduction band edge of the first layer. The second layer includes a first region and a second region. The first region is provided between the first layer and the second region. The third layer is provided between the second layer and the first electrode. The third energy of a conduction band edge of the third layer is higher than the second energy. | 2017-09-14 |
20170263641 | Three-Dimensional Semiconductor Memory Devices - Three-dimensional (3D) nonvolatile memory devices include a substrate having a well region of second conductivity type (e.g., P-type) therein and a common source region of first conductivity type (e.g., N-type) on the well region. A recess extends partially (or completely) through the common source region. A vertical stack of nonvolatile memory cells on the substrate includes a vertical stack of spaced-apart gate electrodes and a vertical active region, which extends on sidewalls of the vertical stack of spaced-apart gate electrodes and on a sidewall of the recess. Gate dielectric layers extend between respective ones of the vertical stack of spaced-apart gate electrodes and the vertical active region. The gate dielectric layers may include a composite of a tunnel insulating layer, a charge storage layer, a relatively high bandgap barrier dielectric layer and a blocking insulating layer having a relatively high dielectric strength. | 2017-09-14 |
20170263642 | Vertical Resistor In 3D Memory Device With Two-Tier Stack - A vertical, columnar resistor in a semiconductor device is provided, along with techniques for fabricating such a resistor. The resistor may be provided in a peripheral area of a 3D memory device which has a two-tier or other multi-tier stack of memory cells. The structure and fabrication of the resistor can be integrated with the structure and fabrication of the stack of memory cells. The resistor may comprise doped polysilicon. In an example implementation, a polysilicon pillar extends a height of a first tier of the stack and a metal pillar above the polysilicon pillar extends a height of a second tier of the stack. | 2017-09-14 |
20170263643 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - A semiconductor device includes a plurality of first insulating layers and a plurality of second layers alternately and vertically stacked on a substrate. Each of the plurality of second layers includes a horizontal electrode horizontally separated by a second insulating layer. A contact plug penetrates the plurality of first insulating layers and the second insulating layer of the plurality of second layers. | 2017-09-14 |
20170263644 | PIXEL STRUCTURE AND FABRICATION METHOD THEREOF - A pixel structure and a fabrication method thereof are provided, and the fabrication method includes steps as follows. A gate and a scan line connected to the gate electrode are formed on a substrate. An insulation layer is formed on the substrate and is patterned to form an opening corresponding to the gate electrode. A gate insulation layer is formed to cover the gate electrode and the scan line. A channel layer is formed on the gate insulation layer and is located in the opening. A first ohmic contact layer and a second ohmic contact layer are formed on the channel layer and are located in the opening. A source electrode, a drain electrode and a data line connected to the source electrode are formed on the first ohmic contact layer and the second ohmic contact layer. A first electrode is formed and is electrically connected to the drain electrode. | 2017-09-14 |
20170263645 | SUBSTRATE, MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE - A substrate comprising a base, and a copper metallic layer and a first barrier layer disposed on the base in sequence, and further comprising a connecting layer positioned on the first barrier layer; the connecting layer is configured to connect photoresist coated on the connecting layer and the first barrier layer. | 2017-09-14 |
20170263646 | THIN FILM TRANSISTOR ARRAY PANEL AND A METHOD FOR MANUFACTURING THE SAME - A thin film transistor array panel including: a substrate; a semiconductor layer disposed on the substrate; a source electrode and a drain electrode overlapping the semiconductor layer, and a gate electrode overlapping the semiconductor layer; and a first ohmic contact disposed between the semiconductor layer and the source electrode and a second ohmic contact disposed between the semiconductor layer and the drain electrode. The semiconductor layer includes a channel part that does not overlap the source electrode and the drain electrode. The first ohmic contact includes a first edge and the second ohmic contact includes a second edge. The first and second edges face each other across the channel part of the semiconductor layer. The first edge of the first ohmic contact is protruded from the source electrode toward the channel part and the second edge of the second ohmic contact is protruded from the drain electrode toward the channel part. | 2017-09-14 |
20170263647 | SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF - A method is provided for fabricating a semiconductor structure. The method includes providing a bottom substrate having a first region and a second region, and forming a trench in the first region by patterning the bottom substrate. The method also includes forming an insulation layer in the trench in the first region, wherein the insulation layer exposes part of side surface of the trench, and forming a top substrate on the exposed side surface of the trench and the insulation layer. Further, the method includes forming a first fin portion in the first region, and forming a gate structure crossing the first fin portion, wherein the gate structure covers part of side and top surfaces of the first fin portion. | 2017-09-14 |
20170263648 | ARRAY SUBSTRATE, DISPLAY DEVICE AND WEARABLE APPARATUS - The present disclosure discloses that an array substrate, including a base substrate having a circular or oval horizontal section, wherein the base substrate comprises a display region and a non-display region, wherein a plurality of first signal lines, a plurality of second signal lines crossing the plurality of first signal lines, a plurality of thin film transistors and a plurality of pixel electrodes are arranged in the display region, and the plurality of thin film transistors and the plurality of pixel electrodes are arranged in a plurality of pixel regions defined by the plurality of first signal lines and the plurality of second signal lines, wherein a connection wire connected to the plurality of first signal lines and the plurality of second signal lines is arranged in the non-display region. | 2017-09-14 |
20170263649 | Display Device - In a display device which includes a display panel in which a plurality of pixels are arranged on a substrate two-dimensionally and which is configured to display an image therein, and a support member which supports the display panel, the support member possesses anisotropy in bending strength so as to encourage one-dimensional deformation (bending along only the X directional) of the display panel while suppressing two-dimensional deformation (bending in the X direction as well as the Y direction) of the display panel. | 2017-09-14 |
20170263650 | SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE - A semiconductor device which can retain data for a long period is provided. The semiconductor device includes a memory circuit and a retention circuit. The memory circuit includes a first transistor and the retention circuit includes a second transistor. The memory circuit is configured to write data by turning on the first transistor and to retain the data by turning off the first transistor. The retention circuit is configured to supply a first potential at which the first transistor is turned off to a back gate of the first transistor by turning on the second transistor and to retain the first potential by turning off the second transistor. The first transistor and the second transistor have different electrical characteristics. | 2017-09-14 |
20170263651 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR WAFER, MODULE, ELECTRONIC DEVICE, AND MANUFACTURING METHOD THE SAME - A semiconductor device including a transistor having high reliability is provided. The semiconductor device includes a transistor. The transistor includes first and second gate electrodes, a source electrode, a drain electrode, first to third oxides, first and second barrier films, and first and second gate insulators. The first barrier film is located over the source electrode, the second barrier film is located over the drain electrode, and the first and second barrier films each have a function of blocking oxygen and impurities such as hydrogen. | 2017-09-14 |
20170263652 | DISPLAY DEVICE - A display device includes a first pixel, a second pixel, a first substrate, and a second substrate. The first pixel includes a first pixel electrode, a first conductive film, and a first transistor. The first pixel electrode is electrically connected to the first transistor. The first conductive film includes a region functioning as a common electrode. The second pixel includes a second pixel electrode, a second conductive film, and a second transistor. The second pixel electrode is electrically connected to the second transistor. The second conductive film includes a region functioning as a common electrode. The first conductive film and the second pixel electrode are provided on the same plane. A first insulating film is provided over the first conductive film and the second pixel electrode. The first pixel electrode and the second conductive film are provided over the first insulating film. | 2017-09-14 |
20170263653 | PIXEL STRUCTURE - A pixel structure including a first pixel unit, a second pixel unit, a first insulating layer, and a common electrode is provided. The first and second pixel units are disposed on a substrate, and includes a first drain and a first pixel electrode, and a second drain and a second pixel electrode, respectively. The first insulating layer covers the first and second drains. The first and second pixel electrodes are disposed on the first insulating layer, and the first insulating layer has first and second contact holes uncovering the first and second drains, respectively. The common electrode is disposed on the first insulating layer, and is electrically insulated from the first and second pixel electrodes, and has a common opening. When projected onto the substrate, the first and second contact holes are disposed within a region of the common opening. | 2017-09-14 |
20170263654 | SEMICONDUCTOR DEVICE - A semiconductor device having a high aperture ratio and including a capacitor capable of increasing the charge capacity is provided. A semiconductor device includes a transistor over a substrate, a first light-transmitting conductive film over the substrate, an oxide insulating film covering the transistor and having an opening over the first light-transmitting conductive film, a nitride insulating film over the oxide insulating film and in contact with the first light-transmitting conductive film in the opening, a second light-transmitting conductive film connected to the transistor and having a depressed portion in the opening, and an organic resin film with which the depressed portion of the second light-transmitting conductive film is filled. | 2017-09-14 |
20170263655 | METHOD FOR MANUFACTURING ARRAY SUBSTRATE, ARRAY SUBSTRATE AND DISPLAY DEVICE - Disclosed is a method for manufacturing an array substrate, the array substrate and a display device which can reduce manufacturing steps of a color filter process and further reduce manufacturing steps of the display device, thereby saving manufacturing cost and time. The method for manufacturing the array substrate includes: forming a thin film transistor on a base substrate; forming a passivation layer having a via hole on a front side of the thin film transistor and forming a photo spacer on a front side of the passivation layer through a halftone mask patterning process. With this method for manufacturing the array substrate, there is no need to prepare the photo spacer on a back side of the color filter substrate. Therefore, it is possible to reduce manufacturing steps of a color filter process, which in turn further reduces manufacturing steps of the display device, thereby saving manufacturing cost and time. | 2017-09-14 |
20170263656 | SENSORS INCLUDING COMPLEMENTARY LATERAL BIPOLAR JUNCTION TRANSISTORS - An integrated radiation sensor for detecting the presence of an environmental material and/or condition includes a sensing structure and first and second lateral bipolar junction transistors (BJTs) having opposite polarities. The first lateral BJT has a base that is electrically coupled to the sensing structure and is configured to generate an output signal indicative of a change in stored charge in the sensing structure. The second lateral BJT is configured to amplify the output signal of the first bipolar junction transistor. The first and second lateral BJTs, the sensing structure, and the substrate on which they are formed comprise a monolithic structure. | 2017-09-14 |
20170263657 | Image Sensor Device and Method - A system and method for forming pixels in an image sensor is provided. In an embodiment, a semiconductor device includes an image sensor including a first pixel region and a second pixel region in a substrate, the first pixel region being adjacent to the second pixel region. A first anti-reflection coating is over the first pixel region, the first anti-reflection coating reducing reflection for a first wavelength range of incident light. A second anti-reflection coating is over the second pixel region, the second anti-reflection coating reducing reflection for a second wavelength range of incident light that is different from the first wavelength range. | 2017-09-14 |
20170263658 | SOLID-STATE IMAGE SENSOR AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a solid-state image sensor, includes forming a first isolation region of a first conductivity type in a semiconductor layer having first and second surfaces, the forming the first isolation region including first implantation for implanting ions into the semiconductor layer through the first surface, forming charge accumulation regions of a second conductivity type in the semiconductor layer, performing first annealing, forming an interconnection on a side of the first surface of the semiconductor layer after the first annealing, and forming a second isolation region of the first conductivity type in the semiconductor layer, the forming the second isolation region including second implantation for implanting ions into the semiconductor layer through the second surface. The first and second isolation regions are arranged between the adjacent charge accumulation regions. | 2017-09-14 |
20170263659 | MECHANISMS FOR FORMING IMAGE SENSOR DEVICE WITH DEEP-TRENCH ISOLATION STRUCTURE - An image-sensor device is provided. The image-sensor device includes a semiconductor substrate and a radiation-sensing region in the semiconductor substrate. The image-sensor device also includes a doped isolation region adjacent to the radiation-sensing region. The image-sensor device further includes a dielectric film extending into the doped isolation region from a surface of the semiconductor substrate. A portion of the doped isolation region is between the dielectric film and the radiation-sensing region. | 2017-09-14 |
20170263660 | SOLID-STATE IMAGING DEVICE - A solid-state imaging device has a plurality of micro lenses, a first substrate, and a second substrate. The first substrate has a plurality of first photoelectric conversion units. Each of the plurality of first photoelectric conversion units corresponds to any one of the plurality of micro lenses. The second substrate has a plurality of second photoelectric conversion units and a plurality of third photoelectric conversion units. A plurality of pairs of photoelectric conversion units are disposed, and each of the plurality of pairs of photoelectric conversion units includes one of the second photoelectric conversion units and one of the third photoelectric conversion units. Each of the plurality of pairs of photoelectric conversion units corresponds to at least one of the plurality of first photoelectric conversion units. The second substrate further includes charge isolation regions disposed between the second photoelectric conversion units and the third photoelectric conversion units. | 2017-09-14 |
20170263661 | IMAGING DEVICE, MODULE, AND ELECTRONIC DEVICE - An object is to provide an imaging device with high efficiency of transferring charge corresponding to imaging data. The imaging device includes first to fifth conductors, first and second insulators, an oxide semiconductor, a photoelectric conversion element, and a transistor. The first conductor is in contact with a bottom surface and a side surface of the first insulator. The first insulator is in contact with a bottom surface of the oxide semiconductor. The oxide semiconductor is in contact with bottom surfaces of the second and third conductors and the second insulator. Each of the second and third conductors is in contact with the bottom surface and a side surface of the second insulator. The second insulator is in contact with bottom surfaces of the fourth and fifth conductors. The first conductor has regions overlapped by the fourth and fifth conductors. The second conductor has a region overlapped by the fourth conductor. The third conductor has a region overlapped by the fifth conductor. The second conductor is electrically connected to one electrode of the photoelectric conversion element. The third conductor is electrically connected to a gate of the transistor. | 2017-09-14 |
20170263662 | IMAGE-SENSOR STRUCTURES - An image-sensor structure is provided. The image-sensor structure includes a substrate with a plurality of photoelectric conversion units formed therein, a plurality of color filters formed above the substrate, wherein the color filters are divided into red color filters, green color filters and blue color filters, a plurality of microlenses correspondingly formed above the color filters, a transparent material layer formed above the microlenses, a first filter blocking infrared (IR) light formed above the transparent material layer, a second filter allowing transmission of visible light formed above the first filter, and a lens module formed above the second filter. | 2017-09-14 |
20170263663 | PHOTOSENSITIVE COLORING COMPOSITION, METHOD FOR MANUFACTURING SOLID-STATE IMAGING ELEMENT USING SAME, AND SOLID-STATE IMAGING ELEMENT - The invention provides a photosensitive coloring composition comprising a specific combination of a coloring agent, a photopolymerization initiator, and a photopolymerizable component that ensures excellent pattern processability and serves to produce a solid state imaging element with high image quality. | 2017-09-14 |
20170263664 | IMAGING APPARATUS - An imaging apparatus includes a micro lens, a second photoelectric conversion element that is located adjacent to a first photoelectric conversion element in a first direction, and a third photoelectric conversion element that is located adjacent to the first photoelectric conversion in a second direction intersecting with the first direction, wherein the height of a potential barrier produced at a region between the first and third photoelectric conversion elements against a signal charge is less than the height of a potential barrier produced at a region between the first and second photoelectric conversion elements against a signal charge. | 2017-09-14 |
20170263665 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND ELECTRONIC APPARATUS - A semiconductor device includes a first semiconductor substrate in which a pixel region where pixel portions performing photoelectric conversion are two-dimensionally arranged is formed and a second semiconductor substrate in which a logic circuit processing a pixel signal output from the pixel portion is formed, the first and second semiconductor substrates being laminated. A protective substrate protecting an on-chip lens is disposed on the on-chip lens in the pixel region of the first semiconductor substrate with a sealing resin interposed therebetween. | 2017-09-14 |
20170263666 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD - A semiconductor device includes a first substrate having an attaching surface on which first electrodes and a first insulating film are exposed, an insulating thin film that covers the attaching surface of the first substrate, and a second substrate which has an attaching surface on which second electrodes and a second insulating film are exposed and is attached to the first substrate in a state in which the attaching surface of the second substrate and the attaching surface of the first substrate are attached together sandwiching the insulating thin film therebetween, and the first electrodes and the second electrodes deform and break a part of the insulating thin film so as to be directly electrically connected to each other. | 2017-09-14 |
20170263667 | Semiconductor Devices, Methods of Manufacturing Thereof, and Image Sensor Devices - Semiconductor devices, methods of manufacturing thereof, and image sensor devices are disclosed. In some embodiments, a semiconductor device comprises a semiconductor chip comprising an array region, a periphery region, and a through-via disposed therein. The semiconductor device comprises a guard structure disposed in the semiconductor chip between the array region and the through-via or between the through-via and a portion of the periphery region. | 2017-09-14 |
20170263668 | IMAGE SENSORS EMPLOYING SENSITIZED SEMICONDUCTOR DIODES - In various example embodiments, the inventive subject matter is an image sensor and methods of formation of image sensors. In an embodiment, the image sensor comprises a semiconductor substrate and a plurality of pixel regions. Each of the pixel regions includes an optically sensitive material over the substrate with the optically sensitive material positioned to receive light. A pixel circuit for each pixel region is also included in the sensor. Each pixel circuit comprises a charge store formed on the semiconductor substrate and a read out circuit. A non-metallic contact region is between the charge store and the optically sensitive material of the respective pixel region, the charge store being in electrical communication with the optically sensitive material of the respective pixel region through the non-metallic contact region. | 2017-09-14 |
20170263669 | IMAGING DEVICE - An imaging device including: pixel cells each comprising: a photoelectric converter including two electrodes and a photoelectric conversion layer therebetween; a field effect transistor having a gate and a channel region; and a node between the photoelectric converter and the field effect transistor. The field effect transistor outputs an electric signal corresponding to change in dielectric constant between the electrodes, the change being caused by incident light on the photoelectric conversion layer. Cpd | 2017-09-14 |
20170263670 | METHOD OF MANUFACTURING IMAGE CAPTURING APPARATUS - A method of manufacturing an image capturing apparatus is provided. The method comprises forming a structure which includes an interlayer insulation film having a plurality of opening portions above an imaging and a peripheral region, forming a first film so as to cover the structure arranged above the imaging and the peripheral region while filling the plurality of opening portions, planarizing the first film to form a waveguide member above the imaging and the peripheral region, forming a second film so as to cover the waveguide member above the imaging and the peripheral region after the planarizing the first film, polishing the second film to expose the waveguide member arranged above the imaging region and removing a portion of the waveguide member arranged above the peripheral region so as to expose the interlayer insulation film after the polishing the second film. | 2017-09-14 |
20170263671 | PROCESS MODULE FOR INCREASING THE RESPONSE OF BACKSIDE ILLUMINATED PHOTOSENSITIVE IMAGERS AND ASSOCIATED METHODS - Backside illuminated photosensitive devices and associated methods are provided. In one aspect, for example, a backside-illuminated photosensitive imager device can include a semiconductor substrate having multiple doped regions forming a least one junction, a textured region coupled to the semiconductor substrate and positioned to interact with electromagnetic radiation where the textured region includes surface features sized and positioned to facilitate tuning to a preselected wavelength of light, and a dielectric region positioned between the textured region and the at least one junction. The dielectric region is positioned to isolate the at least one junction from the textured region, and the semiconductor substrate and the textured region are positioned such that incoming electromagnetic radiation passes through the semiconductor substrate before contacting the textured region. Additionally, the device includes an electrical transfer element coupled to the semiconductor substrate to transfer an electrical signal from the at least one junction. | 2017-09-14 |
20170263672 | DISPLAY APPARATUS - A display apparatus includes: a substrate; a light-emitting diode (“LED”) disposed above the substrate; a pixel-defining layer disposed above the substrate and including a concave portion which defines a space in which the LED is disposed; a light guider disposed in the space and between the LED and a first inner side surface of the concave portion; and a light blocker disposed above the pixel-defining layer to cover a top portion of the LED. The LED is disposed a second inner side surface of the concave portion, which is opposite to the first inner side surface, and spaced apart from a center of the concave portion, and the light guider guides light emitted from the LED to a region adjacent to the second inner side surface of the concave portion. | 2017-09-14 |
20170263673 | LIGHT EMITTING DEVICE AND LIGHTING APPARATUS - A light emitting device is provided. The light emitting device includes a substrate and a plurality of light emitting elements disposed on a major surface of the substrate. The substrate includes a reflector recessed in the major surface and surrounding at least a portion of the plurality of light emitting elements. | 2017-09-14 |
20170263674 | LIGHT-EMITTING STRUCTURE - A light-emitting structure, comprising: a first light-emitting structure unit and a second light-emitting structure unit, adjacent to and spaced apart from each other; and an electrical connection arranged on the first light-emitting structure unit and the second light-emitting structure unit, and electrically connecting the first light-emitting structure unit and the second light emitting structure unit; wherein the first light-emitting structure unit comprises a first side surface and a second side surface; wherein the first side surface is between the first and the second light-emitting structure units, and the second side surface is not between the first light-emitting structure unit and the second light-emitting structure unit; and wherein the first side surface is inclined and a slope of the first side surface is gentler than a slope of the second side surface. | 2017-09-14 |
20170263675 | METHOD FOR MANUFACTURING MAGNETIC MEMORY DEVICE - A method for manufacturing a magnetic memory device includes forming a magnetic tunnel junction layer that includes a first magnetic layer, a tunnel barrier layer, and a second magnetic layer sequentially stacked on a substrate. First line mask patterns are formed extending in a first direction and spaced apart from each other in a second direction crossing the first direction. The magnetic tunnel junction layer is etched by a first ion-beam etch process using the first line mask patterns as an etch mask to form preliminary magnetic tunnel junctions. Second line mask patterns are formed extending in the second direction and spaced apart from each other in the first direction. The preliminary magnetic tunnel junctions are etched by a second ion-beam process using the second line mask patterns as an etch mask to form magnetic tunnel junctions. | 2017-09-14 |
20170263676 | MAGNETORESISTIVE ELEMENT AND MEMORY DEVICE - According to one embodiment, a magnetoresistive element includes a first metal layer having a body-centered cubic structure, a second metal layer having a hexagonal close-packed structure on the first metal layer, a metal nitride layer on the second metal layer, a first magnetic layer on the metal nitride layer, an insulating layer on the first magnetic layer, and a second magnetic layer on the insulating layer. | 2017-09-14 |
20170263677 | MAGNETORESISTIVE MEMORY DEVICE AND MANUFACTURING METHOD OF THE SAME - According to one embodiment, a magnetoresistive memory device includes a magnetoresistive element of a stacked layer structure includes a first magnetic layer, a second magnetic layer, and a nonmagnetic layer between the first and second magnetic layers, and an insulating layer of a group III-V compound provided on a side of the first magnetic layer of the magnetoresistive element, the insulating layer including an chemical element of group II, group IV, or group VI. | 2017-09-14 |
20170263678 | MAGNETIC MEMORY DEVICE - According to one embodiment, a magnetic memory device includes a stacked structure which comprises a first magnetic layer having a variable magnetization direction, a second magnetic layer, and a nonmagnetic layer provided between the first magnetic layer and the second magnetic layer, and is allowed to be selectively set to a low-resistance state and a high-resistance state having a resistance greater than that of the low-resistance state based on a magnetization direction of the first magnetic layer, the high-resistance state being stable in a stationary state where no current flows through the stacked structure, and a magnetic field supply unit which supplies, to the first magnetic layer, a magnetic field having a direction opposite to a direction of a vertical magnetic field component of a total magnetic field applied from the second magnetic layer to the first magnetic layer. | 2017-09-14 |
20170263679 | MAGNETIC MEMORY DEVICE - According to one embodiment, a magnetic memory device includes a first magnetic layer having a variable magnetization direction, and including a first main surface and a second main surface located opposite to the first main surface, a second magnetic layer provided on a first main surface side of the first magnetic layer, and having a fixed magnetization direction, and a nonmagnetic layer provided between the first magnetic layer and the second magnetic layer, wherein saturation magnetization of part of the first magnetic layer which is located close to the first main surface is higher than saturation magnetization of part of the first magnetic layer which is located close to the second main surface. | 2017-09-14 |
20170263680 | MAGNETORESISTIVE MEMORY DEVICE AND MANUFACTURING METHOD OF THE SAME - According to one embodiment, a magnetoresistive memory device includes an electrode, a first layer which is provided on the electrode and includes an amorphous portion in at least a part of an electrode side, and a magnetoresisive element provided on the first layer. | 2017-09-14 |
20170263681 | SEMICONDUCTOR MEMORY DEVICE HAVING LOCAL BIT LINE WITH INSULATION LAYER FORMED THEREIN - According to one embodiment, a semiconductor memory device includes first conductive layers extending in a first direction and stacked in a second direction intersecting the first direction, a first semiconductor layer extending in the second direction and including a material having one of a first conductivity type and a second conductivity type, a first insulation layer disposed inside the first semiconductor layer, a second conductive layer disposed inside the first insulation layer, and a variable resistance layer disposed between the first conductive layers and the first semiconductor layer. | 2017-09-14 |
20170263682 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device according to an embodiment comprises: a semiconductor substrate which extends in first and second directions; first wiring lines which are arranged in a third direction, and which extend in the first direction; second wiring lines which are arranged in the first direction and extend in the third direction; and memory cells disposed at intersections of the first wiring lines and the second wiring lines, one of the memory cells including a first film and a second film whose permittivity is different from that of the first film which are stacked in the second direction between one of the first wiring lines and one of the second wiring lines, and the second films of two of the memory cells adjacent in the third direction being separated between the two memory cells. | 2017-09-14 |
20170263683 | THREE DIMENSIONAL MEMORY ARRAY WITH SELECT DEVICE - Three dimensional memory arrays and methods of forming the same are provided. An example three dimensional memory array can include a stack comprising a plurality of first conductive lines separated from one another by at least an insulation material, and at least one conductive extension arranged to extend substantially perpendicular to the plurality of first conductive lines such that the at least one conductive extension intersects each of the plurality of first conductive lines. Storage element material is arranged around the at least one conductive extension, and a select device is arranged around the storage element material. The storage element material is radially adjacent an insulation material separating the plurality of first conductive lines, and the plurality of materials arranged around the storage element material are radially adjacent each of the plurality of first conductive lines. | 2017-09-14 |
20170263684 | REPLACEMENT MATERIALS PROCESSES FOR FORMING CROSS POINT MEMORY - Methods of forming memory cells comprising phase change and/or chalcogenide materials are disclosed. In one aspect, the method includes providing a lower line stack extending in a first direction, the lower line stack comprising a sacrificial line over a lower conductive line. The method further includes forming a chalcogenide line extending in the first direction by selectively removing the sacrificial material of the sacrificial line and replacing the sacrificial line with a chalcogenide material. | 2017-09-14 |
20170263685 | Constructions Comprising Stacked Memory Arrays - Some embodiments include a construction having a first memory array deck and a second memory array deck over the first memory array deck. The second memory array deck differs from the first memory array deck in one or more operating characteristics, in pitch, and/or in one or more structural parameters; with the structural parameters including different materials and/or different thicknesses of materials. Some embodiments include a construction having a first series and a third series of access/sense lines extending along a first direction, and a second series of access/sense lines between the first and third series and extending along a second direction which crosses the first direction. First memory cells are between the first and second series of access/sense lines and arranged in a first memory array deck. Second memory cells are between the second and third series of access/sense lines and arranged in a second memory array deck. | 2017-09-14 |
20170263686 | IMAGE SENSORS INCLUDING THOSE PROVIDING GLOBAL ELECTRONIC SHUTTER - Various embodiments include an image sensor providing global electronic shutter having an integrated circuit, a first charge-extracting layer, an optically sensitive layer, and a second hole-extracting layer. In a first mode (the ‘on’ mode), electrons are extracted via the first charge-extracting layer. In a second mode (the ‘off’ mode), the extraction of holes is prevented by the first charge-extracting layer. Other embodiments are disclosed. | 2017-09-14 |
20170263687 | Organic Device - An organic device is disclosed. In an embodiment the organic device includes an organic component designed to emit and/or detect radiation, wherein the organic component has a first layer stack and a radiation passage surface and an organic protection diode having a second layer stack, wherein the organic protection diode is arranged directly after the organic component in a stacking direction (Z), and wherein the organic protection diode is designed to protect the organic component from an electrostatic discharge and/or from a polarity reversal of the organic component. | 2017-09-14 |
20170263688 | PIXEL ISOLATION WALL, DISPLAY SUBSTRATE, THEIR MANUFACTURING METHODS, AND DISPLAY DEVICE - The present disclosure provides a pixel isolation wall and its manufacturing method. The pixel isolation wall includes an oleophilic layer arranged on a substrate on which a TFT array and a pixel electrode array is formed, and an oleophobic layer arranged on the oleophilic layer and configured to define, together with the oleophilic layer, a plurality of recess regions corresponding to the pixel electrode array. | 2017-09-14 |
20170263689 | DISPLAY DEVICE - A display device includes a first substrate, a second substrate facing the first substrate, an IC chip mounted in a non-facing region of a surface of the first substrate, a terminal formed between the IC chip and an edge of the first substrate in the non-facing region, and an FPC connected to the terminal. The surface of the first substrate faces the second substrate. The non-facing region is formed between the edge of the first substrate and an edge of the second substrate. The non-facing region does not face the second substrate. The FPC includes a terminal covering portion covering the terminal and connected to the terminal, and a lateral covering portion covering a lateral portion of the non-facing region. The lateral portion is located in a direction along the edge of the second substrate with respect to the IC chip. The lateral covering portion is attached to the lateral portion. | 2017-09-14 |
20170263690 | DISPLAY DEVICE - A display device includes a display panel including a flexible region and a low flexibility region, wherein the flexible region may include a first transistor including a first semiconductor layer and a first gate electrode, a first conductor connected to the first semiconductor layer, and a first interlayer insulating layer between the first transistor and the first conductor. The low flexibility region may include a second transistor including a second semiconductor layer and a second gate electrode, a second conductor connected to the second semiconductor layer, and a second interlayer insulating layer between the second transistor and the second conductor. The first interlayer insulating layer may include an organic insulating material, the second interlayer insulating layer includes an inorganic insulating material, and a ratio of channel width to channel length of the first transistor may be different from that of the second transistor. | 2017-09-14 |
20170263691 | DISPLAY FOR VIRTUAL REALITY - A display for virtual reality is discussed, which is capable of alleviating a screen-door effect, thereby improving its image quality. In the display for virtual reality, a light diffusion member, which diffuses light emitted from a light-transmitting area of a display panel to a light-blocking area of the display panel, is interposed between the display panel and an optical lens, whereby a user who views an image displayed on the display panel at a very close position does not perceive the light-blocking area, which improves the image quality of the display. | 2017-09-14 |
20170263692 | AIR-CORE INDUCTORS AND TRANSFORMERS - According to an embodiment of the present invention, a method for forming a coil comprises patterning a first mask on a handle wafer, and depositing a conductive material on exposed portions of the handle wafer to partially define the coil. A second mask is patterned on portions of the first mask and the conductive material. A solder material is deposited on a portion of the conductive material to partially define a support member. The solder material is bonded to a wafer, and the handle wafer is separated from the conductive material. | 2017-09-14 |
20170263693 | SEMICONDUCTOR DEVICE - A semiconductor device includes a capacitive element that has frequency dependency that a capacitance value obtained when a second frequency signal that is higher in frequency than a first frequency signal has been applied becomes smaller than a capacitance value obtained when the first frequency signal has been applied and thereby improvement of performance of the semiconductor device is promoted. | 2017-09-14 |
20170263694 | METHOD OF FORMING SEMICONDUCTOR STRUCTURES - A method of making a metal insulator metal (MIM) capacitor includes forming a copper bulk layer in a base layer, wherein the copper bulk layer includes a hillock extending from a top surface thereof. The method further includes depositing an etch stop layer over the base layer and the copper bulk layer. The method further includes depositing an oxide-based dielectric layer over the etch stop layer. The method further includes forming a capacitor over the oxide-based dielectric layer. The method further includes forming a contact extending through the oxide-based dielectric layer and the etch stop layer to contact the copper bulk layer, wherein the forming of the contact removes the hillock. | 2017-09-14 |
20170263695 | DEFORMABLE AND FLEXIBLE CAPACITOR - A method for forming a capacitive device comprises forming a first dielectric layer on a substrate. Portions of the first dielectric layer are removed to for form a cavity in the first dielectric layer. A first layer of conductive material is deposited on the first dielectric layer and conformally along sidewalls of the cavity. The method further includes depositing a second dielectric layer on the first layer of conductive material, and depositing a second layer of conductive material on the second dielectric layer to form a capacitive device. | 2017-09-14 |
20170263696 | HIGH VOLTAGE GALVANIC ISOLATION DEVICE - A microelectronic device contains a high voltage component having a high voltage node and a low voltage node. The high voltage node is isolated from the low voltage node by a main dielectric between the high voltage node and low voltage elements at a surface of the substrate of the microelectronic device. A lower-bandgap dielectric layer is disposed between the high voltage node and the main dielectric. The lower-bandgap dielectric layer contains at least one sub-layer with a bandgap energy less than a bandgap energy of the main dielectric. The lower-bandgap dielectric layer extends beyond the high voltage node continuously around the high voltage node. The lower-bandgap dielectric layer has an isolation break surrounding the high voltage node at a distance of at least twice the thickness of the lower-bandgap dielectric layer from the high voltage node. | 2017-09-14 |
20170263697 | Wide Gap Semiconductor Device and Method of Manufacturing the Same - A wide gap semiconductor device comprises a first conductive-type semiconductor layer ( | 2017-09-14 |
20170263698 | POWER METAL-OXIDE-SEMICONDUCTOR DEVICE - A power metal-oxide-semiconductor (MOS) device is provided. The power MOS device is formed on a semiconductor substrate and includes an active region and a breakdown generated region. The active region includes a plurality of P-type doping regions and a plurality of N-type doping region alternatively arrayed between a source electrode and a drain electrode, and also includes a plurality of gate structures for controlling the conductive state of the active region. The breakdown generated region includes at least one P-type doping region and at least one N-type doping region alternatively arrayed between a source electrode and a drain electrode, and the breakdown voltage of the breakdown generated region is smaller than that of the active region. | 2017-09-14 |
20170263699 | SEMICONDUCTOR DEVICE - A semiconductor device includes a layer having first and second surfaces and a first type first region, a second type second region in the layer between the first region and first surface, a first type third region in the layer between the second region and first surface, first and second gate electrodes, wherein the second region is between the first and second gate electrodes, a first field plate electrode between the second surface and first gate electrode, a second field plate electrode between the second surface and second gate electrode, a first film, at least a portion between the first field plate electrode and first region, a second film at least a portion between the second field plate electrode and first region, and a second type fourth region in the first region between the first and second films. A portion of the first region is between second and fourth regions. | 2017-09-14 |
20170263700 | III-Nitride Based Semiconductor Device with Low Vulnerability to Dispersion and Backgating Effects - The present disclosure is related to a III-Nitride semiconductor device comprising a base substrate, a buffer layer, a channel layer, a barrier layer so that a 2-dimensional charge carrier gas is formed or can be formed near the interface between the channel layer and the barrier layer, and at least one set of a first and second electrode in electrical contact with the 2-dimensional charge carrier gas, wherein the device further comprises a mobile charge layer (MCL) within the buffer layer or near the interface between the buffer layer and the channel layer, when the device is in the on-state. The device further comprises an electrically conductive path between one of the electrodes and the mobile charge layer. The present disclosure is also related to a method for producing a device according to the present disclosure. | 2017-09-14 |
20170263701 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor device includes a substrate, a semiconductor layer that is formed on the substrate and includes a pn junction or a hetero-junction, an insulating film that is formed on the semiconductor layer to be in contact with an end of the pn junction or an end of the hetero-junction, and an electrode formed on the semiconductor layer. The insulating film includes an insulating layer that is mainly made of negatively charged microcrystal. | 2017-09-14 |
20170263702 | SELF-FORMING SPACERS USING OXIDATION - A method of forming a self-forming spacer using oxidation. The self-forming spacer may include forming a fin field effect transistor on a substrate, the fin field effect transistor includes a gate on a fin, the gate is perpendicular to the fin; forming a gate spacer on the gate and a fin spacer on the fin, the gate spacer and the fin spacer are formed in a single step by oxidizing an exposed surface of the gate and an exposed surface of the fin; and removing the fin spacer from the fin. | 2017-09-14 |
20170263703 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor region of a first conductivity type on a first electrode and a second semiconductor region of the first conductivity type on a central portion of the first semiconductor region. The second region has a carrier concentration less than a carrier concentration of the first region. A third semiconductor region of a second conductivity type is on the second semiconductor region. A first insulating portion covers a peripheral surface of the second semiconductor region and a peripheral surface of the third semiconductor region. A second insulating portion is spaced from the first insulating portion in a lateral direction. A void space is between the first and second insulating portions. A third insulating portion is on the third semiconductor region and spans and covers the void space. A second electrode is on the third semiconductor region and the third insulating portion. | 2017-09-14 |
20170263704 | METHODS FOR VARIED STRAIN ON NANO-SCALE FIELD EFFECT TRANSISTOR DEVICES - A semiconductor device and a method to form the semiconductor device are disclosed. An n-channel component of the semiconductor device includes a first horizontal nanosheet (hNS) stack and a p-channel component includes a second hNS stack. The first hNS stack includes a first gate structure having a plurality of first gate layers and at least one first channel layer. A first internal spacer is disposed between at least one first gate layer and a first source/drain structure in which the first internal spacer has a first length. The second hNS stack includes a second gate structure having a plurality of second gate layers and at least one second channel layer. A second internal spacer is disposed between at least one second gate layer and a second source/drain structure in which the second internal spacer has a second length that is greater than the first length. | 2017-09-14 |
20170263705 | NANOWIRE ISOLATION SCHEME TO REDUCE PARASITIC CAPACITANCE - A method for manufacturing a semiconductor device includes forming a doped silicon layer on a bulk substrate, forming an undoped silicon cap layer on the doped silicon layer, forming a stacked configuration of silicon germanium (SiGe) and silicon layers on the undoped silicon cap layer, wherein the stacked configuration comprises a repeating arrangement of a silicon layer stacked on an SiGe layer, forming a plurality of dummy gates spaced apart from each other on the stacked configuration, the doped silicon layer and the undoped silicon cap layer, forming a spacer layer on each of the plurality of dummy gates, and on the doped silicon layer and the undoped silicon cap layer, selectively etching the doped silicon layer with respect to the undoped silicon layer, and filling the area from where the doped s silicon layer was selectively removed with a dielectric layer. | 2017-09-14 |
20170263706 | INGAAS EPI STRUCTURE AND WET ETCH PROCESS FOR ENABLING III-V GAA IN ART TRENCH - Embodiments of the invention include nanowire and nanoribbon transistors and methods of forming such transistors. According to an embodiment, a method for forming a microelectronic device may include forming a multi-layer stack within a trench formed in a shallow trench isolation (STI) layer. The multi-layer stack may comprise at least a channel layer, a release layer formed below the channel layer, and a buffer layer formed below the channel layer. The STI layer may be recessed so that a top surface of the STI layer is below a top surface of the release layer. The exposed release layer from below the channel layer by selectively etching away the release layer relative to the channel layer. | 2017-09-14 |
20170263707 | EXPITAXIALLY REGROWN HETEROSTRUCTURE NANOWIRE LATERAL TUNNEL FIELD EFFECT TRANSISTOR - After forming a buried nanowire segment surrounded by a gate structure located on a substrate, an epitaxial source region is grown on a first end of the buried nanowire segment while covering a second end of the buried nanowire segment and the gate structure followed by growing an epitaxial drain region on the second end of the buried nanowire segment while covering the epitaxial source region and the gate structure. The epitaxial source region includes a first semiconductor material and dopants of a first conductivity type, while the epitaxial drain region includes a first semiconductor material different from the first semiconductor material and dopants of a second conductivity type opposite the first conductivity type. | 2017-09-14 |
20170263708 | HIGH VOLTAGE FIELD EFFECT TRANSISTORS - Transistors suitable for high voltage and high frequency operation. A nanowire is disposed vertically or horizontally on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first semiconductor material, a source region electrically coupled with a first end of the channel region, a drain region electrically coupled with a second end of the channel region, and an extrinsic drain region disposed between the channel region and drain region. The extrinsic drain region has a wider bandgap than that of the first semiconductor. A gate stack including a gate conductor and a gate insulator coaxially wraps completely around the channel region, drain and source contacts similarly coaxially wrap completely around the drain and source regions. | 2017-09-14 |
20170263709 | Field Effect Transistors and Methods of Forming Same - Semiconductor devices and methods of forming the same are provided. A semiconductor device includes a substrate having a fin. A first nanowire is disposed on the fin and a second nanowire is disposed on the fin, the second nanowire being laterally separated from the first nanowire. A gate structure extends around the first nanowire and the second nanowire. The gate structure also extends over a top surface of the fin. The first nanowire, the second nanowire, and the fin form a channel of a transistor. | 2017-09-14 |
20170263710 | SEMICONDUCTOR ELEMENT, ELECTRIC EQUIPMENT, BIDIRECTIONAL FIELD EFFECT TRANSISTOR, AND MOUNTED STRUCTURE BODY - Provided is a semiconductor element in which a two-dimensional hole gas with an enough concentration can exist, even though the p-type GaN layer is not provided on the topmost surface of the polarization super junction region. | 2017-09-14 |
20170263711 | METHOD OF FORMING SEMICONDUCTOR DEVICE HAVING MULTI-CHANNEL - A semiconductor device includes an isolation pattern on a substrate, the isolation pattern having a lower insulating pattern on the substrate, and a spacer to cover side surfaces of the lower insulating pattern, a vertical structure through the isolation pattern to contact the substrate, the vertical structure having a first semiconductor layer on the substrate, a lower end of the first semiconductor layer being at a lower level than a lower surface of the isolation pattern, a second semiconductor layer on the first semiconductor layer, and a third semiconductor layer on the second semiconductor layer, and a gate electrode crossing the vertical structure and extending over the isolation pattern. | 2017-09-14 |
20170263712 | WIDE BANDGAP SEMICONDUCTOR DEVICE INCLUDING TRANSISTOR CELLS AND COMPENSATION STRUCTURE - A semiconductor device includes transistor cells in a semiconductor portion, wherein the transistor cells are electrically connected to a gate metallization, a source electrode and a drain electrode. In one example, the semiconductor device further includes a doped region in the semiconductor portion. The doped region is electrically connected to the source electrode. A resistance of the doped region has a negative temperature coefficient. An interlayer dielectric separates the gate metallization from the doped region. A drain structure in the semiconductor portion electrically connects the transistor cells with the drain electrode and forms a pn junction with the doped region. | 2017-09-14 |
20170263713 | POWER MODULE FOR SUPPORTING HIGH CURRENT DENSITIES - A power module is disclosed that includes a housing with an interior chamber wherein multiple switch modules are mounted within the interior chamber. The switch modules comprise multiple transistors and diodes that are interconnected to facilitate switching power to a load. In one embodiment, at least one of the switch modules supports a current density of at least 10 amperes per cm | 2017-09-14 |
20170263714 | SEMICONDUCTOR DEVICE - A semiconductor device includes first and second electrodes spaced apart along a first direction, a first semiconductor region of a first conductivity type between the first and second electrodes, first and second conductive regions between the first semiconductor region and the second electrode and electrically connected to the second electrode, a third electrode between the first and second conductive regions, second and third semiconductor regions of a second conductivity type respectively between the first and second conductive regions and the third electrode, and fourth and fifth semiconductor regions of the first conductivity type respectively between the second and third semiconductor regions and the second electrode. The third electrode extends in the first direction toward the first electrode farther than portions of the second and third semiconductor regions that are alongside the third electrode. | 2017-09-14 |
20170263715 | METHOD, APPARATUS AND SYSTEM FOR A HIGH DENSITY MIDDLE OF LINE FLOW - At least one method, apparatus and system disclosed herein for forming a finFET device. A gate structure comprising a gate spacer on a semiconductor wafer is formed. A self-aligned contact (SAC) cap is formed over the gate structure. A TS structure is formed. At least one M0 metal structure void is formed. At least one CB structure void adjacent the M0 metal structure void is formed. An etch process is performed the M0 and CB structures voids to the gate structure. At least one CA structure void adjacent the CB structure void is formed. The M0, CB, and CA structure voids are metallized. | 2017-09-14 |
20170263716 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first nitride semiconductor layer, a second nitride semiconductor layer on the first nitride semiconductor layer, a source electrode on the second nitride semiconductor layer and spaced from the source electrode, a drain electrode on the second nitride semiconductor layer and spaced from the source electrode, a gate electrode between the drain and source electrodes, an interlayer insulating film on the second nitride semiconductor layer, a first field plate electrode in contact with an upper surface of the second nitride semiconductor layer at a location between the gate and drain electrodes, and a second field plate electrode extending through the interlayer insulating film and connected to the first field plate electrode. An end of the second field plate electrode on the source electrode side is closer to the drain electrode than is an end of the first field plate electrode on the source electrode side. | 2017-09-14 |
20170263717 | SEMICONDUCTOR DEVICE CAPABLE OF HIGH-VOLTAGE OPERATION - A semiconductor device capable of high-voltage operation includes a semiconductor substrate having a first conductivity type. A first well doped region is formed in a portion of the semiconductor substrate. The first well doped region has a second conductivity type. A first doped region is formed on the first well doped region, having the second conductivity type. A second doped region is formed on the first well doped region and is separated from the first doped region, having the second conductivity type. A first gate structure is formed over the first well doped region and is adjacent to the first doped region. A second gate structure is formed beside the first gate structure and is close to the second doped region. A third gate structure is formed overlapping a portion of the first gate structure and a first portion of the second gate structure. | 2017-09-14 |
20170263718 | TERMINATION TRENCH STRUCTURES FOR HIGH-VOLTAGE SPLIT-GATE MOS DEVICES - Apparatus and associated methods relate to an edge-termination structure surrounding a high-voltage MOSFET for reducing a peak lateral electric field. The edge-termination structure includes a sequence of annular trenches and semiconductor pillars circumscribing the high-voltage MOSFET. Each of the annular trenches is laterally separated from the other annular trenches by one of the semiconductor pillars. Each of the annular trenches has dielectric sidewalls and a dielectric bottom electrically isolating a conductive core within each of the annular trenches from a drain-biased region of the semiconductor pillar outside of and adjacent to the annular trench. The conductive core of the innermost trench is biased, while the conductive cores of one or more outer trenches are floating. In some embodiments, a surface of an inner semiconductor pillar is biased as well. The peak lateral electric field can advantageously be reduced by physical arrangement of trenches and electrical biasing sequence. | 2017-09-14 |
20170263719 | METHOD OF MANUFACTURING A SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR STRUCTURE - A method for manufacturing a semiconductor structure is provided, which may include: forming a p-doped region adjacent to an n-doped region in a substrate; carrying out an anodic oxidation to form an oxide layer on a surface of the substrate, wherein the oxide layer in a first portion of the surface extending along the n-doped region has a greater thickness than the oxide layer in a second portion of the surface extending along the p-doped region. | 2017-09-14 |
20170263720 | Method of Forming a Semiconductor Device - According to an embodiment of a method of forming a semiconductor device, a semiconductor layer including a first dopant species of a first conductivity type and a second dopant species of a second conductivity type different from the first conductivity type is formed. The semiconductor layer is part of a semiconductor body having opposite first and second surfaces. Trenches are formed in the semiconductor layer at the first surface. The trenches are filled with a filling material including at least a semiconductor material. A thermal oxide is formed at one or both of the first and second surfaces, the thermal oxide having a thickness of at least 200 nm. Thermal processing of the semiconductor body causes diffusion of the first and second dopants species into the filling material. | 2017-09-14 |
20170263721 | COPPER-FILLED TRENCH CONTACT FOR TRANSISTOR PERFORMANCE IMPROVEMENT - Methods of fabricating a first contact to a semiconductor device, which fundamentally comprises providing a semiconductor device formed on a substrate. The substrate further includes a conductive surface. A dielectric layer is formed over the substrate and has an opening exposing the conductive surface. The opening extends an entire length of the semiconductor device, partway down the entire length of the device, extending from the device onto adjacent field of the device, or and a combination thereof. A barrier layer is formed within the opening. A copper containing material fills the opening to form a first contact to the semiconductor device. | 2017-09-14 |