37th week of 2017 patent applcation highlights part 55 |
Patent application number | Title | Published |
20170263422 | HEATED SUBSTRATE SUPPORT - A substrate support and method of forming a substrate support are described herein. In one example, a substrate support includes an aluminum body having an upper surface configured to support a large area substrate, a heater element, and a filler material. The aluminum body has a groove formed therein. The heater element is disposed in the groove. The filler material is in contact with the heater element and fills the groove. The contact between the filler material and the perimeter of the heater element is the only material interface within the groove, and the filler material has a larger grain size than a grain size of the aluminum body. | 2017-09-14 |
20170263423 | DEVICE EQUIPPED WITH AN ION BEAM SOURCE FOR COATING A SUBSTRATE IN A VACUUM CHAMBER - A device has an ion beam source for coating at least one substrate in a vacuum chamber, which chamber has an inlet that is closable in a pressure-tight manner using a closure apparatus and through which the at least one substrate can be fixed in the vacuum chamber in a substrate holder in a substrate holder receptacle, and can be removed therefrom once the coating process has finished, wherein the substrate holder, together with the substrate, in the substrate holder receptacle is designed to be reversibly movable in a translational manner inside the vacuum chamber, between turning points that are in particular settable, using a motor-drivable transport apparatus of the device. | 2017-09-14 |
20170263424 | Two-Dimensional Separation and Imaging Technique for the Rapid Analysis of Biological Samples - A method of ion mapping is disclosed comprising depositing a sample onto a target surface and separating the sample on the target surface according to a first physico-chemical property in a first dimension and according to a second physico-chemical property in a second dimension. The method further comprises ionising and mass analysing multiple separate regions of the sample so as to generate an ion map of at least a portion of the sample deposited upon the target surface. The sample is deposited onto and separated on the target surface by mechanical, hydrodynamic and/or aerodynamic means. | 2017-09-14 |
20170263425 | Multi-Dimensional Survey Scans for Improved Data Dependent Acquisitions - A method of analysing ions is disclosed comprising performing an initial multi-dimensional survey scan comprising separating parent ions according to a first physico-chemical property (e.g. ion mobility) and then separating the parent ions according to a second physico-chemical property (e.g. mass to charge ratio). A plurality of parent ions of interest are then determined from the initial multi-dimensional survey scan. Once parent ions of interest have been determined, the plurality of parent ions of interest are sequentially selected based upon the first and second physico-chemical properties during a single cycle of separation. The parent ions of interest may then be fragmented and corresponding fragment ions may then be mass analysed. | 2017-09-14 |
20170263426 | Dynamic Baseline Adjuster - A method of adjusting a baseline value in data received from a mass spectrometer includes generating a plurality of data signal values with a converter. The method also includes categorizing the plurality of data signal values relative to a plurality of threshold values. The plurality of threshold values include a high value, a mid-high value, a mid-low value, and a low value. The method further includes determining (i) a first quantity of data signal values categorized between the high value and the mid-high values, (ii) a second quantity of data signal values categorized between the mid-high value and the mid-low value, and (iii) a third quantity of data signal values categorized between the mid-low value and the low value. The method also includes generating a table of the first quantity of data signal values, the second quantity of data signal values, and the third quantity of data signal values. The method further includes determining whether to increase, decrease, or maintain the baseline value based on the first quantity, the second quantity, and the third quantity. | 2017-09-14 |
20170263427 | INSTRUMENTS FOR MEASURING ION SIZE DISTRIBUTION AND CONCENTRATION - Instruments are disclosed for analyzing ions from about 1000 to 10,000,000 Daltons by controlling a gaseous medium through which the ions travel under the influence of an electric field so that properties of the ions, such as diameter, electrical mobility, and charge, are measured. One embodiment of the disclosed instruments includes an ion source, a nozzle, a jet relaxation region, an ion accumulation region, an electronic gate, a flow chamber and an ion detector. | 2017-09-14 |
20170263428 | Impactor Spray Ion Source - There is provided an ion source comprising one or more nebulisers and one or more targets, wherein said one or more nebulisers are arranged and adapted to emit, in use, a stream predominantly of droplets which are caused to impact upon said one or more targets and to ionise said droplets to form a plurality of ions, wherein said one or more targets further comprise one or more structures configured to disturb gas flowing along a surface of said one or more targets. | 2017-09-14 |
20170263429 | RF Ion Guide - A mass spectrometer is provided having an ion source for generating ions from a sample in a high pressure region, a first vacuum chamber having an inlet aperture, and an exit aperture. The at least one ion guide can be between the inlet and exit apertures and can include an entrance end and an exit end. The at least one ion guide can have a plurality of electrodes arranged around a central axis defining an ion channel, each of the plurality of electrodes being tapered, a planar surface of each of the plurality of tapered electrodes facing the interior of the at least one ion guide, and the surface gradually being narrowed and tilted inward to provide a smaller inscribed radius at the exit; and a power supply for providing an RF voltage to the at least one ion guide. | 2017-09-14 |
20170263430 | Low Cross-Talk Fast Sample Delivery System Based Upon Acoustic Droplet Ejection - An ion source for a mass spectrometer is disclosed comprising an ultrasonic transducer which focuses ultrasonic energy onto a surface of a sample fluid without directly contacting the sample fluid. | 2017-09-14 |
20170263431 | Device for Ion Sorting by M/Z - An RF voltage is applied across each electrode of a first array of evenly spaced, parallel, and coplanar electrodes and its corresponding electrode of a second array of evenly spaced, parallel, and coplanar electrodes. The RF voltage varies in amplitude according to an RF voltage amplitude gradient. The RF voltage produces an array of different quadrupole RF electric fields in a uniform gap between the first array and the second array. A DC voltage is superimposed on each electrode of the first array and its corresponding electrode of the second array. The DC voltage varies according to a DC voltage gradient in order to produce a DC electric field in the uniform gap. When ions are introduced in the uniform gap, the DC electric field causes the ions to drift toward quadrupole RF electric fields with increasing RF voltage amplitudes where the ions are trapped according to their m/z. | 2017-09-14 |
20170263432 | MINIATURE CHARGED PARTICLE TRAP WITH ELONGATED TRAPPING REGION FOR MASS SPECTROMETRY - A miniature electrode apparatus is disclosed for trapping charged particles, the apparatus including, along a longitudinal direction: a first end cap electrode; a central electrode having an aperture; and a second end cap electrode. The aperture is elongated in the lateral plane and extends through the central electrode along the longitudinal direction and the central electrode surrounds the aperture in a lateral plane perpendicular to the longitudinal direction to define a transverse cavity for trapping charged particles. | 2017-09-14 |
20170263433 | Dual Parabolic Laser Driven Sealed Beam Lamps - The invention is directed to a sealed high intensity illumination device configured to receive a laser beam from a laser light source. A sealed chamber is configured to contain an ionizable medium. The chamber includes a reflective chamber interior surface having a first parabolic contour and parabolic focal region, a second parabolic contour and parabolic focal region, and an interface surface. An ingress surface is disposed within the interface surface configured to admit the laser beam into the chamber, and an egress surface disposed within the interface surface configured to emit high intensity light from the chamber. The first parabolic contour is configured to reflect light from the first parabolic focal region to the second parabolic contour, and the second parabolic contour is configured to reflect light from the first parabolic contour to the second parabolic focal region. | 2017-09-14 |
20170263434 | Ultraviolet Discharge Lamp Apparatuses With One Or More Reflectors - Apparatuses are disclosed which include an ultraviolet light (UV) lamp and program instructions for activating an automated actuator such that the lamp is repositioned within the apparatus relative to a structure supporting the lamp while the lamp is emitting ultraviolet light. Other apparatuses include a reflector to redirect light emitted from a UV lamp, wherein the reflector and the lamp comprise a moveable assembly. The apparatuses include an actuator for moving the moveable assembly such that the lamp may be repositioned in and out of a structure supporting the moveable assembly. Yet other apparatuses include a reflector arranged along a longitudinal side of a UV lamp and a housing surrounding the lamp, wherein the reflector and the housing comprise a moveable assembly. The apparatuses include an actuator for providing rotational movement of the moveable assembly about a vertical axis and relative to a structure supporting the moveable assembly. | 2017-09-14 |
20170263435 | FILAMENT ASSEMBLY FOR GENERATING ELECTRONS, AND RELATED DEVICES, SYSTEMS AND METHODS - A filament assembly includes a core and a filament. At least a central portion of the filament is disposed on the core. At least the central portion may be straight or may have a high-resistance configuration such as one in which the filament follows a path that changes direction. A thermionically emissive layer may be disposed on the core so as to encapsulate at least the central portion. The filament assembly may be utilized in any application requiring the production of electrons. | 2017-09-14 |
20170263436 | SYSTEMS AND METHODOLOGIES FOR VAPOR PHASE HYDROXYL RADICAL PROCESSING OF SUBSTRATES - An apparatus and method for processing substrates. The method includes positioning a substrate within a processing chamber of a substrate processing system. The substrate includes a layer of a carbon-containing material on a working surface of the substrate. The method also includes receiving hydrogen peroxide vapor in a vapor treatment region of the substrate processing system, generating hydroxyl radical vapor by treating the hydrogen peroxide vapor in the vapor treatment region, and directing the hydroxyl radical vapor and remaining hydrogen peroxide vapor to the working surface of the substrate causing the carbon-containing material to be chemically modified. | 2017-09-14 |
20170263437 | Selective Deposition Of Silicon Nitride Films For Spacer Applications - Methods for forming a spacer comprising depositing a film on the top, bottom and sidewalls of a feature and treating the film to change a property of the film on the top and bottom of the feature so that the film can be selectively etched from the top and bottom of the feature relative to the film on the sidewalls of the feature. | 2017-09-14 |
20170263438 | Methods And Apparatus For Selective Dry Etch - Methods for forming a spacer comprising depositing a film on the top, bottom and sidewalls of a feature and treating the film to change a property of the film on the top and bottom of the feature. Selectively dry etching the film from the top and bottom of the feature relative to the film on the sidewalls of the feature using a high intensity plasma. | 2017-09-14 |
20170263439 | Method of Manufacturing Semiconductor Device, Substrate Processing Apparatus and Recording Medium - The present disclosure provides a technique including a method of manufacturing a semiconductor device, which is capable of improving the characteristics of a film formed on a substrate. The method of manufacturing a semiconductor device may include: (a) forming a first film containing a predetermined element, oxygen, carbon and nitrogen on a substrate; and (b) forming a second film thinner than the first film on a top surface of the first film, the second film having an oxygen concentration lower than an oxygen concentration of the first film or having oxygen and carbon concentrations lower than oxygen and carbon concentrations of the first film. | 2017-09-14 |
20170263440 | METHOD OF REDUCING DEFECTS IN AN EPITAXIAL LAYER - A method of reducing defects in an epitaxial layer. The method includes forming one or more barrier structures within a peripheral edge region of a wafer substrate, and forming an epitaxial layer over a surface of the wafer substrate. | 2017-09-14 |
20170263441 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING APPARATUS, AND RECORDING MEDIUM - There is provided a method of manufacturing a semiconductor device, including forming a seed layer on a substrate by performing a cycle a predetermined number of times, the cycle including supplying a halogen-based first processing gas to the substrate; supplying a non-halogen-based second processing gas to the substrate; and supplying a hydrogen-containing gas to the substrate. Further, the method further includes forming a film on the seed layer by supplying a third processing gas to the substrate. | 2017-09-14 |
20170263442 | PLASMA STABILIZATION METHOD AND DEPOSITION METHOD USING THE SAME - A plasma stabilization method and a deposition method using the same are disclosed. The plasma stabilization method includes (a) supplying a source gas and (b) supplying a purge gas. The method may also include (c) supplying a reactive gas and (d) supplying plasma. The purge gas and the reactive gas are continuously supplied into a reactor during (a) through (d), and the plasma stabilization method is performed in a state where no substrate exists in the reactor. | 2017-09-14 |
20170263443 | TRENCH AND HOLE PATTERNING WITH EUV RESISTS USING DUAL FREQUENCY CAPACITIVELY COUPLED PLASMA (CCP) - A method for treating a substrate is disclosed. The method includes forming a film stack on the substrate, the film stack comprising an underlying layer, a coating layer disposed above the underlying layer, and a patterning layer disposed above the coating layer. In the method, portions of the patterning layer are removed to form sidewalls of the patterning layer and expose portions of the coating layer, a carbon-containing layer is deposited on the exposed portions of the coating layer and non-sidewall portions of the patterning layer, and the carbon-containing layer and a portion of the coating layer are removed to expose other portions of the coating layer and the patterning layer. The method further includes repeating the deposition and removal of the carbon-coating layer at least until portions of the underlying layer are exposed. | 2017-09-14 |
20170263444 | REFLECTIVE MASK BLANK, METHOD FOR MANUFACTURING SAME, REFLECTIVE MASK, METHOD FOR MANUFACTURING SAME, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - The present invention aims to provide a reflective mask blank and a reflective mask which have a highly smooth multilayer reflective film as well as a low number of defects, and methods of manufacturing the same, and aims to prevent charge-up during a mask defect inspection using electron beams. | 2017-09-14 |
20170263445 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND TEMPLATE FOR NANOIMPRINT - According to one embodiment, there is provided a manufacturing method of a semiconductor device. The method includes forming a film to be processed on a substrate. The method includes forming a first resist pattern on the film, the first resist pattern having a first stepped structure including a plurality of steps. The method includes forming a second resist pattern on the first resist pattern by use of a template for nanoimprint. The second resist pattern has a second stepped structure, which is arranged corresponding to the first stepped structure and is formed such that a step-up surface extends perpendicularly to a flat surface. The method includes processing the film through the second resist pattern and the first resist pattern. | 2017-09-14 |
20170263446 | SAPPHIRE SUBSTRATE RECYCLING METHOD - In order to address the high recycling cost, high complexity and other problems encountered by the prior art, the present invention proposes a method for recycling a sapphire substrate, which is applicable to both patterned and smooth sapphire substrates and involves only two steps: high-temperature baking and high-temperature rinsing in a concentrated acid. It entails a simple process which can be completed with high efficiency in a short period by easy operations at significantly reduced cost. | 2017-09-14 |
20170263447 | Method To Transfer Two Dimensional Film Grown On Metal-Coated Wafer To The Wafer Itself In a Face-To-Face Manner - A method of in-situ transfer during fabrication of a component comprising a 2-dimensional crystalline thin film on a substrate is disclosed. In one embodiment, the method includes forming a layered structure comprising a polymer, a 2-dimensional crystalline thin film, a metal catalyst, and a substrate. The metal catalyst, being a growth medium for the two-dimensional crystalline thin film, is etched and removed by infiltrating liquid to enable the in-situ transfer of the two-dimensional crystalline thin film directly onto the underlying substrate. | 2017-09-14 |
20170263448 | COMPOUND SEMICONDUCTOR DEVICE STRUCTURES COMPRISING POLYCRYSTALLINE CVD DIAMOND - A semiconductor device structure comprising:
| 2017-09-14 |
20170263449 | ROBUST HIGH PERFORMANCE LOW HYDROGEN SILICON CARBON NITRIDE (SiCNH) DIELECTRICS FOR NANO ELECTRONIC DEVICES - A method for depositing a dielectric layer that includes introducing a substrate into a process chamber of a deposition tool; and heating the substrate to a process temperature. The method may further include introducing precursors that include at least one dielectric providing gas species for a deposited layer and at least one hydrogen precursor gas into the process chamber of the deposition tool. The hydrogen precursor gas is introduced to the deposition chamber at a flow rate ranging from 50 sccm to 5000 sccm. The molar ratio for Hydrogen/Silicon gas precursor can be equal or greater than 0.05. | 2017-09-14 |
20170263450 | PLASMA ASSISTED ATOMIC LAYER DEPOSITION METAL OXIDE FOR PATTERNING APPLICATIONS - The embodiments herein relate to methods and apparatus for depositing an encapsulation layer over memory stacks in MRAM and PCRAM applications. The encapsulation layer is a titanium dioxide (TiO | 2017-09-14 |
20170263451 | ROBUST HIGH PERFORMANCE LOW HYDROGEN SILICON CARBON NITRIDE (SiCNH) DIELECTRICS FOR NANO ELECTRONIC DEVICES - A method for depositing a dielectric layer that includes introducing a substrate into a process chamber of a deposition tool; and heating the substrate to a process temperature. The method may further include introducing precursors that include at least one dielectric providing gas species for a deposited layer and at least one hydrogen precursor gas into the process chamber of the deposition tool. The hydrogen precursor gas is introduced to the deposition chamber at a flow rate ranging from 50 sccm to 5000 sccm. The molar ratio for Hydrogen/Silicon gas precursor can be equal or greater than 0.05. | 2017-09-14 |
20170263452 | METHOD FOR MANUFACTURING TWO-DIMENSIONAL MATERIAL STRUCTURE AND TWO-DIMENSIONAL MATERIAL DEVICE - A method for manufacturing a two-dimensional material structure and a resultant two-dimensional material device. The method comprises steps of: forming a sacrificial FIN structure on a substrate; covering the sacrificial FIN structure with a dielectric; releasing the sacrificial FIN structure; forming a carrier FIN structure at a position for releasing the sacrificial FIN; and self-restrictedly growing two-dimensional material structure by taking the carrier FIN structure as a substrate. Utilizing the sacrificial FIN structure to implement self-restrictedly growing of the nanometer structure of the two-dimensional material results in a high precision, lower edge roughness, high yields and low process deviation as well as compatibility with the processing of CMOS large scale integrated circuits, making the method suitable for a large scale production of the two-dimensional material and related devices. | 2017-09-14 |
20170263453 | SUBSTRATE AND ELECTRONIC DEVICE - A substrate includes: a support substrate having a first main surface and a surface layer region which includes at least the first main surface and is formed of any one material selected from the group consisting of boron nitride, molybdenum disulfide, tungsten disulfide, niobium disulfide, and aluminum nitride; and a graphene film disposed on the first main surface and having an atomic arrangement oriented in relation to an atomic arrangement of the material forming the surface layer region. Accordingly, the substrate is provided that enables a high mobility to be stably ensured in an electronic device manufactured to include the graphene film forming an electrically conductive portion. | 2017-09-14 |
20170263454 | METHOD FOR FORMING FIN STRUCTURES FOR NON-PLANAR SEMICONDUCTOR DEVICE - A method for forming fin structure includes following steps. A substrate is provided. A first mandrel and a plurality of second mandrels are formed on the substrate simultaneously. A plurality of spacers are respectively formed on sidewalls of the first mandrel and the second mandrels and followed by removing the first mandrel and the second mandrels to form a first spacer pattern and a plurality of second spacer patterns. Then the substrate is etched to simultaneously form at least a first fin and a plurality of second fins on the substrate with the first spacer pattern and the second spacer patterns serving as an etching mask. At least one of the second fins is immediately next to the first fin, and a fin width of the first fin is larger than a fin width of the second fins. Then, the second fins are removed from the substrate. | 2017-09-14 |
20170263455 | MASK STRUCTURE FORMING METHOD AND FILM FORMING APPARATUS - There is provided a method of forming an etching-purpose mask structure on an insulating film containing silicon and oxygen, which includes: forming an intermediate film containing silicon, carbon, nitrogen and hydrogen as main components by supplying a first process gas onto the insulating film formed on a substrate; and subsequently, forming a tungsten film by supplying a second process gas containing a compound of tungsten to the substrate to replace some of silicon constituting the intermediate film with tungsten. | 2017-09-14 |
20170263456 | METHODS OF FORMING NANOSTRUCTURES HAVING LOW DEFECT DENSITY - A method of forming a nanostructure comprises forming self-assembled nucleic acids on at least a portion of a substrate. The method further comprises contacting the self-assembled nucleic acids on the at least a portion of a substrate with a solution comprising at least one repair enzyme to repair defects in the self-assembled nucleic acids. The method may comprise repeating the repair of defects in the self-assembled nucleic acids on the at least a portion of a substrate until a desired, reduced threshold level of defect density is achieved. A semiconductor structure comprises a pattern of self-assembled nucleic acids defining a template having at least one aperture therethrough. At least one of the apertures has a dimension of less than about 50 nm. | 2017-09-14 |
20170263457 | Apparatus and Methods to Remove Unbonded Areas Within Bonded Substrates Using Localized Electromagnetic Wave Annealing - An electromagnetic wave irradiation apparatus and methods to bond unbonded areas in a bonded pair of substrates are disclosed. The unbonded areas between the substrates are eliminated by thermal activation in the unbonded areas induced by electromagnetic wave irradiation having a wavelength selected to effect a phonon or electron excitation. A first substrate of the bonded pair of substrates absorbs the electromagnetic radiation and a portion of a resulting thermal energy transfers to an interface of the bonded pair of substrates at the unbonded areas with sufficient flux to cause opposite sides the first and second substrates to interact and dehydrate to form a bond (e.g., Si—O—Si bond). | 2017-09-14 |
20170263458 | METHOD FOR FABRICATING A METAL HIGH-K GATE STACK FOR A BURIED RECESSED ACCESS DEVICE - A method for fabricated a buried recessed access device comprising etching a plurality of gate trenches in a substrate, implanting and activating a source/drain region in the substrate, depositing a dummy gate in each of the plurality of gate trenches, filling the plurality of gate trenches with an oxide layer, removing each dummy gate and depositing a high-K dielectric in the plurality of gate trenches, depositing a metal gate on the high-K dielectric in each of the plurality of gate trenches, depositing a second oxide layer on the metal gate and forming a contact on the source/drain. | 2017-09-14 |
20170263459 | MULTI-LAYER INTER-GATE DIELECTRIC STRUCTURE AND METHOD OF MANUFACTURING THEREOF - A semiconductor device having a first gate stack on a substrate is disclosed. The first gate stack may include a first gate conductor over a first gate dielectric structure. A dielectric structure can be formed over the first gate stack and the substrate. The dielectric structure layer can include four or more layers of two or more dielectric films disposed in an alternating manner. The dielectric structure can be selectively etched to form an inter-gate dielectric structure. A second gate conductor can be formed over a second gate dielectric structure, adjacent to the integrate dielectric structure. A dielectric layer can be formed over the substrate, the first and second gate conductors, and the inter-gate dielectric structure. The first gate conductor may be used to make a memory gate and the second gate conductor can be used to make a select gate of a split-gate memory cell. | 2017-09-14 |
20170263460 | TECHNIQUES FOR MANIPULATING PATTERNED FEATURES USING IONS - A method may include providing a surface feature on a substrate, the surface feature comprising a feature shape a feature location, and a dimension along a first direction within a substrate plane; depositing a layer comprising a layer material on the surface feature; and directing ions in an ion exposure at an angle of incidence toward the substrate, the angle of incidence forming a non-zero angle with respect to a perpendicular to the substrate plane, wherein the ion exposure comprises the ions and reactive neutral species, the ion exposure reactively etching the layer material, wherein the ions impact a first portion of the surface feature and do not impact a second portion of the surface feature, and wherein an altered surface feature is generated, the altered surface feature differing from the surface feature in at least one of: the dimension along the first direction, the feature shape, or the feature location. | 2017-09-14 |
20170263461 | PLASMA PROCESSING METHOD - A plasma processing method includes an attaching process of attaching a resin film to a first main surface of a substrate which is provided with the first main surface and a second main surface on an opposite side of the first main surface and a patterning process of forming a mask, which includes an opening exposing a region to be processed of the substrate, by patterning the resin film. The plasma processing method includes a first plasma process of generating first plasma of first gas in a depressurized atmosphere including the first gas, exposing the mask to the first plasma, and reducing a void between the mask and the first main surface. The plasma processing method includes a second plasma process of generating second plasma from second gas in atmosphere including the second gas, exposing the region to be processed exposed from the opening to the second plasma, and etching the region to be processed. | 2017-09-14 |
20170263462 | MANUFACTURING METHOD OF ELEMENT CHIP - A manufacturing method of an element chip includes a preparation process of adhering a holding sheet to the first main surface of a substrate so as to prepare the substrate held by the holding sheet, a plasma dicing process of performing plasma etching on the isolation region of the substrate to the first main surface so as to divide the substrate into the plurality of element chips. The plasma dicing process includes a first plasma etching process of performing plasma etching on a the isolation region partially in a thickness direction while a cooling gas is supplied between the stage and the holding sheet, and a second plasma etching process of stopping a supply of the cooling gas after the first plasma etching process, and performing plasma etching on a remaining portion of the isolation region. | 2017-09-14 |
20170263463 | METHOD FOR ETCHING SILICON SUBSTRATE USING PLASMA GAS - There is provided a method for etching a silicon substrate, the method comprising: forming an etch mask on a silicon substrate; forming a first gas comprising a halogen-based gas, a fluorocarbon gas and oxygen; and etching the silicon substrate by generating a plasma on the silicon substrate using the first gas. | 2017-09-14 |
20170263464 | METHOD FOR FORMING SEMICONDUCTOR DEVICE STRUCTURE - A method for forming a semiconductor device structure is provided. The method includes performing a first plasma etching process on a substrate to form a first trench in the substrate. The method includes removing a second portion of the substrate under the bottom surface to form a second trench under and connected to the first trench. The second trench surrounds a third portion of the substrate under the first portion. The third portion has a first sidewall. The first sidewall is inclined relative to the top surface at a second angle, and the first angle is greater than the second angle. The method includes forming an isolation structure in the first trench and the second trench. The method includes forming a gate insulating layer over the top surface and the first inclined surface. The method includes forming a gate over the gate insulating layer and the isolation structure. | 2017-09-14 |
20170263465 | VERTICAL NANOWIRES FORMED ON UPPER FIN SURFACE - One illustrative device includes, among other things, at least one fin defined in a semiconductor substrate and a substantially vertical nanowire having an oval-shaped cross-section disposed on a top surface of the at least one fin. | 2017-09-14 |
20170263466 | BOTTOM PROCESSING - Embodiments disclosed herein generally relate to methods and apparatus for processing of the bottom surface of a substrate to counteract thermal stresses thereon. Correcting strains are applied to the bottom surface of the substrate which compensate for undesirable strains and distortions on the top surface of the substrate. Specifically designed films may be formed on the back side of the substrate by any combination of deposition, implant, thermal treatment, and etching to create strains that compensate for unwanted distortions of the substrate. In some embodiments, localized strains may be introduced by locally altering the hydrogen content of a silicon nitride film or a carbon film, among other techniques. Structures may be formed by printing, lithography, or self-assembly techniques. Treatment of the layers of film is determined by the stress map desired and includes annealing, implanting, melting, or other thermal treatments. | 2017-09-14 |
20170263467 | METHODS OF FORMING A PORTION OF A MEMORY ARRAY HAVING A CONDUCTOR HAVING A VARIABLE CONCENTRATION OF GERMANIUM - An embodiment of a method of forming a portion of a memory array includes forming a conductor with a concentration of germanium that decreases with an increasing thickness of the conductor, removing a portion of the conductor at a rate governed by the concentration of germanium to form a tapered first opening through the conductor, removing a sacrificial material below the conductor to form a second opening contiguous with the tapered first opening, and forming a semiconductor in the contiguous first and second openings, wherein a portion of the semiconductor pinches off within the first opening adjacent an upper surface of the conductor before the contiguous first and second openings are completely filled with the semiconductor. | 2017-09-14 |
20170263468 | MANUFACTURING METHOD FOR REDUCING THE SURFACE ROUGHNESS OF A LOW TEMPERATUREPOLY-SILICON AND A LOW TEMPERATUREPOLY-SILICON THEREOF - The present invention discloses a manufacturing method to reduce the surface roughness of the low temperature poly-silicon, including: a surface pretreatment is performed to a substrate with a a-Si layer on it, to form an oxidation layer on the a-Si layer. A first excimer laser annealing is performed on the substrate to make the a-Si layer into a poly-silicon layer; an acid liquid clean is used on the poly-silicon layer to remove the protrusions on the poly-silicon layer; a second excimer laser annealing is performed to the poly-silicon layer to obtain a low temperature poly-silicon layer with lower surface roughness. The manufacturing method is easy to operation and reduce the surface roughness of the low temperature poly-silicon layer with efficiency to obtain a low temperature poly-silicon layer with low roughness, uniform surface and well crystallization. A low temperature poly-silicon layer formed according to the present invention is also provided. | 2017-09-14 |
20170263469 | SEMICONDUCTOR PACKAGE WITH SIDEWALL-PROTECTED RDL INTERPOSER - A semiconductor package includes a redistribution layer (RDL) interposer having a first side, a second side opposite to the first side, and a vertical sidewall extending between the first side and the second side; at least one semiconductor die mounted on the first side of the RDL interposer; a molding compound disposed on the first side and covering the at least one semiconductor die and the vertical sidewall of the RDL interposer; and a plurality of solder bumps or solder balls mounted on the second side of the RDL interposer. | 2017-09-14 |
20170263470 | Semiconductor Device and Method of Forming Embedded Conductive Layer for Power/Ground Planes in FO-EWLB - A semiconductor device has a first conductive layer and a semiconductor die disposed adjacent to the first conductive layer. An encapsulant is deposited over the first conductive layer and semiconductor die. An insulating layer is formed over the encapsulant, semiconductor die, and first conductive layer. A second conductive layer is formed over the insulating layer. A first portion of the first conductive layer is electrically connected to V | 2017-09-14 |
20170263471 | SUBSTRATE CLEANING APPARATUS - A substrate cleaning apparatus cleans a surface of a substrate such as a semiconductor wafer and dries the substrate. The substrate cleaning apparatus includes a process chamber having a substrate conveying unit configured to hold a substrate horizontally with its upper surface facing upwardly and to convey the substrate in one direction, and a cleaning unit configured to clean the surface of the substrate in non-contact state by supplying a cleaning liquid to the surface of the substrate which is moving in the process chamber. The substrate apparatus has an inert gas blowing unit configured to blow an inert gas toward the front and reverse surfaces of the substrate which has been cleaned in the cleaning unit to produce an inert gas atmosphere in the process chamber while drying the substrate with the inert gas. | 2017-09-14 |
20170263472 | MULTIPLE WAFER ROTARY PROCESSING - A wafer processor has a rotor holding wafers within a process tank. The rotor rotates sequentially moving the wafers through a process liquid held in the process tank. The tank may have an I-beam shape to reduce the volume of process liquid. A load port is provided at a top of the process tank for loading and unloading wafers into and out of the process tank. Rinsing and cleaning chambers may be associated with the load port to remove process liquid from processed wafers. The processor may be oriented with the rotor rotating about a horizontal axis or about a vertical axis. | 2017-09-14 |
20170263473 | LASER PROCESSING APPARATUS - A controller of a laser processing apparatus includes: a storage section that stores processing conditions for forming modified layers along division lines of a wafer; and a processing line calculation section that displays a position at which the modified layer is planned to be formed and which is stored as the processing condition, on a display panel as a processing line. The processing line calculation section displays the processing line on the display panel superimposed on a first division line, in a region in which a start point or end point of the first division line is connected to a second division line. A start point or end point of a first modified layer formed along the first division line is permitted to be re-set on the display panel so as not to interfere with a second modified layer formed along the second division line. | 2017-09-14 |
20170263474 | SEMICONDUCTOR MANUFACTURING APPARATUS - A semiconductor manufacturing apparatus according to the present embodiment includes a first cooler, a second cooler, and a temperature controller. The first cooler includes a first placing portion that can place a central portion of a semiconductor substrate thereon, and cools the central portion by heat exchange with the first placing portion. The second cooler includes a second placing portion that can place a peripheral portion of the semiconductor substrate thereon in a periphery of the first placing portion, and cools the peripheral portion. The temperature controller controls a temperature of the second placing portion to be lower than a temperature of the semiconductor substrate and to be higher than a temperature of the first placing portion. | 2017-09-14 |
20170263475 | Hot Jet Assisted Systems and Methods - A heating device for heating the surface of a substrate. The heating device comprises a gas source comprising an inert material supply inert under the operating conditions of the heating device, the gas source being adapted for supplying a hot jet of a gas comprising at least elements of said inert material on the substrate. The gas source is adapted for heating the hot jet of the gas to a temperature above 1500° C. | 2017-09-14 |
20170263476 | MOLD DEVICE - According to one embodiment, a mold device includes a first mold. The first mold includes a substrate clamping surface, a cavity, a suction part, a vent, first and second intermediate cavities and an opening/closing part. The substrate clamping surface contacts a surface of a processing substrate. The cavity is recessed from the substrate clamping surface. The suction part is recessed from the substrate clamping surface. The vent is provided on a path between the cavity and the suction part, and is recessed from the substrate clamping surface to a vent depth. The first intermediate cavity is provided between the vent and the suction part, and is recessed from the substrate clamping surface. The second intermediate cavity is provided between the first intermediate cavity and the suction part, and is recessed from the substrate clamping surface to a second intermediate cavity depth. The opening/closing part opens and closes the path. | 2017-09-14 |
20170263477 | SUBSTRATE PROCESSING APPARATUS AND CONTROL METHOD OF SUBSTRATE PROCESSING APPARATUS - According to one embodiment, there is provided a substrate processing apparatus including a processing unit and a manipulator. The processing unit processes a substrate. The manipulator is for maintenance. The manipulator is placed near the processing unit. | 2017-09-14 |
20170263478 | Detection System for Tunable/Replaceable Edge Coupling Ring - A substrate processing system includes a processing chamber. A pedestal is arranged in the processing chamber. An edge coupling ring is arranged adjacent to the pedestal and around a radially outer edge of the substrate. An actuator is configured to selectively move the edge coupling ring relative to the substrate to alter an edge coupling profile of the edge coupling ring. The substrate processing system includes a camera-based detection system that instructs the actuator to adjust a position of the edge coupling ring. The camera is configured to communicate with the controller, and the controller adjusts a position and/or focus of the camera. In response to edge coupling ring condition information from the camera, the controller operates the actuator to move the edge coupling ring vertically. In response to edge coupling ring position information from the camera, the controller operates the actuator to move the edge coupling ring horizontally. | 2017-09-14 |
20170263479 | SUBSTRATE CONTAINER, LOAD PORT APPARATUS, AND SUBSTRATE TREATING APPARATUS - A substrate container including a casing, a rack, a casing holder, a casing lifting mechanism, a lid, and a lid holder. When holding of substrates with the rack shifts to holding of the substrates with the casing holder and the lid holder, the casing lifting mechanism moves the casing holder upward, whereby the casing holder moves the substrates upward. When the holding of the substrates with the casing holder and the lid holder shifts to the holding of the substrates with the rack, the casing lifting mechanism moves the casing holder downward, whereby the casing holder moves the substrates downward. | 2017-09-14 |
20170263480 | ARRANGEMENT HAVING A PLURALITY OF CHIPS AND A CHIP CARRIER, AND A PROCESSING ARRANGEMENT - In various embodiments, an arrangement is provided. The arrangement may include a plurality of chips; a chip carrier carrying the plurality of chips, the chip carrier including a chip carrier notch; and encapsulation material encapsulating the chip carrier and filling the chip carrier notch; wherein the outer circumference of the encapsulation material is free from a recess. | 2017-09-14 |
20170263481 | Adapter Tool Configured to be Attached to a Loadport of a Wafer Handling System and Wafer Handling System with Such an Adapter Tool - An adapter tool configured to be attached to a loadport of a wafer handling system includes a support member and first and second guiding elements attached to the support member and being juxtaposed to each other. The first guiding element is arranged for placing a first wafer magazine, and the second guiding element is arranged for placing a second wafer magazine. The adapter tool further includes a housing supported by the support member and configured to house the first and the second wafer magazines, respectively, and first and second openings in the housing, respectively. The first and second openings are aligned with the first and second guiding elements. | 2017-09-14 |
20170263482 | WAFER CARRIER - A wafer carrier for processing a plurality of wafers includes a carrier body which rotatable about a central axis, and a plurality of pockets formed in the carrier body. Each of the pockets has an access opening and an inner periphery surface extending from the access opening to terminate at a floor surface. A lower periphery region of the inner periphery surface has a most distal region which is most distal from the central axis. When the carrier body is rotated about the central axis, a corresponding one of the wafers is less likely to be damaged due to a centrifugal force applied to the corresponding one of the wafers. | 2017-09-14 |
20170263483 | SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING METHOD - During a position deviation detection operation, a hand of a transport mechanism is moved to a true target position in a substrate supporter. A substrate supported at a preset reference position by the substrate supporter is received by the hand of the transport mechanism. A positional relationship between the substrate received by the hand and the hand is detected by a position detector. A deviation amount between the reference position and the true target position in the substrate supporter is acquired based on the detected positional relationship. An alarm is output in the case where the acquired deviation amount is larger than a predetermined threshold value. | 2017-09-14 |
20170263484 | MULTI-ZONE PEDESTAL FOR PLASMA PROCESSING - A method and apparatus for a heated pedestal is provided. In one embodiment, the heated pedestal includes a body comprising a ceramic material, a plurality of heating elements encapsulated within the body, and one or more grooves formed in a surface of the body adjacent each of the plurality of heating elements, at least one side of the grooves being bounded by a ceramic plate. | 2017-09-14 |
20170263485 | SYSTEM AND METHOD FOR MULTI-LOCATION ZAPPING - A system for zapping a wafer, the system may include a pulse generation unit that is configured to generate (a) first zapping pulses for causing a breakdown in a first location of a backside insulating layer of a wafer, and (b) second zapping pulses for causing a breakdown in a second location of the backside insulating layer of the wafer; a first conductive interface that is configured to convey the first zapping pulses to the first location, while contacting the first location; a second conductive interface that is configured to convey the second zapping pulses to the second location, while contacting the second location; and wherein the first location differs from the second location. | 2017-09-14 |
20170263486 | Electrostatic Chuck For Clamping In High Temperature Semiconductor Processing And Method Of Making Same - An electrostatic chuck with a top surface adapted for Johnsen-Rahbek clamping in the temperature range of 500 C to 750 C. The top surface may be sapphire. The top surface is attached to the lower portion of the electrostatic chuck using a braze layer able to withstand corrosive processing chemistries. A method of manufacturing an electrostatic chuck with a top surface adapted for Johnsen-Rahbek clamping in the temperature range of 500 C to 750 C. | 2017-09-14 |
20170263487 | METHOD TO REMOVE RESIDUAL CHARGE ON A ELECTROSTATIC CHUCK DURING THE DE-CHUCKING STEP - A method and apparatus for discharging a residual charge from a substrate support. In one example, a substrate support is provided that includes a body, an electrode disposed in the body, a radiation emitter and a diffuser. The body has one or more holes formed in a workpiece support surface, the workpiece support surface configured to accept a substrate thereon. The electrode is configured to electrostatically hold a substrate to the workpiece support surface. The radiation emitter is disposed in a first hole of the one or more holes formed in the workpiece support surface. The radiation emitter is configured to emit electromagnetic energy out of the first hole. The diffuser is disposed in first hole over the radiation emitter. | 2017-09-14 |
20170263488 | METHOD OF MANUFACTURING FLEXIBLE DISPLAY DEVICE - Methods for manufacturing a flexible display device are provided. A flexible substrate is provided and a first bonding pattern, which encloses a display area, is formed on the flexible substrate. A second bonding pattern is formed on a rigid substrate. The first and second bonding patterns are bonded together to provide a bonding pattern between the flexible substrate and the rigid substrate. At least one display device is formed on the display area of the flexible substrate. The bonding pattern is removed by a cutting process performed so as to separate the flexible substrate having the display device thereon from the rigid substrate. | 2017-09-14 |
20170263489 | Fan-Out Interconnect Structure and Methods Forming the Same - A method includes forming an adhesive layer over a carrier, forming a sacrificial layer over the adhesive layer, forming through-vias over the sacrificial layer, and placing a device die over the sacrificial layer. The Method further includes molding and planarizing the device die and the through-vias, de-bonding the carrier by removing the adhesive layer, and removing the sacrificial layer. | 2017-09-14 |
20170263490 | METHOD FOR PROVIDING A PLANARIZABLE WORKPIECE SUPPORT, A WORKPIECE PLANARIZATION ARRANGEMENT, AND A CHUCK - According to various embodiments, a workpiece planarization arrangement may include: a chuck including at least one portion configured to support one or more workpieces; and a planarization tool configured to planarize the at least one portion of the chuck and to planarize one or more workpieces on the at least one portion of the chuck; wherein the at least one portion of the chuck includes at least one of particles, pores and/or a polymer. | 2017-09-14 |
20170263491 | SUBSTRATE PROCESSING APPARATUS - A transfer path is provided which is extended so as to be passed on a lateral side of a processing portion that processes a substrate. The substrate transferred between a container held by a holding unit and the processing portion passes through the transfer path. A first transfer robot carries the substrate into and out of the container held by the holding unit, and accesses a reception/delivery region arranged within the transfer path. A second transfer robot receives and delivers the substrate from and to the first transfer robot in the reception/delivery region, and carries the substrate into and out of the processing portion. A second transfer robot raising/lowering unit which raises and lowers the second transfer robot is arranged within the transfer path. The reception/delivery region and the second transfer robot raising/lowering unit are located between the first transfer robot and the second transfer robot. | 2017-09-14 |
20170263492 | APPARATUS FOR MANUFACTURING A DISPLAY DEVICE AND A MANUFACTURING METHOD THEREOF - An apparatus for manufacturing a display device includes a first jig including a first side, the first side having a concave groove for receiving a cover window, wherein the cover window includes a first planar portion, a first curved portion and a second curved portion, wherein the first and second curved portions are disposed at opposite ends of the first planar portion in a first direction, a second jig including a planar side for receiving a display panel, wherein when the second jig is moved in a second direction crossing the first direction with the display panel on the planar side, the display panel is disposed between the first and second curved portions of the cover window, and a pair of third jigs for supporting the first and second curved portions of the cover window. | 2017-09-14 |
20170263493 | SUPPORT CYLINDER FOR THERMAL PROCESSING CYLINDER - Embodiments of the disclosure generally relate to a support cylinder used in a thermal process chamber. In one embodiment, the support cylinder includes a hollow cylindrical body comprising an inner peripheral surface, an outer peripheral surface parallel to the inner peripheral surface, wherein the inner peripheral surface and the outer peripheral surface extend along a direction parallel to a longitudinal axis of the support cylinder, and a lateral portion extending radially from the outer peripheral surface to the inner peripheral surface, wherein the lateral portion comprises a first end having a first beveled portion, a first rounded portion, and a first planar portion connecting the first beveled portion and the first rounded portion, and a second end opposing the first end, the second end having a second beveled portion, a second rounded portion, and a second planar portion connecting the second beveled portion and the second rounded portion. | 2017-09-14 |
20170263494 | SEMICONDUCTOR TRANSPORT MEMBER AND SEMICONDUCTOR MOUNTING MEMBER - Provided is a semiconductor transport member that includes a semiconductor mounting member capable of expressing a strong gripping force and unlikely to cause a contaminant to adhere and remain on a semiconductor side. Also provided is a semiconductor mounting member capable of expressing a strong gripping force and unlikely to cause a contaminant to adhere and remain on a semiconductor side. The semiconductor transport member of the present invention includes: a carrying base; and a semiconductor mounting member, in which: the semiconductor mounting member includes a fibrous columnar structure; the fibrous columnar structure includes a fibrous columnar structure including a plurality of fibrous columnar objects; the fibrous columnar objects are each aligned in a direction substantially perpendicular to the carrying base; and a surface of the fibrous columnar structure on an opposite side to the carrying base has a coefficient of static friction against a glass surface of 4.0 or more. | 2017-09-14 |
20170263495 | CO-MANUFACTURING METHOD OF ZONES WITH DIFFERENT UNIAXIAL STRESSES - The method of manufacturing a structure comprising one or several strained semiconducting zones capable of forming one or several transistor channel regions, the method including the following steps:
| 2017-09-14 |
20170263496 | MATERIALS AND DEPOSITION SCHEMES USING PHOTOACTIVE MATERIALS FOR INTERFACE CHEMICAL CONTROL AND PATTERNING OF PREDEFINED STRUCTURES - Embodiments of the invention include microelectronic devices and methods of forming such devices. In an embodiment, a microelectronic device, includes one or more pre-patterned features formed into a interconnect layer, with a conformal barrier layer formed over the first wall, and the second wall of one or more of the pre-patterned features. A photoresist layer may formed over the barrier layer and within one or more of the pre-patterned features and a conductive via may be formed in at least one of the pre-patterned features. | 2017-09-14 |
20170263497 | SEMICONDUCTOR DEVICE - A semiconductor device provided with a plurality of kinds of transistors with different device structures suitable for functions of circuits is provided. The semiconductor device includes first to third transistors with different device structures over one substrate. A semiconductor layer of the first transistor is an oxide semiconductor film with a stacked-layer structure, and a semiconductor layer of each of the second and third transistors is an oxide semiconductor film with a single-layer structure. Each of the first and second transistors includes a back gate electrode connected to its gate electrode. | 2017-09-14 |
20170263498 | SOLDER FILL INTO HIGH ASPECT THROUGH HOLES - A method for filling a through hole with solder includes mounting a substrate having a through hole formed therein on a permeable barrier layer having pores that enable gas to flow through the permeable barrier. A solder source is positioned over the through hole. Molten solder is delivered in the through hole with a positive pressure from the solder source such that gas in the through holes passes the permeable barrier while the molten solder remains in the through hole. | 2017-09-14 |
20170263499 | SEMICONDUCTOR MANUFACTURING METHOD - A semiconductor manufacturing method includes forming a first metal film on a semiconductor wafer by plating, ejecting liquid from a washer bar spaced from the wafer while rotating at least one of the washer and the semiconductor, and forming a second metal film on the first metal film. A plurality of nozzles are located on the washer bar and displaced from the position of the washer bar opposed to the center of the wafer, and a greater number of nozzles are adjacent the peripheral area of the semiconductor wafer than the central area of the semiconductor wafer. The nozzles in the peripheral area of the wafer eject the washing liquid in a direction inclined from the direction of the washer bar, and a nozzle arranged on the central area of the one main surface of the semiconductor wafer ejects the washing liquid towards the center position of the semiconductor wafer. | 2017-09-14 |
20170263500 | METHOD FOR MANUFACTURING ELEMENT CHIP - The method includes a laser scribing step of forming an opening including an exposing portion, where the first layer is exposed, by irradiating the dividing region of the substrate with laser light from the first main surface side, forming a remaining region on which the second layer in the dividing region remains around the opening other than the exposing portion, and forming a first damaged region of a surface layer portion of the first layer including the exposing portion and a second damaged region of a surface layer portion of the first layer to be covered by the remaining region on the first layer of the dividing region. | 2017-09-14 |
20170263501 | ELEMENT CHIP AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing an element chip includes a laser dicing step of dividing the substrate to a plurality of element chips including the element region by irradiating the dividing region of the substrate with laser light, in a state of supported by a supporting member and forming a damaged region on an end surface of the element chip. Furthermore, the method for manufacturing an element chip includes a protection film stacking step of stacking a protection film on the first main surface and the end surface of the element chip, after the laser dicing step and a protection film etching step of removing the protection film stacked on the first main surface through etching the protection film anisotropically by exposing the element chip to plasma, after the protection film stacking, step and remaining the protection film for covering the damaged region. | 2017-09-14 |
20170263502 | METHOD FOR MANUFACTURING ELEMENT CHIP - The method for manufacturing an element chip includes a mounting step and a plasma dicing step. In the mounting step, a semiconductor substrate with flexibility, which has a first main surface and a second main surface located at an opposite side of the first main surface, which has a plurality element regions and a dividing region for defining the element regions, and on which a mask for covering the first main surface in the element region and for exposing the first main surface in the dividing region is formed, is mounted on a stage. In the plasma dicing step, the semiconductor substrate is diced into a plurality of element chips including the element; region by exposing the first main surface side of the semiconductor substrate to plasma on the stage and etching from the first main surface side to the second main surface while forming a groove on the dividing region. | 2017-09-14 |
20170263503 | FIN TYPE FIELD EFFECT TRANSISTORS WITH DIFFERENT PITCHES AND SUBSTANTIALLY UNIFORM FIN REVEAL - A semiconductor device that includes a first plurality of fin structures in a first device region and a second plurality of fin structures in a second device region. The first plurality of fin structures includes adjacent fin structures separated by a lesser pitch than the adjacent fin structures in the second plurality of fin structures. At least one layer of dielectric material between adjacent fin structures, wherein a portion of the first plurality of fin structures extending above the at least one layer of dielectric material in the first device region is substantially equal to the portion of the second plurality of fin structures extending above the at least one layer of dielectric material in the second device region. Source and drain regions are present on opposing sides of a gate structure that is present on the fin structures. | 2017-09-14 |
20170263504 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a plurality of fin shaped structures and an insulating layer. The substrate has a fin field-effect transistor (finFET) region, a first region, a second region and a third region. The first region, the second region and the third region have a first surface, a second surface, and a third surface, respectively, where the first surface is relatively higher than the second surface and the second surface is relatively higher than the third surface. The fin shaped structures are disposed on a surface of the fin field-effect transistor region. The insulating layer covers the first surface, the second surface and the third surface. | 2017-09-14 |
20170263505 | METHOD OF MAKING A FINFET DEVICE - A method for fabricating a fin field-effect transistor (FinFET) device includes forming a first dielectric layer over a substrate and then etching the first dielectric layer and the substrate to form a first fin and a second fin. A second dielectric layer is formed along sidewalls of the first fin and the second fin. A protection layer is deposited over the first fin and the second fin. A portion of the protection layer and the first dielectric layer on the second fin is removed and the second fin is then recessed to form a trench. A semiconductor material layer is epitaxially grown in the trench. The protection layer is removed to reveal the first fin and the second fin. | 2017-09-14 |
20170263506 | METHODS, APPARATUS AND SYSTEM FOR A PASSTHROUGH-BASED ARCHITECTURE - At least one method, apparatus and system disclosed herein for forming a finFET device having a pass-through structure. A first gate structure and a second gate structure are formed on a semiconductor wafer. A first active area is formed on one end of the first and second gate structures. A second active area is formed on the other end of the first and second gate structures. A trench silicide (TS) structure self-aligned to the first and second gate structures is formed. The TS structure is configured to operatively couple the first active area to the second active area. | 2017-09-14 |
20170263507 | NANOWIRE SEMICONDUCTOR DEVICE - A method for forming a nanowire device comprises depositing a hard mask on portions of a silicon substrate having a <110>orientation wherein the hard mask is oriented in the <112>direction, etching the silicon substrate to form a mandrel having (111) faceted sidewalls; forming a layer of insulator material on the substrate; forming a sacrificial stack comprising alternating layers of sacrificial material and dielectric material disposed on the layer of insulator material and adjacent to the mandrel; patterning and etching the sacrificial stack to form a modified sacrificial stack adjacent to the mandrel and extending from the mandrel; removing the sacrificial material from the modified sacrificial stack to form growth channels; epitaxially forming semiconductor in the growth channels; and etching the semiconductor to align with the end of the growth channels and form a semiconductor stack comprising alternating layers of dielectric material and semiconductor material. | 2017-09-14 |
20170263508 | MEASUREMENT METHOD, MANUFACTURING METHOD OF DEVICE, AND MEASUREMENT SYSTEM - According to one embodiment, there is provided a measurement method. The method includes measuring an amount of overlay shift between a first layer and a second layer using a first overlay mark and a second overlay mark. The first layer is provided as a layer including the first overlay mark above a first substrate. The second layer is provided as a layer including the second overlay mark above the first overlay mark. The method includes acquiring a parameter related to asymmetry of a shape of the second overlay mark. The method includes obtaining an amount of correction with respect to a measured value of the amount of overlay shift based on the acquired parameter and the measured amount of overlay shift. | 2017-09-14 |
20170263509 | METHOD FOR REDUCING CORE-TO-CORE MISMATCHES IN SOC APPLICATIONS - Methods for reducing core-to-core mismatch are provided. The method includes measuring gate lengths of a representative pattern of each core in a first lot of SOC products by a measurement apparatus. Each of the SOC products in the first lot includes more than two cores identical to each other. The method also includes determining a tuning amount according to the differences between the gate lengths of each core, and adjusting at least one mask for critical dimensions of gate length of each core in a second lot of SOC products respectively according to the tuning amounts. | 2017-09-14 |
20170263510 | METHOD OF PERFORMING ANALYSIS OF PATTERN DEFECT, IMPRINT APPARATUS, AND ARTICLE MANUFACTURING METHOD - There is provided a method of performing an analysis of a defect in a pattern of an imprint material on a substrate that has undergone an imprint process of transferring a pattern of a mold onto the substrate. The method includes obtaining a defect distribution of the pattern on the substrate, obtaining map information indicating an arrangement of the imprint material on the substrate, and determining a type of a defect based on a relationship between a position of the defect in the defect distribution and a position of a gap in the imprint material generated in a process of spreading the imprint material by the imprint process, wherein the position of the gap is predicted based on the map information. | 2017-09-14 |
20170263511 | WAFER PROCESSING TOOL HAVING A MICRO SENSOR - Embodiments include devices and methods for detecting material deposition and material removal performed by a wafer processing tool. In an embodiment, one or more micro sensors mounted on a process chamber of the wafer processing tool are capable of operating under vacuum conditions and/or may measure material deposition and removal rates in real-time during a plasma-less wafer fabrication process. Other embodiments are also described and claimed. | 2017-09-14 |
20170263512 | CONTROL DEVICE AND CONTROL METHOD OF SEMICONDUCTOR MANUFACTURING APPARATUS - A control device of a semiconductor manufacturing apparatus includes a processor and a memory connected to the processor and storing instructions executable by the processor. The instructions collect a sound of processing a substrate by the semiconductor manufacturing apparatus. The instructions calculate a difference of a power spectrum of the processing sound between a first point of time and a second point of time. The instructions determine a change point of processing of the substrate based on the difference. | 2017-09-14 |
20170263513 | SOLID-STATE IMAGING DEVICE AND METHOD FOR PRODUCING THE SAME - A solid-state imaging device includes a substrate having a rectangular shape; a first region configured to extend on the substrate in a length direction of the substrate, and to include a plurality of electrode pads arranged above the substrate through a multilayer interconnection; and a second region configured to extend in the length direction, and to include an imaging element, an optical filter, and an insulating film. The second region extends on the substrate on which the imaging element is arranged. The optical filter is arranged above the substrate and faces the imaging element through the insulating film. The second region extends in parallel to the first region to be apart from the first region by a given distance. The plurality of electrode pads are arranged to be apart from each other by a given space, equal to or smaller than the given distance, in the length direction. | 2017-09-14 |
20170263514 | METHOD OF FORMING A TEMPORARY TEST STRUCTURE FOR DEVICE FABRICATION - A method of forming a temporary test structure for device fabrication is provided. The method allows for electrically testing conductive interconnects during controlled collapse chip connections (C4) fabrication and/or through-silicon vias (TSVs) during interposer fabrication. The method includes providing a substrate containing a plurality of electrically conductive interconnects extending vertically to top surface of the substrate. A temporary test structure is formed to connect the plurality of interconnects for electrical testing. Electrical testing is performed on the substrate by probing at different test locations on the temporary test structure. All or part of the temporary test structure is removed so as not to affect product performance. The temporary test structure can contain electrical test pads which provide a way to make temporary connections to small interconnect landings or features at extreme tight pitch to fan them out to testable pads sizes and pitches. | 2017-09-14 |
20170263515 | SEAL FOR SEMICONDUCTOR PACKAGE - Semiconductor packages and methods of manufacturing semiconductor packages are described herein. In certain embodiments, the semiconductor package includes a substrate, a wall attached to the substrate, a first adhesive layer disposed between a bottom surface of the wall and a top surface of the substrate, and a second adhesive layer disposed around an outer perimeter of the first adhesive layer, the second adhesive layer disposed adjacent and contacting the wall, the second adhesive layer different from the first adhesive layer, wherein at least one of the first adhesive layer and the second adhesive layer connects the wall to electrical ground. | 2017-09-14 |
20170263516 | Semiconductor Device, and Alternator and Power Converter Using the Semiconductor Device - Provided is a semiconductor device including: a first external electrode which includes a circular outer peripheral portion; a MOSFET chip; a control circuit chip which receives voltages of a drain electrode and a source electrode of the MOSFET and supplies a signal to a gate electrode to control the MOSFET on the basis of the voltage; a second external electrode which is disposed on an opposite side of the first external electrode with respect to the MOSFET chip and includes an external terminal on a center axis of the circular outer peripheral portion of the first external electrode; and an isolation substrate which isolates the control circuit chip from the external electrode. The first external electrode, the drain electrode and the source electrode of the MOSFET chip, and the second external electrode are disposed to be overlapped in a direction of the center axis. The drain electrode of the MOSFET chip and the first external electrode are connected. The source electrode of the MOSFET chip and the second external electrode are connected. | 2017-09-14 |
20170263517 | METHOD FOR FORMING AN ELECTRICAL DEVICE AND ELECTRICAL DEVICES - A method for forming an electrical device includes attaching a semiconductor die on a carrier. The method further includes dispensing a fillet material at at least one edge of the semiconductor die arranged on the carrier. The method further includes dispensing an underfill material into a gap between the semiconductor die and the carrier after dispensing the fillet material. | 2017-09-14 |
20170263518 | Integrated Fan-Out Package Including Voltage Regulators and Methods Forming Same - A method includes adhering a voltage regulator die over a carrier through a die-attach film, with the die-attach film being in the voltage regulator die and encircles metal pillars of the voltage regulator die, encapsulating the voltage regulator die in an encapsulating material, and planarizing the encapsulating material. A back portion of the voltage regulator die is removed to expose a through-via in a semiconductor substrate of the voltage regulator die. The method further includes forming first redistribution lines over the encapsulating material and electrically coupled to the through-via, replacing the die-attach film with a dielectric material, forming second redistribution lines on an opposite side of encapsulating material than the first redistribution lines, and bonding an additional device die to the second redistribution lines. The voltage regulator die is electrically coupled to the additional device die. | 2017-09-14 |
20170263519 | 3D STACKED-CHIP PACKAGE - Disclosed herein is a package comprising a first die having a first redistribution layer (RDL) disposed on a first side of a first substrate and a second die having a second RDL disposed on a first side of a second substrate, with the first RDL bonded to the second RDL. A third die having a third RDL is disposed on a first side of a third substrate, the third die mounted over the second die, with the second die disposed between the first die and the third die. First vias extend through, and are electrically isolated from, the second substrate, with the first vias each contacting a conductive element in the first RDL or the second RDL. Second vias extend through, and are electrically isolated from, the third substrate, with the second vias each contacting a conductive element in the third RDL or one of the first vias. | 2017-09-14 |
20170263520 | SEMICONDUCTOR DEVICE HAVING ELECTRODE PADS ARRANGED BETWEEN GROUPS OF EXTERNAL ELECTRODES - The semiconductor device has the CSP structure, and may include a plurality of electrode pads formed on a semiconductor integrated circuit in order to input/output signals from/to exterior; solder bumps for making external lead electrodes; and rewiring. The solder bumps may be arranged in two rows along the periphery of the semiconductor device. The electrode pads may be arranged inside the outermost solder bumps so as to be interposed between the two rows of solder bumps. Each trace of the rewiring may be extended from an electrode pad, and may be connected to any one of the outermost solder bumps or any one of the inner solder bumps. | 2017-09-14 |
20170263521 | RESIN-ENCAPSULATED SEMICONDUCTOR DEVICE - A first resin encapsulated body and a second resin encapsulated body are stacked to form a resin-encapsulated semiconductor device. The first resin encapsulated body includes: a first semiconductor element; an external terminal; inner wiring; and a first resin for covering those components, at least a rear surface of the external terminal, a rear surface of the semiconductor element, and a surface of the inner wiring are exposed from the first resin. The second resin encapsulated body includes: a second semiconductor element having an electrode pad formed on a surface thereof; a second resin for covering the second semiconductor element; and a metal body connected to the electrode pad, and is partly exposed from the second resin. The inner wiring and the metal body are electrically connected to each other. | 2017-09-14 |