37th week of 2012 patent applcation highlights part 63 |
Patent application number | Title | Published |
20120233360 | Unified DMA - In one embodiment, an apparatus comprises a first interface circuit, a direct memory access (DMA) controller coupled to the first interface circuit, and a host coupled to the DMA controller. The first interface circuit is configured to communicate on an interface according to a protocol. The host comprises at least one address space mapped, at least in part, to a plurality of memory locations in a memory system of the host. The DMA controller is configured to perform DMA transfers between the first interface circuit and the address space, and the DMA controller is further configured to perform DMA transfers between a first plurality of the plurality of memory locations and a second plurality of the plurality of memory locations. | 2012-09-13 |
20120233361 | HOST DEVICE SUSPENDING COMMUNICATION LINK TO CLIENT DEVICE BASED ON CLIENT DEVICE NOTIFICATION - A communication link between a host device and a client device can be suspended based on a suspend request or notification provided by the client device. The suspend request can be transmitted by a client device to a host device if the client device determines that suspension is appropriate, and can be sent in response to receiving a polling request from the host device. After receiving a suspend request, the host device can initiate an operation to suspend the communication link between the devices. | 2012-09-13 |
20120233362 | BUFFER MANAGEMENT METHOD AND OPTICAL DISC DRIVE - A buffer management method operates by receiving a read command, wherein the read command comprises a read destination address for designating an associated area of a storage media; receiving write commands, wherein each of the write command comprises a data block and a write destination address for designating an associated location of the storage media to store the data block; buffering the data blocks of the write commands in a buffer; generating a latest list, wherein the latest list comprises a plurality of buffer indexes indicating buffer areas for storing the data blocks associated with the latest certain amount of received write commands; and determining whether the read destination address of the read command is associate with the latest list. | 2012-09-13 |
20120233363 | QUALITY OF SERVICE MANAGEMENT - A method for measuring latencies caused by processing performed within a common resource is provided. A current latency value representing a time of residency of an IO request in a queue prior to receipt of acknowledgment from the common resource of completion of the IO request is received from a device comprising the queue, which maintains entries for IO requests that have been dispatched to and are pending at the common resource. An average latency value is calculated based in part on the current latency value. An adjusted capacity size for the queue is calculated based in part on the average latency value and the queue's capacity is set to the adjusted capacity size. IO requests are held in a buffer if the queue's capacity is full to reduce the effect of an amount of work transmitted to the common resource on current latency values provided by the device. | 2012-09-13 |
20120233364 | DYNAMIC RESOURCE ALLOCATION FOR DISTRIBUTED CLUSTER-STORAGE NETWORK - An apparatus, method and computer program in a distributed cluster storage network comprises storage control nodes to write data to storage on request from a host; a forwarding layer at a first node to forward data to a second node; a buffer controller at each node to allocate buffers for data to be written; and a communication link between the buffer controller and the forwarding layer at each node to communicate a constrained or unconstrained status indicator of the buffer resource to the forwarding layer. A mode selector selects a constrained mode of operation requiring allocation of buffer resource at the second node and communication of the allocation before the first node can allocate buffers and forward data, or an unconstrained mode of operation granting use of a predetermined resource credit provided by the second to the first node and permitting forwarding of a write request with data. | 2012-09-13 |
20120233365 | INPUT INTERFACE PROVIDING USB APPARATUS AND INTERFACE PROVIDING METHOD - The present invention relates to an input interface providing USB apparatus which is capable of providing an input interface for a variety of external devices in Bluetooth communication with the USB apparatus without a separate input means by connecting the USB apparatus to USB ports of a terminal and sharing an input means of the terminal with the external devices, and an interface providing method. The input interface providing USB apparatus and method in accordance with the present invention is capable of providing an input interface for a variety of external devices in Bluetooth communication with the USB apparatus without a separate input means by connecting the USB apparatus to USB ports of a terminal and sharing an input means of the terminal with the external devices, thereby providing excellent user convenience. | 2012-09-13 |
20120233366 | Integrating Non-Peripheral Component Interconnect (PCI) Resources Into A Personal Computer System - In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed. | 2012-09-13 |
20120233367 | Interrupt Latency Measurement - A system and method for setting a first indicator indicating that interrupts are virtually locked, receiving a first interrupt at a processor of a computing device, setting a second indicator indicating the receipt of the first interrupt and recording a first timestamp based on the receipt of the first interrupt. The system and method further adapted to virtually execute a routine for the first interrupt that includes determining if the second indicator is set, record a second timestamp based on the virtual execution of the routine and determine an interrupt latency based on the first and second timestamp. | 2012-09-13 |
20120233368 | AUTOMATED PROTOCOL SELECTION FOR HOST ADAPTER CARD - A networking system includes a host adapter card including a card connector having four transceiver pairs and a mechanical connector configuration, and a controller having control logic for detecting whether a single-channel connection or a four-channel connection is made to the card connector. The controller further includes control logic for communicating over a network using a default, four-channel-protocol in response to detecting the four-channel connection or using an alternative, single-channel-protocol in response to detecting the single-channel connection. The system further includes an alternative-network compatibility device including a first connector configured for releasably mating with the card connector and a second connector having a different mechanical connector configuration than the card connector. The alternative-network compatibility device includes a transceiver lane from the first connector end to the second connector end, which transceiver lane is placed in connection with one of the four transceiver pairs when mated with the card connector. | 2012-09-13 |
20120233369 | DOCK FOR PORTABLE DEVICES - Another embodiment of the invention provides a dock for connecting to a portable device. The dock includes a charging module, a backup program and a controller. The controller controls the dock to operate at a first mode or a second mode. When the dock operates at the first mode, the controller controls the charging module to charge the portable device, and when the dock operates at the second mode, the controller controls the charging module to charge the portable device and the backup program is executed to backup data of the portable device simultaneously. | 2012-09-13 |
20120233370 | PROCESS CONTROL ASSEMBLY FOR A PROCESS AND/OR AUTOMATION TECHNOLOGY APPARATUS - A process control arrangement (PKA), having a number of fieldbus systems (DP | 2012-09-13 |
20120233371 | Method and System for an Integrated Host PCI I/O Bridge and Dual Port Gigabit Ethernet Controller - Embodiments may include two gigabit Ethernet controllers integrated within a single chip and an I/O bridge coupled to the two gigabit Ethernet controllers and integrated within the single chip. The system may further include an I/O function coupled to the I/O bridge that is integrated within the single chip. The I/O function may include I/O logic and an I/O buffer integrated within the single chip and coupled to the I/O bridge and/or the two gigabit Ethernet controllers. A timing function or timing block may also be coupled to the I/O bridge and integrated within the single chip. A host system may be coupled to the I/O bridge. The I/O bridge may further include a primary bus controller, which may be a primary PCI bus controller. The controller or controller block may include control and status registers that may be coupled to the primary bus controller. | 2012-09-13 |
20120233372 | DATA TRANSFER CONTROL DEVICE, INTEGRATED CIRCUIT OF SAME, DATA TRANSFER CONTROL METHOD OF SAME, DATA TRANSFER COMPLETION NOTIFICATION DEVICE, INTEGRATED CIRCUIT OF SAME, DATA TRANSFER COMPLETION NOTIFICATION METHOD OF SAME, AND DATA TRANSFER CONTROL SYSTEM - A data transfer control device | 2012-09-13 |
20120233373 | ELECTRONIC EQUIPMENT SYSTEM, ELECTRONIC EQUIPMENT AND CONNECTION EQUIPMENT - A branching device (connection equipment) | 2012-09-13 |
20120233374 | DUAL MODE SERIAL/PARALLEL INTERFACE AND USE THEREOF IN IMPROVED WIRELESS DEVICES AND SWITCHING COMPONENTS - Systems, methods, and devices for communicating with a serial/parallel interface are described herein. In an aspect, a wireless device includes a transceiver configured to output a plurality of transmission paths, and an antenna configured to output a signal corresponding to at least one of the transmission paths. The wireless device further includes a wireless switching component including a radio-frequency switch configured to selectively connect the antenna to one of the transmission paths, a plurality of signal pins, a serial interface including a plurality of serial inputs electrically coupled to at least one pin of the plurality of signal pins, a parallel interface including a plurality of parallel inputs electrically coupled to at least one pin of the plurality of signal pins, a decoder, and a level shifter configured to control the radio-frequency switch, the at least one pin electrically coupled to both a serial input and a parallel input. | 2012-09-13 |
20120233375 | ADJUSTMENT OF POST AND NON-POST PACKET TRANSMISSIONS IN A COMMUNICATION INTERCONNECT - In a communication interconnect such as PCIe which favors post transmissions such as write requests over non-post transmissions such as read requests and completions, methods and systems for shortening the delay for non-post transmissions while maintaining fairness among the post transmissions. Undispatched non-post transmission requests are monitored on a running basis; and when a running value of the undispatched non-post transmission requests exceeds a threshold; ones of the post transmission requests are randomly dropped. | 2012-09-13 |
20120233376 | CONTROL DEVICE FOR STORAGE - A control device for controlling a storage device in which data is stored, the control device includes a processor that sets protection condition of the storage device through a signal line coupled with the storage device and sets the protection condition of the storage device through a first transmission line coupled with the control device, and an exchange switch coupled with the control device and an arithmetic operation device through the first transmission line and a second transmission line, respectively, the exchange switch being configured to switch between the first transmission line and the second transmission line so as to communicably couple either one of the control device and the arithmetic operation device with the storage device. | 2012-09-13 |
20120233377 | Cache System and Processing Apparatus - According to an embodiment, a cache system includes a volatile cache memory, a nonvolatile cache memory, an address decoder, and an evacuation unit. The nonvolatile cache memory has a capacity equal to the volatile cache memory. The address decoder designates a same line to the volatile cache memory and the nonvolatile cache memory. The evacuation unit stores data which is inputted from the volatile cache memory and outputs the stored data to the volatile cache memory. | 2012-09-13 |
20120233378 | PROTECTING GUEST VIRTUAL MACHINE MEMORY - A hypervisor runs on a host computer system and defines at least one virtual machine. An address space of the virtual machine resides on physical memory of the host computer system under control of the hypervisor. A guest operating system runs in the virtual machine. At least one of a host operating system and the hypervisor sets parts of the address space of the host computer system corresponding to parts of the address space of the virtual machine to a locked state in which those parts can be read but not written to. | 2012-09-13 |
20120233379 | METHOD OF CONTROLLING MEMORY, MEMORY CONTROL CIRCUIT, STORAGE DEVICE AND ELECTRONIC DEVICE - A method of controlling a memory including a first storage area and a second storage area. The method includes determining, in response to a request for writing a write data string, whether the write data string changes a logical value stored in the memory from a first logical value to a second logical value, writing, to the first storage area, a logical value that is located in a position of the write data string and does not change an existing logical value of the memory from the first logical value to the second logical value, and writing the second logical value that is located in a position of the write data string and changes an existing logical value of the memory from the first logical value to the second logical value to the second storage area which is different from the first storage area. | 2012-09-13 |
20120233380 | SYSTEMS, DEVICES, MEMORY CONTROLLERS, AND METHODS FOR CONTROLLING MEMORY - Systems, devices, memory controllers, and methods for controlling memory are described. One such method includes activating a memory unit of a memory device; after activating the memory unit, providing a command to the memory device; and returning the memory unit to a previous state if the command does not indicate a target memory volume, wherein the memory unit remains active if the command indicates a target memory volume associated with the memory unit. | 2012-09-13 |
20120233381 | REMAPPING FOR MEMORY WEAR LEVELING - A method and a corresponding apparatus provide for remapping for wear leveling of a memory ( | 2012-09-13 |
20120233382 | DATA STORAGE APPARATUS AND METHOD FOR TABLE MANAGEMENT - According to one embodiment, a data storage apparatus includes a first memory configured to store a first management table, a second memory configured to store a second management table, a counter table memory, and a controller. The first management table has address data representing a storage position of data stored in a flash memory. The second memory has address data representing valid data included in the data stored in the flash memory. The counter table memory stores a counter table showing the count value of valid data in units of addresses. The controller is configured to refer to the first management table, to compare the number of data valid in units of addresses acquired by referring to the first management table, and to perform a matching check process for determining matching between the first and second management tables from a result of the comparison. | 2012-09-13 |
20120233383 | MEMORY SYSTEM AND MEMORY CONTROLLER - A memory system according to the embodiment comprises a memory device including a plurality of memory cells operative to store storage data, the storage containing input data from external to which parity information is added; and a memory controller operative to convert between the input data and the storage data, the storage data containing information data corresponding to the input data, and a relationship between the information data and the input data being nonlinearly. | 2012-09-13 |
20120233384 | METHODS AND SYSTEM FOR ERASING DATA STORED IN NONVOLATILE MEMORY IN LOW POWER APPLICATIONS - The erasing of data stored in a nonvolatile memory is performed using multiple partial erase operations. Each partial erase operation has a time duration that is shorter than the minimum time duration of an erase operation that is needed to reliably erase the data stored in the storage location. However, the sum of the time durations of the multiple partial erase operations is sufficient to reliably erase the data in the storage location. In one example, during a partial erase operation, a voltage is applied to a memory storage transistor to remove some, but not necessarily all, of the charge stored on a charge storage layer of the transistor. Following multiple partial erase operations, sufficient charge is removed from the charge storage layer to ensure reliable data erasure. | 2012-09-13 |
20120233385 | HARD DISK DRIVE WITH OPTIONAL CACHE MEMORY - A computer system includes a hard disk drive, a processor coupled to the hard disk drive, and a cache interface coupled to the processor and detachably connectable to a cache memory. The processor is adapted, subsequent to an initial interrogation of the cache interface, to determine whether the cache memory is connected to the cache interface by inspecting an indication of the presence or the absence of the cache memory, the indication being stored in a register in the processor or in a memory associated with the processor such that the inspecting avoids repeat interrogation of the cache interface, to communicate with the cache memory and the hard disk drive such that the processor has access to the cache memory when the cache memory is connected to the cache interface, and to communicate with the hard disk drive when the cache memory is disconnected from the cache interface. | 2012-09-13 |
20120233386 | MULTI-INTERFACE SOLID STATE DISK, PROCESSING METHOD AND SYSTEM OF MULTI-INTERFACE SOLID STATE DISK - Embodiments of the present disclosure disclose a multi-interface solid state disk, and a processing method and system of the multi-interface solid state disk. The multi-interface solid state disk according to the present disclosure includes: plurality of interface control units, a command scheduling unit, a flash control unit and a flash chip. Each interface control unit corresponds to a communication interface respectively. The interface control unit receives an operating command through the communication interface. The command scheduling unit obtains, according to a scheduling rule, operating commands from the plurality of interface control units, puts the operating commands in a command queue, takes an operating command from the command queue, and sends the operating command to the flash control unit. The flash control unit converts the operating command into a flash operating command to operate the flash chip. | 2012-09-13 |
20120233387 | Copyback Optimization for Memory System - In a copyback or read operation for a non-volatile memory subsystem, data page change indicators are used to manage transfers of data pages between a register in non-volatile memory and a controller that is external to the non-volatile memory. | 2012-09-13 |
20120233388 | DATA WRITING METHOD FOR NON-VOLATILE MEMORY, AND CONTROLLER AND STORAGE SYSTEM USING THE SAME - A data writing method for writing data from a host system into a plurality of memory dies of a rewritable non-volatile memory storage apparatus is provided. The data writing method includes determining whether the data transmission interface of the host system complies with a first interface standard or a second interface standard. The data writing method also includes using a general mode to write the data into the memory dies when the data transmission interface of the host system complies with the first interface standard and using a power saving mode to write the data into the memory dies when the data transmission interface of the host system complies with the second interface standard. Accordingly, the data writing method can effectively prevent the stability of the rewritable non-volatile memory storage apparatus from reducing due to insufficient power supplied by the data transmission interface. | 2012-09-13 |
20120233389 | MULTI-HOST CONCURRENT WRITING TO MAGNETIC TAPE - According to one embodiment, a method for storing data on a magnetic tape comprises receiving data from two different hosts and simultaneously writing the data from the hosts to the magnetic tape using multiple transducers. In another approach, a method for storing data on a magnetic tape comprises receiving requests to establish a concurrent reservation from multiple hosts and allocating a unique stripe in a wrap to each of the hosts that sent the requests, wherein the wrap is a collection of data tracks to be written simultaneously in one direction of tape movement by multiple transducers of a tape head, and the wrap is logically divided into the stripes. Also, the method includes receiving data from the hosts and simultaneously writing the data from the hosts to the magnetic tape using the multiple transducers. Other systems and methods concerning storing data on magnetic tapes are described as well. | 2012-09-13 |
20120233390 | DATA UPDATE METHOD AND FLASH MEMORY APPARATUS UTILIZING THE SAME - A flash memory apparatus includes a plurality of blocks comprising a first block, wherein the first block comprises a first page; and a memory controller receiving a first data to be written into the first page of the first block, and when the first page has already been written to, the memory controller further selects one of the blocks as a first cache block, writes the first data into a first cache page of the first cache block and records a number of the first block and a number of the first page into the first cache page, and when receiving a command for updating the first block, the memory controller further updates the first block according to the number of the first block and the number of the first page recorded in the first cache page. A data update method for such a flash memory is also described. | 2012-09-13 |
20120233391 | Efficient Reduction of Read Disturb Errors in NAND FLASH Memory - Methods and apparatuses for reduction of Read Disturb errors in a NAND FLASH memory system comprise a controller configured to organize FLASH memory devices into blocks, each block having a plurality of pages, and each page defining an individually addressable physical memory location. The controller is further configured to accumulate a Block READ Count corresponding to the number of times any pages in a first block of pages have been read since the first block was last erased. Once the READ count reaches a predetermined number, the controller responds to subsequent READ requests for pages within the first block by moving data associated with a requested page to a page in a second, different block without moving data associated with other pages in the first block, and modifying a logical-to-physical translation table to associate the moved data with the physical address of the page in the second block. | 2012-09-13 |
20120233392 | SOLID STATE STORAGE DEVICE CONTROLLER WITH EXPANSION MODE - Solid state storage device controllers, solid state storage devices, and methods for operation of solid state storage device controllers are disclosed. In one such solid state storage device, the controller can operate in either an expansion DRAM mode or a non-volatile memory mode. In the DRAM expansion mode, one or more of the memory communication channels normally used to communicate with non-volatile memory devices is used to communicate with an expansion DRAM device. | 2012-09-13 |
20120233393 | Scheduling Workloads Based On Cache Asymmetry - In one embodiment, a processor includes a first cache and a second cache, a first core associated with the first cache and a second core associated with the second cache. The caches are of asymmetric sizes, and a scheduler can intelligently schedule threads to the cores based at least in part on awareness of this asymmetry and resulting cache performance information obtained during a training phase of at least one of the threads. | 2012-09-13 |
20120233394 | MEMORY CONTROLLER AND A CONTROLLING METHOD ADAPTABLE TO DRAM - A memory controller and controlling method adaptable to a dynamic random access memory (DRAM) are disclosed. A DRAM controller is configured to manage flow of data to and from the DRAM. A write buffer is controlled by the DRAM controller to temporarily store an entry of data to be written to the DRAM. The data to be written is stored in the write buffer if the write buffer is empty, and the stored data and a succeeding data to be written are both written to the DRAM. | 2012-09-13 |
20120233395 | EMULATION OF ABSTRACTED DIMMS USING ABSTRACTED DRAMS - One embodiment of the present invention sets forth an abstracted memory subsystem comprising abstracted memories, which each may be configured to present memory related characteristics onto a memory system interface. The characteristics can be presented on the memory system interface via logic signals or protocol exchanges, and the characteristics may include any one or more of, an address space, a protocol, a memory type, a power management rule, a number of pipeline stages, a number of banks, a mapping to physical banks, a number of ranks, a timing characteristic, an address decoding option, a bus turnaround time parameter, an additional signal assertion, a sub-rank, a number of planes, or other memory-related characteristics. Some embodiments include an intelligent register device and/or, an intelligent buffer device. One advantage of the disclosed subsystem is that memory performance may be optimized regardless of the specific protocols used by the underlying memory hardware devices. | 2012-09-13 |
20120233396 | APPARATUS, SYSTEM, AND METHOD FOR EFFICIENT MAPPING OF VIRTUAL AND PHYSICAL ADDRESSES - An apparatus, system, and method are disclosed for efficiently mapping virtual and physical addresses. A forward mapping module uses a forward map to identify physical addresses of data of a data segment from a virtual address. The data segment is identified in a storage request. The virtual addresses include discrete addresses within a virtual address space where the virtual addresses sparsely populate the virtual address space. A reverse mapping module uses a reverse map to determine a virtual address of a data segment from a physical address. The reverse map maps the data storage device into erase regions such that a portion of the reverse map spans an erase region of the data storage device erased together during a storage space recovery operation. A storage space recovery module uses the reverse map to identify valid data in an erase region prior to an operation to recover the erase region. | 2012-09-13 |
20120233397 | SYSTEM AND METHOD FOR STORAGE UNIT BUILDING WHILE CATERING TO I/O OPERATIONS - Provided is a method for copying data as stored in at least one source storage entity, including copying data from a source storage entity into a destination storage entity and catering to at least one I/O operation directed toward the source storage entity during copying, the copying including reading at least one chunk of data in a predetermined order; and reading, responsive to a request, at least one relevant chunk containing data related to at least one I/O operation out of the predetermined order. | 2012-09-13 |
20120233398 | STORAGE SYSTEM AND DATA MANAGEMENT METHOD - The present invention comprises a CHA | 2012-09-13 |
20120233399 | STORAGE APPARATUS AND METHOD OF CONTROLLING THE SAME - The present invention aims to improve the performance of a storage apparatus. | 2012-09-13 |
20120233400 | DISK ARRAY UNIT - A disk array unit connected to a host unit to give information thereto and receive information therefrom. The disk unit includes a plurality of disk units for storing information transmitted from the host unit and a management information recording device, formed by utilizing information storage areas in the disk units, for causing information relating to a logical unit for storing information from the host unit to correspond to information relating to the units. The invention further includes a control unit, when there is no access from the host unit to the logical unit for a predetermined time, for determining the disk units corresponding to the logical unit based on information recorded in the management information recording device and performing power saving of power supply for the disk units. | 2012-09-13 |
20120233401 | EMBEDDED MEMORY SYSTEM - An embedded memory system is disclosed. A main interface is configured to communicate with an electronic system via a main bus. A memory-sharing auxiliary interface is configured to communicate with the electronic system via a memory-sharing auxiliary bus. An arbiter is configured to arbitrate among the main interface, the memory-sharing auxiliary interface, a primary memory, and a secondary memory. Accordingly, the electronic system is capable of sharing either the primary memory or the secondary memory via the memory-sharing auxiliary interface and the memory-sharing auxiliary bus, and the embedded memory system is capable of sharing a system memory of the electronic system via the memory-sharing auxiliary interface and the memory-sharing auxiliary bus. | 2012-09-13 |
20120233402 | Apparatus and Method for a Removable Memory Module - In accordance with an example embodiment of the present invention, an apparatus is provided, comprising: a first part configured to receive a first and second removable memory module, a second part coupled with the first part with a hinge, and conductive terminals configured to contact the first removable memory module in a first closed position and the second removable memory module in a second closed position. | 2012-09-13 |
20120233403 | ELECTRONIC DEVICE, CONTROL METHOD THEREOF, PROGRAM, AND STORAGE MEDIUM - An electronic device is provided. The electronic device includes a drive for attaching a removable storage, a reader for reading update information acquired from a network through a device having a network connection function when the removable storage is attached to the drive, the information being recorded in a predetermined directory in the removable storage, and a writer for writing device information necessary for acquiring the update information in a predetermined directory in the removable storage when the removable storage is attached to the drive. The electronic device is not provided with a function for connecting to the network. | 2012-09-13 |
20120233404 | DELETING RELATIONS IN MULTI-TARGET, POINT-IN-TIME-COPY ARCHITECTURES WITH DATA DEDUPLICATION - A method for deleting a relation between a source and a target in a multi-target architecture is described. The multi-target architecture includes a source and multiple targets mapped thereto. In one embodiment, such a method includes initially identifying a relation for deletion from the multi-target architecture. A target associated with the relation is then identified. The method then identifies a sibling target that inherits data from the target. Once the target and the sibling target are identified, the method copies the data from the target to the sibling target. The relation between the source and the target is then deleted. A corresponding computer program product is also disclosed and claimed herein. | 2012-09-13 |
20120233405 | Caching Method and System for Video Coding - A method of caching reference data in a reference data cache is provided that includes receiving an address of a reference data block in the reference data cache, wherein the address includes an x coordinate and a y coordinate of the reference data block in a reference block of pixels and a reference block identifier specifying which of a plurality of reference blocks of pixels includes the reference data block, computing an index of a set of cache lines in the reference data cache using bits from the x coordinate and bits from the y coordinate, using the index and a tag comprising the reference block identifier to determine whether the reference data block is in the set of cache lines, and retrieving the reference data block from reference data storage when the reference data block is not in the set of cache lines. | 2012-09-13 |
20120233406 | STORAGE APPARATUS, AND CONTROL METHOD AND CONTROL APPARATUS THEREFOR - A control apparatus, coupled to a storage medium via communication links, controls data write operations to the storage medium. A cache memory is configured to store a temporary copy of first data written in the storage medium. A processor receives second data with which the first data in the storage medium is to be updated, and determines whether the received second data coincides with the first data, based on comparison data read out of the storage medium, when no copy of the first data is found in the cache memory. When the second data is determined to coincide with the first data, the processor determines not to write the second data into the storage medium. | 2012-09-13 |
20120233407 | CACHE PHASE DETECTOR AND PROCESSOR CORE - A cache phase detector included in a processor core according to example embodiments includes a counting unit and a signal generating unit. The counting unit generates a critical section miscount by counting a request from the processor core resulting in a tag miss and a valid cache line based on a tag miss signal and a cache line valid signal. The signal generating unit compares the critical section miscount from the counting unit with a reference value, and generates a cache phase change signal if the critical section miscount is greater than the reference value. | 2012-09-13 |
20120233408 | INTELLIGENT WRITE CACHING FOR SEQUENTIAL TRACKS - Write caching for sequential tracks is performed by a processor device in a computing storage environment for destaging data from nonvolatile storage (NVS) to a storage unit. If a first track is determined to be sequential, and an earlier track is also determined to be sequential, a temporal bit associated with the earlier track is cleared to allow for destage of data of the earlier track. If a temporal bit for one of a plurality of additional tracks in one of a plurality of strides in a modified cache is determined to be not set, a stride associated with the one of the plurality of additional tracks is selected for a destage operation. If the NVS exceeds a predetermined storage threshold, a predetermined one of the plurality of strides is selected for the destage operation. | 2012-09-13 |
20120233409 | MANAGING SHARED MEMORY USED BY COMPUTE NODES - A technology can be provided for managing shared memory used by a plurality of compute nodes. An example system can include a shared globally addressable memory to enable access to shared data by the plurality of compute nodes. A memory interface can process memory requests sent to the shared globally addressable memory from the plurality of processors. A memory write module can be included for the memory interface to allocate memory locations in the shared globally addressable memory and write read-only data to the globally addressable memory from a writing compute node. In addition, a read module for the memory interface can map read-only data in the globally addressable shared memory as read-only for subsequent accesses by the plurality of compute nodes. | 2012-09-13 |
20120233410 | Shared-Variable-Based (SVB) Synchronization Approach for Multi-Core Simulation - The present invention discloses a shared-variable-based (SVB) approach for fast and accurate multi-core cache coherence simulation. While the intuitive, conventional approach, synchronizing at either every cycle or memory access, gives accurate simulation results, it has poor performance due to huge simulation overloads. In the present invention, timing synchronization is only needed before shared variable accesses in order to maintain accuracy while improving the efficiency in the proposed shared-variable-based approach. | 2012-09-13 |
20120233411 | Protecting Large Objects Within an Advanced Synchronization Facility - A system and method are disclosed for allowing protection of larger areas than memory lines by monitoring accessed and dirty bits in page tables. More specifically, in some embodiments, a second associative structure with a different granularity is provided to filter out a large percentage of false positives. By providing the associative structure with sufficient size, the structure exactly specifies a region in which conflicting cache lines lie. If entries within this region are evicted from the structure, enabling the tracking for the entire index filters out a substantial number of false positives (depending on a granularity and a number of indices present). In some embodiments, this associative structure is similar to a translation look aside buffer (TLB) with 4 k, 2M entries. | 2012-09-13 |
20120233412 | MEMORY MANAGEMENT SYSTEM AND METHOD THEREOF - The invention discloses a memory management system and a memory management method are disclosed. The memory management system includes a first memory, at least one secondary memory, and a memory management device. The first memory includes a normal access memory bank and at least one switching access memory bank. The secondary memory includes at least one secondary access memory bank corresponding to the switching access memory bank. The memory management device reads/writes the normal access memory bank or the secondary access memory bank. | 2012-09-13 |
20120233413 | METHODS OF ACCESSING MEMORY CELLS, METHODS OF DISTRIBUTING MEMORY REQUESTS, SYSTEMS, AND MEMORY CONTROLLERS - Methods of accessing memory cells, methods of distributing memory requests, systems, and memory controllers are described. In one such method, where memory cells are divided into at least a first region of memory cells and a second region of memory cells, memory cells in the first region are accessed according to a first address definition and memory cells in the second region are accessed according to a second address definition that is different from the first address definition. Additional embodiments are described. | 2012-09-13 |
20120233414 | SHORT POINTERS - A digital processor stores pointers of different sizes in memory. The processor, specifically, executes instructions to store a long or short pointer. Long pointers reference any address in the memory's logical address space, while short pointers merely reference any address in a subset of that space. However, short pointers are smaller in size as stored in memory than long pointers. Long pointers thus support relatively large address range capabilities, while short pointers use less memory. The processor also executes instructions to load a long or short pointer into the register file, and does so in a way that does not require the processor to distinguish between the different pointers when executing other instructions. Specifically, the processor converts long and short pointers into a common format for loading into the register file, and converts pointers in the common format back into long or short pointers for storing in the memory. | 2012-09-13 |
20120233415 | METHOD AND APPARATUS FOR SEARCHING FOR DATA IN MEMORY, AND MEMORY - The invention provides a method and apparatus for searching for data in a memory. The memory includes at least two storage areas, each storage area includes at least two storage blocks, and storage blocks in each storage area are corresponding to each other. The method includes: determining whether a hit storage block that matches with data to be searched for exists in a current storage area; and if it is determined that the hit storage block exists, searching for a storage block corresponding to the hit storage block in a next storage area, so as to determine whether a hit storage block further exists. Accordingly, a storage block corresponding to a missed storage block may execute no operation, thus reducing power consumption. | 2012-09-13 |
20120233416 | MULTI-TARGET, POINT-IN-TIME-COPY ARCHITECTURE WITH DATA DEDUPLICATION - A method for performing a write to a source volume in a multi-target architecture is described. The multi-target architecture includes a source volume and multiple target volumes mapped thereto. In one embodiment, such a method includes copying data in a track of the source volume to a corresponding track of a target volume (target x). The method enables one or more sibling target volumes (siblings) mapped to the source volume to inherit the data from the target x. When the data is successfully copied to the target x, the method performs a write to the track of the source volume. Other methods for reading and writing data to volumes in the multi-target architecture are also described. | 2012-09-13 |
20120233417 | BACKUP AND RESTORE STRATEGIES FOR DATA DEDUPLICATION - Techniques for backup and restore of optimized data streams are described. A chunk store includes each optimized data stream as a plurality of chunks including at least one data chunk and corresponding optimized stream metadata. The chunk store includes data chunks in a deduplicated manner. Optimized data streams stored in the chunk store are identified for backup. At least a portion of the chunk store is stored in backup storage according to an optimized backup technique, an un-optimized backup technique, an item level backup technique, or a data chunk identifier backup technique. Optimized data streams stored in the backup storage may be restored. A file reconstructor includes a callback module that generates calls to a restore application to request optimized stream metadata and any referenced data chunks from the backup storage. The file reconstructor reconstructs the data streams from the referenced data chunks. | 2012-09-13 |
20120233418 | MASSIVELY SCALABLE OBJECT STORAGE - Several different embodiments of a massively scalable object storage system are described. The object storage system is particularly useful for storage in a cloud computing installation whereby shared servers provide resources, software, and data to computers and other devices on demand. In several embodiments, the object storage system includes a ring implementation used to associate object storage commands with particular physical servers such that certain guarantees of consistency, availability, and performance can be met. In other embodiments, the object storage system includes a synchronization protocol used to order operations across a distributed system. In a third set of embodiments, the object storage system includes a metadata management system. In a fourth set of embodiments, the object storage system uses a structured information synchronization system. Features from each set of embodiments can be used to improve the performance and scalability of a cloud computing object storage system. | 2012-09-13 |
20120233419 | COMPUTER SYSTEM, METHOD OF SCHEDULING DATA REPLICATION, AND COMPUTER-READABLE NON-TRANSITORY STORAGE MEDIUM - An embodiment of this invention schedules data replications for backing up a first storage system providing a plurality of applications with volumes to a second storage system. This scheduling determines scheduled finish times of respective data replications for the plurality of applications and determines start times of the respective data replications for the plurality of applications from the scheduled finish times of the respective data replications and the respective amounts of data to be transferred for the plurality of applications, using a data transfer rate between the storage systems and an overlap degree of data replication periods of the plurality of applications. | 2012-09-13 |
20120233420 | FAULT-TOLERANT SYSTEM, MEMORY CONTROL METHOD, AND COMPUTER-READABLE RECORDING MEDIUM STORING PROGRAMS - The object is to prevent the processing of a fault-tolerant computer from slowing down. The memory of the active system comprises a memory table and a transfer table. When data stored in the memory table are updated, the updated data are stored also in the transfer table. When data are transferred from the transfer table to the standby system, only update of data stored in the transfer table is restricted. The memory table is continuously used as the work area for normal operation. Consequently, slowing down in the processing of a fault-tolerant computer due to restriction on update of data stored in the memory is prevented. | 2012-09-13 |
20120233421 | CYCLIC POINT-IN-TIME-COPY ARCHITECTURE WITH DATA DEDUPLICATION - A method for performing a write to a volume x in a cyclic point-in-time-copy architecture is described. In one embodiment, such a method includes determining whether the volume x has a child volume. The method then determines whether the target bit maps (TBMs) of both the volume x and the child volume are set. If the TBMs are set, the method finds a higher source (HS) volume from which to copy the desired data to the child volume. Once the HS volume is found, the method determines whether the HS volume and the child volume are the same volume. If the HS volume and the child volume are not the same volume, the method copies the data from the HS volume to the child volume. The method then performs the write to the volume x. | 2012-09-13 |
20120233422 | DATA INTEGRITY PROTECTION IN STORAGE VOLUMES - A plurality of logical volumes are stored at a plurality of sites. A command to execute an operation on a logical volume is received. A determination is made as to whether a rule associated with the logical volume permits execution of the operation on the logical volume. In response to determining that the rule associated with the logical volume permits execution of the operation on the logical volume, the operation is executed on the logical volume. | 2012-09-13 |
20120233423 | SUBSTITUTION OF A TARGET VOLUME OF A SECONDARY STORAGE CONTROLLER FOR A SOURCE VOLUME OF A PRIMARY STORAGE CONTROLLER FOR EXECUTING A WRITE OPERATION - A secondary storage controller receives metadata that uniquely identifies a source volume of a primary storage controller. Data stored in the source volume of the primary storage controller is synchronously copied to a target volume of the secondary storage controller. The secondary storage controller receives a command from a primary host to write selected data to the source volume. In response to receiving the command at the secondary storage controller, the selected data is written to the target volume of the secondary storage controller. | 2012-09-13 |
20120233424 | DATA STORAGE CONTROL ON STORAGE DEVICES - An object of the present invention is to improve the usage efficiency of a storage extent in a storage system using the Allocation on Use (AOU) technique. A controller in the storage system allocates a storage extent in an actual volume to an extent in a virtual volume accessed by a host computer, detects any decrease in necessity for maintaining that allocation, and cancels the allocation of the storage extent in the actual volume to the extent in the virtual volume based on the detection result. | 2012-09-13 |
20120233425 | DE-DUPLICATION IN A VIRTUALIZED STORAGE ENVIRONMENT - A data de-duplication application de-duplicates redundant data in the pooled storage capacity of a virtualized storage environment. The virtualized storage environment includes a plurality of storage devices and a virtualization or abstraction layer that aggregates all or a portion of the storage capacity of each storage device into a single pool of storage capacity, all or portions of which can be allocated to one or more host systems. For each host system, the virtualization layer presents a representation of at least a portion of the pooled storage capacity wherein the corresponding host system can read and write data. The data de-duplication application identifies redundant data in the pooled storage capacity and replaces it with one or more pointers pointing to a single instance of the data. The de-duplication application can operate on fixed or variable size blocks of data and can de-duplicate data either post-process or in-line. | 2012-09-13 |
20120233426 | DATA COPYING - A data processing system includes a host and a plurality of locations. A difference recording operation between a first location of the plurality of locations and a second location of the plurality of locations is started. A first operational relationship between a third location of the plurality of locations and the first location is started. A signal is sent is response to the first operational relationship starting after the difference recording operation. A first dataset is updated in response to the host writing data to at least one of the first location or the second location. The first dataset is updated with changes to the first location in response to the signal. | 2012-09-13 |
20120233427 | Data Storage Device and Data Management Method Thereof - An embodiment of the invention provides a data storage device and data management method thereof. The data storage device is coupled to a host, and includes a storage media having data sectors for storing data and a controller. The controller is coupled to the storage media for sequentially receiving one or more read commands and corresponding one or more logical addresses thereto, reads a plurality of first data sectors from the storage media according to the read commands and the corresponding logical addresses, outputs data of the first data sectors to the host, calculates a valid duration required for the one or more read commands, calculates an average data throughput according to the number of the first data sectors and the valid duration, and determines whether the average data throughput exceeds a predetermined threshold. When the average data throughput exceeds the predetermined threshold, the controller performs a blocking procedure to prevent the storage media from being accessed. | 2012-09-13 |
20120233428 | APPARATUS AND METHOD FOR SECURING PORTABLE STORAGE DEVICES - An apparatus and method for controlling and securing information stored on portable USB storage devices. Using the software application stored on the USB storage device in conjunction with functionality performed by a designed server, use of the storage device is limited to authorized users, PCs and locations, and other criteria while information contained within the device is protected from unauthorized access. | 2012-09-13 |
20120233429 | CASCADED, POINT-IN-TIME-COPY ARCHITECTURE WITH DATA DEDUPLICATION - A method for performing a write to a volume x in a cascaded architecture is described. In one embodiment, such a method includes determining whether the volume x has a child volume, wherein each of the volume x and the child volume have a target bit map (TBM) associated therewith. The method then determines whether the TBMs of both the volume x and the child volume are set. If the TBMs are set, the method finds a higher source (HS) volume from which to copy the desired data to the child volume. Finding the HS volume includes travelling up the cascaded architecture until the source of the data is found. Once the HS volume is found, the method copies the data from the HS volume to the child volume and performs the write to the volume x. A method for performing a read is also disclosed herein. | 2012-09-13 |
20120233430 | CYCLIC POINT-IN-TIME-COPY ARCHITECTURE WITH DATA DEDUPLICATION - A method for performing a write to a volume x in a cyclic point-in-time-copy architecture is described. In one embodiment, such a method includes determining whether the volume x has a child volume. The method then determines whether the target bit maps (TBMs) of both the volume x and the child volume are set. If the TBMs are set, the method finds a higher source (HS) volume from which to copy the desired data to the child volume. Once the HS volume is found, the method determines whether the HS volume and the child volume are the same volume. If the HS volume and the child volume are not the same volume, the method copies the data from the HS volume to the child volume. The method then performs the write to the volume x. A corresponding computer program product is also described. | 2012-09-13 |
20120233431 | RELAY DEVICE - A relay device | 2012-09-13 |
20120233432 | DYNAMIC GUARDING OF A STORAGE MEDIA - A fixed data region on a storage medium may be allocated with one of a variety of allocation schemes (e.g., a randomly writable allocation scheme, a non-randomly writeable allocation scheme with a first data isolator spacing, a non-randomly writeable allocation scheme with a second data isolator spacing, and a non-randomly writeable allocation scheme with no dynamic isolators). Dynamic sub-region spacing refers at least to the number of data tracks in a data region of a magnetic disc between dynamic isolators and the number of bits in a data region in flash memory between dynamic isolators. The presently disclosed technology adapts isolators on the storage medium to create dynamic sub-regions based on characteristics of the storage medium, characteristics of the data, and/or expected access patterns of data to be written to the storage medium. | 2012-09-13 |
20120233433 | SYSTEMS, DEVICES, MEMORY CONTROLLERS, AND METHODS FOR MEMORY INITIALIZATION - Systems, devices, memory controllers, and methods for initializing memory are described. Initializing memory can include configuring memory devices in parallel. The memory devices can receive a shared enable signal. A unique volume address can be assigned to each of the memory devices. | 2012-09-13 |
20120233434 | Virtual Disk Storage Techniques - This document describes techniques for storing virtual disk payload data. In an exemplary configuration, each virtual disk extent can be associated with state information that indicates whether the virtual disk extent is described by a virtual disk file. Under certain conditions the space used to describe a virtual disk extent can be reclaimed and state information can be used to determine how read and/or write operations directed to the virtual disk extent are handled. In addition to the foregoing, other techniques are described in the claims, figures, and detailed description of this document. | 2012-09-13 |
20120233435 | DYNAMIC MEMORY MANAGEMENT IN A VIRTUALIZED COMPUTING ENVIRONMENT - A memory management method in a virtualized computing environment is provided, in which a hypervisor implements at least a virtual machine (VM) over a host machine, wherein a guest operating system (OS) is executed over the VM and an application supporting memory management capabilities is executed over the guest OS. The method comprises invoking a first memory manager (java balloon) implemented by the application to deallocate memory allocated to the application for use by the hypervisor, in response to a request submitted by the hypervisor; and invoking a second memory manager (guest balloon) implemented over the guest operating system to deallocate memory allocated to the guest OS, in response to a request submitted by the hypervisor. | 2012-09-13 |
20120233436 | Data Management Method in Storage Pool and Virtual Volume in DKC - A storage system connected to a computer and a management computer, includes storage devices accessed by the computer, and a control unit for controlling the storage devices. A first-type logical device corresponding to a storage area set in at least one of the storage devices and a second-type logical device that is a virtual storage area are provided. The control unit sets at least two of the first-type logical devices different in a characteristic as storage areas included in a storage pool through mapping. The first-type logical device stores data by allocating a storage area of the second-type logical device to a storage area of the first-type logical device mapped to the storage pool. The characteristic of the second-type logical device can be changed by changing the allocated storage area of the second-type logical device to a storage area of another first-type logical device. | 2012-09-13 |
20120233437 | HIERARCHICAL STORAGE SYSTEM - Pools of a plurality of types of storage devices are configured and are included in different layers. Based on at least one storage device of the same type, the pools of types corresponding to the type are configured. The controller in the storage system carries out storage location change processing in which the storage location of targeted data that has been stored into the targeted first real page allocated to a virtual page in a virtual volume is changed to the second real page that has not been allocated in a pool of the second type different from a pool of the first type including the targeted first real page in the case in which the controller conforms to the prescribed storage location change conditions. A size of a real page is different depending on a type of a pool. | 2012-09-13 |
20120233438 | PAGEFILE RESERVATIONS - A system and method for maintaining a pagefile of a computer system using a technique of reserving portions of the pagefile for related memory pages. Pages near one another in a virtual memory space often store related information and it is therefore beneficial to ensure that they are stored near each other in the pagefile. This increases the speed of reading data out of the pagefile because total seek time of a disk drive that stores the pagefile may decrease when adjacent pages in a virtual memory address space are read back from the disk drive. By implementing a reservation system that allows related pages to be stored adjacent to one another, the efficiency of memory management to of the computer system is increased. | 2012-09-13 |
20120233439 | Implementing TLB Synchronization for Systems with Shared Virtual Memory Between Processing Devices - Page faults arising in a graphics processing unit may be handled by an operating system running on the central processing unit. In some embodiments, this means that unpinned memory can be used for the graphics processing unit. Using unpinned memory in the graphics processing unit may expand the capabilities of the graphics processing unit in some cases. | 2012-09-13 |
20120233440 | ADDRESS GENERATION IN A DATA PROCESSING APPARATUS - A data processing apparatus is provided comprising processing circuitry and an instruction decoder responsive to program instructions to control processing circuitry to perform the data processing. The instruction decoder is responsive to an address calculating instruction to perform an address calculating operation for calculating a partial address result from a non-fixed reference address and a partial offset value such that a full address specifying a memory location of an information entity is calculable from said partial address result using at least one supplementary program instruction. The partial offset value has a bit-width greater than or equal to said instruction size and is encoded within at least one partial offset field of said address calculating instruction. A corresponding data processing method, virtual machine and computer program product are also provided. | 2012-09-13 |
20120233441 | MULTI-THREADED INSTRUCTION BUFFER DESIGN - An instruction buffer for a processor configured to execute multiple threads is disclosed. The instruction buffer is configured to receive instructions from a fetch unit and provide instructions to a selection unit. The instruction buffer includes one or more memory arrays comprising a plurality of entries configured to store instructions and/or other information (e.g., program counter addresses). One or more indicators are maintained by the processor and correspond to the plurality of threads. The one or more indicators are usable such that for instructions received by the instruction buffer, one or more of the plurality entries of a memory array can be determined as a write destination for the received instructions, and for instructions to be read from the instruction buffer (and sent to a selection unit), one or more entries can be determined as the correct source location from which to read. | 2012-09-13 |
20120233442 | RETURN ADDRESS PREDICTION IN MULTITHREADED PROCESSORS - Techniques and structures are disclosed relating to predicting return addresses in multithreaded processors. In one embodiment, a processor is disclosed that includes a return address prediction unit. The return address prediction unit is configured to store return addresses for different ones of a plurality of threads executable on the processor. The return address prediction unit is configured to receive a request for a predicted return address for one of the plurality of threads. The first request includes an identification of the requesting thread. The return address prediction unit is configured to provide the predicted return address to the requesting thread. In some embodiments, the return address prediction unit is configured to store the return addresses in a memory that has a plurality of dedicated portions. In some embodiments, the return address prediction unit is configured to store the return addresses in a memory that has dynamically allocable entries. | 2012-09-13 |
20120233443 | PROCESSOR TO EXECUTE SHIFT RIGHT MERGE INSTRUCTIONS - Method, apparatus, and program means for performing bitstream buffer manipulation with a SIMD merge instruction. The method of one embodiment comprises determining whether any unprocessed data bits for a partial variable length symbol exist in a first data block is made. A shift merge operation is performed to merge the unprocessed data bits from the first data block with a second data block. A merged data block is formed. A merged variable length symbol comprised of the unprocessed data bits and a plurality of data bits from the second data block is extracted from the merged data block. | 2012-09-13 |
20120233444 | MIXED SIZE DATA PROCESSING OPERATION - A data processing system | 2012-09-13 |
20120233445 | Multi-Thread Processors and Methods for Instruction Execution and Synchronization Therein and Computer Program Products Thereof - Methods for instruction execution and synchronization in a multi-thread processor are provided, wherein in the multi-thread processor, multiple threads are running and each of the threads can simultaneously execute a same instruction sequence. A source code or an object code is received and then compiled to generate the instruction sequence. Instructions for all of function calls within the instruction sequence are sorted according to a calling order. Each thread is provided a counter value pointing to one of the instructions in the instruction sequence. A main counter value is determined according to the counter values of the threads such that all of the threads simultaneously execute an instruction of the instruction sequence that the main counter value points to. | 2012-09-13 |
20120233446 | Program-Instruction-Controlled Instruction Flow Supervision - A signature module calculates a signature during the execution of a program by a central processing unit based on program instructions to the central processing unit, and stores the signature in a signature register of the signature module. The signature module includes: a calculation unit configured to generate a signature value based on program instructions executed on the central processing unit; and an instruction information interface configured to receive at least one item of instruction information from the central processing unit which indicates whether an instruction currently being executed by the central processing unit was jumped to indirectly or directly. | 2012-09-13 |
20120233447 | Systems and Methods Providing Data Module and Processing Platform Integration - A system includes a data module with a data bus interface to a host processing platform. The data module has a data resource hardware component, and a non-volatile memory storing an Operating System (OS) image. The non-volatile memory is in communication with the data bus interface to the host processing platform. The OS image, when executed by the processing platform, exposes a control Application Programming Interface (API) thereby providing access to the data resource hardware component. | 2012-09-13 |
20120233448 | MANAGING SOFTWARE CHANGES - The claimed subject matter provides a system or method for managing software changes. An exemplary method comprises creating a reset boot loader, a last known good (LKG) boot loader, and a current boot loader, then pointing the reset boot loader, LKG boot loader, and current boot loader to a parent virtual hard disk (VHD) containing a default master image. An operation to perform is determined, and a service partition is booted into. The LKG boot loader or current boot loader is pointed to a child VHD loaded with another desired image based on the operation selected, and the system is rebooted into the parent VHD or child VHD pointed to by the current boot loader. | 2012-09-13 |
20120233449 | METHODS AND SYSTEMS FOR MEASURING TRUSTWORTHINESS OF A SELF-PROTECTING DRIVE - A method for measuring the trustworthiness of a self-protecting drive includes receiving a measurement from an element within a transitive chain of trust, processing the received measurement, storing the measurement as a verification value, comparing the verification value with a reference verification value stored on the self-protecting drive, and unlocking at least a portion of the self-protecting drive when the reference verification value corresponds to the verification value. A self-protecting drive includes a boot partition, a trusted partition, a master boot partition, a primary partition, a secondary partition, and a particular table that has a verification platform configuration register and a reference platform configuration register. The primary partition is inaccessible until the self-protecting drive determines that a value stored in the verification platform configuration register corresponds to a value stored in the reference platform configuration register. | 2012-09-13 |
20120233450 | SYSTEM AND METHOD OF BOOTING A COMPUTER SYSTEM USING AN EFI PERSONALITY OF A DIFFERENT COMPUTER SYSTEM - Booting a computer system using an EFI personality of a different computer system. At least some of the illustrative embodiments are methods including: reading, by a first computer system, a plurality of parameters of an EFI personality of a second computer system different than the first computer system; modifying, by the first computer system, a first parameter of the plurality of parameters thereby creating a modified EFI personality; and booting an operating system on the first computer system based on modified EFI personality. | 2012-09-13 |
20120233451 | METHOD FOR FAST RESUMING COMPUTER SYSTEM AND COMPUTER SYSTEM - A method for fast resuming a computer system from a shutdown state is provided. The computer system comprises a basic input output system (BIOS), a system memory and a storage device storing a system memory data of the system memory and a used system memory block address table before the computer system enters the shutdown state. The method comprises receiving a starting signal for power supplying the computer system and starting the storage device. A fast boot built-in program of the BIOS is started and, according to the used system memory block address table, the fast boot built-in program sequentially reads the stored system memory data from the storage device and writes the read system memory data into the system memory with a use of an optimized read-and-write block size as a read-and-write unit. The computer system enters a suspended state and is resumed from the suspended state. | 2012-09-13 |
20120233452 | Reducing Current Draw Of A Plurality Of Solid State Drives At Computer Startup - Reducing current draw of solid state drives from a shared power supply of a computer at computer startup, each SSD including computer memory, a capacitor, a disk controller, and a charge controller, the disk controller configured to enable the charge controller to charge the capacitor upon receiving a charge command, the SSDs organized into startup groups characterized by a position in a predefined startup order. Upon startup of the computer, beginning with a first startup group in the predefined startup order and until the last startup group in the predefined startup order has received a charge command, embodiments include, sending, by a storage device initiator, a charge command to a startup group to initiate charging of the capacitor of each solid state drive in the startup group and waiting a predefined period of time before sending another charge command to a next startup group in the predefined startup order. | 2012-09-13 |
20120233453 | Reducing Processing Load in Proxies for Secure Communications - In one embodiment, a method for providing secure communications using a proxy is provided. The proxy negotiates with a client and a server to determine a session key to use with communications between the client and the proxy and between the proxy and the server. Encrypted data may then be received from the client at the proxy. The proxy can decrypt the encrypted data for processing using the session key. In one embodiment, the decrypted data is not altered. The proxy then sends the encrypted data that was received from the client to the server without re-encrypting the data that was decrypted. Because the proxy did not alter the data in its processing of the decrypted data and the same session key is used between communications for the proxy and the server, the encrypted data stream that was received from the client can be forwarded to the server. | 2012-09-13 |
20120233454 | DATA SECURITY FOR DIGITAL DATA STORAGE - A computing system includes data encryption in the data path between a data source and data storage devices. The data storage devices may be local or they may be network resident. The data encryption may utilize a key which is derived at least in part from an identification code stored in a non-volatile memory. The key may also be derived at least in part from user input to the computer. In a LAN embodiment, public encryption keys may be automatically transferred to a network server for file encryption prior to file transfer to a client system. | 2012-09-13 |
20120233455 | REDUNDANT KEY SERVER ENCRYPTION ENVIONMENT - Provided are a computer program product, system and method for a redundant key server encryption environment. A key server receives from at least one remote key server public keys associated with the at least one remote key server. The key server receives a request for an encryption key from a requesting device and generates the encryption key for use by the requesting device to unlock a storage. The key server generates a first wrapped encryption key by encrypting the encryption key with a requesting device public key, a second wrapped encryption key by encrypting the encryption key with a public key associated with the key server, and at least one additional wrapped encryption key by encrypting the encryption key with the at least one public key provided by the at least one remote key server. The key server transmits the generated keys to the requesting device. | 2012-09-13 |
20120233456 | METHOD FOR SECURELY INTERACTING WITH A SECURITY ELEMENT - A method for secured interaction with a security module which is integrated into an end device, via an input device of the end device, the input device being reserved by a security application which is executable in a trustworthy region of the end device. Subsequently, first authentication data are input via the reserved input device. The security application derives from the first authentication data by a secret data stored in the trustworthy region second authentication data. The latter are subsequently encrypted by the security application and transferred to the security module and/or to a server. In the security module and/or the server the received, encrypted second authentication data are finally decrypted. | 2012-09-13 |
20120233457 | ISSUING IMPLICIT CERTIFICATES - Methods, systems, and computer programs for issuing an implicit certificate are disclosed. In some implementations, a certificate authority of an elliptic curve cryptography (ECC) system performs one or more operations for issuing the implicit certificate. A certificate request associated with a requester is received, and the certificate request includes a first element R | 2012-09-13 |
20120233458 | INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND COMPUTER PROGRAM - An information processing apparatus and method that prior to using a digital certification considers a validity expiration date of the digital certificate as well as a usable deadline of an algorithm or a public key used in the digital certificate. | 2012-09-13 |
20120233459 | System and Method for Content Protection on a Computing Device - Systems and methods for handling user interface field data. A system and method can be configured to receive input which indicates that the mobile device is to enter into a protected mode. Data associated with fields displayed on a user interface are stored in a secure form on the mobile device. After the mobile device leaves the protected mode, the stored user interface filed data is accessed and used to populate one or more user interface fields with the accessed user interface field data for display to a user. | 2012-09-13 |