37th week of 2013 patent applcation highlights part 44 |
Patent application number | Title | Published |
20130236958 | Viral expression plasmids for production of proteins, antibodies, enzymes, virus-like particles and for use in cell-based assays - This disclosure shows that the EBV FR-element comprised of EBNA1 multimeric binding sites can provide the stable maintenance replication function to the mouse polyomavirus (PyV) core origin plasmids in the presence of BPV-1 E2 protein and PyV large T-antigen (LT). | 2013-09-12 |
20130236959 | FGF-2 HAVING ENHANCED STABILITY - Thermostable FGF-2 proteins having enhanced ability to support human pluripotent stem cell cultures are provided. Also provided are methods and compositions utilizing thermostable FGF-2 proteins. | 2013-09-12 |
20130236960 | VITRIFICATED STORAGE SOLUTION FOR CELLS - The vitrification medium for cells according to the present invention is a vitrification medium for cells comprising a cell membrane permeable substance and a cell membrane non-permeable substance, in which, the content of the cell membrane permeable substance is in the range of 30 to 50% by volume, and the osmotic pressure generated in association with the cell membrane non-permeable substance, which is a fraction of the total osmotic pressure on the cell membrane on suspending the cells in the vitrification medium, is in the range of 280 mOsm or more. The vitrification medium for cells according to the present invention is excellent in operability and safety. | 2013-09-12 |
20130236961 | NOVEL METHODS AND CULTURE MEDIA FOR CULTURING PLURIPOTENT STEM CELLS - Provided is an isolated population of human pluripotent stem cells comprising at least 50% human pluripotent stem cells characterized by an OCT4 | 2013-09-12 |
20130236962 | Medium and Culture of Embryonic Stem Cells - Previous methods for culturing primate pluripotent stem cells have required either fibroblast feeder cells or a medium which was exposed to fibroblast feeder cells to maintain the stem cells in an undifferentiated state. It has now been found that high levels of fibroblast growth factor in a medium together with at least one of gamma aminobutyric acid, pipecolic acid, and lithium, enables pluripotent stem cells to remain undifferentiated indefinitely through multiple passages, even without feeder cells or conditioned medium. Without beta-mercaptoethanol, the medium improves cloning efficiency. Also, a matrix of human proteins can be used to culture the undifferentiated cells without exposing the cells to animal products. Further disclosed are new primate pluripotent cell lines made using the defined culture conditions, including the medium and the matrix. Such new cell lines will have never been exposed to animal cells, animal products, feeder cells or conditioned medium. | 2013-09-12 |
20130236963 | Cells Useful for Immuno-Based Botulinum Toxin Serotype A Activity Assays - The present specification discloses clonal cell lines susceptible to BoNT/A intoxication, methods of producing such clonal cell lines, and methods of detecting Botulinum toxin serotype A activity using such clonal cell lines. | 2013-09-12 |
20130236964 | METHODS, NUCLEIC ACID CONSTRUCTS AND CELLS FOR TREATING NEURODEGENERATIVE DISORDERS - A method of treating a neurodegenerative disorder is provided. The method is effected by administering to an individual in need thereof cells capable of exogenously regulatable neurotransmitter synthesis thereby treating the neurodegenerative disorder. | 2013-09-12 |
20130236965 | METHOD FOR ENZYMATIC TREATMENT, DEVICE AND KIT USED THE SAME - One embodiment provides a method for enzymatic treatment, including the steps of forming a closed space on a local tissue area with a device and infusing an enzyme solution into the closed space for enzymatic treatment. The method according to the embodiment is capable of treating the local tissue area with enzymes for enhancing cell proliferation in the treated tissue area and preventing damage of the adjacent normal tissues. A device and kit used for the method are also provided. | 2013-09-12 |
20130236966 | NK-1 Receptor Mediated Delivery of Agents to Cells - Provided herein are conjugates including a targeting vehicle coupled to an agent. The targeting vehicle includes a tachykinin receptor ligand and a reactive moiety. Conjugates including a tachykinin receptor ligand attached to an antibody or fragment thereof that is specific for an intracellular target are also provided. Also provided are methods of delivering agents to cells expressing tachykinin receptors, methods of delivering antibodies or fragments thereof to an intracellular extra-endosomal target, and methods of arresting cell growth or introducing cell death of a cancer cell. | 2013-09-12 |
20130236967 | Modifications for Antisense Compounds - The invention pertains to modifications for antisense oligonucleotides, wherein the modifications are used to improve stability and provide protection from nuclease degradation. The modifications could also be incorporated into double-stranded nucleic acids, such as synthetic siRNAs and miRNAs. | 2013-09-12 |
20130236968 | MULTIFUNCTIONAL COPOLYMERS FOR NUCLEIC ACID DELIVERY - The present invention relates to multifunctional polymers represented by the following formula: | 2013-09-12 |
20130236969 | Use of Compounds for Inducing Differentiation of Mesenchymal Stem Cells to Chondrocytes - Use of a compound of Formula 1 for inducing differentiation of mesenchymal stem cells to chondrocytes, and a pharmaceutical composition for treating a cartilage disease, which includes chondrocytes in which differentiation from mesenchymal stem cells is induced by the compound of Formula 1, are provided. Differentiation of the mesenchymal stem cells treated with the compound of Formula 1 to chondrocytes is specifically induced, and thus the compound can be used to effectively treat a cartilage disease such as arthritis, cartilage damage, and a cartilage defect. | 2013-09-12 |
20130236970 | METHOD FOR CELL EXPANSION - The present invention relates to a method for cell expansion. More closely, it relates to a method for expansion of cells, such as mesenchymal stem cells, on microcarriers in a plastic bag bioreactor. The invention enables expansion to therapeutic amounts of stem cells. The method comprises the following steps: a) addition of cells in cell culture medium and microcarriers to a plastic bag container; b) allowing the cells to adhere to the microcarriers while the container is kept substantially still; c) addition of further cell culture medium once the cells have adhered; d) culturing the cells under gentle and constant agitation; e) increase the surface area for continued culturing; and f) final harvesting of cells by an active detachment and separation step. | 2013-09-12 |
20130236971 | HYDROGEL SCAFFOLDS FOR TISSUE ENGINEERING - Disclosed herein are biodegradable hydrogel scaffolds for use in tissue engineering. The hydrogel scaffolds are composed of synthetic terpolymers complexed with polyvinyl alcohol (PVA), which facilitate cell-sheet and tissue growth. In the presence of a monosaccharide, the PVA-hydrogel is dissolved and cell-sheets are released for harvesting. Further disclosed herein are methods for producing PVA hydrogels which support tissue growth. Tissue engineering applications and methods are also disclosed. | 2013-09-12 |
20130236972 | Liver Sinusoid Model - A liver sinusoid model includes a generally planar substrate having first and second generally parallel microchannels formed therein. A microporous membrane is disposed between and separating the first and second generally parallel microchannels. A first layer of cells lines one side of the membrane in the first microchannel. The first layer of cells are all a first common cell type. A second layer of cells extends parallel to the first layer of cells in one of the first microchannel and the second microchannel. The second layer of cells is all of a second common cell type. A liver sinusoid bioreactor utilizing the inventive model is also disclosed. | 2013-09-12 |
20130236973 | Defined Media for Expansion and Maintenance of Pluripotent Stem Cells - The present invention provides methods to promote the proliferation of undifferentiated pluripotent stem cells in defined media. Specifically, the invention provides a defined cell culture formulation for the culture, maintenance, and expansion of pluripotent stem cells, wherein culturing stem cells in the defined cell culture formulation maintains the pluripotency and karyotypic stability of the cells for at least 10 passages. Further disclosed is a cell population grown under defined media conditions that express OCT4, SOX2, NANOG, and FOXA2. | 2013-09-12 |
20130236974 | METHOD FOR INCREASING THE PRODUCTION OF A PROTEIN OF INTEREST - The present disclosure provides, inter alia, formulation compositions comprising modified nucleic acid molecules which may encode a protein, a protein precursor, or a partially or fully processed form of the protein or a protein precursor. The formulation composition may further include a modified nucleic acid molecule and a delivery agent. The present invention further provides nucleic acids useful for encoding polypeptides capable of modulating a cell's function and/or activity. | 2013-09-12 |
20130236975 | TRACKING OF THE RATE OF CORROSION OF A METAL CONDUIT TRAVERSED BY A CORROSIVE FLUID - A method of tracking the rate of corrosion of a metal conduit traversed by a corrosive fluid, in which is provided a device arranged so as to form, when said device is installed on a wall of the metal conduit, a chamber able to receive gaseous hydrogen issuing by permeation across said wall of said conduit, the method comprising: (i) a step of treatment to eliminate a metallic species from the chamber, (ii) a step of measuring a quantity of hydrogen received in the chamber, with a view to estimating the rate of corrosion of the metal conduit. | 2013-09-12 |
20130236976 | DETERMINATION OF SULPHUR DIOXIDE IN A LIQUID - A system for the measurement of free and bound SO2 in a liquid beverage product sample comprising a sample container having a volume sufficient to provide a headspace above the sample into which a gas can pass; a gas flow system adapted to extract gas from the headspace and recirculating it back into the liquid volume; a measurement system configured to monitor a time dependent evolution of SO2 in gas from the gas flow system; and a dosing apparatus fluidly connected to the container to supply an hydrolysis reagent thereto. A heater unit is provided for supplying thermal radiation into the container to elevate the temperature of sample therein sufficient to facilitate the hydrolysis reaction and a signal processor operates to deconvolute the monitored evolution to generate an indication of the concentration of each of the free SO2 and the total SO2 content of the sample. | 2013-09-12 |
20130236977 | COMPOSITIONS AND METHODS FOR PLASMA PEPTIDE ANALYSIS - Provided herein are composition, methods and kits for peptide analysis in blood by mass spectroscopy. Isotopic peptides are also provided that facilitate quantification of peptide levels, e.g., hepcidin levels, in blood by mass spectroscopy. Further disclosed are methods and compositions for quantifying blood hepcidin levels and evaluating iron-associated disorders. | 2013-09-12 |
20130236978 | Methods and Compositions for Biomarkers of Fatigue, Fitness and Physical Performance Capacity - The present invention provides methods and compositions for identifying a subject in a fatigued state, a subject recovering from a fatigued state and/or a subject having an increased likelihood of performing a physical activity at a sufficient level by detecting and/or quantitating, in a sample from the subject, one or more biomarkers associated with fatigue and/or physical performance capability. | 2013-09-12 |
20130236979 | METHODS FOR DETECTING VITAMIN D METABOLITES BY MASS SPECTROMETRY - Provided are methods of detecting the presence or amount of a vitamin D metabolite in a sample using mass spectrometry. The methods generally comprise ionizing a vitamin D metabolite in a sample and detecting the amount of the ion to determine the presence or amount of the vitamin D metabolite in the sample. Also provided are methods to detect the presence or amount of two or more vitamin D metabolites in a single assay. | 2013-09-12 |
20130236980 | Methods, Devices, Systems and Compositions for Detecting Gases - A method of monitoring a respiratory stream can be provided by monitoring color change of a color change material to determine a CO2 level of the respiratory stream in contact with the color change material by emitting visible light onto the color change material. Related devices, systems, and compositions are also disclosed. | 2013-09-12 |
20130236981 | Detection Of Chronic Kidney Disease And Disease Progression - The present invention provides a sensor or a system comprising gold nanoparticles coated with specific organic coatings for diagnosing, staging or monitoring chronic kidney disease. | 2013-09-12 |
20130236982 | LUMINESCENCE BASED SENSOR - A sensor comprising a substrate ( | 2013-09-12 |
20130236983 | Oilfield Chemicals with Attached Spin Probes - Detecting a spin probe in an oilfield fluid may indicate or determine the amount of the particular chemicals within an oilfield fluid. The detection of the spin probe may also indicate at least one property of the oilfield fluid, such as but not limited to pH, dielectric constant, rotational freedom of the spin probe, at least one chemical, the concentration of at least one chemical, residue of at least one chemical in the fluid, the speciation of coupled chemistry between the spin probe and the chemical, and combinations thereof. In one non-limiting embodiment, the spin probe may be attached to at least one chemical. The oilfield fluid may be or include, but is not limited to, a drilling fluid, a completion fluid, a production fluid, a servicing fluid, and combinations thereof. | 2013-09-12 |
20130236984 | METHOD FOR CONCENTRATION OF LOW-MOLECULAR-WEIGHT PROTEINS AND PEPTIDES IN BODY FLUID SAMPLE - (Problem to be Solved) There is to be provided a method for extracting low-molecular-weight proteins/peptides contained in a body fluid sample, particularly, in serum or plasma. | 2013-09-12 |
20130236985 | METHOD AND DEVICE FOR OPTICAL EXAMINATION - A method and a device for the optical examination of a surface region are proposed. Fluorescence measurement is used to determine the amount of a substance bound to the surface region. Light interference is shut out thanks to the surface region being covered with an optically active liquid which filters, reflects, scatters and/or absorbs light with a wavelength at least substantially corresponding to the light radiated in and/or out. | 2013-09-12 |
20130236986 | METHODS OF SEPARATING NUCLEIC ACID POLYMER CONJUGATES - Described herein are nucleic acid-polymer conjugates and methods of separating these conjugates from a mixture, such as a reaction mixture. | 2013-09-12 |
20130236987 | SYSTEM, METHOD AND APPARATUS FOR MASK STRUCTURE FOR PATTERNING A WORKPIECE BY IONS - A method of fabricating workpieces includes one or more layers on a substrate that are masked with an ion implantation mask comprising two or more layers. The mask layers include a first mask layer closer to the substrate, and a second mask layer on the first mask layer. The method also comprises ion implanting one or more of the layers on the substrate. Ion implantation may form portions with altered physical properties from the layers under the mask. The portions may form a plurality of non-magnetic regions corresponding to apertures in the mask. | 2013-09-12 |
20130236988 | METHODS AND STRUCTURES OF INTEGRATED MEMS-CMOS DEVICES - A method for fabricating an integrated MEMS-CMOS device uses a micro-fabrication process that realizes moving mechanical structures (MEMS) on top of a conventional CMOS structure by bonding a mechanical structural wafer on top of the CMOS and etching the mechanical layer using plasma etching processes, such as Deep Reactive Ion Etching (DRIE). During etching of the mechanical layer, CMOS devices that are directly connected to the mechanical layer are exposed to plasma. This sometimes causes permanent damage to CMOS circuits and is termed Plasma Induced Damage (PID). Embodiments of the present invention presents methods and structures to prevent or reduce this PID and protect the underlying CMOS circuits by grounding and providing an alternate path for the CMOS circuits until the MEMS layer is completely etched. | 2013-09-12 |
20130236989 | SIDEWALL AND CHAMFER PROTECTION DURING HARD MASK REMOVAL FOR INTERCONNECT PATTERNING - A method for method for removing a hard mask is described. The method includes forming at least a portion of a trench-via structure in a low-k insulation layer on a substrate using one or more etching processes and a hard mask layer overlying the low-k insulation layer. Thereafter, the method includes depositing a SiOCl-containing layer on exposed surfaces of the trench-via structure to form an insulation protection layer, performing one or more etching processes to anisotropically remove at least a portion of the SiOCl-containing layer from at least one surface on the trench-via structure, and removing the hard mask layer using a mask removal etching process. | 2013-09-12 |
20130236990 | COATING APPARATUS AND MANUFACTURING METHOD OF COATED BODY - According to one embodiment, a coating apparatus includes a stage having a mounting surface on which a coating target is mounted, a rotating mechanism that rotates the stage, a coating nozzle that discharges a coating material, a moving mechanism that moves the coating nozzle, a supply device that supplies a material to the coating nozzle, an ejection device that ejects the material, a communication tube that allows the supply device, and a valve device. Further, the coating apparatus includes a control unit which rotates the stage by the rotating mechanism, switches the valve device to achieve the continuity of the supply unit and the coating nozzle, drives the moving mechanism to move the coating nozzle, and applies the coating material to the coating target on the stage. | 2013-09-12 |
20130236991 | RESIN COATING DEVICE AND A RESIN COATING METHOD - In a resin coating which is used in the manufacture of an LED package which is made by covering an LED element with resin that includes fluorescent substance, a light-passing member ( | 2013-09-12 |
20130236992 | TESTING METHOD, TESTING DEVICE, AND MANUFACTURING METHOD FOR LASER DIODE - In a testing method for an LD, an LD die is held. Then, electric current increasing with a fixed increment and having a sequence of current values is supplied to the LD die to drive the LD die to emit light and a sequence of voltage values across the LD die and corresponding to the sequence of current values, respectively, is metered. A sequence of power values corresponding to the sequence of current values, respectively, is also metered. Next, an electro-optical property of the LD die is determined according to the sequence of current values, the sequence of voltage values, and the sequence of power values. Finally, if the LD die is determined to be qualified based upon the electro-optical property of the LD die, the LD die is packaged into the LD. | 2013-09-12 |
20130236993 | METHOD OF FABRICATING SEMICONDUCTOR PACKAGE - A stacked semiconductor package having a unit package, cover substrates, adhesive members and connection electrodes is presented. The unit package includes a substrate, a first circuit pattern and a second circuit pattern. The first circuit pattern is disposed over an upper face of the substrate. The second circuit pattern is disposed over a lower face of the substrate. The lower and upper faces of the substrate oppose each other. The first and second semiconductor chips are respectively electrically connected to the first and second circuit patterns. The cover substrates are opposed to the first semiconductor chip and the second semiconductor chip. The adhesive members are respectively interposed between the unit package and the cover substrates. The connection electrodes pass through the unit package, the cover substrates and the adhesive members and are electrically connected to the first and second circuit patterns. | 2013-09-12 |
20130236994 | Non-Uniform Alignment of Wafer Bumps with Substrate Solders - An integrated circuit structure includes a work piece selected from the group consisting of a semiconductor chip and a package substrate. The work piece includes a plurality of under bump metallurgies (UBMs) distributed on a major surface of the work piece; and a plurality of metal bumps, with each of the plurality of metal bumps directly over, and electrically connected to, one of the plurality of UBMs. The plurality of UBMs and the plurality of metal bumps are allocated with an overlay offset, with at least some of the plurality of UBMs being misaligned with the respective overlying ones of the plurality of metal bumps. | 2013-09-12 |
20130236995 | ELECTRONIC APPARATUS HAVING AN ENCAPSULATING LAYER WITHIN AND OUTSIDE OF A MOLDED FRAME OVERLYING A CONNECTION ARRANGEMENT ON A CIRCUIT BOARD - In an electronic apparatus comprising a circuit board supporting semiconductor components and traces or conductors for supplying electrical energy to the semiconductor components, and a connection arrangement by which the conductors are connected to a power supply cable, the circuit board being covered by an electrically insulating encapsulating layer, a molded frame part is mounted on the circuit board so as to cover the connection arrangement, the molded frame part having a circumferential edge structure which extends on one end into the encapsulating layer and at the other end projects above the encapsulating layer so as to create an interior space which, when the encapsulating layer is at least partially cured, is filled with additional encapsulating compound to form, after curing, a relatively thick protective layer over the wire or cable and conductor connecting area. | 2013-09-12 |
20130236996 | METHOD FOR MANUFACTURING LED PACKAGE STRUTURE AND METHOD FOR MANUFACTURING LEDS USING THE LED PACKANGE STRUTURE - A method for manufacturing an LED package structure is disclosed wherein a substrate with a first electrode, a second electrode and a connecting layer is provided. A photoresist coating is provided to cover the substrate, the first electrode, the second electrode and the connecting layer. A portion of the photoresist coating is removed to define a groove corresponding to the connecting layer. A metal layer is formed in the groove to join the connecting layer. A remaining portion of the photoresist coating is removed and a concave is formed and surrounded by the metal layer. A reflective layer is formed on an inside surface of the concave to join the metal layer to form a reflective cup. An LED die is mounted in the reflective cup and electrically connects with the first and second electrodes. | 2013-09-12 |
20130236997 | METHOD OF FABRICATING LIGHT EMITTING DEVICE - A light emitting device and a method for fabricating the same are provided. The method includes: forming a plurality of light emitting laminates in which a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer are sequentially laminated on a growth substrate; mounting the growth substrate on a substrate including a plurality of terminal units each including a pair of electrode terminals; electrically connecting the second conductivity-type semiconductor layer of each of the light emitting laminates to a first electrode terminal of a corresponding terminal unit; removing the growth substrate to expose the first conductivity-type semiconductor layer; forming an insulating layer on a lateral surface of each of the plurality of light emitting laminates; and electrically connecting the exposed first conductivity-type semiconductor layer of each of the light emitting laminates to a second electrode terminal of the corresponding terminal unit. | 2013-09-12 |
20130236998 | Method for Manufacturing Array Substrate of Transflective Liquid Crystal Display - A method for manufacturing an array substrate of a transflective LCD includes: ( | 2013-09-12 |
20130236999 | METHOD FOR FORMING A MULTICOLOR OLED DEVICE - A method is provided for forming a multi-color OLED device that includes providing a substrate, coating the substrate with a fluorinated photoresist solution to form a first photo-patternable layer and exposing it to produce a first pattern of exposed fluorinated photoresist material and a second pattern of unexposed fluorinated photoresist material, developing the photo-patternable layer with a fluorinated solvent to remove the second pattern of unexposed fluorinated photoresist material without removing the first pattern of exposed fluorinated photoresist material, depositing a first organic light-emitting material over the substrate to form a first organic light-emitting layer for emitting a first color of light and applying the first pattern of exposed fluorinated photoresist material to control the removal of a portion of the first organic light-emitting layer. A second fluorinated photoresist solution is then coated over the first patterened organic light-emitting layer and exposed to form a third pattern of exposed fluorinated photoresist material having a pattern different from the first pattern and a fourth pattern of unexposed fluorinated photoresist material, and developing the photo-patternable layer in a fluorinated solvent to remove the fourth pattern of unexposed fluorinated photoresist material without removing the third pattern of exposed fluorinated photoresist material, depositing at least a second light-emitting material to form a second light-emitting layer for emitting a second color of light that is different than the first color of light and applying the third pattern of exposed fluorinated photoresist material to control the removal of a portion of the second organic light-emitting layer. | 2013-09-12 |
20130237000 | METHOD OF MANUFACTURING SOLAR CELL MODULE - An aspect of the invention is a method of manufacturing a solar cell module in which wiring members are electrically connected to front and back electrodes on front and back sides of a solar cell with resin adhesion films. The total area of the front electrode is smaller than that of the back electrode. The method includes: arranging the resin adhesion films on the front and back electrodes; arranging a first cushion sheet and a lower press member below the lower resin adhesion film and arranging a second cushion sheet being thicker than the first cushion sheet and an upper press member above the upper resin adhesion film; pressing the press members against each other thereby bonding the resin adhesion films to the solar cell; and releasing the pressure to the press members and moving the first and second cushion sheets away from the solar cell. | 2013-09-12 |
20130237001 | METHODS OF PREPARING FLEXIBLE PHOTOVOLTAIC DEVICES USING EPITAXIAL LIFTOFF, AND PRESERVING THE INTEGRITY OF GROWTH SUBSTRATES USED IN EPITAXIAL GROWTH - There is disclosed methods of making photosensitive devices, such as flexible photovoltaic (PV) devices, through the use of epitaxial liftoff. Also described herein are methods of preparing flexible PV devices comprising a structure having a growth substrate, wherein the selective etching of protective layers yields a smooth growth substrate that us suitable for reuse. | 2013-09-12 |
20130237002 | METHOD AND APPARATUS PROVIDING COMBINED SPACER AND OPTICAL LENS ELEMENT - A method and apparatus used for forming a lens and spacer combination, and imager module employing the spacer and lens combination. The apparatus includes a mold having a base, spacer section, and mold feature. The method includes using the mold with a blank to create a spacer that includes an integral lens. The spacer and lens combination and imager modules can be formed on a wafer level. | 2013-09-12 |
20130237003 | DIRECT READOUT FOCAL PLANE ARRAY - An image detector comprises a plurality of photosensitive detector unit cells interconnected to a plurality of integrated circuits by a plurality of direct bond interconnects. Each unit cell includes an absorber layer and a separation layer. The absorber layer absorbs incident photons such that the absorbed photons excite photocurrent comprising first charged carriers and second charged carriers having opposite polarities. The separation layer separates the first charged carriers for collection at one or more first contacts and the second charged carriers for collection at one or more second contacts. The first and second contacts include the direct bond interconnects to conduct the first charged carriers and the second charged carriers from the unit cells in order to facilitate image processing. | 2013-09-12 |
20130237004 | Backside Illuminated Image Sensor - A backside illuminated image sensor includes a substrate, a backside passivation layer disposed on backside of the substrate, and a transparent conductive layer disposed on the backside passivation layer. | 2013-09-12 |
20130237005 | METHOD FOR FABRICATING SEMICONDUCTOR LAYER HAVING TEXTURED SURFACE AND METHOD FOR FABRICATING SOLAR CELL - The disclosure provides a method for fabricating a semiconductor layer having a textured surface, including: (a) providing a textured substrate; (b) forming at least one semiconductor layer on the textured substrate; (c) forming a metal layer on the semiconductor layer; and (d) conducting a thermal process or a low temperature process to the textured substrate, the semiconductor layer and the metal layer, wherein the semiconductor layer is separated from the textured substrate by the thermal process to obtain the semiconductor layer having the metal layer and a textured surface. | 2013-09-12 |
20130237006 | DYE-SENSITIZED SOLAR CELL AND METHOD OF FABRICATING THE SAME - Provided are a dye-sensitized solar cell and a method of fabricating the same. The dye-sensitized solar cell includes an electrode structure including a conductive layer having pores that are regularly arranged, a semiconductor oxide layer disposed on a surface of the conductive layer, and a dye layer disposed on a surface of the semiconductor oxide layer. | 2013-09-12 |
20130237007 | TRENCH PROCESS AND STRUCTURE FOR BACKSIDE CONTACT SOLAR CELLS WITH POLYSILICON DOPED REGIONS - A solar cell includes polysilicon P-type and N-type doped regions on a backside of a substrate, such as a silicon wafer. An interrupted trench structure separates the P-type doped region from the N-type doped region in some locations but allows the P-type doped region and the N-type doped region to touch in other locations. Each of the P-type and N-type doped regions may be formed over a thin dielectric layer. Among other advantages, the resulting solar cell structure allows for increased efficiency while having a relatively low reverse breakdown voltage. | 2013-09-12 |
20130237008 | METHOD FOR MANUFACTURING NONVOLATILE MEMORY DEVICE - According to one embodiment, a method is disclosed for manufacturing a nonvolatile memory device. The nonvolatile memory device includes a memory cell connected to a first interconnect and a second interconnect. The method can include forming a first electrode film on the first interconnect. The method can include forming a layer including a plurality of carbon nanotubes dispersed inside an insulator on the first electrode film. At least one carbon nanotube of the plurality of carbon nanotubes is exposed from a surface of the insulator. The method can include forming a second electrode film on the layer. In addition, the method can include forming a second interconnect on the second electrode film. | 2013-09-12 |
20130237009 | METHOD FOR MANUFACTURING A GATE-CONTROL DIODE SEMICONDUCTOR DEVICE - The present invention belongs to the technical field of semiconductor device manufacturing, and specifically relates to a method for manufacturing a gate-control diode semiconductor device. The present invention manufactures gate-control diode semiconductor devices through a low-temperature process, features a simple process, low manufacturing cost, and capacity of manufacturing gate-control diode devices able to reduce the chip power consumption through advantages of high driving current and small sub-threshold swing. The method for manufacturing a gate-control diode semiconductor device proposed by the present invention is especially applicable to the manufacturing of reading & writing devices having flat panel displays and phase change memory, and semiconductor devices based on flexible substrates. | 2013-09-12 |
20130237010 | METHOD FOR MANUFACTURING A GATE-CONTROL DIODE SEMICONDUCTOR MEMORY DEVICE - The present invention belongs to the technical field of semiconductor device manufacturing, and specifically discloses a method for manufacturing a gate-control diode semiconductor storage device. The present invention manufactures gate-control diode semiconductor memory devices through a low-temperature process featuring a simple process, low manufacturing cost and capacity of manufacturing gate-control diode memory devices with a high driving current and small sub-threshold swing. The method for manufacturing a gate-control diode semiconductor memory device proposed by the present invention is especially applicable to the manufacturing of flat panel displays and phase change memories and memory devices based on flexible substrate. | 2013-09-12 |
20130237011 | COMPOSITION FOR OXIDE SEMICONDUCTOR AND METHOD OF MANUFACTURING A THIN FILM TRANSISTOR SUBSTRATE USING THE SAME - A method of manufacturing a thin-film transistor substrate includes: applying a composition on a substrate to form a thin-film on the substrate, heating the thin-film, and patterning the thin-film to form an oxide semiconductor pattern. The composition includes a metal nitrate and water. The potential of hydrogen (pH) of the composition is about 1 to about 4. | 2013-09-12 |
20130237012 | METHOD OF FABRICATING A THIN-FILM DEVICE - A method of forming a thin-film device includes forming an oxide-semiconductor film formed on the first electrical insulator, and forming a second electrical insulator formed on the oxide-semiconductor film, the oxide-semiconductor film defining an active layer. The oxide-semiconductor film is comprised of a first interface layer located at an interface with the first electrical insulating insulator, a second interface layer located at an interface with the second electrical insulator, and a bulk layer other than the first and second interface layers. The method further includes oxidizing the oxide-semiconductor film to render a density of oxygen holes in at least one of the first and second interlayer layers is smaller than a density of oxygen holes in the bulk layer. | 2013-09-12 |
20130237013 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A manufacturing method of a semiconductor device, which includes the steps of forming a gate electrode layer over a substrate having an insulating surface, forming a gate insulating layer over the gate electrode layer, forming an oxide semiconductor layer over the gate insulating layer, forming a source electrode layer and a drain electrode layer over the oxide semiconductor layer, forming an insulating layer including oxygen over the oxide semiconductor layer, the source electrode layer, and the drain electrode layer, and after formation of an insulating layer including hydrogen over the insulating layer including oxygen, performing heat treatment so that hydrogen in the insulating layer including hydrogen is supplied to at least the oxide semiconductor layer. | 2013-09-12 |
20130237014 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Disclosed is a technique in which an excessive resin can be stably cut and removed in a molding step. In a step for separating part of a runner leading to a resin-sealing body from the resin-sealing body, the runner is formed by a first runner and a second runner coupled to the first runner and the resin-sealing body. The runner is separated from a middle of the second runner by supporting, with a first supporting portion, the second runner from the side of the second surface of a lead frame, and by pushing down, with a break pin, the first runner in the direction from the side of the first surface of the lead frame toward the side of the second surface thereof, while the resin-sealing body is in a condition of floating in the air. | 2013-09-12 |
20130237015 | MICROFABRICATED PILLAR FINS FOR THERMAL MANAGEMENT - An electrical package with improved thermal management. The electrical package includes a die having an exposed back surface. The package further includes a plurality of fins extending outwardly from the back surface for dissipating heat from the package. The die can be arranged in a multi-die stacking configuration. In another embodiment, a method of forming a die for improved thermal management of an electrical package is provided. | 2013-09-12 |
20130237016 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device and manufacturing method are disclosed which prevent breakage and chipping of a semiconductor chip and improve device characteristics. A separation layer is in a side surface of an element end portion of the chip. An eave portion is formed by a depressed portion in the element end portion. A collector layer on the rear surface of the chip extends to a side wall and bottom surface of the depressed portion, and is connected to the separation layer. A collector electrode is over the whole surface of the collector layer, and is on the side wall of the depressed portion. The thickness of an outermost electrode film is 0.05 μm or less. The collector electrode on the rear surface of the chip is joined onto an insulating substrate via a solder layer, which covers the collector electrode on a flat portion of the rear surface of the semiconductor chip. | 2013-09-12 |
20130237017 | PRESSURE-SENSITIVE ADHESIVE TAPE FOR RESIN ENCAPSULATION AND METHOD FOR PRODUCING RESIN ENCAPSULATION TYPE SEMICONDUCTOR DEVICE - The present invention provides a pressure-sensitive adhesive tape for resin encapsulation in production of a resin encapsulation type semiconductor device, which includes a base material layer which does not have a glass transition temperature in a temperature region of 260° C. or lower and a pressure-sensitive adhesive layer laminated on the base material layer, and a method for producing a resin encapsulation type semiconductor device using the pressure-sensitive adhesive tape. The pressure-sensitive adhesive tape according to the present invention highly prevents resin leakage even under severe conditions as in MAP-QFN production process, does not affect certainty of wire bonding and has excellent peelability after resin encapsulation. | 2013-09-12 |
20130237018 | ADHESIVE FOR ELECTRONIC COMPONENTS, AND MANUFACTURING METHOD FOR SEMICONDUCTOR CHIP MOUNT - An object of the present invention is to provide an adhesive for electronic components that allows suppression of occurrence of voids and is prevented from wicking up to an upper surface of a semiconductor chip. Another object of the present invention is to provide a production method for a semiconductor chip mount using the adhesive for electronic components. The present invention is an adhesive for electronic components, including a curable compound, a curing agent, and an inorganic filler, wherein A1 and A2/A1 fall within a range surrounded by solid lines and a dashed line in FIG. | 2013-09-12 |
20130237019 | STACKED MEMORY DEVICE AND METHOD OF FABRICATING SAME - A stacked semiconductor memory device comprises a semiconductor substrate having a functional circuit, a plurality of memory cell array layers, and at least one connection layer. The memory cell array layers are stacked above the semiconductor substrate. The connection layers are stacked above the semiconductor substrate independent of the memory cell array layers. The connection layers electrically connect memory cell selecting lines arranged on the memory cell array layers to the functional circuit. | 2013-09-12 |
20130237020 | THIN FILM TRANSISTOR STRUCTURE, METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC DEVICE - A high-performance thin film transistor structure which is easily manufactured is provided. The thin film transistor structure includes: a first electrode; second and third electrodes apart from each other in a hierarchical level different from that of the first electrode; first, second, and third wirings connected to the first, second, and third electrodes, respectively; a main stack body disposed so as to be opposed to the first electrode with an interlayer insulating layer in between, between the first electrode, and the second and third electrodes; and a sub stack body including an insulating layer and a semiconductor layer, disposed so as to be opposed to the first wiring with the interlayer insulating layer in between, between the first and second wirings in a position where the first and second wirings overlap and/or between the first and third wirings in a position where the first and third wirings overlap. | 2013-09-12 |
20130237021 | ENHANCEMENT MODE FIELD EFFECT DEVICE AND THE METHOD OF PRODUCTION THEREOF - A method is disclosed for producing Group III-N field-effect devices, such as HEMT, MOSHFET, MISHFET or MESFET devices, comprising two active layers, e.g. a GaN/AlGaN layer. The method produces an enhancement mode device of this type, i.e. a normally-off device, by providing a passivation layer on the AlGaN layer, etching a hole in the passivation layer and not in the layers underlying the passivation layer, and depositing the gate contact in the hole, while the source and drain are deposited directly on the passivation layer. The characteristics of the active layers and/or of the gate are chosen such that no two-dimensional electron gas layer is present underneath the gate, when a zero voltage is applied to the gate. A device with this behavior is also disclosed. | 2013-09-12 |
20130237022 | METHOD AND APPARATUS FOR PROTECTION AGAINST PROCESS-INDUCED CHARGING - A semiconductor device ( | 2013-09-12 |
20130237023 | Methods Of Forming A Vertical Transistor And At Least A Conductive Line Electrically Coupled Therewith - Trenches are formed into semiconductive material. Masking material is formed laterally over at least elevationally inner sidewall portions of the trenches. Conductivity modifying impurity is implanted through bases of the trenches into semiconductive material there-below. Such impurity is diffused into the masking material received laterally over the elevationally inner sidewall portions of the trenches and into semiconductive material received between the trenches below a mid-channel portion. An elevationally inner source/drain is formed in the semiconductive material below the mid-channel portion. The inner source/drain portion includes said semiconductive material between the trenches which has the impurity therein. A conductive line is formed laterally over and electrically coupled to at least one of opposing sides of the inner source/drain. A gate is formed elevationally outward of and spaced from the conductive line and laterally adjacent the mid-channel portion. Other embodiments are disclosed. | 2013-09-12 |
20130237024 | ULTRAHIGH DENSITY VERTICAL NAND MEMORY DEVICE AND METHOD OF MAKING THEREOF - Monolithic, three dimensional NAND strings include a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, the blocking dielectric comprising a plurality of blocking dielectric segments, a plurality of discrete charge storage segments, and a tunnel dielectric located between each one of the plurality of the discrete charge storage segments and the semiconductor channel. | 2013-09-12 |
20130237025 | METHOD FOR FABRICATING NON-VOLATILE MEMORY DEVICE - A method for fabricating a non-volatile memory device includes forming a stacked structure where a plurality of inter-layer dielectric layers and a plurality of second sacrificial layers are alternately stacked over the first gate electrode layer, forming a first channel hole that exposes the first sacrificial layer by penetrating through the stacked structure, forming a second channel hole by removing the exposed first sacrificial layer, forming an oxide layer by oxidizing a surface of the first gate electrode layer exposed through the first and second channel holes, forming a channel layer in the first and second channel holes, and forming second gate electrode layers in spaces from which the second sacrificial layers are removed, wherein a memory layer is interposed between the channel layer and the second gate electrode layer. | 2013-09-12 |
20130237026 | FINFET DEVICE HAVING A STRAINED REGION - A method of fabricating a semiconductor device includes providing a substrate having a fin disposed thereon. A gate structure is formed on the fin. The gate structure interfaces at least two sides of the fin. A stress film is formed on the substrate including on the fin. The substrate including the stress film is annealed. The annealing provides a tensile strain in a channel region of the fin. For example, a compressive strain in the stress film may be transferred to form a tensile stress in the channel region of the fin. | 2013-09-12 |
20130237027 | HIGH VOLTAGE DEVICE AND METHOD FOR FABRICATING THE SAME - A high voltage device includes drift regions formed in a substrate, an isolation layer formed in the substrate to isolate neighboring drift regions, wherein the isolation layer has a depth greater than that of the drift region, a gate electrode formed over the substrate, and source and drain regions formed in the drift regions on both sides of the gate electrode. | 2013-09-12 |
20130237028 | METHOD OF FABRICATING SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a method of fabricating a semiconductor memory device includes patterning a first memory cell layer and a first interconnect layer to form a first structure of a linear pattern in a first region and a second structure in a second region, forming a second interconnect layer and a second memory cell layer, and patterning the second memory cell layer and the second interconnect layer to form, in the first region, a third structure having a linear pattern and having a folded pattern immediately on the second structure. The method further includes removing the second memory cell layer and the second interconnect layer in the folded pattern, and the first memory cell layer of the second structure positioned under the folded pattern. | 2013-09-12 |
20130237029 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a non-volatile semiconductor memory device includes: a semiconductor substrate; a plurality of first lines; a plurality of second lines; and a plurality of non-volatile memory cells arranged at positions where the plurality of first lines intersect with the plurality of second lines, wherein each of the plurality of non-volatile memory cells includes a resistance change element and a rectifying element connected in series to the resistance change element, and a resistance change film continuously extending over the plurality of second lines is arranged between the plurality of first lines and the plurality of second lines, and the resistance change element includes a portion where the first line intersect with the second line in the resistance change film. | 2013-09-12 |
20130237030 | METAL-INSULATOR-METAL (MIM) DEVICE AND METHOD OF FORMATION THEREOF - In a method of fabricating a metal-insulator-metal (MIM) device, initially, a first electrode is provided. An oxide layer is provided on the first electrode, and a protective layer is provided on the oxide layer. An opening through the protective layer is provided to expose a portion of the oxide layer, and a portion of the first electrode underlying the exposed portion of the oxide layer is oxidized. A second electrode is provided in contact with the exposed portion of the oxide layer. In alternative embodiments, the initially provided oxide layer may be eliminated, and spacers of insulating material may be provided in the opening. | 2013-09-12 |
20130237031 | MEMORY DEVICES HAVING REDUCED INTERFERENCE BETWEEN FLOATING GATES AND METHODS OF FABRICATING SUCH DEVICES - A memory array comprising transistors having isolated inter-gate dielectric regions with respect to one another. Transistors are formed such that each of the transistors in the array has a charge storage region such as a floating gate, a control gate and an inter-gate dielectric layer therebetween. The inter-gate dielectric layer for each transistor is isolated from the inter-gate dielectric of each of the other transistors in the array. | 2013-09-12 |
20130237032 | Method of Manufacturing Silicon-On-Insulator Wafers - A method is provided for preparing multilayer semiconductor structures, such as silicon-on-insulator wafers, having reduced warp and bow. Reduced warp multilayer semiconductor structures are prepared by forming a dielectric structure on the exterior surfaces of a bonded pair of a semiconductor device substrate and a semiconductor handle substrate having an intervening dielectric layer therein. Forming a dielectric layer on the exterior surfaces of the bonded pair offsets stresses that may occur within the bulk of the semiconductor handle substrate due to thermal mismatch between the semiconductor material and the intervening dielectric layer as the structure cools from process temperatures to room temperatures. | 2013-09-12 |
20130237033 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device makes it possible to efficiently polish with a polishing tape a peripheral portion of a silicon substrate under polishing conditions particularly suited for a deposited film and for silicon underlying the deposited film. The method includes pressing a first polishing tape against a peripheral portion of a device substrate having a deposited film on a silicon surface while rotating the device substrate at a first rotational speed, thereby removing the deposited film lying in the peripheral portion of the device substrate and exposing the underlying silicon. A second polishing tape is pressed against the exposed silicon lying in the peripheral portion of the device substrate while rotating the device substrate at a second rotational speed, thereby polishing the silicon to a predetermined depth. | 2013-09-12 |
20130237034 | Glass Piece and Methods of Manufacturing Glass Pieces and Semiconductor Devices with Glass Pieces - A source material, which is based on a glass, is arranged on a working surface of a mold substrate. The mold substrate is made of a single-crystalline material. A cavity is formed in the working surface. The source material is pressed against the mold substrate. During pressing a temperature of the source material and a force exerted on the source material are controlled to fluidify source material. The fluidified source material flows into the cavity. Re-solidified source material forms a glass piece with a protrusion extending into the cavity. After re-solidifying, the glass piece may be bonded to the mold substrate. On the glass piece, protrusions and cavities can be formed with slope angles less than 80 degrees, with different slope angles, with different depths and widths of 10 micrometers and more. | 2013-09-12 |
20130237035 | METHOD AND APPARATUS FOR LASER SINGULATION OF BRITTLE MATERIALS - An improved method for singulation of electronic substrates into dice uses a laser to first form cuts in the substrate and then chamfers the edges of the cuts by altering the laser parameters. The chamfers increase die break strength by reducing the residual damage and removes debris caused by the initial laser cut without requiring additional process steps, additional equipment or consumable supplies. | 2013-09-12 |
20130237036 | METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR LAYER - According to one embodiment, a method for manufacturing a nitride semiconductor layer is disclosed. The method can include forming a first lower layer on a major surface of a substrate and forming a first upper layer on the first lower layer. The first lower layer has a first lattice spacing along a first axis parallel to the major surface. The first upper layer has a second lattice spacing along the first axis larger than the first lattice spacing. At least a part of the first upper layer has compressive strain. A ratio of a difference between the first and second lattice spacing to the first lattice spacing is not less than 0.005 and not more than 0.019. A growth rate of the first upper layer in a direction parallel to the major surface is larger than that in a direction perpendicular to the major surface. | 2013-09-12 |
20130237037 | CRYSTALLINE ALUMINUM CARBIDE THIN FILM, SEMICONDUCTOR SUBSTRATE HAVING THE ALUMINUM CARBIDE THIN FILM FORMED THEREON AND METHOD OF FABRICATING THE SAME - Embodiments of the invention provide a crystalline aluminum carbide thin film, a semiconductor substrate having the crystalline aluminum carbide thin film formed thereon, and a method of fabricating the same. Further, the method of fabricating the AlC thin film includes supplying a carbon containing gas and an aluminum containing gas to a furnace, to growing AlC crystals on a substrate. | 2013-09-12 |
20130237038 | TWO-STEP HYDROGEN ANNEALING PROCESS FOR CREATING UNIFORM NON-PLANAR SEMICONDUCTOR DEVICES AT AGGRESSIVE PITCH - A two-step hydrogen anneal process has been developed for use in fabricating semiconductor nanowires for use in non-planar semiconductor devices. In the first part of the two-step hydrogen anneal process, which occurs prior to suspending a semiconductor nanowire, the initial roughness of at least the sidewalls of the semiconductor nanowire is reduced, while having at least the bottommost surface of the nanowire pinned to an uppermost surface of a substrate. After performing the first hydrogen anneal, the semiconductor nanowire is suspended and then a second hydrogen anneal is performed which further reduces the roughness of all exposed surfaces of the semiconductor nanowire and reshapes the semiconductor nanowire. By breaking the anneal into two steps, smaller semiconductor nanowires at a tight pitch survive the process and yield. | 2013-09-12 |
20130237039 | TWO-STEP HYDROGEN ANNEALING PROCESS FOR CREATING UNIFORM NON-PLANAR SEMICONDUCTOR DEVICES AT AGGRESSIVE PITCH - A two-step hydrogen anneal process has been developed for use in fabricating semiconductor nanowires for use in non-planar semiconductor devices. In the first part of the two-step hydrogen anneal process, which occurs prior to suspending a semiconductor nanowire, the initial roughness of at least the sidewalls of the semiconductor nanowire is reduced, while having at least the bottommost surface of the nanowire pinned to an uppermost surface of a substrate. After performing the first hydrogen anneal, the semiconductor nanowire is suspended and then a second hydrogen anneal is performed which further reduces the roughness of all exposed surfaces of the semiconductor nanowire and reshapes the semiconductor nanowire. By breaking the anneal into two steps, smaller semiconductor nanowires at a tight pitch survive the process and yield. | 2013-09-12 |
20130237040 | RESIN COMPOSITION, LAMINATE AND PROCESS FOR PRODUCTION THEREOF, STRUCTURE AND PROCESS FOR PRODUCTION THEREOF, AND PROCESS FOR PRODUCTION OF ELECTRONIC DEVICE - The present invention relates to a resin composition containing: a polyimide silicone which has, in a silicone moiety therein, a crosslinking site at which a crosslinking reaction occurs upon heating at a second temperature, in which the crosslinking reaction proceeds by heating a third temperature that exceeds the second temperature further than the second temperature; and a solvent which vaporizes upon heating at a first temperature that is lower than the second temperature. | 2013-09-12 |
20130237041 | DEFECT CAPPING METHOD FOR REDUCED DEFECT DENSITY EPITAXIAL ARTICLES - A method for forming an epitaxial layer on a substrate surface having crystalline defect or amorphous regions and crystalline non-defect regions includes preferential polishing or etching the crystalline defect or amorphous regions relative to the crystalline non-defect regions to form a decorated substrate surface having surface recess regions. A capping layer is deposited on the decorated substrate surface to cover the crystalline non-defect regions and to at least partially fill the surface recess regions. The capping layer is patterned by removing the capping layer over the crystalline non-defect regions to form exposed non-defect regions while retaining the capping layer in at least a portion of the surface recess regions. Selective epitaxy is then used to form the epitaxial layer, wherein the capping layer in the surface recess regions restricts epitaxial growth of the epitaxial layer over the surface recess regions. | 2013-09-12 |
20130237042 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device of an embodiment includes: preparing a silicon carbide substrate of a hexagonal system; implanting ions into the silicon carbide substrate; forming, by epitaxial growth, a silicon carbide film on the silicon carbide substrate into which the ions have been implanted; and forming a pn junction region in the silicon carbide film. | 2013-09-12 |
20130237043 | SiC SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing an SiC semiconductor device according to the present invention includes the steps of (a) by using a single mask, etching regions of an SiC semiconductor layer which serve as an impurities implantation region and a mark region, to form recesses, (b) by using the same mask as in the step (a), performing ion-implantation in the recesses of the regions which serve as the impurities implantation region and the mark region, at least from an oblique direction relative to a surface of the SiC semiconductor layer and (c) positioning another mask based on the recess of the region which serves as the impurities implantation region or the mark region, and performing well implantation in a region containing the impurities implantation region. | 2013-09-12 |
20130237044 | METHOD OF MANUFACTURING METAL GATES - A method of manufacturing metal gates comprises the steps of: forming a plurality of parallel trenches on a substrate; forming sequentially a conductive layer and a protective layer on the surfaces of the substrate and trenches; removing the protective layer and conductive layer on the surface of the substrate and the protective layer on the bottom walls of the trenches through anisotropic etching to retain only the protective layer and conductive layer on the side walls; and finally removing the conductive layer not covered by the protective layer through isotropic etching to retain only the protective layer and conductive layer on the side walls so that two insulating gates are respectively formed on the side walls. Thus no isolation material is needed to be disposed at the bottom of the trenches, and the problem of excessive etching to the trenches that results in undesirable insulation can be averted. | 2013-09-12 |
20130237045 | METHODS OF FABRICATING SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICES FORMED THEREBY - A method of fabricating a semiconductor device comprises: forming an etch stop layer to cover sidewall and top surfaces of first and second dummy gate patterns on a substrate; and forming an interlayer insulating layer on the substrate and the etch stop layer. The interlayer insulating layer is planarized to expose the etch stop layer on the first and second dummy gate patterns, and the etch stop layer is etched to expose the top surfaces and upper sidewall surfaces of the first and second dummy gate patterns, thereby forming a groove between the interlayer insulating layer and the first and second dummy gate patterns. The dummy gate patterns are removed, and gate electrodes are formed in their places. | 2013-09-12 |
20130237046 | SEMICONDUCTOR PROCESS - A semiconductor process includes the following steps. A substrate having a first area and a second area is provided. A thick oxide layer and a dummy gate layer are formed on the substrate and in the first area and the second area. The dummy gate layer is removed to expose the thick oxide layer. The thick oxide layer in the first area is removed and then a thinner oxide layer is formed in the first area; or, the thick oxide layer in the first area is thinned down and a thinner oxide layer is therefore formed. | 2013-09-12 |
20130237047 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a nonvolatile semiconductor memory device includes a substrate, a stacked structural body, a semiconductor pillar, and a memory unit. The stacked structural body is provided on a major surface of the substrate. The stacked structural body includes electrode films alternately stacked with inter-electrode insulating films in a direction perpendicular to the major surface. The pillar pierces the body in the direction. The memory unit is provided at an intersection between the pillar and the electrode films. The electrode films include at least one of amorphous silicon and polysilicon. The stacked structural body includes first and second regions. A distance from the second region to the substrate is greater than a distance from the first region to the substrate. A concentration of an additive included in the electrode film in the first region is different from that included in the electrode film in the second region. | 2013-09-12 |
20130237048 | METHOD OF FABRICATING ERASABLE PROGRAMMABLE SINGLE-PLOY NONVOLATILE MEMORY - The present invention provides method of fabricating an erasable programmable single-poly nonvolatile memory, comprising steps of: defining a first area and a second area in a first type substrate; forming a second type well region in the first area; forming a first gate oxide layer and a second gate oxide layer covered on a surface of the first area, wherein the second gate oxide layer is extended to and is adjacent to the second area; forming a DDD region in the second area; etching a portion of the second gate oxide layer above the second area; forming two polysilicon gates covered on the first and the second gate oxide layers; and defining a second type doped region in the DDD region and a first type doped regions in the second type well region. | 2013-09-12 |
20130237049 | METHOD OF FABRICATING A PACKAGE SUBSTRATE - A method of fabricating a package substrate including preparing a substrate having at least one conductive pad, forming an insulating layer having an opening to expose the conductive pad on the substrate, forming a separation barrier layer on the conductive pad inside the opening to be higher than the upper surface of the insulating layer along the side walls thereof, forming a post terminal on the separation barrier layer, and forming a solder bump on the post terminal. | 2013-09-12 |
20130237050 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a method of manufacturing a semiconductor device, includes forming first layer on first and second regions in substrate, first layer having first width in first region and having larger dimension than first width in second region, forming first sidewall on first layer, forming second layer covering first sidewall in the second region and forming third layer having second width smaller than first width on the side face of first sidewall having second width after removing first layer, forming second and third sidewalls having second width so that second and third sidewalls is adjacent to first sidewall across third layer by second width in first region and across second and third layers by second interval larger than second width in the second region. | 2013-09-12 |
20130237051 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a method of manufacturing a device, includes forming a first core including a line portion extending between first and second regions and having a first width and a fringe having a dimension larger than the first width, forming a mask on the fringe and on a first sidewall on the first core, removing the first core so that a remaining portion having a dimension larger than the first width is formed below the mask, forming a second sidewall on a pattern corresponding the first sidewall and the remaining portion, the second sidewall having a second width less than the first width and facing a first interval less than the first width in the first region and facing a second interval larger than the first interval in the second region. | 2013-09-12 |
20130237052 | METHOD OF FABRICATING ARRAY SUBSTRATE FOR IN-PLANE SWITCHING MODE LIQUID CRYSTAL DISPLAY DEVICE - A method of fabricating an array substrate for an in-plane switching (IPS)-mode liquid crystal display (LCD) device, which includes a common electrode and a pixel electrode with a fine line width, are provided. The formation of the pixel electrode and the common electrode of the array substrate includes depositing two different metal layers and patterning the two different metal layers using a selective etching process. Thus, the pixel electrode and a central common electrode may be formed to have a fine line width so that the IPS-mode LCD device can have an improved aperture ratio. | 2013-09-12 |
20130237053 | FILM FORMING METHOD AND FILM FORMING APPARATUS - A film forming method which generates metal ions from a metal target with a plasma in a processing chamber and attracts the metal ions with a bias to deposit a metal thin film on a target object wherein trenches are formed. The method includes: generating metal ions from a target and attracting the metal ions into a target object with a bias to form a base film in a trench; ionizing a rare gas with the bias in a state where no metal ion is generated and attracting the generated ions into the target object to etch the base film; and plasma sputtering the target to generate metal ions and attracting the metal ions into the object with a high frequency power for bias to deposit a main film as a metal film, while reflowing the main film by heating. | 2013-09-12 |
20130237054 | THREE DIMENSIONAL INTEGRATION AND METHODS OF THROUGH SILICON VIA CREATION - A method includes patterning a photoresist layer on a structure to define an opening and expose a first planar area on a substrate layer, forming doped portions of the substrate layer in the first planar area, removing a portion of the photoresist to form a second opening defining a second planar area on the substrate layer, and etching to form a first cavity having a first depth defined by the first opening to expose a first contact in the structure and to form a second cavity defined by the second opening to expose a second contact in the structure. | 2013-09-12 |
20130237055 | METHOD OF REDISTRIBUTING FUNCTIONAL ELEMENT - According to a method of redistributing a functional element of the present invention, an insulating resin layer is supplied onto a functional element wafer such as an LSI. A portion to be a via hole on an electrode pad of the functional element is filled with a sacrificial layer. The top of the sacrificial layer filled in the via hole is exposed from the insulating layer by grinding or polishing. Therefore, it is possible to prevent breakage of a brittle material such as a low-k material in the functional element, which would be caused by transmission of shearing stress when a conventional pillar or a conventional gold projecting electrode is used. The reliability, the yield, and the level of flatness can be improved by forming an interconnection conductive layer after the flattening process of grinding or polishing. Accordingly, a fine conductive interconnection can be formed. | 2013-09-12 |
20130237056 | Semiconductor Processing Methods - Some embodiments include methods in which insulative material is simultaneously deposited across both a front side of a semiconductor substrate, and across a back side of the substrate. Subsequently, openings may be etched through the insulative material across the front side, and the substrate may then be dipped within a plating bath to grow conductive contact regions within the openings. The insulative material across the back side may protect the back side from being plated during the growth of the conductive contact regions over the front side. In some embodiments, plasma-enhanced atomic layer deposition may be utilized to for the deposition, and may be conducted at a temperature suitable to anneal passivation materials so that such annealing occurs simultaneously with the plasma-enhanced atomic layer deposition. | 2013-09-12 |
20130237057 | CONTACT ELEMENTS OF A SEMICONDUCTOR DEVICE FORMED BY ELECTROLESS PLATING AND EXCESS MATERIAL REMOVAL WITH REDUCED SHEER FORCES - The present disclosure is directed to, among other things, an illustrative method that includes forming an opening in a dielectric material of a contact level of a semiconductor device, and selectively depositing a conductive material in the opening to form a contact element therein, the contact element extending to a contact area of a circuit element and having a laterally restricted excess portion formed outside of the opening and above the dielectric material. The disclosed method further includes forming a sacrificial material layer above the dielectric material and the contact element, the sacrificial material layer surrounding the laterally restricted excess portion. Additionally, the method includes planarizing a surface topography of the contact level in the presence of the sacrificial material so as to remove the laterally restricted excess portion from above the dielectric material. | 2013-09-12 |