37th week of 2014 patent applcation highlights part 19 |
Patent application number | Title | Published |
20140252359 | Semiconductor Device and Method of Making - The present disclosure is related to semiconductor technologies and discloses a semiconductor device and its method of making. In the present disclosure, a transistor's source and drain are led out by forming vias or contact holes in an insulator layer covering the transistor and at metal silicide contact regions corresponding to the source and drain, and by filling the vias with metal-semiconductor compound. Because the metal-semiconductor compound has relatively low resistivity, the resistance of the material in the vias can be minimized. Also, because the material used to fill the vias and the material forming the source/drain contact regions are both metal-semiconductor compound, contact resistance between the material filling the vias and the source/drain contact regions can be minimized. Furthermore, because the material filling the vias is metal-semiconductor compound, the conducting material in the vias and dielectric material in the insulator layer can form good interface and have good adhesion properties, and the conducting material would not cause structural damage in the dielectric material. Thus, there is no need to form a barrier layer between the insulator layer and the material filling the vias. | 2014-09-11 |
20140252360 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - An insulating film provided between adjacent pixels is referred to as a bank, a partition, a barrier, an embankment or the like, and is provided above a source wiring or a drain wiring for a thin film transistor, or a power supply line. In particular, at an intersection portion of these wirings provided in different layers, a larger step is formed there than in other portions. Even when the insulating film provided between adjacent pixels is formed by a coating method, thin portions are problematically partially formed due to this step and the withstand pressure is reduced. In the present invention, a dummy material is arranged near the large step portion, particularly, around the intersection portion of wirings, so as to alleviate unevenness formed thereover. The upper wiring and the lower wiring are arranged in a misaligned manner so as not to align the end portions. | 2014-09-11 |
20140252361 | EL Display Device and Method for Manufacturing the Same - A plurality of pixels are arranged on the substrate. Each of the pixels is provided with an EL element which utilizes as a cathode a pixel electrode connected to a current control TFT. On a counter substrate, a light shielding film, a first color filter having a first color and a second color filter having a second color are provided. The second color is different from the first color. | 2014-09-11 |
20140252362 | THIN FILM APPARATUS - A thin film apparatus having a plurality of thin film cells is disclosed. Each thin film cell includes a crystalline layer and a surrounding layer. The crystalline layer has a shape of polygon. The surrounding layer is partially located on the crystalline layer. The crystalline layer is surrounded by the surrounding layer. | 2014-09-11 |
20140252363 | THREE DIMENSIONAL MEMORY STRUCTURE - A method to fabricate a three dimensional memory structure includes forming an array stack, creating a layer of sacrificial material above the array stack, etching a hole through the layer of sacrificial material and the array stack, creating a pillar of semiconductor material in the hole to form at least two vertically stacked flash memory cells that use the pillar as a common body, removing at least some of the layer of sacrificial material around the pillar to expose a portion of the pillar, and forming a field effect transistor (FET) using the portion of the pillar as the body of the FET. | 2014-09-11 |
20140252364 | THIN FILM TRANSISTOR ARRAY PANEL - A thin film transistor (TFT) array panel includes: first and second pixel electrodes neighboring each other; a data line extending between the first and the second pixel electrodes; first and second gate lines extending perpendicularly to the data line; a first TFT including a first gate electrode connected to the first gate line, a first source electrode connected to the data line, and a first drain electrode facing the first source electrode and connected to the first pixel electrode; and a second TFT including a second gate electrode connected to the second gate line, a second source electrode connected to the data line, and a second drain electrode facing the second source electrode and connected to the second pixel electrode. The first source electrode has the same relative position with respect to the first drain electrode as the second source electrode with respect to the second drain electrode. | 2014-09-11 |
20140252365 | THIN FILM TRANSISTOR ARRAY AND EL DISPLAY EMPLOYING THEREOF - EL display has a luminescence unit having a luminescence layer being disposed between a pair of electrodes and a thin film transistor array unit controlling luminescence of the luminescence unit. An interlayer insulation film is disposed between the luminescence unit and the transistor array unit. An anode of the luminescence unit is connected electrically to the thin film transistor array via a contact hole of the interlayer insulation film. The thin film transistor array further has a current supplying relaying electrode that is connected to the anode of the luminescence unit via the contact hole of the interlayer insulation film. A diffusion prevention film is formed on the boundary face of the anode of the luminescence unit and the relaying electrode. | 2014-09-11 |
20140252366 | Semiconductor Structure Including Buffer With Strain Compensation Layers - A semiconductor structure includes a substrate and a semiconductor buffer structure overlying the substrate. The semiconductor buffer structure includes a semiconductor body of a gallium nitride material, and a stack of strain compensation layers. The stack of strain compensation layers includes a layer of a first semiconductor material with an in-plane lattice constant that is smaller than a lattice constant of the semiconductor body, and a layer of a second semiconductor material with an in-plane lattice constant that is greater than the lattice constant of the semiconductor body. | 2014-09-11 |
20140252367 | DRIVER FOR NORMALLY ON III-NITRIDE TRANSISTORS TO GET NORMALLY-OFF FUNCTIONALITY - A semiconductor device includes a depletion mode GaN FET and an integrated driver/cascode IC. The integrated driver/cascode IC includes an enhancement mode cascoded NMOS transistor which is connected in series to a source node of the GaN FET. The integrated driver/cascode IC further includes a driver circuit which conditions a gate input signal and provides a suitable digital waveform to a gate node of the cascoded NMOS transistor. The cascoded NMOS transistor and the driver circuit are formed on a same silicon substrate. | 2014-09-11 |
20140252368 | HIGH-ELECTRON-MOBILITY TRANSISTOR - A high-electron-mobility transistor (HEMT) device includes a plurality of semiconductor layers formed on a substrate, wherein a two-dimensional electron gas (2DEG) layer is formed in the semiconductor layers; an etch-stop layer formed on the plurality of semiconductor layers; a p-type semiconductor layer pattern formed on the etch-stop layer; and a gate electrode formed on the p-type semiconductor layer pattern. | 2014-09-11 |
20140252369 | NITRIDE-BASED SEMICONDUCTOR DEVICE - A nitride-based semiconductor device including a substrate; a GaN-containing layer on the substrate; a nitride-containing layer on the GaN layer; a channel blocking layer on the nitride-containing layer, the channel blocking layer including a nitride-based semiconductor; a gate insulation layer on the channel blocking layer; and a gate electrode on the gate insulation layer. | 2014-09-11 |
20140252370 | NITRIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Exemplary embodiments of the present invention disclose a unidirectional heterojunction transistor including a channel layer made of a first nitride-based semiconductor having a first energy bandgap, a barrier layer made of a second nitride-based semiconductor having a second energy bandgap different from the first energy bandgap, the barrier layer including a recess, a drain electrode disposed on a first region of the barrier layer, and a recessed-drain Schottky electrode disposed in the recess of the barrier layer, the recessed-drain Schottky electrode contacting the drain electrode. | 2014-09-11 |
20140252371 | HETEROJUNCTION TRANSISTOR AND METHOD OF FABRICATING THE SAME - Exemplary embodiments of the present invention disclose a heterojunction transistor having a normally off characteristic using a gate recess structure and a method of fabricating the same. The heterojunction transistor may include a substrate, a channel layer disposed on the substrate and made of a first nitride-based semiconductor having a first energy bandgap, a first barrier layer disposed on the channel layer and made of a second nitride-based semiconductor having a second energy bandgap different from the first energy bandgap, a gate electrode disposed in a gate control region of the first barrier layer, and a second barrier layer disposed in gate non-control regions of the first barrier layer and separated from the first barrier layer. | 2014-09-11 |
20140252372 | VERTICAL GALLIUM NITRIDE SCHOTTKY DIODE - A vertical conduction nitride-based Schottky diode is formed using an insulating substrate which was lifted off after the diode device is encapsulated on the front side with a wafer level molding compound. The wafer level molding compound provides structural support on the front side of the diode device to allow the insulating substrate to be lifted off so that a conductive layer can be formed on the backside of the diode device as the cathode electrode. A vertical conduction nitride-based Schottky diode is thus realized. In another embodiment, a protection circuit for a vertical GaN Schottky diode employs a silicon-based vertical PN junction diode connected in parallel to the GaN Schottky diode to divert reverse bias avalanche current. | 2014-09-11 |
20140252373 | Semiconductor Device and Method for Producing the Same - A method for producing a semiconductor device is provided. The method includes providing a semiconductor substrate, providing at least one semiconductor device on the substrate, having a back face opposite the semiconductor substrate and a front face towards the semiconductor substrate, providing a contact layer on the back face of the semiconductor device, bonding the contact layer to an auxiliary carrier, and separating the at least one semiconductor device from the substrate. Further, a semiconductor device produced according to the method and an intermediate product are provided. | 2014-09-11 |
20140252374 | SILICON CARBIDE SEMICONDUCTOR DEVICE - A first drift layer has a first surface facing a first electrode and electrically connected to a first electrode, and a second surface opposite to the first surface. The first drift layer has an impurity concentration N | 2014-09-11 |
20140252375 | Delamination and Crack Prevention in III-Nitride Wafers - In an exemplary implementation, a method includes growing a III-Nitride body over a group IV substrate in a semiconductor wafer. The method includes forming at least one device layer over the III-Nitride body. The method also includes etching grid array trenches in the III-Nitride body, where the etching of the grid array trenches may extend into the group IV substrate. The method can also include forming an edge trench around a perimeter of the semiconductor wafer. The method further includes forming separate dies by cutting the semiconductor wafer approximately along the grid array trenches. | 2014-09-11 |
20140252376 | SILICON CARBIDE SUBSTRATE, METHOD FOR MANUFACTURING SAME AND METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - A method for manufacturing a silicon carbide substrate includes the following steps. A silicon carbide single-crystal substrate is prepared. A silicon carbide epitaxial layer is formed in contact with the silicon carbide single-crystal substrate. A silicon layer is formed in contact with a second surface of the silicon carbide epitaxial layer opposite to a first surface thereof that makes contact with the silicon carbide single-crystal substrate. Accordingly, there are provided a silicon carbide substrate, a method for manufacturing the silicon carbide substrate, and a method for manufacturing a silicon carbide semiconductor device so as to achieve prevention of contamination of a silicon carbide epitaxial layer in a simple manner. | 2014-09-11 |
20140252377 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF - The semiconductor device includes a SiC substrate; an aluminum nitride layer provided on the substrate and having an island-shaped pattern consisting of plural islands: a channel layer provided on the AlN layer and comprising a nitride semiconductor; an electron supplying layer provided on the channel layer and having a band gap larger than that of the channel layer; and a gate, source and drain electrodes on the electron supply layer. The AlN layer has an area-averaged circularity Y/X of greater than 0.2. Y is a sum of values obtained by multiplying circularities of the plural islands by areas of the plural islands respectively, X is a sum of the areas of the plural islands. The circularity are calculated by a formula of (4π×area)/(length of periphery) | 2014-09-11 |
20140252378 | SEMICONDUCTOR SUBSTRATE AND SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor substrate includes a substrate and a semiconductor layer. The substrate has a first surface and containing a silicon carbide. The semiconductor layer is provided on the first surface. The semiconductor layer has a thickness of H centimeters in a perpendicular direction to the first surface. The semiconductor layer contains an epitaxially grown silicon carbide with an off angle θ provided relative to a (0001) face of the substrate. The semiconductor layer includes k pieces of basal plane dislocation per one square centimeter viewed in the perpendicular direction. When S=(½)×H | 2014-09-11 |
20140252379 | PHOTOCONDUCTIVE ANTENNAS, METHOD FOR PRODUCING PHOTOCONDUCTIVE ANTENNAS, AND TERAHERTZ TIME DOMAIN SPECTROSCOPY SYSTEM - A photoconductive antenna that generates and detects a terahertz wave has a substrate, a buffer layer, a first semiconductor layer, a second semiconductor layer, and an electrode in this order. The substrate is made of Si, the buffer layer contains Ge, and the first and second semiconductor layers both contain Ga and As. The element ratio Ga/As of the second semiconductor layer is smaller than the element ratio Ga/As of the first semiconductor layer. | 2014-09-11 |
20140252380 | Shadow Mask Assembly - A shadow mask assembly includes a securing assembly configured to hold a substrate that is configured to hold a plurality of dies. The securing assembly includes a number of guide pins and a shadow mask comprising holes for the guide pins, said holes allowing the guide pins freedom of motion in one direction. The securing assembly includes a number of embedded magnets configured to secure the shadow mask to the securing assembly. | 2014-09-11 |
20140252381 | ACTIVE DEVICE ARRAY SUBSTRATE - An active device array substrate for saving material cost includes a substrate, scan lines, data lines, a thin film transistor, a color filter layer, a transparent conductive layer, an insulating layer and a pixel electrode. The color filter layer covers and contacts the scan lines, data lines and the thin film transistor. The transparent conductive layer is disposed on the color filter layer and electrically isolated from the scan lines, the data lines and the thin film transistor by the color filter layer. The insulating layer covers the transparent conductive layer. The pixel electrode is disposed on the insulating layer and connected to the thin film transistor. | 2014-09-11 |
20140252382 | SEMICONDUCTOR LIGHT EMITTING ELEMENT AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor light emitting element includes a light reflecting layer, first second, third and fourth semiconductor layers, first and second light emitting layers, and a first light transmitting layer. The second semiconductor layer is provided between the first semiconductor layer and the light reflecting layer. The first light emitting layer is provided between the first and second semiconductor layers. The first light transmitting layer is provided between the second semiconductor layer and the light reflecting layer. The third semiconductor layer is provided between the first light transmitting layer and the light reflecting layer. The fourth semiconductor layer is provided between the third semiconductor layer and the light reflecting layer. The second light emitting layer is provided between the third and fourth semiconductor layers. The light reflecting layer is electrically connected to one selected from the third and fourth semiconductor layers. | 2014-09-11 |
20140252383 | LIGHT-EMITTING DEVICE - Occurrence of a crosstalk phenomenon in a light-emitting device is inhibited. The light-emitting device includes an insulating layer; a first lower electrode over the insulating layer; a second lower electrode over the insulating layer; a structure over the insulating layer and between the first lower electrode and the second lower electrode; a first partition wall between the first lower electrode and the structure, over the insulating layer; a second partition wall between the second lower electrode and the structure, over the insulating layer; a first light-emitting unit over the first lower electrode, the first partition wall, the structure, the second partition wall, and the second lower electrode; an intermediate layer over the first light-emitting unit; a second light-emitting unit over the intermediate layer; and an upper electrode over the second light-emitting unit. | 2014-09-11 |
20140252384 | White LED Assembly With LED String And Intermediate Node Substrate Terminals - A white LED assembly includes a string of series-connected blue LED dice mounted on a substrate. The substrate has a plurality of substrate terminals. A first of the substrate terminals is coupled to be a part of first end node of the string. A second of the substrate terminals is coupled to be a part of an intermediate node of the string. A third of the substrate terminals is coupled to be a part of a second end node of the string. Other substrate terminals may be provided and coupled to be parts of corresponding other intermediate nodes of the string. A single contiguous amount of phosphor covers all the LED dice, but does not cover any of the substrate terminals. In one example, the amount of phosphor contacts the substrate and has a circular periphery. All the LEDs are mounted to the substrate within the circular periphery. | 2014-09-11 |
20140252385 | LIGHT EMITTING DEVICE WITH ENHANCED PRE-DIP AND METHOD OF MANUFACTURING THE SAME - An illumination device is disclosed. The illumination device includes a light source a pre-dip material that at least partially encapsulates the light source. The pre-dip material may include one or both of thermally-conductive particles and a cyclo-aliphatic composition. The pre-dip material may further include a resin and a hardener for the resin. Methods of manufacturing an illumination device are also disclosed. | 2014-09-11 |
20140252386 | Sealing structure, device, and method for manufacturing device - Provided is a device in which heat conduction from a sealant to a functional element is suppressed and whose bezel is slim. The sealing structure includes a first substrate, a second substrate whose surface over which a sealed component is provided faces the first substrate, and a frame-like sealant which seals a space between the first substrate and the second substrate with the first substrate and the second substrate. The second substrate includes a groove portion between the sealant and the sealed component. The groove portion is in a vacuum or includes a substance whose heat conductivity is lower than that of the second substrate. | 2014-09-11 |
20140252387 | SEMICONDUCTOR LIGHT EMITTING DEVICE - According to one embodiment, a semiconductor light emitting device includes first and second columnar units, a wavelength conversion layer, a light emitting unit, a resin unit and an intermediate layer. The first columnar unit extends in a first direction. The second columnar unit is provided apart from the first columnar unit, and extends in the first direction. The wavelength conversion layer is provided apart from the first and second columnar units in the first direction. The light emitting unit includes first and second semiconductor layers, and a light emitting layer configured to emit a first light. The resin unit covers side surfaces along the first direction of the first and second columnar units and the light emitting unit, and a surface of the light emitting unit. The intermediate layer includes first and second portions, and has a thickness thinner than a peak wavelength of the first light. | 2014-09-11 |
20140252388 | SEMICONDUCTOR LIGHT EMITTING ELEMENT AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor light emitting element includes: a first conductive pillar extending in a first direction; a second conductive pillar extending in the first direction; a first semiconductor layer of a first conductivity type provided on the first conductive pillar; a light emitting layer provided on the first semiconductor layer; a second semiconductor layer of a second conductivity type provided on the light emitting layer and on the second conductive pillar; a sealing unit covering a side surface of the first conductive pillar and a side surface of the second conductive pillar; and a light transmissive layer provided on the second semiconductor layer and having light transmissivity, a hardness of an upper surface portion of the light transmissive layer being higher than a hardness of a lower portion between the upper surface portion and the second semiconductor layer. | 2014-09-11 |
20140252389 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a method for manufacturing a semiconductor light emitting device is disclosed. The method can include applying a resin liquid onto a first major surface of a workpiece. The workpiece has the first major surface and includes a plurality of element units and a resin layer holding the plurality of element units. The method causes the particles in the resin liquid to sink and forms a first region on a surface side of the resin liquid and a second region provided between the first region and the workpiece. The method raises a temperature of the workpiece to a second temperature higher than the first temperature to cure the resin liquid to form an optical layer including a first portion and a second portion. In addition, the method divides the optical layer and the resin layer for the plurality of element units. | 2014-09-11 |
20140252390 | SEMICONDUCTOR LIGHT-EMITTING DEVICE - A semiconductor light-emitting device includes a semiconductor region having a light-emitting structure, an electrode layer formed on the semiconductor region, and a reflective protection structure extending exposing the upper surface of the electrode layer and covering the semiconductor region adjacent to the electrode layer. | 2014-09-11 |
20140252391 | LIGHT-EMITTING DEVICE - A light-emitting device of an embodiment includes a light-emitting element emitting blue excitation light and a first phosphor excited by the blue excitation light and emitting fluorescence. A peak wavelength of the fluorescence is not shorter than 520 nm and shorter than 660 nm and the peak wavelength of the fluorescence shifting in the same direction when a peak wavelength of the blue excitation light shifts. The first phosphor is one of a yellow phosphor emitting yellow fluorescence, a green phosphor emitting green fluorescence, a yellow-green/yellow phosphor emitting yellow-green/yellow fluorescence and a red phosphor emitting red fluorescence. | 2014-09-11 |
20140252392 | LIGHT EMITTING DIODE - An embodiment of the present invention provides a light emitting diode including a chip having a light emitting layer on the front surface side and a translucent member that is bonded between a back surface of the chip and a lead frame to support the chip by a resin having translucency, and is transmissive to light emitted from the light emitting layer. According to this configuration, the light emitting diode includes the translucent member that is transmissive to light emitted from the light emitting layer on the back surface side of the chip having the light emitting layer. Therefore, the ratio of light reflected at the interface with the lead frame to return to the light emitting layer can be suppressed to a low ratio and the light extraction efficiency can be enhanced. | 2014-09-11 |
20140252393 | LIGHT-EMITTING STRUCTURE - A light-emitting structure is provided. The disclosed light-emitting structure may include a light-emitting diode (LED) die, a plurality of light-penetrating microspheres covered a light emitting surface of the LED die, and a light-penetrating structure, disposed over the LED die and the light-penetrating microspheres, for converting light emitting from the LED die. Another light-emitting structure is also provided. The disclosed light-emitting structure may include a light-emitting diode (LED) die, a plurality of light-penetrating microspheres covered a light emitting surface of the LED die, and a light-penetrating structure, disposed between the LED die and the light-penetrating microspheres, for converting light emitting from the LED die. | 2014-09-11 |
20140252394 | LIGHT EMITTING DEVICE - Provided is a light emitting device. In one embodiment, a light emitting device including: a support member; a light emitting structure on the support member, the light emitting structure comprising a first conductive type semiconductor layer, a second conductive type semiconductor layer, and an active layer between the first conductive type semiconductor layer and the second conductive type semiconductor layer; a protective member at a peripheral region of an upper surface of the support member; an electrode including an upper portion being on the first conductive type semiconductor layer, a side portion extended from the upper portion and being on a side surface of the light emitting structure, and an extended portion extended from the side portion and being on the protective member; and an insulation layer between the side surface of the light emitting structure and the electrode. | 2014-09-11 |
20140252395 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND LIGHT EMITTING APPARATUS - According to one embodiment, a semiconductor light emitting device includes a p-type semiconductor layer, an n-type semiconductor layer, a light emitting layer, a p-side electrode and an n-side electrode. The p-type semiconductor layer includes a nitride semiconductor and has a first major surface. The n-type semiconductor layer includes a nitride semiconductor and has a second major surface. The light emitting layer is provided between the n-type semiconductor layer and the p-type semiconductor layer. The p-side electrode contacts a part of the p-type semiconductor layer on the first major surface. The n-side electrode contacts a part of the n-type semiconductor layer on the second major surface. The n-side electrode is provided outside and around the p-side electrode in a plan view along a direction from the p-type semiconductor layer to the n-type semiconductor layer. | 2014-09-11 |
20140252396 | HIGHLY EFFICIENT GALLIUM NITRIDE BASED LIGHT EMITTING DIODES VIA SURFACE ROUGHENING - A gallium nitride (GaN) based light emitting diode (LED), wherein light is extracted through a nitrogen face (N-face) of the LED and a surface of the N-face is roughened into one or more hexagonal shaped cones. The roughened surface reduces light reflections occurring repeatedly inside the LED, and thus extracts more light out of the LED. The surface of the N-face is roughened by an anisotropic etching, which may comprise a dry etching or a photo-enhanced chemical (PEC) etching. | 2014-09-11 |
20140252397 | SEMICONDUCTOR LIGHT-EMITTING DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor light-emitting device of the invention includes: a semiconductor layer including a light-emitting layer and having a first major surface and a second major surface opposite to the first major surface; a phosphor layer facing to the first major surface; an interconnect layer provided on the second major surface side and including a conductor and an insulator; and a light-blocking member provided on a side surface of the semiconductor layer and being opaque to light emitted from the light-emitting layer. | 2014-09-11 |
20140252398 | OPTOELECTRONIC SEMICONDUCTOR CHIP AND METHOD FOR PRODUCING AN OPTOELECTRONIC SEMICONDUCTOR CHIP - An optoelectronic semiconductor chip includes a semiconductor layer sequence having an active layer that generates an electromagnetic radiation and a light exit side, and a light coupling-out layer applied to the light exit side, wherein the light coupling-out layer includes of radiation-inactive nanocrystals composed of a material transmissive to the radiation generated, and a refractive index of the radiation-transmissive material for the radiation is at least 1.9. | 2014-09-11 |
20140252399 | ELECTRONIC PACKAGING SUBSTRATE WITH ETCHING INDENTATION AS DIE ATTACHMENT ANCHOR AND METHOD OF MANUFACTURING THE SAME - An electronics package is disclosed. The electronics package is disclosed as including a substrate core, a metal layer established on top of the substrate core, the metal layer being etched so as to include a die attachment anchor and at least one gap that separates a die bonding pad from at least one of a trace and wire bonding pad, for example. The die attachment anchor is established on top of the die bonding pad and has a depth that does not extend all the way through the die bonding pad. | 2014-09-11 |
20140252400 | LIGHT EMITTING DEVICE - A light emitting device including a carrier, a substrate, at least one electrode pair, at least one light emitting diode (LED) and at least one positioning element is provided. The substrate is disposed on the carrier and has a body portion and at least one bending portion. The bending portion connects to the body portion. The bending portion is not coplanar with the body portion. The electrode pair is located on the body portion of the substrate. The LED is disposed on the body portion of the substrate and electrically connected to the electrode pair. The positioning element is disposed on the bending portion of the substrate for fixing the substrate on the carrier. | 2014-09-11 |
20140252401 | LEAD FRAME AND LIGHT EMITTING DEVICE - A lead frame of high quality which can endure direct bonding to a light emitting element, and a light emitting device of high reliability which utilizing the lead frame. A lead frame includes a clad material which is a stacked layer of at least a first metal layer and a second metal layer, the second metal layer made of a metal which is different from the metal of the first metal layer, and a through portion. In the through-portion, an end surface of the first metal layer and an end surface of the second metal layer are covered with a plated layer. The end surface of either the first metal layer or the second metal layer protrudes farther into the through-portion than the end surface of the other metal layer. | 2014-09-11 |
20140252402 | LIGHT-EMITTING DIODE (LED) PACKAGE HAVING FLIP-CHIP BONDING STRUCTURE - A light-emitting diode (LED) package includes a package substrate, a first electrode pad, a second electrode pad, an upper insulating layer and an LED chip. The first electrode pad is disposed on an upper surface of the package substrate and includes a groove. The second electrode pad includes a protruding portion disposed in the groove of the first electrode pad. The upper insulating layer insulates the first electrode pad from the second electrode pad on the package substrate. The LED chip includes a first electrode and a second electrode which are respectively electrically connected in the form of a flip-chip to the first electrode pad and the protruding portion of the second electrode pad. | 2014-09-11 |
20140252403 | ESD Protection Component and Component Comprising an ESD Protection Component and an LED - An ESD protection component includes a ceramic material and a BGA or LGA termination. In addition, an ESD protection component includes a basic body with a lower side. The basic body includes a ceramic material. At least one floating inner electrode is located at a distance from the lower side of two to 100 ceramic grains. Also a component includes a carrier, on which an LED and an ESD protection component are arranged. | 2014-09-11 |
20140252404 | THERMALLY-CONDUCTIVE SHEET, LED MOUNTING SUBSTRATE, AND LED MODULE - The present invention provides a thermally-conductive sheet excellent in heat dissipation properties. The thermally-conductive sheet includes a polymer matrix and a thermally-conductive filler dispersed in the polymer matrix. The present invention is a thermally-conductive sheet including a polymer matrix and non-spherical particles of a thermally-conductive filler that are dispersed in the polymer matrix. At least a part of the thermally-conductive filler particles are oriented in a thickness direction of the sheet. When a portion of the sheet where the thermally-conductive filler particles have the highest degree of orientation in the thickness direction of the sheet is defined as a center of orientation, and an axis passing through the center of orientation and perpendicular to sheet surfaces is defined as a central axis of orientation, the thermally-conductive sheet has a region where the thermally-conductive filler particles are oriented toward one point on the central axis of orientation and where the degree of orientation of the thermally-conductive filler particles in the thickness direction of the sheet decreases from the center of orientation toward a periphery of the sheet. | 2014-09-11 |
20140252405 | LOW WARPAGE WAFER BONDING THROUGH USE OF SLOTTED SUBSTRATES - In a wafer bonding process, one or both of two wafer substrates are scored prior to bonding. By creating slots in the substrate, the wafer's characteristics during bonding are similar to that of a thinner wafer, thereby reducing potential warpage due to differences in CTE characteristics associated with each of the wafers. Preferably, the slots are created consistent with the singulation/dicing pattern, so that the slots will not be present in the singulated packages, thereby retaining the structural characteristics of the full-thickness substrates. | 2014-09-11 |
20140252406 | ENCAPSULATION STRUCTURE FOR AN OPTO-ELECTRONIC COMPONENT, AND METHOD FOR ENCAPSULATING AN OPTOELECTRONIC COMPONENT - An encapsulation structure for an optoelectronic component, may include: a thin-film encapsulation for protecting the optoelectronic component against chemical impurities; an adhesive layer formed on the thin-film encapsulation; and a cover layer formed on the adhesive layer and serving for protecting the thin-film encapsulation and/or the optoelectronic component against mechanical damage, wherein the adhesive layer is formed such that particle impurities situated at the surface of the thin-film encapsulation are at least partly enclosed by the adhesive layer. | 2014-09-11 |
20140252407 | TUNNEL EFFECT TRANSISTOR - A tunnel effect transistor includes a channel made of an intrinsic semiconductor material; source and drain extension regions on either side of the channel, the source extension region being made of a semiconductor material doped according to a first type of doping P or N and the drain extension region being made of a semiconductor material doped according to a second type of doping opposite to said first type of doping; source and drain conductive regions respectively in contact with the source and drain extension regions; a gate structure including a gate dielectric layer in contact with the channel and a gate area arranged such that the gate dielectric layer is arranged between the gate area and the channel; and an area doped according to the first type of doping inserted between the channel and the drain extension region. | 2014-09-11 |
20140252408 | REVERSE CONDUCTING IGBT - A reverse conducting IGBT that includes an insulated gate; a semiconductor layer having a first conductivity type drift region, a second conductivity type body region, a first conductivity type emitter region, and a second conductivity type intermediate region; and an emitter electrode provided on a surface of the semiconductor layer. The first conductivity type drift region of the semiconductor layer contacts the insulated gate. The second conductivity type body region of the semiconductor layer is provided on the drift region and contacts the insulated gate. The first conductivity type emitter region of the semiconductor layer is provided on the body region and contacts the insulated gate. The second conductivity type intermediate region of the semiconductor layer is provided on the emitter region and is interposed between the emitter region and the emitter electrode. | 2014-09-11 |
20140252409 | Circuit Including a Switching Element, a Rectifying Element, and a Charge Storage Element - A circuit can include a pair of switching elements that have terminals electrically connected to terminals of a power supply and have other terminals electrically connected to an output terminal. The circuit can include rectifying elements and one or more charge storage elements. The circuit may be used as a Buck converter. The rectifying element(s) and charge storage element(s) may help to reduce ringing at an output terminal of the circuit during normal operation and reduce the likelihood of exceeding a breakdown voltage between current-carrying electrodes of a switching element within the circuit during a switching operation. | 2014-09-11 |
20140252410 | Module and Assembly with Dual DC-Links for Three-Level NPC Applications - A power semiconductor module has four power terminals. An IGBT has a collector connected to the first power terminal and an emitter coupled to the third power terminal. An anti-parallel diode is coupled in parallel with the IGBT. A DC-link is connected between the second and fourth power terminals. The DC-link may involve two diodes and two IGBTs, where the IGBTs are connected in a common collector configuration. The first and second power terminals are disposed in a first line along one side of the module, and the third and fourth power terminals are disposed in a second line along the opposite side of the module. Two identical instances of the module can be interconnected together to form a three-level NPC phase leg having low stray inductances, where the phase leg has two parallel DC-links. | 2014-09-11 |
20140252411 | LOW VOLTAGE AVALANCHE PHOTODIODE WITH RE-ENTRANT MIRROR FOR SILICON BASED PHOTONIC INTEGRATED CIRCUITS - A low voltage APD is disposed at an end of a waveguide extending laterally within a silicon device layer of a PIC chip. The APD is disposed over an inverted re-entrant mirror co-located at the end of the waveguide to couple light by internal reflection from the waveguide to an under side of the APD. In exemplary embodiments, a 45°-55° facet is formed in the silicon device layer by crystallographic etch. In embodiments, the APD includes a silicon multiplication layer, a germanium absorption layer over the multiplication layer, and a plurality of ohmic contacts disposed over the absorption layer. An overlying optically reflective metal film interconnects the plurality of ohmic contacts and returns light transmitted around the ohmic contacts to the absorption layer for greater detector responsivity. | 2014-09-11 |
20140252412 | Strained and Uniform Doping Technique for FINFETs - The present disclosure relates to a device and method of forming enhanced channel carrier mobility within a transistor. Silicon carbon phosphorus (SiCP) source and drain regions are formed within the transistor with cyclic deposition etch (CDE) epitaxy, wherein both resistivity and strain are controlled by substitutional phosphorus. A carbon concentration of less than approximately 1% aids in control of the phosphorus dopant diffusion. Phosphorus dopant diffusion is also controlled by an anneal step which promotes uniform doping through both source and drain, as well as lightly-doped drain regions. | 2014-09-11 |
20140252413 | SILICON-GERMANIUM FINS AND SILICON FINS ON A BULK SUBSTRATE - A first silicon-germanium alloy layer is formed on a semiconductor substrate including silicon. A stack of a first silicon layer and a second silicon-germanium alloy layer is formed over a first region of the first silicon-germanium alloy layer, and a second silicon layer thicker than the first silicon layer is formed over a second region of the first silicon-germanium alloy layer. At least one first semiconductor fin is formed in the first region, and at least one second semiconductor fin is formed in the second region. Remaining portions of the first silicon layer are removed to provide at least one silicon-germanium alloy fin in the first region, while at least one silicon fin is provided in the second region. Fin field effect transistors can be formed on the at least one silicon-germanium alloy fin and the at least one silicon fin. | 2014-09-11 |
20140252414 | Passivated III-V or Ge Fin-Shaped Field Effect Transistor - A semiconductor device includes a semiconductor substrate having a top surface, and at least one coated fin protruding perpendicularly from the surface and having a height h and side walls. The at least one coated fin further includes a core of one or more layers selected from the group consisting of (a) III-V compound layers and (b) a Ge layer, and a coating overlaying the core. The coating includes one or more metal oxide layers, at least one of which is aluminium. The device also includes a recess surrounding the at least one coated fin and being defined between two coated fins when more than one fin is present. The recess is filled up with a dielectric material so as to cover the coating on the side walls of the at least one fin up to a certain height h′, which is less than the height h. The present disclosure also relates to a method for producing the semiconductor device. | 2014-09-11 |
20140252415 | HIGH MOBILITY, THIN FILM TRANSISTORS USING SEMICONDUCTOR/INSULATOR TRANSITION-METALDICHALCOGENIDE BASED INTERFACES - Electronic devices and methods of forming an electronic device are disclosed herein. An electronic device may include a first 2D atomic crystal layer; a second 2D atomic crystal layer disposed atop the first 2D atomic crystal layer; and an interface comprising van-der-Waals bonds between the first 2D atomic crystal layer and the second 2D atomic crystal layer. A method of forming an electronic device may include depositing a first 2D atomic crystal layer; and depositing a second 2D atomic crystal layer atop the first 2D atomic crystal layer; wherein an interface is formed between the first 2D atomic crystal layer and the second 2D atomic crystal layer via van-der-Waals bonding. | 2014-09-11 |
20140252416 | FIELD EFFECT TRANSITOR AND SEMICONDUCTOR DEVICE USING THE SAME - An field effect transistor has a plurality of cells provided on a first straight line. Each cell has a plurality of multi-finger electrodes and is connected to a gate terminal electrode and a drain terminal electrode. The multi-finger electrode has at least two finger gate electrodes, a finger drain electrode, and a finger source electrode. The gate terminal electrode connects the finger gate electrodes of two adjoining cells in common. The drain terminal electrode connects the finger drain electrodes of two adjoining cells in common. The finger gate electrode of one cell of two adjoining cells and the finger gate electrode of another cell of the two adjoining cells cross perpendicularly. The gate terminal electrode and the drain terminal electrode are provided alternately in a region where the finger gate electrodes of the two adjoining cells cross. | 2014-09-11 |
20140252417 | SEMICONDUCTOR DEVICE AND ELECTRONIC APPARATUS - A semiconductor device includes: a device region having a semiconductor layer that includes a channel section; a device peripheral region adjoining the device region; a gate electrode provided within the device region, and having a boundary section that spans the device region and the device peripheral region; a conductive layer provided between the gate electrode and the semiconductor layer; and an insulating layer provided between the gate electrode in the boundary section and the semiconductor layer. | 2014-09-11 |
20140252418 | ELECTRICAL COUPLING OF MEMORY CELL ACCESS DEVICES TO A WORD LINE - A memory array and a method for electrically coupling memory cell access devices to a word line. The memory array includes a source line electrically coupled to each source terminal of the memory cell access devices. The memory array also includes a first set of at least two vertical pillars positioned above and electrically coupled to the source line. A second set of vertical pillars electrically isolated from the source line and positioned such that the source line does not extend below the second set of vertical pillars is also included. Furthermore, gate terminals of the memory cell access devices laterally surround the first set of vertical pillars and the second set of vertical pillars. Finally, a first word line contact is positioned between two of the second set of vertical pillars. The first word line contact is electrically coupled to the gate terminals. | 2014-09-11 |
20140252419 | MEMS DEVICE AND METHOD OF MANUFACTURE - A MEMS logic device comprising agate which pivots on a torsion hinge, two conductive channels on the gate, one on each side of the torsion hinge, source and drain landing pads under the channels, and two body bias elements under the gate, one on each side of the torsion hinge, so that applying a threshold bias between one body bias element and the gate will pivot the gate so that one channel connects the respective source and drain landing pad, and vice versa. An integrated circuit with MEMS logic devices on the dielectric layer, with the source and drain landing pads connected to metal interconnects of the integrated circuit. A process of forming the MEM switch. | 2014-09-11 |
20140252420 | SEMICONDUCTOR DEVICES INCLUDING GATE ELECTRODES WITH MULTIPLE PROTRUSIONS CONFIGURED FOR CHARGE TRANSFER - An image sensor device can include device isolation regions in a substrate and a photoelectric conversion portion in the substrate that can be between the device isolation regions. A transfer gate of the image sensor device, can be located over, and be electrically coupled to, the photoelectric conversion portion. The transfer gate can include at least two protrusions, that are separated from the device isolation regions, and that protrude toward the photoelectric conversion portion. | 2014-09-11 |
20140252421 | Backside CMOS Compatible BioFET with No Plasma Induced Damage - The present disclosure provides a bio-field effect transistor (BioFET) device and methods of fabricating a BioFET and a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device includes a gate structure disposed on a first surface of a substrate and an interface layer formed on a second surface of the substrate. The substrate is thinned from the second surface to expose a channel region before forming the interface layer. | 2014-09-11 |
20140252422 | CAVITY STRUCTURES FOR MEMS DEVICES - Embodiments relate to MEMS devices, particularly MEMS devices integrated with related electrical devices on a single wafer. Embodiments utilize a modular process flow concept as part of a MEMS-first approach, enabling use of a novel cavity sealing process. The impact and potential detrimental effects on the electrical devices by the MEMS processing are thereby reduced or eliminated. At the same time, a highly flexible solution is provided that enables implementation of a variety of measurement principles, including capacitive and piezoresistive. A variety of sensor applications can therefore be addressed with improved performance and quality while remaining cost-effective. | 2014-09-11 |
20140252423 | SEMICONDUCTOR DEVICE HAVING METAL GATE AND MANUFACTURING METHOD THEREOF - A manufacturing method of semiconductor devices having metal gate includes following steps. A substrate having a first semiconductor device and a second semiconductor device formed thereon is provided. The first semiconductor device includes a first gate trench and the second semiconductor device includes a second gate trench. A first work function metal layer is formed in the first gate trench and the second gate trench. A portion of the first work function metal layer is removed from the second gate trench. A second work function metal layer is formed in the first gate trench and the second gate trench. The second work function metal layer and the first work function metal layer include the same metal material. A third work function metal layer and a gap-filling metal layer are sequentially formed in the first gate trench and the second gate trench. | 2014-09-11 |
20140252424 | METHODS OF FORMING SEMICONDUCTOR DEVICE WITH SELF-ALIGNED CONTACT ELEMENTS AND THE RESULTING DEVICES - One method discloses performing an etching process to form a contact opening in a layer of insulating material above at least a portion of a source/drain, region wherein, after the completion of the etching process, a portion of a gate structure of the transistor is exposed, selectively forming an oxidizable material on the exposed gate structure, converting at least a portion of the oxidizable material to an oxide material, and forming a conductive contact in the contact opening that is conductively coupled to the source/drain region. A novel transistor device disclosed herein includes an oxide material positioned between a conductive contact and a gate structure of the transistor, wherein the oxide material contacts the conductive contact and contacts a portion, but not all, of the exterior surface of the gate structure. | 2014-09-11 |
20140252425 | METHODS OF FORMING SEMICONDUCTOR DEVICE WITH SELF-ALIGNED CONTACT ELEMENTS AND THE RESULTING DEVICES - One method includes performing a first etching process to form a contact opening in a layer of insulating material that exposes a portion of a gate structure of the transistor, performing a second etching process on the exposed portion of the gate structure to thereby define a gate recess, selectively forming an oxidizable material in the gate recess, converting the oxidizable material to an oxide material, and forming a conductive contact in the contact opening that is conductively coupled to a source/drain region. A device includes an oxide material that is positioned at least partially in a recess formed in a gate structure, wherein the oxide material contacts a conductive contact and contacts a portion, but not all, of the exterior surface of the gate structure. | 2014-09-11 |
20140252426 | Semiconductor Structure with Dielectric-Sealed Doped Region - Leakage current can be substantially reduced by the formation of a seal dielectric in place of the conventional junction between source/drain region(s) and the substrate material. Trenches are formed in the substrate and lined with a seal dielectric prior to filling the trenches with semiconductor material. Preferably, the trenches are overfilled and a CMP process planarizes the overfill material. An epitaxial layer can be grown atop the trenches after planarization, if desired. | 2014-09-11 |
20140252427 | Self-aligned Contacts For Replacement Metal Gate Transistors - Embodiments of the invention include methods of forming gate caps. Embodiments may include providing a semiconductor device including a gate on a semiconductor substrate and a source/drain region on the semiconductor substrate adjacent to the gate, forming a blocking region, a top surface of which extends above a top surface of the gate, depositing an insulating layer above the semiconductor device, and planarizing the insulating layer using the blocking region as a planarization stop. Embodiments further include semiconductor devices having a semiconductor substrate, a gate above the semiconductor substrate, a source/drain region adjacent to the gate, a gate cap above the gate that cover the full width of the gate, and a contact adjacent to the source/drain region having a portion of its sidewall defined by the gate cap. | 2014-09-11 |
20140252428 | Semiconductor Fin Structures and Methods for Forming the Same - An integrated circuit structure includes a semiconductor substrate, an insulation region extending into the semiconductor substrate, and a semiconductor strip between two opposite portions of the insulation region. The semiconductor strip includes an upper portion higher than top surfaces of the insulation regions and a lower portion in the insulation region. The lower portion has a sidewall including a first sidewall portion having a first slope and a second sidewall portion over and connected to the first sidewall portion. The second sidewall portion has a second slope smaller than the first slope. | 2014-09-11 |
20140252429 | CONTACT GEOMETRY HAVING A GATE SILICON LENGTH DECOUPLED FROM A TRANSISTOR LENGTH - Methods for forming a semiconductor device are provided. In one embodiment, a gate structure having a gate insulating layer and a gate electrode structure formed on the gate insulating layer is provided. The methods provide reducing a dimension of the gate electrode structure relative to the gate insulating layer along a direction extending in parallel to a direction connecting the source and drain. A semiconductor device structure having a gate structure including a gate insulating layer and a gate electrode structure formed above the gate insulating layer is provided, wherein a dimension of the gate electrode structure extending along a direction which is substantially parallel to a direction being oriented from source to drain is reduced relative to a dimension of the gate insulating layer. According to some examples, gate structures are provided having a gate silicon length which is decoupled from the channel width induced by the gate structure. | 2014-09-11 |
20140252430 | Electronic Device Including a Dielectric Layer Having a Non-Uniform Thickness and a Process of Forming The Same - An electronic device can include a transistor having a drain region, a source region, a dielectric layer, and a gate electrode. The dielectric layer can have a first portion and a second portion, wherein the first portion is relatively thicker and closer to the drain region; the second portion is relatively thinner and closer to the source region. The gate electrode of the transistor can overlie the first and second portions of the dielectric layer. In another aspect, an electronic device can be formed using two different dielectric layers having different thicknesses. A gate electrode within the electronic device can be formed over portions of the two different dielectric layers. The process can eliminate masking and doping steps that may be otherwise used to keep the drain dopant concentration closer to the concentration as originally formed. | 2014-09-11 |
20140252431 | Semiconductor Device Structure and Method of Forming Same - An embodiment is a semiconductor device comprising a first gate structure over a semiconductor substrate, a first etch stop layer (ESL) over the semiconductor substrate and the first gate, the first ESL having a curved top surface, and a first inter-layer dielectric (ILD) on the first ESL, the first ILD having a curved top surface. The semiconductor device further comprises a second ESL on the first ILD, the second ESL having a curved top surface, and a second ILD on the second ESL. | 2014-09-11 |
20140252432 | Semiconductor Device and Method for Forming the Same - A semiconductor device includes a substrate and a gate structure formed over the substrate. The semiconductor device further includes an insulator feature formed in the substrate. The insulator feature includes an insulating layer and a capping layer over the insulating layer. | 2014-09-11 |
20140252433 | Multi-Layer Metal Contacts - A method for forming metal contacts within a semiconductor device includes forming a first-layer contact into a first dielectric layer that surrounds at least one gate electrode, the first-layer contact extending to a doped region of an underlying substrate. The method further includes forming a second dielectric layer over the first dielectric layer and forming a second-layer contact extending through the second dielectric layer to the first-layer contact. | 2014-09-11 |
20140252434 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device includes forming isolation layers in a first direction at trenches at isolation regions defined at a semiconductor substrate and forming gate lines in a second direction crossing the first direction over the isolation layers and active regions defined between the isolation layers, performing a dry-etch process to remove the isolation layers, and forming an insulating layer over the semiconductor substrate to form a first air gap extending in the first direction in the trenches and a second air gap extending in the second direction between the gate lines. | 2014-09-11 |
20140252435 | SEMICONDUCTOR DEVICE - A semiconductor device concerning an embodiment is provided with a plate-like semiconductor substrate, electrode pads, electrode connecting conductors, and a source electrode back pad. The semiconductor substrate has a first cutout section in a first side, and has a second cutout section and a third cutout section in a second side. A drain electrode connecting conductor is provided in the first cutout section, and one end thereof touches the drain electrode pad, and the other end thereof is exposed in a back surface of the semiconductor substrate. A gate electrode connecting conductor is provided in the third cutout section, and one end thereof touches the gate electrode pad, and the other end thereof is exposed in the back of the semiconductor substrate. A source electrode connecting conductor is provided in the second cutout section, and one end thereof touches the source electrode pad. | 2014-09-11 |
20140252436 | SEMICONDUCTOR DEVICE - There is provided a semiconductor device with basic electronic elements in a three-dimensional structure. The semiconductor device has a source region and a drain region each of which includes an electrode and a silicide region, and is formed with a plurality of different crystal planes. The silicide regions on different crystal planes of the source region and the drain region have different thicknesses. | 2014-09-11 |
20140252437 | DEPTH PIXEL INCLUDED IN THREE-DIMENSIONAL IMAGE SENSOR AND THREE-DIMENSIONAL IMAGE SENSOR INCLUDING THE SAME - A depth pixel includes a photo detection region, first and second photo gates and first and second floating diffusion regions. The photo detection region collects photo charges based on light reflected by an object. The collected photo charges are drifted in a first direction and a second direction different from the first direction based on an internal electric field in the photo detection region. The first photo gate is activated in response to a first photo control signal. The first floating diffusion region accumulates first photo charges drifted in the first direction if the first photo gate is activated. The second photo gate is activated in response to the first photo control signal. The second floating diffusion region accumulates second photo charges drifted in the second direction if the second photo gate is activated. | 2014-09-11 |
20140252438 | Three-Dimensional Magnetic Random Access Memory With High Speed Writing - One embodiment of a magnetic random access memory includes a magnetic memory cell comprising a transistor disposed on a substrate, electrically coupled to a first conductive line and comprising a gate width; a plurality of magnetoresistive elements, each magnetoresistive element comprising an element width, a pinned magnetic layer comprising a fixed magnetization direction directed perpendicular to the substrate, a free magnetic layer comprising a reversible magnetization direction directed perpendicular to the substrate, and a tunnel barrier layer residing between the pinned and free layers; and a plurality of parallel second conductive lines overlapping the first conductive line. The plurality of the parallel second lines is independently electrically coupled to the plurality of magnetoresistive elements at first terminals, and the plurality of magnetoresistive elements is jointly electrically coupled to the transistor at second terminals, wherein the gate width is substantially larger than the element width. Other embodiments are described and shown. | 2014-09-11 |
20140252439 | MRAM HAVING SPIN HALL EFFECT WRITING AND METHOD OF MAKING THE SAME - A spin-transfer-torque magnetoresistive memory comprises apparatus and method of manufacturing a three terminal magnetoresistive memory element having highly conductive bottom electrodes overlaid on top of a SHE-metal layer in the regions outside of an MTJ stack. The memory cell comprises a bit line positioned adjacent to selected ones of the plurality of magnetoresistive memory elements to supply a reading current across the magnetoresistive element stack and two highly conductive bottom electrodes overlaid and electrically contacting on top of a SHE-metal layer in the outside of an MTJ region and to supply a bi-directional spin Hall effect recording current, and accordingly to switch the magnetization of the recording layer. Thus magnetization of a recording layer can be readily switched or reversed to the direction in accordance with a direction of a current along the SHE-metal layer by applying a low write current. | 2014-09-11 |
20140252440 | SEMICONDUCTOR DEVICES INCLUDING CONDUCTIVE PLUG - Semiconductor devices include a substrate having a target connection region; a conductive line having a first side wall spaced apart from the substrate by at least an insulating layer, and a conductive plug structure electrically connecting the conductive line to the target connection region, wherein the conductive plug includes a first conductive plug having a first side wall, a bottom surface contacting the target connection region of the substrate, and a second side wall facing the first side wall of the conductive line, and a second conductive plug between the conductive line and the first conductive plug. The second conductive plug contacts both the first side wall of the conductive line and the second side wall of the first conductive plug. | 2014-09-11 |
20140252441 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - A technique for enhancing the performance of a memory- and logic-equipped semiconductor device is provided. The semiconductor device comprises a semiconductor substrate, and insulating layer on the semiconductor substrate, a plurality of contact plugs in the insulating layer, and an insulating layer where capacitors, a plurality of contact plugs, barrier metal layers and copper interconnections are formed. Source/drain regions in the upper surface of the semiconductor substrate are electrically connected to the copper interconnections. One of adjacent source/drain regions in the upper surface of the semiconductor substrate is electrically connected to the copper interconnection, while the other is electrically connected to the capacitor. | 2014-09-11 |
20140252442 | Method and Structure for Vertical Tunneling Field Effect Transistor and Planar Devices - The present disclosure provides one embodiment of a method of forming a tunnel field effect transistor (TFET). The method includes forming a semiconductor mesa on a semiconductor substrate; performing a first implantation to the semiconductor substrate and the semiconductor mesa to form a drain of a first type conductivity; forming a first dielectric layer on the semiconductor substrate and sidewall of the semiconductor mesa; forming a gate stack on the sidewall of the semiconductor mesa and the first dielectric layer; forming a second dielectric layer on the first dielectric layer and the gate stack; and forming, on the semiconductor mesa, a source having a second type conductivity opposite to the first type conductivity. The gate stack includes a gate dielectric and a gate electrode on the gate dielectric. The source, drain and gate stack are configured to form the TFET. | 2014-09-11 |
20140252443 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a nonvolatile semiconductor memory device comprises a semiconductor substrate, a first layer formed above the semiconductor substrate, a first conductive layer, an inter-electrode insulating layer, and a second conductive layer sequentially stacked above the first layer, a memory film formed on an inner surface of each of a pair of through holes provided in the first conductive layer, the inter-electrode insulating layer, and the second conductive layer and extending in a stacking direction, a semiconductor layer formed on the memory film in the pair of through holes, and a metal layer formed in part of the pair of through holes and/or in part of a connection hole that is provided in the first layer and connects lower end portions of the pair of through holes, the metal layer being in contact with the semiconductor layer. | 2014-09-11 |
20140252444 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE AND DEVICE FABRICATED THEREBY - A semiconductor device includes a plurality of lines disposed on a semiconductor substrate, and remaining line patterns disposed spaced apart from the lines on extensions from the lines. The lines include first end-portions adjacent to the remaining line patterns. The remaining line patterns include second end-portions adjacent to the lines. The first end-portions and second end-portions are formed to have mirror symmetry with respect to each other. | 2014-09-11 |
20140252445 | METHOD OF FORMING SPLIT-GATE CELL FOR NON-VOLATIVE MEMORY DEVICES - Fabrication of a slim split gate cell and the resulting device are disclosed. Embodiments include forming a first gate on a substrate, the first gate having an upper surface and a hard-mask covering the upper surface, forming an interpoly isolation layer on side surfaces of the first gate and the hard-mask, forming a second gate on one side of the first gate, with an uppermost point of the second gate below the upper surface of the first gate, removing the hard-mask, forming spacers on exposed vertical surfaces, and forming a salicide on exposed surfaces of the first and second gates. | 2014-09-11 |
20140252446 | EXTREMELY THIN SEMICONDUCTOR ON INSULATOR (ETSOI) LOGIC AND MEMORY HYBRID CHIP - A method of forming a semiconductor device that includes providing a logic device on a semiconductor on insulating layer of a transfer substrate. The transfer substrate may further include a dielectric layer and a first handle substrate. A second handle substrate may be contacted to the semiconductor on insulating layer of the transfer substrate that includes logic device. The first handle substrate may be removed to expose the dielectric layer. A memory device can then be formed on the dielectric layer. Interconnect wiring can then be formed connecting the logic device with the memory device. | 2014-09-11 |
20140252447 | Nanodot-Enhanced Hybrid Floating Gate for Non-Volatile Memory Devices - A memory device and a method of making a memory device that includes a semiconductor channel, a tunnel dielectric layer located over the semiconductor channel, a floating gate located over the tunnel dielectric layer, the floating gate comprising a continuous layer of an electrically conductive material and at least one protrusion of an electrically conductive material facing the tunnel dielectric layer and electrically shorted to the continuous layer, a blocking dielectric region located over the floating gate, and a control gate located over the blocking dielectric layer. | 2014-09-11 |
20140252448 | EXTREMELY THIN SEMICONDUCTOR ON INSULATOR (ETSOI) LOGIC AND MEMORY HYBRID CHIP - A method of forming a semiconductor device that includes providing a logic device on a semiconductor on insulating layer of a transfer substrate. The transfer substrate may further include a dielectric layer and a first handle substrate. A second handle substrate may be contacted to the semiconductor on insulating layer of the transfer substrate that includes logic device. The first handle substrate may be removed to expose the dielectric layer. A memory device can then be formed on the dielectric layer. Interconnect wiring can then be formed connecting the logic device with the memory device. | 2014-09-11 |
20140252449 | SEMICONDUCTOR DEVICES COMPRISING FLOATING GATE TRANSISTORS AND METHODS OF FORMING SUCH SEMICONDUCTOR DEVICES - Semiconductor devices include one or more transistors having a floating gate and a control gate. In at least one embodiment, the floating gate comprises an intermediate portion extending between two end portions. The intermediate portion has an average cross-sectional area less than one or both of the end portions. In some embodiments, the intermediate portion may comprise a single nanowire. In additional embodiments, semiconductor devices have one or more transistors having a control gate and a floating gate in which a surface of the control gate opposes a lateral side surface of a floating gate that defines a recess in the floating gate. Electronic systems include such semiconductor devices. Methods of forming semiconductor devices include, for example, forming a floating gate having an intermediate portion extending between two end portions, and configuring the intermediate portion to have an average cross-sectional area less than one or both of the end portions. | 2014-09-11 |
20140252450 | SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR STORAGE DEVICE - According to one embodiment, a columnar semiconductor, a floating gate electrode formed on a side surface of the columnar semiconductor via a tunnel dielectric film, and a control gate electrode formed to surround the floating gate electrode via a block dielectric film are provided. | 2014-09-11 |
20140252451 | MEMORY DEVICE COMPRISING ELECTRICALLY FLOATING BODY TRANSISTOR - A semiconductor memory cell comprising an electrically floating body. A method of operating the memory cell is provided. | 2014-09-11 |
20140252452 | ULTRAHIGH DENSITY VERTICAL NAND MEMORY DEVICE AND METHOD OF MAKING THEREOF - Monolithic, three dimensional NAND strings include a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, the blocking dielectric comprising a plurality of blocking dielectric segments, a plurality of discrete charge storage segments, and a tunnel dielectric located between each one of the plurality of the discrete charge storage segments and the semiconductor channel. | 2014-09-11 |
20140252453 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - According to one embodiment, a nonvolatile semiconductor memory device including a semiconductor layer with a main surface, a first insulating layer formed on the main surface of the semiconductor layer, a charge storage layer formed on the first insulating layer, a second insulating layer formed on the charge storage layer, and a control gate electrode formed on the second insulating layer. At least one inelastic scattering film that reduces energy of electrons by scattering is contained in at least one of the charge storage layer and second insulating layer. | 2014-09-11 |
20140252454 | VERTICAL BIT LINE TFT DECODER FOR HIGH VOLTAGE OPERATION - A 3D memory array having a vertically oriented thin film transistor (TFT) selection device that has a channel extension, otherwise referred to as a gate/junction offset, is disclosed. The vertically oriented TFT selection device with channel extension serves as a vertical bit line selection device in the 3D memory array. A vertical TFT select device having a channel extension has a high breakdown voltage and low leakage current. The channel extension can be at the top junction or bottom junction of the TFT. Depending on whether the memory elements undergo a forward FORM or reverse FORM, either the bottom or top junction can have the channel extension. This provides for a high voltage junction where needed. | 2014-09-11 |
20140252455 | Structure And Method For Static Random Access Memory Device Of Vertical Tunneling Field Effect Transistor - The present disclosure provides one embodiment of a SRAM cell that includes first and second inverters cross-coupled for data storage, each inverter including at least one pull-up device and at least one pull-down devices; and at least two pass-gate devices configured with the two cross-coupled inverters. The pull-up devices, the pull-down devices and the pass-gate devices include a tunnel field effect transistor (TFET) that further includes a semiconductor mesa formed on a semiconductor substrate and having a bottom portion, a middle portion and a top portion; a drain of a first conductivity type formed in the bottom portion and extended into the semiconductor substrate; a source of a second conductivity type formed in the top portion, the second conductivity type being opposite to the first conductivity type; a channel in a middle portion and interposed between the source and drain; and a gate formed on sidewall of the semiconductor mesa and contacting the channel. | 2014-09-11 |
20140252456 | SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD - In one embodiment, a semiconductor device can include: (i) a first doped pillar region having a doping concentration that sequentially increases from bottom to top in a vertical direction; (ii) second doped pillar regions arranged on either side of the first doped pillar region in a horizontal direction; and (iii) where sidewalls of the second doped pillar regions form sides of an inverted trapezoidal structure. | 2014-09-11 |
20140252457 | MULTI-LANDING CONTACT ETCHING - A method for contacting MOS devices. First openings in a photosensitive material are formed over a substrate having a top dielectric in a first die area and a second opening over a gate stack in a second die area having the top dielectric, a hard mask, and a gate electrode. The top dielectric layer is etched to form a semiconductor contact while etching at least a portion the hard mask layer thickness over a gate contact area exposed by the second opening. An inter-layer dielectric (ILD) is deposited. A photosensitive material is patterned to generate a third opening in the photosensitive material over the semiconductor contact and a fourth opening inside the gate contact area. The ILD is etched through to reopen the semiconductor contact while etching through the ILD and residual hard mask if present to provide a gate contact to the gate electrode. | 2014-09-11 |
20140252458 | SEMICONDUCTOR DEVICE HAVING VERTICAL CHANNEL TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A semiconductor device having a substrate; a plurality of pillar structures, wherein each pillar structure includes an active pillar disposed over the substrate; a gate electrode surrounding an outer wall of the active pillar; an interlayer dielectric (ILD) layer insulating adjacent pillar structures; a gate contact penetrating the ILD layer and configured to connect to a sidewall of the gate electrode; and a word line connected to the gate contact. | 2014-09-11 |