37th week of 2008 patent applcation highlights part 63 |
Patent application number | Title | Published |
20080222408 | CIRCUIT FOR PROTECTING MOTHERBOARD - A circuit for protecting a motherboard includes a power button ( | 2008-09-11 |
20080222409 | Memory access system and memory access method thereof - A memory access system for accessing a basic input output system (BIOS) program is provided. The memory access system includes a flash memory, a CPU, a peripheral component interconnect (PCI) slave, an address converter and a flash memory controller. The flash memory stores a number of BIOS data of the BIOS program, and each BIOS data corresponds to a default BIOS address and is allocated in a flash memory type BIOS address. The CPU delivers a BIOS access instruction. The BIOS access instruction corresponds to a default target address of the default BIOS addresses. After the PCI slave interprets the BIOS access instruction, the address converter converts the default target address into a flash memory type target address, which is one of the flash memory type BIOS address. The flash memory controller accesses the BIOS data allocated at the flash memory type target address accordingly. | 2008-09-11 |
20080222410 | Apparatus, method, computer program and recording medium for processing information - An information processing apparatus for transitioning from an operating state for performing a process in accordance with an application program to a pause state and for transitioning back from the pause state to the operating state in one of a plurality of startup methods, may include a startup method determination unit for determining whether the startup method in a transition from the pause state to the operating state is a predetermined one of the plurality of startup methods, a capacity calculation unit for calculating a capacity available in a recording medium loaded on own information processing apparatus if the startup method is the predetermined one of the plurality of startup methods, and a recovery execution determination unit for determining whether to perform a recovery program for recovering an index of a file system managing data, recorded on the recording medium, based on the calculated capacity available in the recording medium. | 2008-09-11 |
20080222411 | SYSTEM FOR MANAGING PROGRAM APPLICATIONS STORABLE IN A MOBILE TERMINAL - Management server | 2008-09-11 |
20080222412 | Network data security system and protecting method thereof - The invention presents a network data security system and a protecting method applied in network data transmission. Meanwhile the network data security system includes a client, an authentication dispatching server and a number of distributed servers. The authentication dispatching server includes a first determination device and a user certificate generator; and each distributed server includes a second determination device, a second user certificate generator and a processor. The method for protecting data of the present invention introduces the authentication dispatching server providing the client with a user certificate in a valid period of time and further introduces an updated certificate mechanism for preventing the user certificate from being stolen and further preventing network data from being let out. | 2008-09-11 |
20080222413 | METHOD AND APPARATUS FOR INTEGRATED PROVISIONING OF A NETWORK DEVICE WITH CONFIGURATION INFORMATION AND IDENTITY CERTIFICATION - According to one aspect, a provisioning server comprises a configuration module that configures a network device and an identification certification module that certifies the identity of the network device. With use of the provisioning server, the network device does not require configuration with network connectivity in order to obtain its certified identity. In one embodiment, configuration module configures the device for operation at the device's point of deployment in a network. In one embodiment, the identity certification module is configured to generate a digital certificate for the network device and the configuration module is configured to automatically configure the network device based on its digital certificate. The provisioning server is coupled to the network device with a secure communication link. As a result, a more trusted network device is ultimately deployed into its network of operation. | 2008-09-11 |
20080222414 | Transparent Authentication of Continuous Data Streams - A system, apparatus and method for transparently authenticating continuous data streams. A continuous data stream is divided into data blocks. Block authentication code(s) are determined using the data in the data blocks, a hash function and a key. The block authentication code(s) are embedded into the data block(s) by adjusting the timing between the packets in the data block(s). Timing delays may be used to separate the blocks. The continuous data stream may be received and authenticated by comparing an extracted block authentication code with a new calculated content-based block authentication code. | 2008-09-11 |
20080222415 | AGILE NETWORK PROTOCOL FOR SECURE COMMUNICATIONS WITH ASSURED SYSTEM AVAILABILITY - A plurality of computer nodes communicate using seemingly random Internet Protocol source and destination addresses. Data packets matching criteria defined by a moving window of valid addresses are accepted for further processing, while those that do not meet the criteria are quickly rejected. Improvements to the basic design include (1) a load balancer that distributes packets across different transmission paths according to transmission path quality; (2) a DNS proxy server that transparently creates a virtual private network in response to a domain name inquiry; (3) a large-to-small link bandwidth management feature that prevents denial-of-service attacks at system chokepoints; (4) a traffic limiter that regulates incoming packets by limiting the rate at which a transmitter can be synchronized with a receiver; and (5) a signaling synchronizer that allows a large number of nodes to communicate with a central node by partitioning the communication function between two separate entities. | 2008-09-11 |
20080222416 | Secure Network Connection - Implementations described and claimed herein provide a secure network connection for remote access, e.g., to building automation systems. A secure network connection may be established according to one implementation between a remote client and a system host for the building automation system. The system host provides its network address to a security host. When the remote client desires access to the system host, the remote client requests the network address from the security host. The security host authenticates the remote client as an authorized user. If the remote client is an authorized user, the security host provides the network address and a security key to the remote client. The remote client then uses the network address to request access to the system host. The system host authenticates the remote client by requesting the security host to verify the security key before granting the remote client access to the system host. | 2008-09-11 |
20080222417 | Method, System, And Apparatus For Nested Security Access/Authentication With Media Initiation - The disclosure details a nested security access system that manages access points/verification requests to create a series of layered security applications for securing access/user identification data. The NSA system works in coordination with an access point/verification module to generate a series of instructions as a login/verification module that may be executed locally. The login/verification module is executed by the access point/verification module to create a system user access/verification data entry form. Depending on the implementation, the access point/verification module may be configured to accept typed text or clicked image access/verification data, token access/verification data or selected image sequence access/verification data. The process of selected image sequence access involves the system user selecting a series of images that represent individual elements of a password without having to type the information into a data entry form. | 2008-09-11 |
20080222418 | Signature Generation Device and Signature Verification Device - A signature generation apparatus capable of preventing transcript attack on signature data is provided. The signature generation apparatus performing a digital signature operation with the use of a signature key: stores the signature key; performs the digital signature operation on signature target data with the use of the signature key to generate signature data; counts the cumulative count of digital signature operations having been performed by the signature generation unit with the use of the signature key; judges whether the cumulative count has reached a predetermined count; and inhibits the use of the signature key in the digital signature operation from then onward in a case where the judgment unit determines that the cumulative count has reached the predetermined count. | 2008-09-11 |
20080222419 | Content Management of Public/Private Content, Including Use of Digital Watermarks to Access Private Content - A public version of content includes information to access a private version. The private version is typically of higher value, as it is a complete version and/or of higher audio or video quality than the public version. The public version can be shared or played without restriction, which enables the content to be promoted, yet provides an incentive for the user to access the private version. The public version can include information that enables a user to obtain software necessary to get the private version. In addition, the public version can include a digital watermark used to access the private version. | 2008-09-11 |
20080222420 | Systems and Methods for Authenticating and Protecting the Integrity of Data Streams and Other Data - Systems and methods are disclosed for enabling a recipient of a cryptographically-signed electronic communication to verify the authenticity of the communication on-the-fly using a signed chain of check values, the chain being constructed from the original content of the communication, and each check value in the chain being at least partially dependent on the signed root of the chain and a portion of the communication. Fault tolerance can be provided by including error-check values in the communication that enable a decoding device to maintain the chain's security in the face of communication errors. In one embodiment, systems and methods are provided for enabling secure quasi-random access to a content file by constructing a hierarchy of hash values from the file, the hierarchy deriving its security in a manner similar to that used by the above-described chain. The hierarchy culminates with a signed hash that can be used to verify the integrity of other hash values in the hierarchy, and these other hash values can, in turn, be used to efficiently verify the authenticity of arbitrary portions of the content file. | 2008-09-11 |
20080222421 | SIGNATURE INFORMATION PROCESSING METHOD, ITS PROGRAM AND INFORMATION PROCESSING APPARATUS - A signature information processing method using a relay apparatus which executes information processing on data containing signature information which is information concerning a signature is provided in order to prevent a signature from being invalidated. A signature information extraction unit conducts extraction processing to extract signature information from the data and store the signature information in the signature information storage unit. A message processing unit executes processing on the data. Thereafter, a signature information substitution unit conducts substitution processing to substitute signature information stored in the signature information storage unit for signature information contained in data obtained after execution of the processing. | 2008-09-11 |
20080222422 | MANAGING ELECTRONIC DOCUMENTS UTILIZING A DIGITAL SEAL - A method for storing electronic documents can include associating a digital seal with at least one electronic document. An image within a user interface can be displayed, wherein the image is a user selectable representation for the digital seal. At least one metadata attribute can be stored as a characteristic related to the digital seal. A storage characteristic of at least one electronic document can be modified based on one or more of the metadata attributes. | 2008-09-11 |
20080222423 | SYSTEM AND METHOD FOR PROVIDING SECURE AUTHENTICATION OF DEVICES AWAKENED FROM POWERED SLEEP STATE - In one embodiment, a system wake-up vector points to a native OS wake-up routine. As the native OS awakens from sleep it passes the wake-up message to the appropriate device drivers. A hardware device whose security context to be restored hooks the appropriate driver in order to intercept and handle the wake-up message. In a second embodiment, a system wake-up vector is redirected to a device specific S3 wake-up subroutine that handles a resume from S3 prior to allowing the call of the native OS wake-up vector. This S3 wake-up subroutine challenges a user for authentication credentials or retrieves them from a hardware device. The supplied credentials are used directly or to decrypt an unlock key from an encrypted key in memory. The unlock key would then be used to unlock the hardware device or fed to the native OS for processing by a device driver capable of unlocking the hardware device. | 2008-09-11 |
20080222424 | Method And Apparatus For Path Concealment In Networks And Graphs - A method for data concealment between two parties in a system, including: permitting the system to solicit one or more data from a user; permitting the system to generate a traversed path in a graph by using the one or more data provided by the user to generate the traversed path; performing a sequence of computations; associating square matrices to each connected node of the plurality of nodes of the traversed path in the graph; initiating each of the sequence of computations with a random vector; performing matrix multiplications at each step in the sequence of computations; obtaining a result vector; using the result vector of a matrix and a vector product of each connected node of the plurality of nodes of the traversed path as a vector in a subsequent node in the traversed path; comparing an outcome of the sequence of computations to a value associated with the traversed path of a correct password. | 2008-09-11 |
20080222425 | System and Method for Expressing and Evaluating Signed Reputation Assertions - A method for expressing and evaluating signed reputation assertions is disclosed. In one embodiment, a first entity receives a request to generate a signed assertion relating to a piece of content. The first entity generates a reputation statement about a second entity from reputation-forming information (RFI) about the second entity available to the first entity. The first entity then generates a signed assertion from the reputation statement and the piece of content at least in part by binding the piece of content to the reputation statement and signing a portion encompassing at least one of the bound piece of content and the bound reputation statement. The signed assertion is then transmitted to a receiving entity. | 2008-09-11 |
20080222426 | Security Device - A security device comprising means for authenticating an entity using biometric data, characterized by means for alternatively authenticating the entity using a security code such as a personal identification number. Also a system configured to grant an authorization upon a successful authorization by the security device, in which the authorization granted after the authentication using the security code is restricted in scope compared to the authorization granted after the authentication using the biometric data. | 2008-09-11 |
20080222427 | DEVICE AND METHOD WITH REDUCED INFORMATION LEAKAGE - The invention is directed to a data-processing system comprising a processor and first encrypted information in a first persistent memory whose level of information leakage is higher than that of a second persistent memory. In the second persistent memory is stored a first cryptographic key for decrypting the first encrypted information, thereby generating therefrom first unencrypted information that is usable by the processor for executing an operation. The same cryptographic key may also be used for encrypting the first unencrypted information, thereby generating the first encrypted information. It is also directed to a method of processing such a data-processing system with an operating system, comprising a writing step for writing first unencrypted information into the first persistent memory, an encryption step for encrypting the first unencrypted information under use of the first cryptographic key, creating therefrom first encrypted information in the first persistent memory, and an access-limitation step for setting the data-processing system to a state in which writing into the first persistent memory is controlled by the operating system. It also relates to a method of executing an operation on such a data-processing system comprising a decryption step for decrypting the first encrypted information under use of the first cryptographic key, thereby generating therefrom first unencrypted information and an execution step for executing an operation by the processor, using the first unencrypted information. | 2008-09-11 |
20080222428 | Method for Securing Authenticity of Data in a Digital Processing System - The invention describes a method and a corresponding digital processing system for ensuring that data is unmodified while reducing the amount of one-time programmable memory in the system. The data is stored in modifiable memory and an authentication value of the data is stored in unmodifiable memory. Before the data is used according to its purpose the digital processing system authenticates that the data is unmodified, for example by using a cryptographic hash algorithm. | 2008-09-11 |
20080222429 | DATA MANAGEMENT SYSTEM - A data management system and method are provided. Specifically, the present invention includes a system for controlling access to data and ensuring that the confidentiality of the data maintained. In addition, the present invention provides a system for updating data so that confidential data, which has become non-confidential, can be identified and exposed. | 2008-09-11 |
20080222430 | Protection of Secure Electronic Modules Against Attacks - A method and apparatus is disclosed for preventing the unintended retention of secret data caused by preferred state/burn in secure electronic modules. Sequentially storing the data, and its inverse on alternating clock cycles, and by actively overwriting it to destroy it, prevents SRAM devices from developing a preferred state. By encrypting a relatively large amount of secret data with a master encryption key, and storing said master key in this non-preferred state storage, the electronic module conveniently extends this protection scheme to a large amount of data, without the overhead of investing or actively erasing the larger storage area. | 2008-09-11 |
20080222431 | Power Adapter Capable of Communicating Digitally with Electronic Devices - A power adapter capable of communicating digitally with a device or a legacy adapter associated with a device is described. The power adapter includes an input port to receive power from a power source, a regulator to convert the received power from the power source, an output port configured to deliver power from the regulator to a device, and a microprocessor configured to communicate digitally with a communication module associated with the device to determine the power requirements of the device. The regulator converts the power from the power source in accordance with the power requirements of the device. A related method of adapting power to a device is also described. | 2008-09-11 |
20080222432 | APPARATUS, SYSTEM AND METHOD FOR SUPPLYING A PORTABLE ELECTRONIC DEVICE BY COMBINING A PLURALITY OF I/O PORTS BELONGING TO AT LEAST ONE OTHER ELECTRONIC DEVICE - Apparatus for combining powers coming from a plurality of I/O ports. Use of the apparatus to power electronic appliances that can require more power than can be delivered by a single I/O port, e.g. in order to charge more quickly energy storage means forming part of the portable electronic appliance connected to the apparatus. | 2008-09-11 |
20080222433 | Method and Apparatus for Supplying Power, and Display Device - A power supply apparatus for a display device includes a power unit for receiving commercial power, converting the commercial power into main power, supplying or cutting off a supply of the main power to the display device, and supplying the main power to a device installed in the display device, a user interface unit for receiving a power control signal from a user, and a control unit for, when the power control signal is inputted, supply or cutting off a supply of the main power to the display device, detecting a power control state of the device, and transmitting the power control signal to the device according to a detected power control state. | 2008-09-11 |
20080222434 | Method of power-aware job management and computer system - Provided is a method used in a computer system which includes at least one host computer, the method including managing a job to be executed by the host computer and a power supply of the host computer, the method including the procedures of: receiving the job; storing the received job; scheduling an execution plan for the stored job; determining, based on the execution plan of the job, a timing to execute power control of the host computer; determining a host computer to execute the power control when the determined timing to execute the power control is reached; controlling the power supply of the determined host computer; and executing the scheduled job. | 2008-09-11 |
20080222435 | POWER MANAGEMENT IN A POWER-CONSTRAINED PROCESSING SYSTEM - Systems and methods are provided for managing power in a processing system. In one embodiment, a target system having a plurality of electronic devices is operated within a net power limit. A local controller detects power consumption for each device, and communicates the power consumption to a power management module. The power management module dynamically apportions the net power limit among the devices, and communicates the apportioned power limit for each device back to the associated local controller. Each local controller enforces the apportioned power limit to an associated device on behalf of the power management module. | 2008-09-11 |
20080222436 | POWER SUPPLY VOLTAGE REGULATOR CIRCUIT AND MICROCOMPUTER - A power supply voltage regulator circuit including a power supply circuit which switches to a first through a fourth state; the first state being the state wherein voltage is supplied to neither a normal circuit nor a backup system circuit based on the combination of logic for the normal circuit power control signal, the second state being the state wherein a primary power supply voltage is supplied to the normal circuit and a secondary power supply voltage is supplied to the backup system circuit, the third state being the state wherein voltage is not supplied to the normal circuit and the secondary power supply voltage is supplied to the backup system circuit, the fourth state being the state wherein the primary power supply voltage is supplied to both the normal circuit and the backup system circuit. | 2008-09-11 |
20080222437 | Low power computer with main and auxiliary processors - An architecture for a computer includes a primary processor that consumes power at a first rate, that is operated when the computer is in an high power mode and that is not powered when the computer is in a low power mode. A primary graphics processor communicates with the primary processor, is operated when the computer is in the high power mode and is not powered when the computer is in the low power mode. A secondary graphics processor communicates with a secondary processor. The secondary processor consumes power at a second rate that is less than the first rate. The secondary processor and the secondary graphics processor are operated when the computer is in the low power mode. | 2008-09-11 |
20080222438 | Apparatus For Automatically Detecting And Differentiating Between USB Host And Device - An apparatus for automatically detecting and differentiating between a USB host and a USB device is provided. In a device with a USB interface, the present invention is coupled with the VBUS pin of the USB interface of the device. By monitoring the voltage change on the VBUS pin, the present invention determines whether the external device connected through the USB interface is a USB host or a USB device. The apparatus for automatically detecting and differentiating between a USB host and a USB device of the present invention includes a voltage detection circuit and a voltage detector. The voltage detection circuit is coupled with the voltage detector and the VBUS pin of the USB interface. The voltage detection circuit can be a voltage splitter. The voltage of voltage detection circuit can be changed according to the voltage signal inputted externally from the VBUS pin of the USB interface. The voltage detector is used to detect the voltage change of node A of voltage detection circuit to determine whether the external device connected through the USB interface is a USB host or a USB device. | 2008-09-11 |
20080222439 | Notebook battery replacement time-saving method and battery detector thereof - A method to save time needed in battery replacement for a Notebook and a battery detector thereof is comprised of having placed the battery detector containing a voltage detection circuit and a register module in the Notebook. When the power level of the battery falls below a first threshold, a prompt menu including a battery replacement option is displayed. When battery replacement option is selected, the Notebook enters a sleep mode and a numeric value marking the need of an automatic power on for the Notebook is stored in the register module. If the voltage detected by the voltage detection circuit is greater than a second threshold, and a numeric value marking the need of an automatic power on for the Notebook is stored in the register module, the Notebook is driven to perform a power on procedure. | 2008-09-11 |
20080222440 | Real time clock calibration system - A temperature-based real time clock calibration system and method for performing the same. The system in one embodiment includes a real time clock calibrated against a reference frequency, a temperature sensor being operative to measure a instantaneous temperature T | 2008-09-11 |
20080222441 | Software programmable timing architecture - One disclosed circuit comprises a clock cycle counter circuit, a memory, and a clock cycle count comparison circuit. The clock cycle counter circuit may be configured to produce an output count. The memory may be configured to store at least first and second count values. The cycle count comparison circuit may be configured to compare the output count with each of the first and second stored count values and to generate a particular type of output event at a node if the output count corresponds to either of the first and second stored count values. Another disclosed circuit comprises a digital pattern generator, a general purpose output controller, at least one memory element, and a selection circuit. The digital pattern generator may be configured to generate a pattern of digital signals at M nodes. The general purpose output controller may be configured to generate general purpose digital signals at N nodes. The at least one memory element may be configured to store particular values for M outputs of the circuit corresponding to the M nodes of the digital pattern generator and for N outputs of the circuit corresponding to the N nodes of the general purpose output controller. The selection circuit may be configured to select, independently for each of the M outputs of the circuit, whether the particular value stored in the at least one memory element or the corresponding output signal of the digital pattern generator is provided on that output, and may be further configured to select, independently for each of the N outputs of the circuit, whether the standby value stored in the at least one memory element or the corresponding output signal of the general purpose output controller is provided on that output. | 2008-09-11 |
20080222442 | CIRCUIT FOR GENERATING OUTPUT ENABLE SIGNAL IN SEMICONDUCTOR MEMORY APPARATUS - A circuit for generating an output enable signal in a semiconductor memory apparatus which can include an interval setting unit capable of delaying a burst length signal in synchronized with a clock, thereby generating an interval setting signal, and a signal generating unit for generating an output enable signal in response to a read command signal and the interval setting signal. | 2008-09-11 |
20080222443 | Controller - The invention relates to a controller for generating control signals (evload_o, odload_o, st_chgclk_o, clk_o , clkorfiford_i) synchronous with a continuous clock signal (clk_hr_i) input to it for a device ( | 2008-09-11 |
20080222444 | Variable instruction width software programmable data pattern generator - A method for generating a digital signal pattern at M outputs involves retrieving an instruction from memory comprising a first set of bits identifying a first group of N outputs that includes fewer than all of the M outputs, and a second set of N bits each corresponding to a respective output included in the identified first group of N outputs. For each of the M outputs that is included in the identified first group of N outputs, the signal at the output is toggled if the one of the N bits corresponding to that output is in a first state and is kept in the same state if the one of the N bits corresponding to that output is in a second state. For each of the M outputs that is not included in the identified first group of N outputs, the signal at that output is kept in the same state. | 2008-09-11 |
20080222445 | BIAS AND RANDOM DELAY CANCELLATION - A system and method for digital communication wherein a host provides a host clock and a clockless device transmits to the host a bit stream synchronized according to the clock at a data rate that is an integer multiple of the clock rate. A training mechanism using training data detects time skew between host clock and bit stream, and a digital skew compensation mechanism compensates, substantially in real time, for the skew and for variations in the skew that may occur with the passage of time, in accordance with a vote among at least three samples of a bit of the bit stream, subsequent sampling being retarded or advanced if, respectively, an early or late sample is in disagreement with the vote. Preferably, the compensation value is selected from at least four possible compensation values, and can be stored in a memory to hasten subsequent restarts of the system. | 2008-09-11 |
20080222446 | STATUS DISPLAY CONTROL APPARATUS - an apparatus comprises a data display unit which causes a display device to output display data that indicates a drawing screen complying with the display request, a reliability decision unit which decides a legality of a transmission source of the display request, and which makes an output request for information capable of confirming a reliability of the display data that the data display unit causes the display device to output, on the basis of a result of the decision, and an output unit which outputs the information capable of confirming the reliability of the display data as complies with the output request from the reliability decision unit, separately from the display data that is caused to be outputted by the data display unit. | 2008-09-11 |
20080222447 | PREVENTION OF FRAME DUPLICATION IN INTERCONNECTED RING NETWORKS - A method for communication includes, in a communication network that includes multiple ring nodes arranged in at least first and second ring networks that are connected by two or more of the ring nodes serving as interconnect nodes, accepting at the two or more interconnect nodes respective copies of a data packet, which is sent from a source user node connected to the first ring network. | 2008-09-11 |
20080222448 | SYSTEM, METHOD AND PROGRAM PRODUCT FOR RECOVERING FROM A FAILURE - System, method and computer program product for recovering from a failure of a computing device. Start up of a first component of the device is monitored and a determination is made whether the first component has started successfully. If so, a second, higher level component of the device is started. Operational data received from the second component is monitored. If the operational data falls outside of an operational boundary, an action is performed on the second component to enable the second component to operate within a preferred operational boundary. If the first component does not start up successfully, a determination is made if start up of the first component is critical to operation of the second component. If so, a corrective action is performed relative to the first component and afterwards, an attempt is made to start up the second component. | 2008-09-11 |
20080222449 | System and Method for Information Handling System Error Recovery - An information handling system recovers from memory errors associated with a memory unit that supports operation of an SMI handler by using another memory unit to support operation of the SMI handler. For example, if an SMI handler detects an error associated with a DIMM that supports operation of the SMI handler, then an SMI handler location module moves the SMI handler to another DIMM. For instance, a jump command is activated to jump to a pre-existing copy of the SMI handler stored at another DIMM. As another example, a relocation of the SMI handler to another DIMM is performed by changing address information used by the chipset and CPUs to run the SMI handler. | 2008-09-11 |
20080222450 | Zero-penalty RAID controller memory leak detection and isolation method and system utilizing sequence numbers - A method and system for detecting and isolating memory leak in RAID controllers utilizing sequence numbers. The system monitors whether the count of un-freed memory blocks for a sequence number (SN) zone (after a start-of-day SOD operation, but smaller than the current sequence number zone) is not eventually decremented to zero. The memory leak can be detected when un-freed memory blocks exist and follow a similar pattern with respect to all other adjacent SN zones. The detected memory leak can be isolated utilizing shell commands, task information, caller information, sequence number, memory allocation size and a pointer to the next allocated memory block. | 2008-09-11 |
20080222451 | ACTIVE SPAM TESTING SYSTEM - A method and system for introducing spam into a search engine for testing purposes is provided. An active spam testing system receives from a tester a specification of spam that is to be introduced into the search engine for testing purposes. The testing system may then generate auxiliary data structures for storing indications of the spam that is to be introduced. A search engine has original data structures that may include a content index and a link data structure. The testing system stores the indications of the spam in the auxiliary data structures so that use of the search engine for non-testing purposes is not affected. When the search engine is used for testing purposes, the search engine generates search results based on a combination of the original data structures and the auxiliary data structures. | 2008-09-11 |
20080222452 | TEST APPARATUS FOR TESTING A CIRCUIT UNIT - Test apparatus for testing a circuit unit. A first test device is arranged outside the circuit unit. A second test device, which is arranged integrally with the circuit unit, has a sample-and-hold unit for sampling at least one voltage value of an output signal output from the circuit unit and for holding the sampled voltage value, and a logic unit for driving the sample-and-hold unit. The voltage value sampled by the second test device is fed to the first test device as a test result signal. | 2008-09-11 |
20080222453 | METHOD FOR INTEGRATING EVENT-RELATED INFORMATION AND TRACE INFORMATION - A method for emulating and debugging a microcontroller. In one embodiment, an event thread is executed on an emulator that operates in lock-step with the microcontroller. Event information is sampled at selected points. Trace information is also recorded at the selected points. As such, the event information and trace information are effectively pre-filtered. Accordingly, it is not incumbent on a designer to read and understand the event and trace information and sort out the information that is of interest. Instead, this task is essentially done automatically, helping the designer and reducing the probability of error. Furthermore, because only selected event and trace information is recorded, the resources of the in-circuit emulator system are not taxed. | 2008-09-11 |
20080222454 | PROGRAM TEST SYSTEM - An improved automated software testing system provides the ability to generate and reuse test cases over multiple platforms. Keywords and natural language are used in test case creation, simplifying the process for non-technical business users. Business users can write test cases without scripts. Test cases can be generated even before the application to be tested is available. Data substitution provides ability for test cases to adapt to changing data. Abstraction allows use of all third-party and custom software test tools to be incorporated. Persistent data handling allows capture of data generated during test execution for later use. Testing can be performed entirely automatically or can incorporate some manual interaction. Test results, screen captures of the system tested, along with environment and machine variables are saved in results logs for later review. | 2008-09-11 |
20080222455 | Reporting diagnostic information for code of an application program interface - A technology for reporting diagnostic information for code of an application program interface is disclosed. In one method approach, diagnostic information for a line of code in a file associated with an application program interface is received. The diagnostic information includes a designation of the line of code. The diagnostic information is stored in a fixed sized buffer. Efficient use of memory is provided without requiring elimination of other diagnostic information previously stored in the fixed sized buffer. | 2008-09-11 |
20080222456 | Method and System for Implementing Dependency Aware First Failure Data Capture - A method and system for implementing failure data capture in a system having multiple components and where the components have processing dependencies with respect to other of the components. Trace data is collected for a first of the components using failure data capture data tracing. In response to detecting a failure condition in the first component, and in response to further determining that the first component is operating in a fail dependency mode, a correlation database that correlates errors' failure conditions with one or more of the multiple components is accessed to determine whether the correlation database specifies a correlation between the failure condition and at least one of the multiple components. Responsive to the correlation table specifying a correlation between the failure condition and one or more of the components, fail messages are sent only to the components for which the correlation table specifies the correlation | 2008-09-11 |
20080222457 | ELECTRONIC DATA PROCESSING SYSTEM AND METHOD FOR MONITORING THE FUNCTIONALITY THEREOF - A method for monitoring of the functionality of an EDP system that is monitored in portions thereof by respectively associated agents that are designed to evaluate errors and to send error messages should increase the operating security in an EDP system. Each agent is monitored by a simulated error being sent to the agent and the reaction of the agent being evaluated. | 2008-09-11 |
20080222458 | DATA PROTECTING METHOD OF STORAGE DEVICE - A data protection method of a storage device, applied in a computer having a storage device, is provided. The storage device is consisted of a plurality of blocks. The method includes the following steps. When a data containing a plurality of bit data is stored in the storage device in the computer, the stored bit data is checked bit by bit. If an incorrect bit data is checked, the data in the block containing the incorrect bit data is backed up to a reserved block. Therefore, the memory capacity of the storage device is not occupied while backing up data, so as to improve the reliability of the computer. | 2008-09-11 |
20080222459 | Methods, Systems, and Products for Verifying Integrity of Web-Server Served Content - Methods, systems, and products are disclosed for verifying the integrity of web server content. A client-side integrity verification of a web page communicated from a web server to a client computer is received. A server-side error in the web page is received from the web server. The results of the client-side integrity verification are merged with the server-side error. The results of the client-side integrity verification and the server-side error are presented. | 2008-09-11 |
20080222460 | Memory test circuit - A memory test circuit is provided, comprising: an output data selector configured to receive the plurality of read data bits and output a fraction of the plurality of read data bits as a plurality of fractional data bits; and a control circuit configured to select a set of bit positions in the plurality of read data bits whose corresponding values will form the plurality of fractional data bits, wherein the selected set of bit positions is selectable from a plurality of possible sets of bit positions, each actual bit position in the plurality of read data bits being contained in at least one of the possible sets of bit positions, and wherein a fractional length of the plurality of fractional data bits is smaller than a full length of the plurality of read data bits. | 2008-09-11 |
20080222461 | APPARATUS AND METHOD FOR CALCULATING ERROR METRICS IN A DIGITAL COMMUNICATION SYSTEM - A method and an apparatus for calculating an error metric in a digital communication receiver. In the receiver, an input data stream is used to generate at least one input bit stream. The combinational logic unit performs an error-check operation on delayed and current bits of the input bit stream using a polynomial error-check equation previously determined. Finally, an accumulator is used to accumulate a number of trials with respect to the error check operation and generates a nominal error-check number based on the number of the correct trials. | 2008-09-11 |
20080222462 | IMAGE FORMING SYSTEM, IMAGE PROCESSING APPARATUS, DETERMINATION DEVICE, AND IMAGE PROCESSING METHOD - An object of the present invention is to provide an image forming system, an image processing apparatus, a determination device, and image processing method that are capable of preventing users' convenience from reducing even when an image forming apparatus prints a coded image with a low print precision. A first MFP is connected through a LAN to a second MFP for performing error-correcting coding of original information, for creating a coded image by imaging the original information with the error-correcting code, and for forming the created coded image on a sheet. The first MFP extracts the original information from the coded image on the sheet obtained by reading the sheet on which the coded image is formed. Thereafter, the first MFP transmits to the second MFP an error detection rate at the time when the original information is extracted. | 2008-09-11 |
20080222463 | APPARATUS, METHOD AND PRODUCT FOR TESTING COMMUNICATIONS COMPONENTS - An apparatus, method and product for independently testing communications components are disclosed. A testing apparatus is provided that has a test control component which includes an input configured to receive a test script, an upper interface coupling and a lower upper interface coupling. In operation, a protocol stack component to be tested is coupled to the test control component via upper and lower interfaces. | 2008-09-11 |
20080222464 | Structure for System for and Method of Performing High Speed Memory Diagnostics Via Built-In-Self-Test - A design structure for a system for and method of performing high speed memory diagnostics via built-in-self-test (BIST) is disclosed. In particular, a test system includes a tester for testing an integrated circuit that includes a BIST circuit and a test control circuit. The BIST circuit further includes a BIST engine and fail logic for testing an imbedded memory array. The test control circuit includes three binary up/down counters, a variable delay, and a comparator circuit. A method of performing high speed memory diagnostics via BIST includes, but is not limited to, presetting the counters of the test control circuit, presetting the variable delay to a value that is equal to the latency of the fail logic, setting the BIST cycle counter to decrement mode, presetting the variable delay to zero, re-executing the test algorithm and performing a second test operation of capturing the fail data, and performing a third test operation of transmitting the fail data to the tester. | 2008-09-11 |
20080222465 | Checkpointing user design states in a configurable IC - Some embodiments provide a configurable integrated circuit (IC) that has several configurable circuits and several user design state (UDS) circuits. The UDS circuits store user-design state values. The configurable IC also includes a debug network communicatively coupled to the UDS circuits. The debug network is for retrieving the user-design state values of several UDS circuits at various stoppages of the operation of the IC without retrieving configuration data that is used to configure the configurable circuits of the IC. The retrieved user-design state values at each stoppage are used as the checkpointed state of the IC while debugging the IC. In some embodiments, the debug network allows the checkpointing of only certain portions of the configurable IC. | 2008-09-11 |
20080222466 | Meeting point thread characterization - An apparatus associated with identifying a critical thread based on information gathered during meeting point processing is provided. One embodiment of the apparatus may include logic to selectively update meeting point counts for threads upon determining that they have arrived at a meeting point. The embodiment may also include logic to periodically identify which thread in a set of threads is a critical thread. The critical thread may be the slowest thread and criticality may be determined by examining meeting point counts. The embodiment may also include logic to selectively manipulate a configurable attribute of the critical thread and/or core upon which the critical thread will run. | 2008-09-11 |
20080222467 | METHOD OF CONTROLLING A TEST MODE OF CIRCUIT - A test vector decode circuit includes a lockout circuit to prevent inadvertent latching of output vectors. The test vector decode circuit is driven by an additional output vector from the test vector decode circuit. The additional output vector, as well as the other output vectors, undergo at least one latching. The signal transmitted by the additional output vector as a result of the final latching activates the lockout circuit. The test vector decode circuit also receives a supervoltage signal. Only by turning off the supervoltage signal can all of the output test vectors be reset, including the additional output vector. | 2008-09-11 |
20080222468 | Method and Dual Interlocked Storage Cell Latch for Implementing Enhanced Testability - A method and a Dual Interlocked Storage Cell (DICE) latch implementing enhanced testability includes an L1 latch and an L2 latch coupled to the L1 latch. Each L1 latch and each L2 latch includes redundant latch structures. A separate output is provided with the redundant L2 latch. The DICE latch includes a Redundant Test Latch Enable (RTLE) input. Each L1 latch and each L2 latch includes a path selector control in the redundant latch structures controlled by the RTLE input providing each of the redundant latch structures in a scan path during a test mode. | 2008-09-11 |
20080222469 | Method and Dual Interlocked Storage Cell Latch for Implementing Enhanced Testability - A method and Dual Interlocked Storage Cell (DICE) latch for implementing enhanced testability, and a design structure on which the subject DICE latch circuit resides are provided. DICE latch includes an L1 latch and an L2 latch are coupled to the L1 latch. Each L1 latch and each L2 latch includes redundant latch structures. A separate output is provided with the redundant L2 latch. The DICE latch includes a Redundant Test Latch Enable (RTLE) input. Each L1 latch and each L2 latch includes a path selector control in the redundant latch structures controlled by the RTLE input providing each of the redundant latch structures in a scan path during a test mode. | 2008-09-11 |
20080222470 | SCAN TEST CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT AND SCAN ENABLE SIGNAL TIME CONTROL CIRCUIT - A SCAN test circuit for giving a semiconductor integration circuit a scan test includes a scan enable signal generating device that generates scan enable signals based on a scan enable external input signal, a clock generator that generate launch and capture clocks for collectively detecting a delay malfunction at a practical operation speed, and a controller configured to control the clock generator based on the scan enable signals. | 2008-09-11 |
20080222471 | CIRCUITRY TO PREVENT PEAK POWER PROBLEMS DURING SCAN SHIFT - In some embodiments, a chip includes first and second scan chain segments each including registers and multiplexers to provide to the registers scan input signals during scan input periods and captured output signals during a capture periods. The chip also includes circuitry to provide first and second test clock signals to the registers of the first and second scan chain segments, respectively, wherein the second test clock signal is provided by a different signal path in the circuitry during the scan input periods than during the capture periods, and during the scan input periods the second test clock signal is skewed with respect to the first test clock signal. Other embodiments are described and claimed. | 2008-09-11 |
20080222472 | METHOD FOR AUTOMATIC TEST PATTERN GENERATION FOR ONE TEST CONSTRAINT AT A TIME - A method for automatically generating test patterns for an IC device includes initially generating a subset of available test patterns according to each of a plurality of test constraints for the IC device, determining an incremental amount of total test coverage of the IC device attributable to each of the test constraints as a result of the initially generated subset of test patterns therefor; determining the test constraint initially providing the largest amount of incremental test coverage, and thereafter generating another subset of test patterns therefor; and iteratively determining the current test constraint providing the largest amount of incremental test coverage, and continuing to generate additional test patterns therefor until one or more test exit criteria is reached. | 2008-09-11 |
20080222473 | TEST PATTERN GENERATING DEVICE AND TEST PATTERN GENERATING METHOD - An apparatus for LSI test has a risk place extraction unit supplied with a design information of the LSI to specify a place by estimating an error in LSI operation based on the design information of the LSI to write the place on a risk place list, and a pattern generator unit coupled to the risk extraction unit to generate a test pattern responsive to the risk place list, wherein the pattern generator unit generates the test pattern with an operation of the LSI being controlled to be lower than a predetermined threshold to prevent the error in LSI operation from occurring. | 2008-09-11 |
20080222474 | Pseudorandom number generator, semiconductor integrated circuit, pseudorandom number generator control apparatus, pseudorandom number generator control method, and computer product - In a linear feedback shift register (LFSR), a four-bit shift register mainly using F/Fs is formed and an XOR circuit that feeds back an exclusive OR of a first bit and a last bit to the first bit is also provided, thereby outputting a test pattern having a maximum cycle of 15. A phase change circuit that can perform arbitrary phase change of a test pattern based on input of a control signal having a maximum clock number 4 and an average clock number log | 2008-09-11 |
20080222475 | METHOD AND APPARATUS FOR COMPENSATING FOR PACKET LOSS - A client, system, and method are provided to compensate for the loss of multicast data packets. When data packets transmitted to two or more clients are lost, a client determines whether compensation for the data packet is needed; if so, the client requests other clients to compensate, receives a compensated data packet, and performs packet rearrangement. To process a request for compensation for a data packet, a first client receiving such a request transmits the lost data packet to the second client so as not to collide with transmission by a third client which also received the request from the second client. Accordingly, if a client loses a data packet, it can be compensated for, preventing reproduction of multimedia data from interruption due to the loss. Also, since clients, not the server, compensate for the lost packet, it is possible to avoid interruptions in data transmission from the server. | 2008-09-11 |
20080222476 | UTILIZING A NETWORK TO CORRECT FLAWED MEDIA DATA - A system and method of utilizing a network to correct flawed media data. The media device includes a processor, a memory, a network adapter, a removable media interface, an error-correction module, and a communication module. The network device enables the media device to connect to the network and server. The removable media interface enables a user to couple a removable medium to the media device. After a user inserts a removable medium into the removable media interface, the processor and error-correction module examines the removable medium for physical errors. If the number of detected errors exceeds a predetermined threshold, the media device, via the network adapter and the communication module, queries a server for correction data. This correction data may be utilized by the media device to enable successful processing of the data stored on the removable medium. | 2008-09-11 |
20080222477 | Communication system using communication network and communication method - A communication system for guaranteeing only one each of two processing operations, correlated with each other and executed on different devices. A server has a unit which, on receipt of a first processing request, with identification information, executes this processing only once for one item of the identification, and a unit for transmitting a first processing completion notice to the transmission source of the processing request on completion of the first processing or on re-receipt of the processing request for the first processing with the same identification of the completed first processing. The client has a server, a unit for transmitting the processing request for first processing with identification information, a unit for executing a second processing, previously correlated with the first processing, on receipt of the completion notice, and a unit for re-transmitting a processing request on detection of an error before receipt of a transmitted completion notice. | 2008-09-11 |
20080222478 | Retransmission method and wireless communication system - Disclosed herewith is a communication method employed for a wireless communication system. The method controls retransmission in case where wireless communication between a data transmitter and a data receiver in the system is unstable, thereby suppressing increasing of a communication delay time that might otherwise be caused by the retransmission control, thereby reducing transmission error occurrence. The transmitter node transmits a wireless signal including data while the receiver node receives the wireless signal and checks the received signal for error existence. If not detecting any error in the received data, the receiver node transmits an ACK (Acknowledgement) signal to the transmitter node. If detecting an error in the received data, the receiver node does not transmit the ACK (Acknowledgement) signal to the transmitter node. At this time, an interception node intercepts the data transmitted from the transmitter node and stores the intercepted data in a data storage unit. And if not detecting the ACK (Acknowledgement) signal transmitted from the receiver node, the interception node retransmits the stored data to the receiver node. If detecting the ACK (Acknowledgement) signal, the interception node does not retransmit the stored data to the receiver node. | 2008-09-11 |
20080222479 | Method and apparatus for handling reordered data packets - The present invention provides a method and apparatus for handling reordered data packets. A method comprises receiving a data packet and determining if the data packet is received out of order. The method further comprises delaying transmission of an acknowledgement indicating that a data packet is missing in response to determining that the data packet is received out of order. | 2008-09-11 |
20080222480 | ERASURE-RESILIENT CODES HAVING MULTIPLE PROTECTION GROUPS - A multiple protection group (MPG) erasure-resilient coding method for constructing MPG codes for encoding and decoding data. The MPG codes constructed herein protect data chunks of data in multiple protection groups and subgroups. In general, the MPG erasure-resilient codes are constructed by locating data chunks into multiple protection groups and assigning at least one parity chunk to each protection group. Basic MPG codes are constructed from existing Maximum Distance Separable (MDS) codes by splitting at least some of the parity chunks into local parities for each of the multiple protection groups and projecting local parities onto each of the groups. Generalized MPG codes have a Maximally Recoverable property that can be used to determine whether an erasure pattern is recoverable or unrecoverable. Generalized MPG codes can recover any erasure pattern that is recoverable. | 2008-09-11 |
20080222481 | MULTIPLE PROTECTION GROUP CODES HAVING MAXIMALLY RECOVERABLE PROPERTY - A multiple protection group (MPG) erasure-resilient coding method for constructing MPG codes for encoding and decoding data. The MPG codes constructed herein protect data chunks of data in multiple protection groups and subgroups. In general, the MPG erasure-resilient codes are constructed by locating data chunks into multiple protection groups and assigning at least one parity chunk to each protection group. Basic MPG codes are constructed from existing Maximum Distance Separable (MDS) codes by splitting at least some of the parity chunks into local parities for each of the multiple protection groups and projecting local parities onto each of the groups. Generalized MPG codes have a Maximally Recoverable property that can be used to determine whether an erasure pattern is recoverable or unrecoverable. Generalized MPG codes can recover any erasure pattern that is recoverable. | 2008-09-11 |
20080222482 | TRANSMITTER AND RECEIVER - There is provided with a transmitter including: an input unit configured to input a data symbol sequence; a block generator configured to sequentially generate data blocks each including a plurality of data symbols by using the data symbol sequence; an addition unit configured to add a duplicate of h data symbols at an end of a first data block to a head of the first data block as a cyclic prefix to obtain a first data block with the cyclic prefix; and a transmission unit configured to transmit the first data block with the cyclic prefix, wherein the block generator uses, as k data symbols that precede the h data symbols at the end of the first data block, a duplicate of k data symbols at an end of a second data block that precedes the first data block. | 2008-09-11 |
20080222483 | Method, system, and apparatus for distributed decoding during prolonged refresh - Methods, apparatuses and systems are disclosed for preserving, verifying, and correcting data in DRAM device during a power-saving mode. In the power-saving mode, memory cells in the DRAM device may be refreshed using a self-refresh operation. This self-refresh operation may allow bit errors to occur in the DRAM device. However, by employing error correction coding (ECC), embodiments of the present invention may detect and correct these potential errors that may occur in the power-saving mode. Furthermore, a partial ECC check cycle is employed to check and correct a sub-set of the memory cells during a periodic self-refresh process that occurs during the power-saving mode. | 2008-09-11 |
20080222484 | Single engine turbo decoder with single frame size buffer for interleaving/deinterleaving - A method and apparatus for decoding and de-interleaving a received encoded and interleaved signal, the method employing and the apparatus including a single decoder coupled to a common buffer, the common buffer size equal to a frame of the received signal and the method further employing, and the apparatus further including, an address controller that causes data to be de-interleaved when read from the buffer and data to be interleaved when written to the buffer. | 2008-09-11 |
20080222485 | ERROR CORRECTION METHODS AND APPARATUS FOR MOBILE BROADCAST SERVICES - An apparatus and method of an outer Forward Error Correcting (FEC) code for a mobile broadcast service based on TD-SCDMA network is disclosed. | 2008-09-11 |
20080222486 | METHODS AND APPARATUS FOR ENCODING AND DECODING LOW DENSITY PARITY CHECK (LDPC) CODES - A novel apparatus and method for encoding data using a low density parity check (LDPC) code capable of representation by a bipartite graph are provided. To encode the data, an accumulate chain of a plurality of low degree variable nodes may be generated. The accumulate chain may then be closed to form a loop twice, once using a low degree variable nodes and once using a higher degree variable which is higher than the low degree variable node, where the higher degree variable node comprises a non-loop-closing edge. In one embodiment, the plurality of low degree variable nodes may have the same permutation on each edge. | 2008-09-11 |
20080222487 | Quantum Key Distribution Mehtod and Communication Apparatus - An error of reception data is corrected using check matrixes for an “Irregular-LDPC code” that are definite and have stable characteristics and a part of shared information is discarded according to error correction information opened to the public. A parity check matrix corresponding to a specific coding rate is extracted from parity check matrix optimized at a coding rate in a desired range while a coding rate is lowered until the error of the reception data is completely corrected, an additional syndrome is generated, and error correction processing is repeatedly executed using the additional syndrome. | 2008-09-11 |
20080222488 | METHOD OF COMPUTING PARTIAL CRCS - Method of generating cyclic redundancy checks (CRCs) for a message with N data blocks. The method includes calculating a partial CRC for an out of order data block and storing the result, generating, using a division operation, a CRC remainder multiplier associated with the out of order data block and storing the result, repeating the calculating and generating steps until all N data blocks for the message are received, and combining the results of the calculating step and the generating step. | 2008-09-11 |
20080222489 | APPARATUS FOR IMPLEMENTING PROCESSOR BUS SPECULATIVE DATA COMPLETION - A method, and apparatus are provided for implementing processor bus speculative data completion in a computer system. A memory controller in the computer system sends uncorrected data from a memory to a processor bus. The memory controller also applies the uncorrected data to error correcting code (ECC) checking and correcting circuit. When a single bit error (SBE) is detected, corrected data is sent to the processor bus a predefined number of cycles after the uncorrected data. | 2008-09-11 |
20080222490 | METHOD, APPARATUS, AND SYSTEM FOR DYNAMIC ECC CODE RATE ADJUSTMENT - A method, apparatus, and system for dynamic adjustment of an error control coding (ECC) code rate are disclosed. In one embodiment, a code rate may be changed from a first code rate to a second code rate in response to a change in a bit error rate. | 2008-09-11 |
20080222491 | FLASH MEMORY SYSTEM FOR IMPROVING READ PERFORMANCE AND READ METHOD THEREOF - A method of transmitting data from a flash memory device to a host includes: detecting whether the data includes an error or not; performing an error correction operation for correcting the data having the error when the error exists in the data; and sequentially storing the data having the error and a plurality of subsequent read data without outputting. The storing of the data is performed during the performing of the error correction operation. | 2008-09-11 |
20080222492 | DATA PROTECTION SYSTEM - The present invention provides systems and methods for logically organizing data for storage and recovery on a data storage medium using a multi-level format. The present invention also provides systems and methods for protecting data stored on data storage medium so that the data may be recovered without errors. | 2008-09-11 |
20080222493 | METHOD AND SYSTEM FOR CONTROL LOOP RESPONSE TIME OPTIMIZATION - A method and system for optimizing a response time of a monitoring loop with forward error correction. Characteristics of a fiber optic communications channel are adjusted based on the number of errors corrected in the FEC decoder. An adaptive BER is calculated much faster by using a signal from an FEC decoder, than by comparing input and output transmission. Thereby, the lag time in adjusting the transmission characteristics of the fiber optic channel is minimized and the overall performance of the system is improved. | 2008-09-11 |
20080222494 | COMMUNICATION APPARATUS, COMMUNICATION METHOD AND COMPUTER READABLE MEDIUM - There is provided with a communication method including: attempting to receive a media packet from a network; storing a received media packet in a first buffering unit; receiving an FEC packet including redundant data to recover a lost media packet and information which specifies a plurality of media packets associated with the redundant data; storing a received FEC packet in a second buffering unit; selecting the FEC packet from the second buffering unit; dividing FEC operation processing to be carried out using the redundant data included in selected FEC packet and the media packets related to the redundant data into a plurality of processes and sequentially carrying out each process so that one process is carried out every time the receiving of a media packet is attempted; and inserting a media packet recovered through the FEC operation processing in the first buffering unit. | 2008-09-11 |
20080222495 | Data storage apparatus - A data storage apparatus with multiple-modes for error detecting and correcting is disclosed, comprising a controller, a data storage media, and a multiple-modes error detecting and correcting device, wherein the multiple-modes error detecting and correcting device is provided within the controller, wherein the controller further comprises a ECC register electrically connected with a codec, a status and timing controller, a error formula generator, an error position solver, and a multiple-modes adjusting controller, wherein the multiple-modes adjusting controller can be used to control the codec, the error formula generator, or the error position solver, accordingly, a final-selected-mode error detecting and correcting device can be set up, thus, the detecting circuit can be miniaturized and the detecting efficiency of the error correction code can be improved. | 2008-09-11 |
20080222496 | Secure Protection of Biometric Templates - This invention relates to methods and devices for verifying the identity of a person based on a sequence of feature components extracted from a biometric sample. Thereafter, the feature components are quantized and assigned a data bit sequence in such a way that adjacent quantization intervals have a Hamming distance of 1. The data bit sequences are concatenated into a bit string, and said bit string is combined with a helper data set by using an exclusive disjunction (XOR) operation into a codeword. Finally, the codeword is decoded into a secret V and a secret S is matched with the secret V. | 2008-09-11 |
20080222497 | Decoding method and decoding circuit - An approach to dividing syndrome calculations into two steps and serially processing them requires a long time for the syndrome calculations with respect to an entire decoding process. Therefore, there is disclosed an error correction decoding circuit for a playing signal having a code sequence having a decoding unit generating first decoded signal and second decoded signal based on the code sequence and an error correction unit performing error correction for the second signal in response to the first signal. | 2008-09-11 |
20080222498 | SEQUENTIAL DECODING METHOD AND APPARATUS THEREOF - A sequential decoding method and a decoding apparatus are provided. According to the method, an open stack is adopted for storing a plurality of paths. When the codeword generated by an internal decoder in the decoding apparatus is incorrect, a codeword is generated again by using the paths stored in the open stack. Accordingly, the complexity of decoding is reduced. | 2008-09-11 |
20080222499 | CYCLIC COMPARISON METHOD FOR LOW-DENSITY PARITY-CHECK DECODER - The present invention discloses a cyclic comparison method for an LDPC decoder, which applies to the comparators used in an LDPC decoder. According to the cyclic comparison algorithm of the present invention, the nth element of the input k elements, wherein n=1, . . . , k, is sequentially removed by the corresponding comparator to obtain k first series. Next, pairs of two elements selected from the k elements are used to form k second series. The preceding step is repeated k×log | 2008-09-11 |
20080222500 | Data relay apparatus, data relay method and data relay integrated circuit - According to an aspect of an embodiment, a data relay apparatus for transferring writing data and an associated check code sequentially sent from a host into a memory device, said writing data containing a plurality of fields classified by the kind of information in said writing data, comprising: a memory for storing said writing data and said check code for checking an error of said writing data; a calculating module for calculating said check code to determine whether the writing data sent from the host contains an error; a transfer module for transferring the writing data into the memory, the transferring of the writing data into the memory being initiated before determination by the calculating module. | 2008-09-11 |
20080222501 | Analyzing Test Case Failures - Apparatus and method for categorizing test failures are disclosed. In one embodiment, a data set of a current test failure is compared with the data sets of historical test failures to result in a set of correspondence values. The current test failure is categorized with respect to the historical test failures at least in part on the basis of the correspondence values. | 2008-09-11 |
20080222502 | ERROR DETERMINING APPARATUS AND METHOD - An error determining apparatus includes an Error Detection Code (EDC) error detector to detect an EDC error of data read from an optical disk, a continuity error detector to detect a continuity error of a currently decoded address by comparing the currently decoded address and a previously decoded address, and an error determiner to receive information on the previously determined error state and to determine a final error state of the currently decoded address of the optical disk based on the EDC error detected by the EDC error detector, the continuity error detected by the continuity error detector, and the previously determined error state. | 2008-09-11 |
20080222503 | RENDERING OF TWO-DIMENSIONAL MARKUP MESSAGES - Embodiments of the present invention provide methods, systems, and apparatuses configured to receive or retrieve markup data associated with a message formatted for two-dimensional (2D) rendering, virtually render, by a first rendering module, the message in a non-displayed image in accordance with the markup data, and render, by a second rendering module, a three-dimensional (3D) object in a 2D display environment including texturing the non-displayed image on a surface of the 3D object in order to render the message. Other embodiments are also described. | 2008-09-11 |
20080222504 | SCRIPT-BASED SYSTEM TO PERFORM DYNAMIC UPDATES TO RICH MEDIA CONTENT AND SERVICES - A system and method is provided for delivering content to a client device including at least one script without at least one of embedding the at least one script within a web page and referencing the at least one script from the web page. A signal is transmitted to a client device, the signal carrying within a packet stream, a multimedia presentation specified using a markup language and comprised of at least a single data unit. The single data unit includes at least one of a scene content and a scene update, the scene update including at least one of a scene command and a script fragment. | 2008-09-11 |
20080222505 | METHOD OF CAPTURING A PRESENTATION AND CREATING A MULTIMEDIA FILE - According to the preferred embodiment of the invention, the method of capturing a presentation from a presentation program and creating a multimedia file includes the steps of capturing an audio file having a time structure; capturing user commands for the presentation program; creating chapters and assigning chapter markers within the time structure of the audio file based on the timing of the user commands; receiving an image set associated with the presentation; associating a particular image of the image set with a particular chapter of the audio file based on the timing of the user commands, and creating a multimedia file based on the audio file, the assigned chapter markers, and the associated images. | 2008-09-11 |
20080222506 | Minimizing Accesses to a Repository During Document Reconstitution in a Content Management System - A content management system (CMS) provides a way to minimize accesses to a repository when reconstituting a document. When a document is first reconstituted, the CMS reads links in the document, reads the corresponding objects from the repository, then stores the values of those objects in fallback elements in the document. In addition, a list is generated that provides both original links to the objects in the repository and voidable links to those object, and the document is then modified, if needed, to reference the voidable links. When the document needs to be subsequently reconstituted, the repository is queried to determine which of the objects corresponding to the original links have not changed since the last reconstitution. If the object has not changed, the voidable link in the list is invalidated for the object, causing the fallback element to be used without accessing the repository. | 2008-09-11 |
20080222507 | METHOD AND SYSTEM FOR DECOMPOSING A SPREADSHEET - In one embodiment, the invention provides a method comprising receiving at least one spreadsheet file corresponding to a spreadsheet having at least one constituent spreadsheet object, the spreadsheet file being encoded in a file format capable of being rendered by a spreadsheet program; decomposing the at least one spreadsheet file into its constituent spreadsheet objects; and saving the spreadsheet objects in a database as database objects. | 2008-09-11 |