37th week of 2015 patent applcation highlights part 55 |
Patent application number | Title | Published |
20150255496 | SOLID-STATE IMAGING DEVICE AND MANUFACTURING METHOD OF THE SAME, AND ELECTRONIC APPARATUS - The present disclosure relates to a solid-state imaging device and a manufacturing method of the same, and an electronic apparatus, capable of more reliably suppressing occurrence of color mixing. | 2015-09-10 |
20150255497 | SHARED ACTIVE PIXEL SENSOR - A shared active pixel sensor with a shared photodiode, a shared sense node, a transfer gate, a shared reset gate and a shared source follower gate is disclosed. A shared photodiode includes at least a first signal node and a second signal node. A shared sense node electrically connected to the shared photodiode. A transfer gate disposed between the first signal node and the shared sense node to control the first signal node and the shared sense node. A shared reset gate is electrically connected to the shared sense node and a shared source follower gate reads a photocurrent from the shared photodiode. | 2015-09-10 |
20150255498 | SOLID-STATE IMAGING DEVICE - According to one embodiment, a solid-state imaging device includes a semiconductor layer, an organic photoelectric conversion layer, and microlenses. A plurality of photoelectric conversion elements are provided in the semiconductor layer. The organic photoelectric conversion layer is provided on a light receiving surface of the semiconductor layer, absorbs and photoelectrically converts light of a predetermined wavelength region, and transmits light of a wavelength region except for the predetermined wavelength region. The microlenses are provided at positions facing the respective light receiving surfaces of the plurality of photoelectric conversion elements with the organic photoelectric conversion layer interposed therebetween, and concentrate incident light on the photoelectric conversion elements. | 2015-09-10 |
20150255499 | CHIP PACKAGE AND METHOD OF FABRICATING THE SAME - A chip package includes a semiconductor chip, insulation layer, redistribution layer and packaging layer and is formed with a cavity. The semiconductor chip has an electronic component and a conductive pad. The conductive pad and the electronic component are disposed on an upper surface of the semiconductor chip and electrically connected. The cavity opens from a lower surface of the semiconductor chip and tapers toward the upper surface to expose the conductive pad. The insulation layer coats the lower surface and a portion of the cavity. The insulation layer is formed with a gap to expose the conductive pad. The redistribution layer coats the lower surface and a portion of the cavity and is electrically connected to the conductive pad through the gap. The packaging layer coats the lower surface and a portion of the cavity. | 2015-09-10 |
20150255500 | OPTICAL APPARATUS AND METHOD FOR MANUFACTURING SAME - A downsized, highly reliable optical apparatus is stably and easily manufactured with high productivity. The optical apparatus includes: an optical device having a principal surface including an optical unit; a transparent member disposed facing the optical unit; a semiconductor device disposed above a back surface of the optical device and electrically connected to the optical device, the back surface being opposite the principal surface; and a resin member provided in a region adjacent to the optical device and the semiconductor device above a surface of the transparent member, the surface of the transparent member facing the optical device. | 2015-09-10 |
20150255501 | SOLID STATE IMAGING DEVICE AND METHOD OF FABRICATING THE SAME - According to one embodiment, a first semiconductor layer is of a first conductivity type. A second semiconductor layer is of the first conductivity type, is provided on the first semiconductor layer and is larger in absorbance coefficient to light rays in a long wavelength region than the first semiconductor layer. A third semiconductor layer is of the first conductivity type, is provided on the second semiconductor layer. A first semiconductor regions are of a second conductivity type, and are located to extend over the respective insides of the first, second and third semiconductor layers, and arranged apart from each other in a first direction parallel to the upper surface of the first semiconductor layer. A element isolation portion is arranged between adjacent ones of the first semiconductor regions. | 2015-09-10 |
20150255502 | SEMICONDUCTOR DEVICES AND METHODS FOR FORMING PATTERNED RADIATION BLOCKING ON A SEMICONDUCTOR DEVICE - Several embodiments for semiconductor devices and methods for forming semiconductor devices are disclosed herein. One embodiment is directed to a method for manufacturing a microelectronic imager having a die including an image sensor, an integrated circuit electrically coupled to the image sensor, and electrical connectors electrically coupled to the integrated circuit. The method can comprise covering the electrical connectors with a radiation blocking layer and forming apertures aligned with the electrical connectors through a layer of photo-resist on the radiation blocking layer. The radiation blocking layer is not photoreactive such that it cannot be patterned using radiation. The method further includes etching openings in the radiation blocking layer through the apertures of the photo-resist layer. | 2015-09-10 |
20150255503 | Image Device and Methods of Forming the Same - A method of forming of an image sensor device includes a patterned hardmask layer is formed over a substrate. The patterned hard mask layer has a plurality of first openings in a periphery region, and a plurality of second openings in a pixel region. A first patterned mask layer is formed over the pixel region to expose the periphery region. A plurality of first trenches is etched into the substrate in the periphery region. Each first trench, each first opening and each second opening are filled with a dielectric material. A second patterned mask layer is formed over the periphery region to expose the pixel region. The dielectric material in each second opening over the pixel region is removed. A plurality of dopants is implanted through each second opening to form various doped isolation features in the pixel region. | 2015-09-10 |
20150255504 | WAFER LEVEL LIGHT-EMITTING DIODE ARRAY - A light emitting diode array is provide to include: a substrate; light emitting diodes positioned over the substrate, each including a first semiconductor layer, an active layer, and a second semiconductor layer, wherein each light emitting diode is disposed to form a first via hole structure exposing a portion of the corresponding first semiconductor layer; lower electrodes disposed over the second semiconductor layer; a first interlayer insulating layer disposed over the lower electrodes and configured to expose the portion of the first semiconductor layer of corresponding light emitting diodes; upper electrodes electrically connected to the first semiconductor layer through the first via hole structure, wherein the first via hole structure is disposed in parallel with one side of the corresponding second semiconductor layer and the first interlayer insulating layer is disposed to form a second via hole structure exposing a portion of the lower electrodes. | 2015-09-10 |
20150255505 | DISPLAY DEVICE USING SEMICONDUCTOR LIGHT EMITTING DEVICE - A display device including a wiring substrate having a first substrate layer and a second substrate layer, a conductive adhesive layer configured to cover the wiring substrate, a plurality of semiconductor light emitting devices coupled to the conductive adhesive layer and electrically connected to a first electrode and a second electrode. Further, the first electrode is disposed on the first substrate layer, and the second substrate layer has one surface facing the conductive adhesive layer and the other surface covering the first electrode, and an auxiliary electrode electrically connected to the first electrode and the second electrode are disposed on one surface of the second substrate layer. | 2015-09-10 |
20150255506 | SEMICONDUCTOR STORAGE DEVICE - A memory includes a semiconductor substrate. Magnetic tunnel junction elements are provided above the semiconductor substrate. Each of the magnetic tunnel junction elements stores data by a change in a resistance state, and the data is rewritable by a current. Cell transistors are provided on the semiconductor substrate. Each of the cell transistors is in a conductive state when the current is applied to the corresponding magnetic tunnel junction element. Gate electrodes are included in the respective cell transistors. Each of the gate electrodes controls the conductive state of the corresponding cell transistor. In active areas, the cell transistors are provided, and the active areas extend in an extending direction of intersecting the gate electrodes at an angle of (90−a tan(1/3)) degrees. | 2015-09-10 |
20150255507 | METHOD OF FORMING MAGNETIC TUNNELING JUNCTIONS - A method for fabricating an MRAM bit that includes depositing a spacer layer that protects the tunneling barrier layer during processing is disclosed. The deposited spacer layer prevents byproducts formed in later processing from redepositing on the tunneling barrier layer. Such redeposition may lead to product failure and decreased manufacturing yield. The method further includes non-corrosive processing conditions that prevent damage to the layers of MRAM bits. The non-corrosive processing conditions may include etching without using a halogen-based plasma. Embodiments disclosed herein use an etch-deposition-etch sequence that simplifies processing. | 2015-09-10 |
20150255508 | NON-VOLATILE MEMORY DEVICE - According to an embodiment, a nonvolatile memory device includes: a first interconnection layer extending in a first direction; a second interconnection layer extending in a second direction crossing the first direction, the second interconnection layer including a metal-containing layer and a metal ion source layer, and the metal ion source layer being provided on the first interconnection layer side; and a resistance change layer provided in a position where the first interconnection layer and the second interconnection layer cross each other and a metal ion released from the metal ion source layer being capable to be diffused into the resistance change layer. At least part of the second interconnection layer protrudes to the first interconnection layer side in a cross section of the second interconnection layer cut perpendicularly to the second direction. | 2015-09-10 |
20150255509 | NONVOLATILE MEMORY DEVICE - A nonvolatile memory device having a first resistive element coupled between a common node and a bit line; a second resistive element coupled between the common node and a word line; and a pass transistor having a gate coupled to the common node, a first node coupled to a reference voltage, and a second node coupled to an output, wherein the word line is orthogonal to the bit line. | 2015-09-10 |
20150255510 | SEMICONDUCTOR DEVICE - According to one embodiment, a first transistor includes a first semiconductor region, a second semiconductor region, a third semiconductor region, a first gate insulating film, and a first gate electrode. The first semiconductor region is provided in a first semiconductor layer extending in a second direction substantially perpendicular to the surface of the semiconductor substrate from the first line. The second semiconductor region is provided above the first semiconductor region in the first semiconductor layer. The third semiconductor region is provided above the second semiconductor region in the first semiconductor layer. The first gate insulating film covers a first side face of the first semiconductor layer. The first gate electrode covers the first side face of the first semiconductor layer through the first gate insulating film. The first transistor has an asymmetrical structure with respect to a center face of the second semiconductor region in the second direction. | 2015-09-10 |
20150255511 | NONVOLATILE MEMORY DEVICE - According to one embodiment, a plurality of first wirings are arranged along a first direction and a second direction that intersect each other and extending in a third direction perpendicular to the first and second directions. A plurality of second wirings extend in the second direction and are provided at predetermined intervals along the third direction of the first wirings. N channel field-effect transistors are provided at ends of the first wirings. Memory cells are placed at intersections of the first wirings and the second wirings. The memory cells are formed of a variable resistive layer of which the first wiring side is large in resistivity and the second wiring side is small in resistivity. | 2015-09-10 |
20150255512 | NONVOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a plurality of first wirings are disposed in a first direction and a second direction which intersect with each other, and extended in a third direction. A second wiring stack is configured to include second wirings and interlayer insulating films which are extended and alternately stacked in the second direction. A memory cell includes, in the first direction, a first variable resistive layer which is disposed on a side near the first wiring and a second variable resistive layer which is disposed on a side near the second wiring. The second variable resistive layer is disposed between the interlayer insulating films in the third direction, and made of a material which is obtained by oxidizing the second wiring. | 2015-09-10 |
20150255513 | SEMICONDUCTOR MEMORY DEVICE - In accordance with an embodiment, a semiconductor memory device includes a substrate, first and second wirings on the substrate across each other, and a storage element at an intersection of the first and second wirings between the first and second wirings. The storage element includes first and second electrodes having first and second materials, respectively, a first film having a first dielectric constant, and a second film having a second dielectric constant lower than the first dielectric constant. The first film is formed on the first electrode. The second electrode is formed on the first film. The second film is disposed between the second electrode and the first film. An energy difference between a vacuum level and a Fermi level of the second material is equal to or more than an energy difference between the vacuum level and a Fermi level of the first material. | 2015-09-10 |
20150255514 | INTEGRATED CIRCUIT DEVICE - An integrated circuit device according to an embodiment includes a semiconductor substrate, a first semiconductor member and a second semiconductor member provided on the semiconductor substrate, a first electrode disposed between the first semiconductor member and the second semiconductor member, and a second electrode disposed between the semiconductor substrate and the first electrode. The first semiconductor member and the second semiconductor member extend in a first direction perpendicular to an upper surface of the semiconductor substrate. The first semiconductor member and the second semiconductor member are separated in a second direction orthogonal to the first direction. The first electrode extends in a third direction intersecting both the first direction and the second direction. The second electrode extends in the third direction. | 2015-09-10 |
20150255515 | INTEGRATED CIRCUIT DEVICE - An integrated circuit device according to an embodiment, includes a semiconductor member, a first electrode and a second electrode. The semiconductor member includes a first portion of a first conductivity type, a second portion of a second conductivity type, and a third portion of the first conductivity type disposed in this order along a first direction. The first electrode is disposed on a second direction side as viewed from the semiconductor member. The second electrode is disposed on an opposite side of the second direction as viewed from the semiconductor member. An end portion of the second electrode on a first direction side is located in the first direction side rather than that of the first electrode. An end portion of the second electrode on an opposite side of the first direction is located in the first direction side rather than that of the first electrode. | 2015-09-10 |
20150255516 | COMPLEMENTARY METAL OXIDE SEMICONDUCTOR TRANSISTOR AND FABRICATING METHOD THEREOF - A fabricating method of CMOS transistor includes following steps. A first gate and a second gate are formed on a substrate. A gate insulator is formed on the substrate to cover the first and second gates. A first source, a first drain, a second source, and a second drain are formed on the gate insulator. The first source and the first drain are above the first gate. The second source and the second drain are above the second gate. A first channel layer and a mask layer are formed on the gate insulator. The mask layer is on the first channel layer. The first channel layer is above the first gate and contacts with the first source and the first drain. A second channel layer is formed on the gate insulator. The second channel layer is above the second gate and contacts with the second source and the second drain. | 2015-09-10 |
20150255517 | METHOD OF MANUFACTURING ORGANIC EL DEVICE, ORGANIC EL DEVICE AND ELECTRONIC APPARATUS - An organic EL device according to the present application includes a substrate, a plurality of organic EL elements arranged on the substrate, the plurality of organic EL elements including an organic light-emitting layer interposed between an anode and a cathode, a plurality of connection terminals disposed on the substrate, a sealing layer covering the plurality of organic EL elements such that the plurality of organic EL elements lie between the substrate and the sealing layer, and an organic layer formed above the sealing layer. The organic layer and the sealing layer have an opening portion that exposes at least one of the plurality of connection terminals. | 2015-09-10 |
20150255518 | Touch Sensor, Touch Panel, and Manufacturing Method of Touch Panel - To provide a touch sensor including a transistor and a capacitor in which the transistor and the capacitor are electrically connected to each other, the capacitor includes a pair of electrodes and a dielectric layer, the dielectric layer is located between the pair of electrodes, and one of the pair of electrodes includes an oxide conductor layer. To provide a touch panel including the touch sensor, a light-blocking layer, and a display element in which the touch sensor is located more on the display surface side of the touch panel than on the display element side, the light-blocking layer is located more on the display surface side than on the touch sensor side, the display element includes a portion overlapping with the capacitor, and the light-blocking layer includes a portion overlapping with the transistor. | 2015-09-10 |
20150255519 | DISPLAY DEVICE - A display device is provided. The display device includes a transparent display panel; and an optical switching element arranged on the transparent display panel and configured to be switched to one of a transmissive state, a non-transmissive state, and a reflective state, wherein the optical switching element includes a non-transmission layer formed to contact the transparent display panel and configured to switch to the transmissive state or the non-transmissive state, and a reflection layer formed on a first side of the non-transmission layer and configured to switch to the transmissive state or the reflective state. | 2015-09-10 |
20150255520 | Light-Emitting Element, Light-Emitting Device, Electronic Device, and Lighting Device - Provided is a light-emitting device which can emit monochromatic light with high purity due to a microcavity effect and which can emit white light in the case of a combination of monochromatic light. Provided is a high-definition light-emitting device. Provided is a light-emitting device with low power consumption. In a light-emitting device with a white-color filter top emission structure, one pixel is formed of four sub-pixels of RBGY, an EL layer includes a first light-emitting substance which emits blue light and a second light-emitting substance which emits light corresponding to a complementary color of blue, and a semi-transmissive and semi-reflective electrode (an upper electrode) is formed so as to cover an edge portion of the EL layer. | 2015-09-10 |
20150255521 | METHOD FOR PRODUCING A PASSIVE ELECTRONIC COMPONENT, METHOD FOR PRODUCING AN OPTOELECTRONIC ASSEMBLY AND PASSIVE ELECTRONIC COMPONENT - Various embodiments may relate to a method for producing a passive electronic component, including forming a first electrically conductive layer on a substrate, forming a second electrically conductive layer on the first electrically conductive layer, forming a first trench in the first and second electrically conductive layers such that the substrate is exposed in the first trench, wherein the first trench separates a first contact region from a second contact region, applying a dielectric in a structured fashion to the second electrically conductive layer in the first contact region and at least partly to the substrate in the first trench such that the dielectric electrically insulates the first contact region from the second contact region, and applying an electrically conductive electrode layer in a structured fashion to the dielectric above the first contact region and to the second contact region. | 2015-09-10 |
20150255522 | DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME - How a flat panel display is bent by external forces is controlled. A display panel | 2015-09-10 |
20150255523 | ORGANIC LIGHT-EMITTING DIODE (OLED) DISPLAY - An organic light-emitting diode (OLED) display is disclosed. In one aspect, the OLED display includes a plurality of pixels, each including a driving thin film transistor (TFT) formed over a substrate and including a driving gate electrode, a first storage capacitor comprising a first electrode and a second electrode, and a second storage capacitor comprising a third electrode and a fourth electrode. The first electrode is electrically connected to the driving gate electrode and the second electrode is formed over the first electrode and electrically insulated from the first electrode. The third electrode is electrically connected to the first electrode, is formed on a different layer from each of the first and second electrodes, and does not overlap the second electrode. The fourth electrode is formed over the third electrode and electrically insulated from the third electrode. | 2015-09-10 |
20150255524 | Semiconductor Device and a Method of Manufacturing the Same - A reduction in contaminating impurities in a TFT, and a TFT which is reliable, is obtained in a semiconductor device which uses the TFT. By removing contaminating impurities residing in a film interface of the TFT using a solution containing fluorine, a reliable TFT can be obtained. | 2015-09-10 |
20150255525 | DUAL EMITTING DEVICE FOR ACTIVE MATRIX ORGANIC ELECTROLUMINESCENCE - An organic electroluminescence (EL) device is provided, including a transparent substrate and an array of pixels over the transparent substrate. Each of the pixels includes at least one first sub-pixel and at least one second sub-pixel, wherein the at least one first sub-pixel each includes a first organic light emitting diode for providing light in a first direction, and the second sub-pixel each includes a second organic light emitting diode for providing light in a second direction substantially opposite to the first direction. | 2015-09-10 |
20150255526 | ORGANIC LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - Disclosed is an organic light emitting device (OLED) that may include a first electrode on a substrate, the first electrode having a pattern of a plurality of cells, with each cell defined with an emitting area and a non-emitting area; a second electrode facing the first electrode; an organic layer between the first electrode and the second electrode; a short-circuit preventing layer contacting at least a portion of the first electrode; and an auxiliary electrode on the short-circuit preventing layer in the non-emitting area of each cell, wherein an aperture ratio of the short-circuit preventing layer and the auxiliary electrode in each cell is 30% or more. | 2015-09-10 |
20150255527 | MANUFACTURING METHOD OF DISPLAY DEVICE, DISPLAY DEVICE, AND DISPLAY DEVICE FORMATION SUBSTRATE - A manufacturing method of a display device includes forming a pixel in a display area of a panel, forming a transistor circuit in a peripheral area of the panel, the peripheral area being located in the vicinity of the display area, forming a first pad in a part of the peripheral area, forming a second pad in a peripheral area of another panel adjacent to the part of the panel, the second pad being electrically connected to the transistor circuit, performing a driving inspection on the transistor circuit by use of the second pad, and separating the first pad and the second pad from each other after the driving inspection. | 2015-09-10 |
20150255528 | DIELECTRIC REGION IN A BULK SILICON SUBSTRATE PROVIDING A HIGH-Q PASSIVE RESONATOR - Structures and methods of making a dielectric region in a bulk silicon (Si) substrate of a mixed-signal integrated circuit (IC) provide a high-Q passive resonator. Deep trenches within the bulk Si substrate in <100> directions are expanded by wet etching to form contiguous cavities, which are filled by Si oxide to form a dielectric region. The dielectric region enhances the quality (Q) of an overlying passive resonator, formed in metallization layers of the mixed-signal IC. | 2015-09-10 |
20150255529 | SILICON PROCESS COMPATIBLE TRENCH MAGNETIC DEVICE - A mechanism is provided for integrating an inductor into a semiconductor. A circular or other closed loop trench is formed in a substrate with sidewalls connected by a bottom surface in the substrate. A first insulator layer is deposited on the sidewalls of the trench so as to coat the sidewalls and the bottom surface. A conductor layer is deposited on the sidewalls and the bottom surface of the trench so as to coat the first insulator layer in the trench such that the conductor layer is on top of the first insulator layer in the trench. A first magnetic layer is deposited on the sidewalls and bottom surface of the trench so as to coat the first insulator layer in the trench without filling the trench. The first magnetic layer deposited on the sidewalls forms an inner closed magnetic loop and an outer closed magnetic loop within the trench. | 2015-09-10 |
20150255530 | MAGNETIC COUPLING AND CANCELLATION ARRANGEMENT - An inductor arrangement comprises a first inductor formed on a substrate, a second inductor formed on the substrate, a first loop formed on the substrate adjacent to the first inductor and a phasing network connected to the first loop which is arranged to receive an input signal representative of a flow of magnetic flux through the second inductor and to apply a first current to the first loop for generating a flow of magnetic flux for reducing magnetic coupling between the second inductor and the first inductor. A second loop can be formed on the substrate adjacent to the second inductor which is arranged to generate a second current in response to a flow of magnetic flux through the second loop, with the second current being the signal representative of a flow of magnetic flux through the second inductor. | 2015-09-10 |
20150255531 | 3-D Inductor and Transformer - In accordance with an embodiment, a semiconductor device comprises a semiconductor die, an interposer, and conductive bumps bonding the semiconductor die to the interposer. The semiconductor die comprises a first metallization layer, and the first metallization layer comprises a first conductive pattern. The interposer comprises a second metallization layer, and the second metallization layer comprises a second conductive pattern. Some of the conductive bumps electrically couple the first conductive pattern to the second conductive pattern to form a coil. Other embodiments contemplate other configurations of coils, inductors, and/or transformers, and contemplate methods of manufacture. | 2015-09-10 |
20150255532 | RESISTOR STRUCTURE AND METHOD FOR FORMING THE SAME - A metal resistor structure and a method for forming the same are provided. The method includes: providing a substrate including a first and a second metallic plugs disposed in a first and a second regions respectively; forming a first metallic layer on the substrate; forming an insulating material layer on the first metallic layer; patterning the insulating material layer to form a first and a second insulating layer above the first and the second regions respectively; forming a second metallic layer overlaying exposed part of the first metallic layer, the first insulating layer, and the second insulating layer; forming a patterned mask layer on the second metallic layer; and etching, by using the patterned mask layer as a mask, until the substrate is exposed. Accordingly, a capacitor and a metallic resistor are formed on a set of steps, thus processing steps for forming the metallic resistor can be reduced. | 2015-09-10 |
20150255533 | SEMICONDUCTOR STRUCTURE HAVING A CAPACITOR AND METAL WIRING INTEGRATED IN A SAME DIELECTRIC LAYER - Semiconductor structures having capacitors and metal wiring integrated in a same dielectric layer are described. For example, a semiconductor structure includes a plurality of semiconductor devices disposed in or above a substrate. One or more dielectric layers are disposed above the plurality of semiconductor devices. Metal wiring is disposed in each of the dielectric layers. The metal wiring is electrically coupled to one or more of the semiconductor devices. A metal-insulator-metal (MIM) capacitor is disposed in one of the dielectric layers, adjacent to the metal wiring of the at least one of the dielectric layers. The MIM capacitor is electrically coupled to one or more of the semiconductor devices. | 2015-09-10 |
20150255534 | SEMICONDUCTOR DEVICE - A method for forming an oxide that can be used as a semiconductor of a transistor or the like is provided. In particular, a method for forming an oxide with fewer defects such as grain boundaries is provided. One embodiment of the present invention is a semiconductor device including an oxide semiconductor, an insulator, and a conductor. The oxide semiconductor includes a region overlapping with the conductor with the insulator therebetween. The oxide semiconductor includes a crystal grain with an equivalent circle diameter of 1 nm or more and a crystal grain with an equivalent circle diameter less than 1 nm. | 2015-09-10 |
20150255535 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A termination structure located in an outer periphery portion of a semiconductor element includes an N-type drift region formed in a semiconductor substrate and a P-type impurity region formed in an upper surface portion in the N-type drift region. The P-type impurity region has, in macroscopic view, a P-type impurity concentration that decreases from an inner periphery portion toward an outer periphery portion of the termination structure. The P-type impurity region includes, in microscopic view, a plurality of high-concentration regions of the P-type and a low-concentration region surrounding the plurality of high-concentration regions and has a part including the low-concentration regions separate from each other. | 2015-09-10 |
20150255536 | SEMICONDUCTOR DEVICE - A semiconductor device in an embodiment includes a first semiconductor region of a first conductivity type on a cathode electrode and a second semiconductor region of the first conductivity type between an anode electrode and the cathode electrode and in direct contact with the first semiconductor region. A first conductivity type dopant concentration of the second semiconductor region is higher than a first conductivity type dopant concentration of the first semiconductor region. A third semiconductor region of a second conductivity type is between the anode electrode and the second semiconductor region and in direct contact with the second semiconductor region. A fourth semiconductor region is in direct contact with the second semiconductor region and a portion of the third semiconductor region. | 2015-09-10 |
20150255537 | DEEP TRENCH ISOLATION STRUCTURE LAYOUT AND METHOD THEREOF - The embodiments described herein provide a semiconductor device layout and method that can be utilized in a wide variety of semiconductor devices. In one embodiment a semiconductor device is provided that includes a plurality of deep trench isolation structures that define and surround a first plurality of first trench-isolated regions in the substrate, and further define a second plurality of second trench-isolated regions in the substrate. The first plurality of first trench-isolated regions is arranged in a plurality of first columns, with each of the first columns including at least two of the first plurality of first trench-isolated regions. Likewise, the plurality of first columns are interleaved with the second trench-isolated regions to alternate in an array such that a second trench-isolated region is between consecutive first columns in the array and such that at least two first trench-isolated regions are between consecutive second trench-isolated regions in the array. | 2015-09-10 |
20150255538 | SHALLOW TRENCH ISOLATION STRUCTURES - Shallow trench isolation structures are provided for use with UTBB (ultra-thin body and buried oxide) semiconductor substrates, which prevent defect mechanisms from occurring, such as the formation of electrical shorts between exposed portions of silicon layers on the sidewalls of shallow trench of a UTBB substrate, in instances when trench fill material of the shallow trench is subsequently etched away and recessed below an upper surface of the UTBB substrate. | 2015-09-10 |
20150255539 | DUAL SHALLOW TRENCH ISOLATION (STI) FIELD EFFECT TRANSISTOR (FET) AND METHODS OF FORMING - Various embodiments include field effect transistor (FET) structures and methods of forming such structures. In various embodiments, an FET structure includes: a deep n-type well; a shallow n-type well within the deep n-type well; and a shallow trench isolation (STI) region within the shallow n-type well, the STI region including: a first section having a first depth within the shallow n-type well as measured from an upper surface of the shallow n-type well, and a second section contacting and overlying the first section, the second section having a second depth within the shallow n-type well as measured from the upper surface of the shallow n-type well. | 2015-09-10 |
20150255540 | COMPONENT, FOR EXAMPLE NMOS TRANSISTOR, WITH ACTIVE REGION WITH RELAXED COMPRESSION STRESSES, AND FABRICATION METHOD - An integrated circuit includes a substrate and at least one NMOS transistor having, in the substrate, an active region surrounded by a trench insulating region. The transistor, active region and trench insulating region are covered by an additional insulating region. A metal contact extends through the additional insulating region to make contact with the trench insulating region. The metal contact may penetrate into the trench insulating region. | 2015-09-10 |
20150255541 | BACK-END TRANSISTORS WITH HIGHLY DOPED LOW-TEMPERATURE CONTACTS - A back end of line device and method for fabricating a transistor device include a substrate having an insulating layer formed thereon and a channel layer formed on the insulating layer. A gate structure is formed on the channel layer. Dopants are implanted into an upper portion of the channel layer on opposite sides of the gate structure to form shallow source and drain regions using a low temperature implantation process. An epitaxial layer is selectively grown on the shallow source and drain regions to form raised regions above the channel layer and against the gate structure using a low temperature plasma enhanced chemical vapor deposition process, wherein low temperature is less than about 400 degrees Celsius. | 2015-09-10 |
20150255542 | METHODS OF FORMING STRESSED CHANNEL REGIONS FOR A FINFET SEMICONDUCTOR DEVICE AND THE RESULTING DEVICE - One method disclosed includes, among other things, covering the top surface and a portion of the sidewalls of an initial fin structure with etch stop material, forming a sacrificial gate structure around the initial fin structure, forming a sidewall spacer adjacent the sacrificial gate structure, removing the sacrificial gate structure, with the etch stop material in position, to thereby define a replacement gate cavity, performing at least one etching process through the replacement gate cavity to remove a portion of the semiconductor substrate material of the fin structure positioned under the replacement gate cavity that is not covered by the etch stop material so as to thereby define a final fin structure and a channel cavity positioned below the final fin structure and substantially filling the channel cavity with a stressed material. | 2015-09-10 |
20150255543 | STRAINED FinFET BY EPITAXIAL STRESSOR INDEPENDENT OF GATE PITCH - A semiconductor device fabrication process includes forming a fin and a plurality of gates upon a semiconductor substrate, forming sacrificial spacers upon opposing gate sidewalls, forming a mask upon an upper surface of the fin between neighboring gates, removing the sacrificial spacers, recessing a plurality of regions of the fin to create a dummy fin and fin segments, removing the mask, and epitaxially merging the dummy fin and fin segments. The fins may be partially recessed prior to forming the sacrificial spacers. The device may include the substrate, gates, fin segments each associated with a particular gate, the dummy fin between a fin segment pair separated by the wider pitch, and merged epitaxy connecting the dummy fin and the fin segment pair. The dummy fin may serve as a filler between the fin segment pair and may add epitaxial growth planes to allow for epitaxial merging within the wider pitch. | 2015-09-10 |
20150255544 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor device includes first and second second-conductivity-type region groups containing multiple second-conductivity-type regions that are disposed on a first silicon carbide semiconductor layer of a first conductivity type, arrayed in parallel following one direction with a space between each other, and first and second electrodes disposed on the first silicon carbide semiconductor layer and forming a Schottky junction with the first silicon carbide semiconductor layer. The first electrode covers a position where a distance from adjacent first and second second-conductivity-type regions included in a first second-conductivity-type region group, and a distance from a third second-conductivity-type region included in a second second-conductivity-type region group and adjacent to the first and second second-conductivity-type regions, are equal. A Schottky barrier between the first electrode and the first silicon carbide semiconductor layer is larger than a Schottky barrier between the second electrode and the first silicon carbide semiconductor layer. | 2015-09-10 |
20150255545 | Methods of Forming Semiconductor Devices and FinFET Devices, and FinFET Devices - Methods of forming semiconductor devices and fin field effect transistors (FinFETs), and FinFET devices, are disclosed. In some embodiments, a method of forming a semiconductor device includes forming a barrier material comprising AlInAsSb over a substrate, and forming a channel material of a transistor over the barrier layer. | 2015-09-10 |
20150255546 | TRANSISTOR-TYPE VISCOSITY SENSOR, AND VISCOSITY MEASUREMENT SYSTEM AND VISCOSITY MEASURING METHOD USING THE SAME - A viscosity measurement system, which is for measuring the viscosity of a fluid, comprises a transistor-type viscosity sensor, an electrical measurement unit, and a processing unit. The transistor-type viscosity sensor includes a semiconductor structure, a source terminal, and a drain terminal. The semiconductor structure includes a GaN layer and an AlGaN layer disposed on the GaN layer. The portion of the semiconductor structure that is between the source terminal and the drain terminal has a gate region, which has an exposed surface for being in contact with the fluid. The electrical measurement unit is in electrical connection with the source terminal and the drain terminal and for measuring an electronic signal of the semiconductor structure. The processing unit is coupled to the electrical measurement unit and for determining the viscosity of the fluid according to the electronic signal measured. | 2015-09-10 |
20150255547 | III-Nitride High Electron Mobility Transistor Structures and Methods for Fabrication of Same - Structures for III-nitride GaN high electron mobility transistors (HEMT), method for fabricating for GaN devices and integrated chip-level power systems using the GaN devices are provided. The GaN HEMT structure includes a substrate, an AlGaN/GaN heterostructure grown on the substrate, and a normally-off GaN device fabricated on the AlGaN/GaN heterostructure. The AlGaN/GaN heterostructure includes a GaN buffer layer and an AlGaN barrier layer. The integrated chip-level power system includes a substrate, an AlGaN/GaN heterostructure layer grown on the substrate and a plurality of GaN devices. The AlGaN/GaN heterostructure layer includes a GaN buffer layer and an AlGaN barrier layer and is formed into mesa areas and valley areas. Each of the plurality of GaN devices are fabricated on a separate one of the mesa areas. | 2015-09-10 |
20150255548 | Methods of Forming Semiconductor Devices and FinFETs - Methods of forming semiconductor devices and fin field effect transistors (FinFETs) are disclosed. In some embodiments, a method of forming a semiconductor device includes forming a group III material over a substrate, the group III material comprising a thickness of about 2 monolayers or less. The method includes forming a group III-V material over the group III material. | 2015-09-10 |
20150255549 | CONTROLLING GAASP/SIGE INTERFACES - Initiation conditions and strain techniques are described that enable forming high quality GaAsP semiconductor material on an SiGe semiconductor material with low threading defect density. Suitable initiation conditions include exposing the SiGe semiconductor material to a gas comprising arsenic. A tensilely-strained region may be formed in the semiconductor structure between regions of GaAsP semiconductor material and SiGe semiconductor material. | 2015-09-10 |
20150255550 | BIPOLAR TRANSISTOR HAVING COLLECTOR WITH DOPING SPIKE - This disclosure relates to bipolar transistors, such as heterojunction bipolar transistors, having at a doping spike in the collector. The doping spike can be disposed relatively near an interface between the collector and the base. For instance, the doping spike can be disposed within half of the thickness of the collector from the interface between the collector and the base. Such bipolar transistors can be implemented, for example, in power amplifiers. | 2015-09-10 |
20150255551 | SEMICONDUCTOR STRUCTURE INCLUDING GUARD RING - One or more embodiments relate to a semiconductor structure, comprising: a conductive feature; an outer guard ring; and an inner guard ring between the outer guard ring and the conductive feature, the inner guard ring being electrically coupled to the conductive feature. | 2015-09-10 |
20150255552 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a substrate, and a gate electrode formed on the substrate on a gate insulation film. The semiconductor device also includes a source diffusion layer and a drain diffusion layer which are formed on the substrate where the gate electrode is sandwiched between the source diffusion layer and the drain diffusion layer, one or more source contacts formed on the source diffusion layer; and one or more drain contacts formed on the drain diffusion layer. At least one of the source contacts and the drain contacts includes a first contact region having a first size and a second contact region having a second size larger than the first size on the same source diffusion layer or on the same drain diffusion layer. | 2015-09-10 |
20150255553 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device having a groove provided in a semiconductor substrate, a gate insulating film provided so as to cover an inside surface of the groove, a first conductive film provided inside the groove in a position in which a first upper end surface is lower than the outer surface of the semiconductor substrate, a second conductive film provided inside the groove in a position that protrudes beyond the first upper end surface and in which a second upper end surface is higher than the outer surface of the semiconductor substrate, and a cap insulating film provided inside the groove so as to cover a protruding part of the second conductive film that protrudes beyond the first upper end surface. | 2015-09-10 |
20150255554 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate, a first insulation film disposed on the semiconductor substrate, a film including silicon disposed over the first insulation film, a second insulation film disposed on the film, and a plurality of metal dots disposed on the second insulation film, a semiconductor film selectively formed on the plurality of metal dots, and a high dielectric constant insulation film disposed on the semiconductor film and the second insulation film. | 2015-09-10 |
20150255555 | METHODS OF FORMING A NON-PLANAR ULTRA-THIN BODY DEVICE - One illustrative method disclosed herein involves, among other things, forming a first epi semiconductor material on the exposed opposite sidewalls of a fin to thereby define a semiconductor body, performing at least one etching process to remove at least a portion of the substrate portion of the fin positioned between the first epi semiconductor materials positioned on the opposite sidewalls of the fin and to thereby define a back-gate cavity, forming a back-gate insulating material within the back-gate cavity and on the first epi semiconductor materials, forming a back-gate electrode on the back-gate insulation material within the back-gate cavity and forming a gate structure comprised of a gate insulation layer and a gate electrode around the semiconductor bodies. | 2015-09-10 |
20150255556 | SEMICONDUCTOR DEVICE WITH LOW-K GATE CAP AND SELF-ALIGNED CONTACT - A semiconductor device includes at least a gate formed upon a semiconductor substrate, a contact trench self aligned to the gate, and a multilayered gate caps comprising a first gate cap formed upon each gate and a low-k gate cap formed upon the first gate cap. The multilayered gate cap may electrically isolate the gate from a self aligned contact formed by filling the contact trench with electrically conductive material. The multilayered gate cap reduces parasitic capacitance formed between the source-drain region, gate, and multilayered gate cap that may adversely impact device performance and device power consumption. | 2015-09-10 |
20150255557 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method of manufacturing the same are disclosed. The method includes forming a semiconductor fin on a semiconductor substrate. The method further includes forming an interfacial oxide layer on a top surface and sidewalls of the semiconductor fin. The method further includes forming a high K gate dielectric layer on the interfacial oxide layer. The method further includes forming a first metal gate layer on the high K gate dielectric layer. The method further includes implanting dopant to the first metal gate layer through conformal doping. The method further includes performing annealing so that the dopants are diffused and accumulated at an upper interface between the high K gate dielectric layer and the first metal gate layer, as well as at a lower interface between the high K gate dielectric layer and the interfacial oxide layer, generating electrical dipoles at the lower interface through interfacial reaction. | 2015-09-10 |
20150255558 | FORMING A VTFT GATE USING PRINTING - A method of forming a gate layer of a thin film transistor includes providing a substrate including a gate structure having a reentrant profile. A conformal conductive inorganic thin film is deposited over the gate structure. A polymeric resist is printed that wicks along the reentrant profile of the gate structure. The conformal conductive inorganic thin film is etched in areas not protected by the polymeric resist to form a patterned conductive gate layer located in the reentrant profile of the gate structure. | 2015-09-10 |
20150255559 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a first semiconductor layer and a first electrode. The first semiconductor layer includes a nitride semiconductor including a first metal. The first electrode is provided in contact with the first semiconductor layer. The first electrode includes a first region, a second region and a third region. The first region includes a compound of the first metal and a second metal or an alloy of the first metal and the second metal. The second metal has reducing properties for the first semiconductor layer. The second region is provided between the first semiconductor layer and the first region and includes the first metal and the second metal. The third region is provided between the first semiconductor layer and the second region and includes a compound of the first metal and nitrogen. | 2015-09-10 |
20150255560 | SEMICONDUCTOR DEVICE WITH REDUCED LEAKAGE CURRENT AND METHOD FOR MAKING THE SAME - A semiconductor device with reduced leakage current and a method of making the same is disclosed. The semiconductor device includes a substrate having a device layer, a dielectric layer, and a gate metal opening within the dielectric layer between a source contact and a gate contact. A first metal layer is disposed within the gate metal opening, and a second metal layer is disposed directly onto the second metal layer, wherein the second metal layer is oxidized and has a thickness that ranges from about 4 Angstroms to about 20 Angstroms to limit a leakage current of a total gate periphery to between around 0.1 μA/mm and around 50 μA/mm. A current carrying layer is disposed on the second metal layer. In one embodiment, the first metal layer is nickel (Ni), the second metal layer is palladium (Pd), and the current carrying layer is gold (Au). | 2015-09-10 |
20150255561 | SEMICONDUCTOR DEVICE WITH LOW-K SPACERS - One method disclosed herein includes forming at least one sacrificial sidewall spacer adjacent a sacrificial gate structure that is formed above a semiconducting substrate, removing at least a portion of the sacrificial gate structure to thereby define a gate cavity that is laterally defined by the sacrificial spacer, forming a replacement gate structure in the gate cavity, removing the sacrificial spacer to thereby define a spacer cavity adjacent the replacement gate structure, and forming a low-k spacer in the spacer cavity. A novel device disclosed herein includes a gate structure positioned above a semiconducting substrate, wherein the gate insulation layer has two upstanding portions that are substantially vertically oriented relative to an upper surface of the substrate. The device further includes a low-k sidewall spacer positioned adjacent each of the vertically oriented upstanding portions of the gate insulation layer. | 2015-09-10 |
20150255562 | Semiconductor Device and Method of Manufacturing the Semiconductor Device - In a semiconductor device, a first interlayer insulating layer made of an inorganic material and formed on inverse stagger type TFTs, a second interlayer insulating layer made of an organic material and formed on the first interlayer insulating layer, and a pixel electrode formed in contact with the second interlayer insulating layer are disposed on a substrate, and an input terminal portion that is electrically connected to a wiring of another substrate is provided on an end portion of the substrate. The input terminal portion includes a first layer made of the same material as that of the gate electrode and a second layer made of the same material as that of the pixel electrode. With this structure, the number of photomasks used in the photolithography method can be reduced to 5. | 2015-09-10 |
20150255563 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE HAVING MULTI-LAYER HARD MASK - A method for manufacturing a semiconductor device is provided, comprising steps of providing a substrate with an underlying layer formed thereon; forming a gate layer overlying the underlying layer; and forming a multi-layer hard mask layer on the gate layer, and the multi-layer hard mask layer comprising a plurality of material layers and a top hard mask formed on the material layers, wherein the gate layer and the top hard mask contain the same element, such as silicon. | 2015-09-10 |
20150255564 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - Over a semiconductor substrate, a gate insulating film including an interfacial layer, a HfON film, and a HfSiON film is formed. Then, over the HfSiON film, an Al-containing film and a mask layer are formed. Subsequently, the mask layer and the Al-containing film are selectively removed from an n-channel MISFET formation region. Then, a rare-earth-element-containing film is formed over the HfSiON film in the n-channel MISFET formation region and over the mask layer in a p-channel MISFET formation region. Heat treatment is performed to cause a reaction between each of the HfON film and the HfSiON film and the rare-earth-element-containing film in the n-channel MISFET formation region and cause a reaction between each of the HfON film and the HfSiON film and the Al-containing film in the p-channel MISFET formation region. Thereafter, the unreacted rare-earth-element-containing film and the mask layer are removed, and then metal gate electrodes are formed. | 2015-09-10 |
20150255565 | HIGH DENSITY MOSFET ARRAY WITH SELF-ALIGNED CONTACTS ENHANCEMENT PLUG AND METHOD - A semiconductor substrate comprises epitaxial region, body region and source region; an array of interdigitated active nitride-capped trench gate stacks (ANCTGS) and self-guided contact enhancement plugs (SGCEP) disposed above the semiconductor substrate and partially embedded into the source region, the body region and the epitaxial region forming the trench-gated MOSFET array. Each ANCTGS comprises a stack of a polysilicon trench gate embedded in a gate oxide shell and a silicon nitride spacer cap covering the top of the polysilicon trench gate; each SGCEP comprises a lower intimate contact enhancement section (ICES) in accurate registration to its neighboring ANCTGS; an upper distal contact enhancement section (DCES) having a lateral mis-registration (LTMSRG) to the neighboring ANCTGS; and an intervening tapered transitional section (TTS) bridging the ICES and the DCES; a patterned metal layer atop the patterned dielectric region atop the MOSFET array forms self-guided source and body contacts through the SGCEP. | 2015-09-10 |
20150255566 | Diode-Based Devices and Methods for Making the Same - In accordance with an embodiment, a diode comprises a substrate, a dielectric material including an opening that exposes a portion of the substrate, the opening having an aspect ratio of at least 1, a bottom diode material including a lower region disposed at least partly in the opening and an upper region extending above the opening, the bottom diode material comprising a semiconductor material that is lattice mismatched to the substrate, a top diode material proximate the upper region of the bottom diode material, and an active diode region between the top and bottom diode materials, the active diode region including a surface extending away from the top surface of the substrate. | 2015-09-10 |
20150255567 | FABRICATION PROCESS FOR MITIGATING EXTERNAL RESISTANCE OF A MULTIGATE DEVICE - A method for fabricating a multigate device includes forming a fin on a substrate of the multigate device, the fin being formed of a semiconductor material, growing a first conformal epitaxial layer directly on the fin and substrate, wherein the first conformal epitaxial layer is highly doped, growing a second conformal epitaxial layer directly on the first conformal epitaxial layer, wherein the second conformal epitaxial layer is highly doped, selectively removing a portion of second epitaxial layer to expose a portion of the first conformal epitaxial layer, selectively removing a portion of the first conformal epitaxial layer to expose a portion of the fin and thereby form a trench, and forming a gate within the trench. | 2015-09-10 |
20150255568 | FABRICATION PROCESS FOR MITIGATING EXTERNAL RESISTANCE AND INTERFACE STATE DENSITY IN A MULTIGATE DEVICE - A method for fabricating a multigate device includes forming a fin on a substrate of the multigate device, the fin being formed of a semiconductor material, growing a first conformal epitaxial layer directly on the fin and substrate, wherein the first conformal epitaxial layer is undoped or lightly doped, growing a second conformal epitaxial layer directly on the first conformal epitaxial layer, wherein the second conformal epitaxial layer is highly doped, selectively removing a portion of the second epitaxial layer to expose a portion of the first conformal epitaxial layer and thereby form a trench, and forming a gate within the trench. | 2015-09-10 |
20150255569 | FinFET FORMATION WITH LATE FIN REVEAL - A FinFET semiconductor device fabrication process includes forming a plurality of FinFET fins upon a semiconductor substrate, forming a first dielectric layer upon the semiconductor substrate so that an upper surface of the first dielectric layer is coplanar with upper surfaces of the FinFET fins, forming a plurality of dummy gates upon the FinFET fins and the first dielectric layer orthogonal to the FinFET fins, revealing the FinFET fins by removing first portions of the first dielectric layer from source-drain regions, removing the dummy gates, and subsequent to the removal of the dummy gates, revealing the FinFET fins by removing second portions of the first dielectric layer from channel regions. | 2015-09-10 |
20150255570 | FIN FIELD EFFECT TRANSISTOR INCLUDING SELF-ALIGNED RAISED ACTIVE REGIONS - Fin mask structures are formed over a semiconductor material portion on a crystalline insulator layer. A disposable gate structure and a gate spacer are formed over the fin mask structures. Employing the disposable gate structure and the gate spacer as an etch mask, physically exposed portions of the fin mask structures and the semiconductor material portion are removed by an etch. A source region and a drain region are formed by selective epitaxy of a semiconductor material from physically exposed surfaces of the crystalline insulator layer. The disposable gate structure is removed selective to the source region and the drain region. Semiconductor fins are formed by anisotropically etching portions of the semiconductor material portion, employing the gate spacer and the fin mask structures as etch masks. A gate dielectric and a gate electrode are formed within the gate cavity. | 2015-09-10 |
20150255571 | SEMICONDUCTOR DEVICE HAVING A GAP DEFINED THEREIN - In a particular embodiment, a method includes forming a first spacer structure on a dummy gate of a semiconductor device and forming a sacrificial spacer on the first spacer structure. The method also includes etching a structure of the semiconductor device to create an opening, removing the sacrificial spacer via the opening, and depositing a material to close to define a gap. | 2015-09-10 |
20150255572 | IGBT AND DIODE - In an IGBT, defects generated by ion implantation for introduction of the P-type collector region or N-type buffer region into the N | 2015-09-10 |
20150255573 | Method of Manufacturing a Stress-Controlled HEMT - A method of manufacturing a semiconductor device includes providing a heterostructure body with a first doped region, a second doped region spaced apart from the first doped region and a two-dimensional charge carrier gas channel between the first and second doped regions, and forming a gate structure on the heterostructure body for controlling the channel, the gate structure comprising a piezoelectric material and an electrical conductor in contact with the piezoelectric material. | 2015-09-10 |
20150255574 | BACK-END TRANSISTORS WITH HIGHLY DOPED LOW-TEMPERATURE CONTACTS - A back end of line device and method for fabricating a transistor device include a substrate having an insulating layer formed thereon and a channel layer formed on the insulating layer. A gate structure is formed on the channel layer. Dopants are implanted into an upper portion of the channel layer on opposite sides of the gate structure to form shallow source and drain regions using a low temperature implantation process. An epitaxial layer is selectively grown on the shallow source and drain regions to form raised regions above the channel layer and against the gate structure using a low temperature plasma enhanced chemical vapor deposition process, wherein low temperature is less than about 400 degrees Celsius. | 2015-09-10 |
20150255575 | CONTACTS FOR TRANSISTORS - The present disclosure relates to a semiconductor device having a delta doped sheet layer within a transistor's source/drain region to reduce contact resistance, and an associated method. In some embodiments, a dielectric layer is disposed over the transistor. A trench is disposed through the dielectric layer to the source/drain region and a conductive contact is disposed in the trench. The source/drain region comprises a delta doped sheet layer with a doping concentration that is higher than rest of the source/drain region. | 2015-09-10 |
20150255576 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device is described. A spacer is formed on a sidewall of a fin structure. A portion of the fin structure is removed to form a cavity exposing at least a portion of the inner sidewall of the spacer. An epitaxy process is performed based on the remaining fin structure to form a semiconductor layer that has a shovel-shaped cross section including: a stem portion in the cavity, and a shovel plane portion contiguous with the stem portion. A semiconductor device is also described, which includes the spacer, the remaining fin structure and the semiconductor layer that are mentioned above. | 2015-09-10 |
20150255577 | METHOD FOR MANUFACTURING MOSFET - A method for manufacturing a MOSFET, including: performing ion implantation, via a shallow trench surrounding an active region in a semiconductor substrate, into a first sidewall of the active region and into a second sidewall of the active region opposite to the first sidewall to form a first heavily doped region in the first sidewall and a second heavily doped region in the second sidewall; filling the shallow trench with an insulating material, to form a shallow trench isolation; forming a gate stack and an insulating layer on the substrate, wherein the insulating layer surrounds and caps the gate stack; forming openings in the substrate using the shallow trench isolation, the first and second heavily doped regions, and the insulating layer as a hard mask; and epitaxially growing a semiconductor layer with a bottom surface and sidewalls of each of the openings as a seed layer. | 2015-09-10 |
20150255578 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a gate structure located on a substrate and a raised source/drain region adjacent to the gate structure. The raised source/drain region includes: a first epitaxial-grown doped layer of the raised source/drain region in contact with the substrate; a second epitaxial-grown doped layer on the first epitaxial-grown doped layer and including a same dopant species as the first epitaxial-grown doped layer, wherein the second epitaxial-grown doped layer includes a higher dopant concentration than the first epitaxial-grown doped layer and interfacing the gate structure by using a predetermined distance; and a third epitaxial-grown doped layer on the second epitaxial-grown doped layer and including the same dopant species as the first epitaxial-grown doped layer, wherein the third epitaxial-grown doped layer includes a higher dopant concentration than the second epitaxial-grown doped layer. | 2015-09-10 |
20150255579 | VTFT FORMATION USING SELECTIVE AREA DEPOSITION - A method of producing a vertical transistor includes providing a conductive gate structure having a reentrant profile on a substrate. A conformal insulating material layer is formed on the conductive gate structure. A conformal semiconductor material layer is formed on the insulating material layer. A deposition inhibiting material is deposited over a portion of the substrate and the conductive gate structure including filling the reentrant profile. A portion of the deposition inhibiting material is removed without removing all of the deposition inhibiting material from the reentrant profile. A plurality of electrodes is formed by depositing an electrically conductive material layer on portions of the semiconductor material layer using a selective area deposition process in which the electrically conductive material layer is not deposited on the deposition inhibiting material remaining in the reentrant profile. | 2015-09-10 |
20150255580 | FORMING A VTFT USING PRINTING - Fabricating a vertical thin film transistor includes printing a polymeric inhibitor in a cap pattern on a structural polymer layer on a substrate. A polymeric inhibitor is printed in a gate pattern on the substrate, in a dielectric pattern on the substrate, in a semiconductor pattern on a patterned conformal dielectric layer, and in an electrode pattern. The electrode pattern includes an open area over a portion of a reentrant profile that allows the polymeric inhibitor to wick along the reentrant profile in the open area. Fabrication of the vertical transistor also includes depositing an inorganic thin film, a first conductive thin film, a dielectric thin film, a semiconductor thin film, and a second conductive thin film using an atomic layer deposition (ALD) process. | 2015-09-10 |
20150255581 | Semiconductor Devices and Methods of Manufacture Thereof - Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes providing a substrate, the substrate includes a first fin, a second fin, and an isolation region disposed between the first fin and the second fin. The second fin includes a different material than a material of the substrate. The method includes forming an oxide over the first fin, the second fin, and a top surface of the isolation region at a temperature of about 400 degrees C. or less, and post-treating the oxide at a temperature of about 600 degrees C. or less. | 2015-09-10 |
20150255582 | INGAN OHMIC SOURCE CONTACTS FOR VERTICAL POWER DEVICES - A vertical III-nitride field effect transistor includes a drain comprising a first III-nitride material, a drain contact electrically coupled to the drain, and a drift region comprising a second III-nitride material coupled to the drain and disposed adjacent to the drain along a vertical direction. The field effect transistor also includes a channel region comprising a third III-nitride material coupled to the drift region, a gate region at least partially surrounding the channel region, and a gate contact electrically coupled to the gate region. The field effect transistor further includes a source coupled to the channel region. The source includes a GaN-layer coupled to an InGaN layer. The channel region is disposed between the drain and the source along the vertical direction such that current flow during operation of the vertical III-nitride field effect transistor is along the vertical direction. | 2015-09-10 |
20150255583 | FABRICATING VTFT WITH POLYMER CORE - Fabricating a vertical transistor includes providing a structural polymer layer on a substrate. A patterned inorganic thin film is formed on the structural polymer layer, leaving exposed portions of the structural polymer layer not under the inorganic thin film. Exposed portions of the structural polymer layer and portions of the structural polymer layer between the patterned inorganic thin film and the substrate are removed to form a structural polymer post having an inorganic cap that extends beyond an edge of the structural polymer post defining a reentrant profile. A conformal conductive gate layer and a conformal dielectric layer on the gate layer are formed in the reentrant profile. A conformal semiconductor layer is formed on the dielectric layer. First and second electrodes are formed in contact with a first portion (over the cap) and a second portion (not over the post) of the semiconductor layer. | 2015-09-10 |
20150255584 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - To establish a processing technique in manufacture of a semiconductor device including an In—Sn—Zn—O-based semiconductor. An In—Sn—Zn—O-based semiconductor layer is selectively etched by dry etching with the use of a gas containing chlorine such as Cl | 2015-09-10 |
20150255585 | DIRECTED EPITAXIAL HETEROJUNCTION BIPOLAR TRANSISTOR - A directed epitaxial heterojunction bipolar transistor (HBT) structure is directly or indirectly formed on a GaAs substrate that is formed by a (100) face towards a (111)B face with an angle of inclination between 0.6° and 25°, and includes a sub-collector layer, a collector, a base layer, an emitter layer, an emitter cap layer and an ohmic contact layer, which are sequentially formed on the substrate. A tunnel collector layer formed by InGaP or InGaAsP is provided between the collector layer and the base layer. Since an epitaxial process is performed on the substrate from a (100) face towards a (111)B face with an angle of inclination between 0.6° and 25°, indium and gallium contained in InGaP or InGaAsP are affected by the ordering effect such that InGaP or InGaAsP used in the emitter layer and/or the tunnel collector layer has a higher electron affinity or a smaller bandgap. | 2015-09-10 |
20150255586 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes an optional first electrode, a second electrode, a first and a third semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third electrode, and a second insulating film. The first semiconductor region extends between the first electrode and the second electrode. The second semiconductor region extends between the first semiconductor region and the second electrode. The third semiconductor region extends between the second semiconductor region and the second electrode. The third semiconductor region has a dopant concentration higher than a dopant concentration of the first semiconductor region. The third electrode is in contact, via a first insulating film, with the first semiconductor region, the second semiconductor region, and the third semiconductor region. The third semiconductor region is disposed between the second insulating film and the third electrode. | 2015-09-10 |
20150255587 | A SEMICONDUCTOR DEVICE COMPRISING A MAIN REGION, A CURRENT SENSE REGION, AND A WELL REGION - A semiconductor device disclosed herein is configured such that a well region including a well layer is disposed between a main region of a semiconductor substrate and a current sense region of the semiconductor substrate, that a well region electrode is disposed above the well region, and that the well layer and the well region electrode are in contact with each other through a contact hole formed in an interlayer insulating film. | 2015-09-10 |
20150255588 | HOT-ELECTRON TRANSISTOR HAVING METAL TERMINALS - In one aspect, a transistor comprises a metal emitter, a first semiconductor barrier, a metal base, a second semiconductor barrier, and a metal collector. The first semiconductor barrier separates the metal emitter and the metal base and has an average thickness based on a first mean free path of a charge carrier in the first semiconductor barrier emitted from the metal emitter. The second semiconductor barrier separates the metal base from the metal collector and has an average thickness based on a second mean free path of the charge carrier in the second semiconductor barrier injected from the metal base. The metal base comprises two or more metal layers and has an average thickness based on a multi-layer mean free path of the charge carrier. | 2015-09-10 |
20150255589 | INDIUM-CONTAINING CONTACT AND BARRIER LAYER FOR III-NITRIDE HIGH ELECTRON MOBILITY TRANSISTOR DEVICES - A high electron mobility transistor device includes a substrate, a buffer layer on the substrate, a channel layer on the buffer layer, and a contact and barrier layer on the channel layer, the contact and barrier layer being made of indium aluminum nitride with a plurality of indium precipitates exposed on the surface of the contact and barrier layer. The plurality of indium precipitates exposed on the surface of the contact and barrier layer enable metal contacts to be formed directly on the contact and barrier layer with reliable and repeatable electrical performance. The contact and barrier layer may be epitaxially grown in a metal organic chemical vapor deposition process where a ratio of group-V precursors to group-III precursors is low and a flow rate of an indium precursor is greater than a flow rate of an aluminum precursor. | 2015-09-10 |
20150255590 | Group III-Nitride-Based Enhancement Mode Transistor Having a Heterojunction Fin Structure - A Group III-nitride-based enhancement mode transistor having a heterojunction fin structure and a corresponding semiconductor device are described. | 2015-09-10 |
20150255591 | METHODS OF FORMING III-V SEMICONDUCTOR STRUCTURES USING MULTIPLE SUBSTRATES, AND SEMICONDUCTOR DEVICES FABRICATED USING SUCH METHODS - Methods of forming semiconductor devices include epitaxially growing a III-V base layer over a first substrate in a first deposition chamber. The III-V base layer is transferred from the first substrate to a second substrate, and at least one III-V device layer is epitaxially grown on the III-V base layer in a second deposition chamber separate from the first deposition chamber while the III-V base layer is disposed on the second substrate. The first substrate exhibits an average coefficient of thermal expansion (CTE) closer to an average CTE exhibited by the III-V base layer than an average CTE exhibited by the second substrate. Semiconductor devices may be fabricated using such methods. | 2015-09-10 |
20150255592 | SEMICONDUCTOR DEVICE INCLUDING A GATE ELECTRODE ON A PROTRUDING GROUP III-V MATERIAL LAYER AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - A semiconductor device including a group III-V barrier and a method of manufacturing the semiconductor device, the semiconductor device including: a substrate, insulation layers formed to be spaced apart on the substrate, a group III-V material layer for filling the space between the insulation layers and having a portion protruding higher than the insulation layers, a barrier layer for covering the side and upper surfaces of the protruding portion of the group III-V material layer and having a bandgap larger than that of the group III-V material layer, a gate insulation film for covering the surface of the barrier layer, a gate electrode formed on the gate insulation film, and source and drain electrodes formed apart from the gate electrode. The overall composition of the group III-V material layer is uniform. The barrier layer may include a group III-V material for forming a quantum well. | 2015-09-10 |
20150255593 | Finfet Seal Ring - A semiconductor device includes a first front-end-of-line (FEOL) seal ring on a substrate, the seal ring comprising ring-shaped fin-like structures, integrated circuitry formed on the substrate, the integrated circuitry being circumscribed by the first seal ring, an isolation zone between the seal ring and the integrated circuitry, the isolation zone comprising a set of fin structures, each fin structure facing a same direction. | 2015-09-10 |
20150255594 | QUASI-NANOWIRE TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - A quasi-nanowire transistor and a method of manufacturing the same are provided, the quasi-nanowire transistor comprising: providing an SOI substrate comprising a substrate layer ( | 2015-09-10 |
20150255595 | LOW-COST SEMICONDUCTOR DEVICE MANUFACTURING METHOD - Provided are a low-cost semiconductor device manufacturing method and a semiconductor device made using the method. The method includes forming multiple body regions in a semiconductor substrate, forming multiple gate insulating layers and multiple gate electrodes in the body region; implementing a blanket ion implantation in an entire surface of the substrate to form a low concentration doping region (LDD region) in the body region without a mask, forming a spacer at a side wall of the gate electrode, and implementing a high concentration ion implantation to form a high concentration source region and a high concentration drain region around the LDD region. According to the examples, devices have favorable electrical characteristics and at the same time, manufacturing costs are reduced. Since, when forming high concentration source region and drain regions, tilt and rotation co-implants are applied, an LDD masking step is potentially omitted. | 2015-09-10 |