37th week of 2015 patent applcation highlights part 53 |
Patent application number | Title | Published |
20150255296 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND PHOTOMASK - According to one embodiment, a photomask includes first lines and spaces that have a longitudinal side set along a first direction and are arranged in an effective region, and second lines and spaces that have a longitudinal side set along a second direction different from the first direction and are arranged in a peripheral region. | 2015-09-10 |
20150255297 | Method and Apparatus for Plasma Dicing a Semi-conductor Wafer - The present invention provides a method for plasma dicing a substrate. The method comprising providing a process chamber having a wall; providing a plasma source adjacent to the wall of the process chamber; providing a work piece support within the process chamber; placing the substrate onto a support film on a frame to form a work piece work piece; loading the work piece onto the work piece support; providing a clamping electrode for electrostatically clamping the work piece to the work piece support; providing a mechanical partition between the plasma source and the work piece; generating a plasma through the plasma source; and etching the work piece through the generated plasma. | 2015-09-10 |
20150255298 | Sequential Infiltration Synthesis for Advanced Lithography - A plasma etch resist material modified by an inorganic protective component via sequential infiltration synthesis (SIS) and methods of preparing the modified resist material. The modified resist material is characterized by an improved resistance to a plasma etching or related process relative to the unmodified resist material, thereby allowing formation of patterned features into a substrate material, which may be high-aspect ratio features. The SIS process forms the protective component within the bulk resist material through a plurality of alternating exposures to gas phase precursors which infiltrate the resist material. The plasma etch resist material may be initially patterned using photolithography, electron-beam lithography or a block copolymer self-assembly process. | 2015-09-10 |
20150255299 | METHODS FOR FABRICATING INTEGRATED CIRCUITS INCLUDING SELECTIVELY FORMING AND REMOVING FIN STRUCTURES - Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming fin structures in a selected area of a semiconductor substrate. The method includes covering the fin structures and the semiconductor substrate with a mask and forming a trench in the mask to define no more than two exposed fin structures in the selected area. Further, the method includes removing the exposed fin structures to provide the selected area with a desired number of fin structures. | 2015-09-10 |
20150255300 | DENSELY SPACED FINS FOR SEMICONDUCTOR FIN FIELD EFFECT TRANSISTORS - A method of forming a fin-based field-effect transistor device includes forming one or more first fins comprising silicon on a substrate, forming epitaxial layers on sides of the one or more first fins, and removing the one or more first fins to form a plurality of second fins. | 2015-09-10 |
20150255301 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device is disclosed. In the method, a substrate having a first surface and a second surface is provided. The second surface is opposed to the first surface. A via hole is formed to penetrate the substrate from the first surface toward the second surface. The via hole includes a first portion and a second portion. The first portion has a first sidewall which is substantially perpendicular to the first surface. The second portion has a second sidewall which gradually decreases from the first surface toward the second surface, and has a bottom surface that substantially flat. A seed pattern is formed on the first sidewall of the first portion, the second sidewall of the second portion and the bottom surface of the second portion of the via hole. A first thickness (Vt) of the seed pattern on the first sidewall of the first portion is less than a second thickness (VIt) of the seed pattern on the second sidewall of the second portion. A through via is formed to fill the via hole. | 2015-09-10 |
20150255302 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Provided is a method of manufacturing a semiconductor device. The method includes forming an underlying structure on a semiconductor substrate, forming a material layer on the semiconductor substrate having the underlying structure, the material layer including a first region having a first surface disposed at a first height from a surface of the semiconductor substrate and a second region having a second surface disposed at a second height lower than the first height, and planarizing the material layer. The planarization of the material layer includes coating an etchant on the material layer disposed on the semiconductor substrate, and selectively heating the first region of the material layer to increase an etch rate of the first region of the material layer more than an etch rate of the second region of the material layer. | 2015-09-10 |
20150255303 | HARD MASK REMOVAL SCHEME - A method for hard mask layer removal includes dispensing a chemical on a hard mask layer, in which the chemical includes an acidic chemical. The chemical is drained from a chamber after hard mask removal. | 2015-09-10 |
20150255304 | METHODS OF FORMING PATTERNS IN SEMICONDUCTOR DEVICES - Methods of forming a pattern in a semiconductor device may be provided. The methods may include sequentially forming a first hard mask layer and a second hard mask layer on an etching target layer including first and second regions, forming a first spacer layer on the second hard mask layer, forming a second hard mask pattern layer by etching the second hard mask layer using the first spacer layer, forming a second spacer layer on a sidewall of the second hard mask pattern layer, forming a first hard mask pattern layer by etching the first hard mask layer using the second spacer layer, and etching the etching target layer using the first hard mask pattern layer. | 2015-09-10 |
20150255305 | PLASMA ETCHING METHOD AND PLASMA ETCHING APPARATUS - In a plasma etching method for forming a hole in an etching target film, a process of generating a plasma of a processing gas containing at least C | 2015-09-10 |
20150255306 | NANOWIRE MOSFET WITH SUPPORT STRUCTURES FOR SOURCE AND DRAIN - A nanowire field effect transistor (FET) device and method for forming the same is disclosed. The device comprises: a semiconductor substrate; a device layer including a source region and a drain region connected by a suspended nanowire channel; and etch stop layers respectively arranged beneath the source region and the drain region, the etch stop layers forming support structures interposed between the semiconductor substrate and the source and drain regions. The suspended nanowire channel is formed by etching a sacrificial material disposed beneath the suspended nanowire channel and between the etch stop layers. The etching is selective to the sacrificial material to prevent the removal of the etch stop layers beneath the source region and the drain region. | 2015-09-10 |
20150255307 | MANUFACTURING PROCESS OF GATE STACK STRUCTURE WITH ETCH STOP LAYER - A manufacturing process of an etch stop layer is provided. The manufacturing process includes steps of providing a substrate; forming a gate stack structure over the substrate, wherein the gate stack structure at least comprises a dummy polysilicon layer and a barrier layer; removing the dummy polysilicon layer to define a trench and expose a surface of the barrier layer; forming a repair layer on the surface of the barrier layer and an inner wall of the trench; and forming an etch stop layer on the repair layer. In addition, a manufacturing process of the gate stack structure with the etch stop layer further includes of forming an N-type work function metal layer on the etch stop layer within the trench, and forming a gate layer on the N-type work function metal layer within the trench. | 2015-09-10 |
20150255308 | STRESS MODULATION OF SEMICONDUCTOR THIN FILM - An embodiment discloses a method for modulating stress of a semiconductor film and comprises the steps of: providing a substrate; forming a semiconductor film on the substrate; performing an annealing treatment to the formed semiconductor film; and determining a residual stress of the semiconductor film at a certain compress strain, a certain tensile strain, or zero by controlling a temperature of the annealing treatment. | 2015-09-10 |
20150255309 | ETCHING METHOD OF SEMICONDUCTOR SUBSTRATE, AND METHOD OF PRODUCING SEMICONDUCTOR DEVICE - An etching method containing the step of processing a substrate having a first layer containing titanium nitride (TiN) and a second layer containing a transition metal by bringing an etching liquid into contact with the substrate and thereby removing the first layer, wherein the first layer has a surface oxygen content from 0.1 to 10% by mole, and wherein the etching liquid comprises an ammonia compound and an oxidizing agent, and has a pH of from 7 to 14. | 2015-09-10 |
20150255310 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - Provided is a method for manufacturing a semiconductor device with favorable electrical characteristics. The following steps are performed in the following order: forming an oxide semiconductor film over a substrate having a substantially planar surface; selectively etching the oxide semiconductor film to form an oxide semiconductor layer; implanting an oxygen ion on a top surface of the oxide semiconductor layer and a side surface of the oxide semiconductor layer in a cross-section perpendicular to the substantially planar surface in a channel width direction of the oxide semiconductor layer from an angle 0°<θ<90°; forming an insulating layer over the oxide semiconductor layer, and performing heat treatment on the oxide semiconductor layer to diffuse oxygen into the oxide semiconductor layer. | 2015-09-10 |
20150255311 | METHOD OF FABRICATING SEMICONDUCTOR PACKAGE - A semiconductor package is provided, including: a carrier; at least an interposer disposed on the carrier; an encapsulant formed on the carrier for encapsulating the interposer while exposing a top side of the interposer; a semiconductor element disposed on the top side of the interposer; and an adhesive formed between the interposer and the semiconductor element. By encapsulating the interposer with the encapsulant, warpage of the interposer is avoided and a planar surface is provided for the semiconductor element to be disposed thereon, thereby improving the reliability of electrical connection between the interposer and the semiconductor element. | 2015-09-10 |
20150255312 | LOW-STRESS DUAL UNDERFILL PACKAGING - The present invention relates generally to flip chip technology and more particularly, to a method and structure for reducing internal packaging stresses, improving adhesion properties, and reducing thermal resistance in flip chip packages by using more than one underfill material deposited in different regions of the flip chip interface. According to one embodiment, a method of forming a first underfill in an interior region of an interface such that a periphery region of the interface remains open, and forming a second underfill in the periphery region is disclosed. | 2015-09-10 |
20150255313 | Method for Producing a Multiplicity of Optoelectronic Semiconductor Components - Optoelectronic semiconductor devices and methods for producing optoelectronic semiconductor devices are disclosed. In an embodiment the method includes applying a plurality of arrangements of electrically conductive first and second contact elements on an auxiliary carrier, applying an optoelectronic semiconductor chip on the second contact element of each arrangement and electrically conductively connecting the optoelectronic semiconductor chip to the first contact element for each arrangement. The method further includes encapsulating the first contact elements and the second contact elements with an encapsulation material to form an encapsulation body and singulating the encapsulation body into a plurality of optoelectronic semiconductor devices, wherein the encapsulation material finishes flush with an underside, facing the auxiliary carrier, of each first contact element, and wherein the encapsulation material finishes flush with an underside, facing the auxiliary carrier, of each second contact element. | 2015-09-10 |
20150255314 | STORING CONTAINER, STORING CONTAINER MANUFACTURING METHOD, SEMICONDUCTOR MANUFACTURING METHOD, AND SEMICONDUCTOR MANUFACTURING APPARATUS - The present invention is to provide a storing container wherein Si does not drop onto a single crystal SiC substrate, and Si pressure distribution in an internal space can be made uniform. This storing container stores therein a single crystal SiC substrate to be etched by means of a heat treatment under Si vapor pressure. The storing container is formed of a tantalum metal, and has a tantalum carbide layer provided on an internal space side, and a tantalum silicide layer provided on the side further toward the internal space side than the tantalum carbide layer. The tantalum silicide layer supplies Si to the internal space. Furthermore, the tantalum silicide layer is different from adhered Si, and does not melt and drop. | 2015-09-10 |
20150255315 | APPARATUS FOR AND METHOD OF PROCESSING SUBSTRATE - A rinsing liquid adheres to a substrate subjected to a cleaning process. The rinsing liquid on the substrate is first replaced with IPA liquid. While the substrate covered with the IPA liquid is held in a dryer chamber, liquid carbon dioxide is supplied to the surface of the substrate. Liquid nitrogen is supplied to cool down the interior of the dryer chamber. This solidifies the liquid carbon dioxide on the substrate into solid carbon dioxide. Thereafter, the pressure in the dryer chamber is returned to atmospheric pressure, and gaseous nitrogen is supplied into the dryer chamber. Thus, the temperature in the dryer chamber increases. The solid carbon dioxide on the surface of the substrate is sublimated, and is hence removed from the substrate. All of the steps are performed while carbon dioxide is not in a supercritical state but in a non-supercritical state. | 2015-09-10 |
20150255316 | SUBSTRATE CLEANING METHOD, SUBSTRATE CLEANING APPARATUS AND VACUUM PROCESSING SYSTEM - In order to remove a deposit adhered to the backside of the peripheral portion of a wafer, a cleaning gas containing carbon dioxide gas is set to a pressure that is slightly lower than the pressure corresponding to a vapor pressure line of carbon dioxide at a temperature in the nozzle, and a gas cluster of carbon dioxide is generated. A gas cluster of carbon dioxide generated under such a condition is in a state immediately prior to undergoing a phase change to a liquid and therefore is a gas cluster having a large cluster diameter and having molecules that are firmly solidified. | 2015-09-10 |
20150255317 | SEMICONDUCTOR MANUFACTURING EQUIPMENT AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor manufacturing equipment according to an embodiment includes a support unit, a chamber, a microwave generator, a waveguide, and an auxiliary heating unit. The support unit supports a wafer. The chamber accommodates the support unit therein. The microwave generator generates a microwave. The waveguide is mounted on the chamber to irradiate the microwave to a surface of the wafer. The auxiliary heating unit heats the wafer by an electromagnetic wave with a wavelength shorter than a wavelength of the microwave. | 2015-09-10 |
20150255318 | Article Supporting Device - Each of a pair of support members includes a lightweight-article support portion that is inserted into an insertion space of a lightweight article and supports a support-target portion of the lightweight article from below and a heavyweight-article support portion that is inserted into an insertion space of a heavyweight article and supports a support-target portion of the heavyweight article from below. The heavyweight-article support portion is formed to be thick in the vertical direction compared with the lightweight-article support portion. The lightweight-article support portion is provided at a position that is located in the insertion space of the heavyweight article when the heavyweight-article support portion is inserted into the insertion space of the heavyweight article, and formed integrally with the heavyweight-article support portion. | 2015-09-10 |
20150255319 | CONVEYING METHOD AND SUBSTRATE PROCESSING APPARATUS - Provided is a method of conveying a storage container from a placing table to a conveyance place using a conveying mechanism in a substrate processing apparatus. The storage container hermetically stores a substrate and includes a flange portion formed on the top thereof. The conveying mechanism includes a hand portion provided with a flange insertion portion. The substrate processing apparatus is provided with at least two placing tables arranged side by side in a first horizontal direction. The method includes moving the placing table to the conveyance place in the second horizontal direction by a predetermined distance; sliding the hand portion from a side of a placing table neighboring to the placing table in the first horizontal direction such that the flange portion is inserted into the flange inserting portion; and conveying the storage container from the placing table to the conveyance place through the hand portion. | 2015-09-10 |
20150255320 | Mobile Electrostatic Carrier for a Semiconductive Wafer and a Method of Using Thereof for Singulation of the Semiconductive Wafer - A mobile electrostatic carrier (MESC) provides a structural platform to temporarily bond a semiconductive wafer and can be used to transport the semiconductive wafer or be used to perform manufacturing processes on the semiconductive wafer. The MESC uses a plurality of electrostatic field generating (EFG) circuits to generate electrostatic fields across the MESC that allow the MESC to bond to compositional impurities within the semiconductive process. The MESC is particularly useful during singulation for a wafer fabrication process. The MESC holds the semiconductive wafer in a constant position as the semiconductive wafer is cut into a plurality of dies. Once the MESC is discharges its EFG circuits and consequently dissipates its bonding electrostatic fields, the plurality of dies can be easily and readily removed from the MESC. | 2015-09-10 |
20150255321 | BACK GRINDING SHEET - The present invention relates to a back grinding sheet (BG sheet) ( | 2015-09-10 |
20150255322 | WAFER-HANDLING END EFFECTORS - Wafer-handling end effectors and semiconductor manufacturing devices that include and/or are utilized with wafer-handling end effectors are disclosed herein. The end effectors include an end effector body and a plurality of wafer-contacting surfaces that is supported by the end effector body and configured to form an at least partially face-to-face contact with a wafer. The end effectors further include a vacuum distribution manifold that extends between a robot-proximal end of the end effector body and the plurality of wafer-contacting surfaces. The end effectors also include a plurality of vacuum openings that is defined within the plurality of wafer-contacting surfaces and extends between the plurality of wafer-contacting surfaces and the vacuum distribution manifold. The end effectors further include a plurality of sealing structures each of which is associated with a respective one of the plurality of wafer-contacting surfaces. | 2015-09-10 |
20150255323 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - In one embodiment, a semiconductor device includes a semiconductor substrate including device regions which extend in a first direction and are adjacent to one another in a second direction perpendicular to the first direction, and isolation regions disposed between the device regions. The device further includes a gate insulator disposed on a device region, a charge storing layer disposed on the gate insulator, and a hafnium containing film disposed on the charge storing layer, a width of the hafnium containing film in the second direction being larger than a width of at least one of a lower face of the charge storing layer, the gate insulator, and an upper face of the device region in the second direction. | 2015-09-10 |
20150255324 | SEAMLESS GAP-FILL WITH SPATIAL ATOMIC LAYER DEPOSITION - Embodiments disclosed herein generally relate to forming dielectric materials in high aspect ratio features. In one embodiment, a method for filling high aspect ratio trenches in one processing chamber is disclosed. The method includes placing a substrate inside a processing chamber, where the substrate has a surface having a plurality of high aspect ratio trenches and the surface is facing a gas/plasma distribution assembly. The method further includes performing a sequence of depositing a layer of dielectric material on the surface of the substrate and inside each of the plurality of trenches, where the layer of dielectric material is on a bottom and side walls of each trench, and removing a portion of the layer of dielectric material disposed on the surface of the substrate, where an opening of each trench is widened. The sequence repeats until the trenches are filled seamlessly with the dielectric material. | 2015-09-10 |
20150255325 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device having a semiconductor element (a thin film transistor, a thin film diode, a photoelectric conversion element of silicon PIN junction, or a silicon resistor element) which is light-weight, flexible (bendable), and thin as a whole is provided as well as a method of manufacturing the semiconductor device. In the present invention, the element is not formed on a plastic film. Instead, a flat board such as a substrate is used as a form, the space between the substrate (third substrate ( | 2015-09-10 |
20150255326 | EMBEDDED ON-CHIP SECURITY - Embodiments of the invention include a semiconductor structure containing a back end of line randomly patterned interconnect structure for implementing a physical unclonable function (PUF), a method for forming the semiconductor device, and a circuit for enabling the interconnect structure to implement the physical unclonable function. The method includes forming a semiconductor substrate and a dielectric layer on the substrate. The randomly patterned interconnect structure is formed in the dielectric layer. The random pattern of the interconnect structure is used to implement the physical unclonable function and is a result of defect occurrences during the manufacturing of the semiconductor structure. The circuit includes n-channel and p-channel metal oxide semiconductor field effect transistors (MOSFETs) and the randomly patterned interconnect structure, which acts as electrical connections between the MOSFETs. The random electrical connections between MOSFETs are utilized for generation of unique keys for purposes such as authentication or identification. | 2015-09-10 |
20150255327 | MANUFACTURING METHOD OF LIQUID CRYSTAL DISPLAY - A method for manufacturing a liquid crystal display includes: forming a first passivation layer and an organic layer, forming an edge of an inclined portion of the organic layer by partially removing the organic layer at a location where a first drain contact hole that exposes a drain electrode of a thin film transistor is formed, forming a second passivation layer including a third drain contact hole exposing the drain electrode, a first electrode including a second drain contact hole exposing the drain electrode, and the first drain contact hole through an etching process using one etching mask, and forming a second electrode on the second passivation layer. The first drain contact hole, the second drain contact hole, and the third drain contact hole overlap with each other, and a size of the second drain contact hole is greater than a size of the third drain contact hole. | 2015-09-10 |
20150255328 | SELECTIVE LOCAL METAL CAP LAYER FORMATION FOR IMPROVED ELECTROMIGRATION BEHAVIOR - A method of forming a wiring structure for an integrated circuit device includes forming a first metal line within an interlevel dielectric (ILD) layer, and forming a second metal line in the ILD layer adjacent the first metal line; masking selected regions of the first and second metal lines; selectively plating metal cap regions over exposed regions of the first and second metal lines at periodic intervals such that a spacing between adjacent metal cap regions of an individual metal line corresponds to a critical length, L, at which a back stress gradient balances an electromigration force in the individual metal line, so as to suppress mass transport of electrons; and wherein the metal cap regions of the first metal line are formed at staggered locations with respect to the metal cap regions of the second metal line, along a common longitudinal axis. | 2015-09-10 |
20150255329 | METHODS FOR FORMING PASSIVATION PROTECTION FOR AN INTERCONNECTION STRUCTURE - Methods for forming a passivation protection structure on a metal line layer formed in an insulating material in an interconnection structure are provided. In one embodiment, a method for forming passivation protection on a metal line in an interconnection structure for semiconductor devices includes selectively forming a metal capping layer on a metal line bounded by a dielectric bulk insulating layer in an interconnection structure formed on a substrate in a processing chamber incorporated in a multi-chamber processing system, in-situ forming a barrier layer on the substrate in the processing chamber; wherein the barrier layer is a metal dielectric layer, and forming a dielectric capping layer on the barrier layer in the multi-chamber processing system. | 2015-09-10 |
20150255330 | BARRIER-SEED TOOL FOR FINE-PITCHED METAL INTERCONNECTS - A barrier seed tool is configured to clean trenches in a first chamber, line the trenches with a diffusion barrier layer, and form a copper seed layer over the diffusion barrier layer in a second chamber. The clean chamber is configured to reduce overhangs in the copper seed layer by producing a plasma comprising positively and negatively charged ions including halogen ions, filtering the plasma to selectively exclude positively charged ions, and bombarding with the filtered plasma. The tool and related method can be used to reduce overhangs and improve subsequent gap fill while avoiding excessive damage to the dielectric matrix. | 2015-09-10 |
20150255331 | INTEGRATED CIRCUITS WITH A COPPER AND MANGANESE COMPONENT AND METHODS FOR PRODUCING SUCH INTEGRATED CIRCUITS - Integrated circuits with copper and magnesium components and methods for producing such integrated circuits are provided. A method of producing the integrated circuits includes forming an aperture in an interlayer dielectric. A seed layer is formed in the aperture, where the seed layer includes manganese and copper, and where the seed layer has a copper concentration gradient. A core is formed overlying the seed layer, where the core includes copper. | 2015-09-10 |
20150255332 | Ultra-Low Resistivity Contacts - Contacts for semiconductor devices and methods of making thereof are disclosed. A method comprises forming a first layer on a semiconductor, the first layer comprising one or more metals; forming a second layer on the first layer, the second layer comprising the one or more metals, nitrogen and oxygen; and heating the first and second layer such that oxygen migrates from the second layer into the first layer and the first layer comprises a sub-stoichiometric metal oxide after heating. Exemplary embodiments use transition metals such as Ti in the first layer. After heating there is a sub-stoichiometric oxide layer of about 2.5 nm thickness between a metal nitride conductor and the semiconductor. The specific contact resistivity is less than about 7×10 | 2015-09-10 |
20150255333 | COBALT DEPOSITION ON BARRIER SURFACES - Embodiments of the invention provide processes for depositing a cobalt layer on a barrier layer and subsequently depositing a conductive material, such as copper or a copper alloy, thereon. In one embodiment, a method for depositing materials on a substrate surface is provided which includes forming a barrier layer on a substrate, exposing the substrate to dicobalt hexacarbonyl butylacetylene (CCTBA) and hydrogen to form a cobalt layer on the barrier layer during a vapor deposition process (e.g., CVD or ALD), and depositing a conductive material over the cobalt layer. In some examples, the barrier layer and/or the cobalt layer may be exposed to a gas or a reagent during a treatment process, such as a thermal process, an in situ plasma process, or a remote plasma process. | 2015-09-10 |
20150255334 | Method for Via Plating with Seed Layer - Presented herein is a method for plating comprising providing a substrate having a dielectric layer formed over a trace, and forming a via/trench opening extending through the dielectric layer, the via/trench opening exposing a surface of the trace. The method further comprises forming a seed layer in the via/trench opening and contacting the trace and forming a protection layer over the seed layer. The protection layer is removed and a conductive layer deposited on the seed layer in a single plating process step by applying a plating solution in the via/trench opening. | 2015-09-10 |
20150255335 | INTEGRATED CIRCUITS INCLUDING CONTACTS FOR METAL RESISTORS AND METHODS FOR FABRICATING THE SAME - Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes etching an ILD layer of dielectric material overlying a semiconductor substrate that includes a device region to form first contact vias that expose active areas of the device region. The ILD layer is etched to form second contact vias that correspondingly expose a gate that is disposed in the device region and a patterned resistive metal-containing layer that is disposed in the ILD layer adjacent to the device region. The first contact vias and the second contact vias are filled with an electrically-conductive material to form first contacts that are in electrical communication with the active areas and second contacts that include a gate contact and a metal resistor contact that are in electrical communication with the gate and the patterned resistive metal-containing layer, respectively. | 2015-09-10 |
20150255336 | METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES - In a method of manufacturing a semiconductor device, an insulating interlayer is formed on a substrate. The insulating interlayer is partially removed to form an opening. A barrier conductive layer is formed on a sidewall and a bottom of the opening. An RF sputtering process and a DC sputtering process are performed independently on the barrier conductive layer to form a seed layer. A plated layer is formed on the seed layer. | 2015-09-10 |
20150255337 | INTERCONNECT STRUCTURES WITH FUNCTIONAL COMPONENTS AND METHODS FOR FABRICATION - An electronic device includes an interlevel dielectric layer formed over a substrate and has a first set of openings and a second set of openings formed through the interlevel dielectric layer. The substrate includes conductive areas. A conductive contact structure is formed in the first set of openings in the interlevel dielectric layer to make electrical contact with the conductive areas of the substrate. A functional component is formed in the second set of openings in the interlevel dielectric layer and occupies a same level as the conductive contact structure. | 2015-09-10 |
20150255338 | Distributed Metal Routing - A system and method for a distributed metal routing is disclosed. An embodiment comprises a metal_0 layer with a metal_1 layer overlying the metal_0 layer. The metal_1 layer comprises separate parallel lines, with lines having different signals being distributed across the metal_1 layer. Such a layout decreases the parasitic resistance within the metal_0 layer as it decreases the distance current travels. Additionally, the distributed layout in metal_1 allows connections to be made to a metal_2 layer without the need for a hammer head connection of vias. | 2015-09-10 |
20150255339 | METHODS OF FORMING A METAL CAP LAYER ON COPPER-BASED CONDUCTIVE STRUCTURES ON AN INTEGRATED CIRCUIT DEVICE - One method includes forming a barrier layer in a trench/opening in an insulating material, forming a first region of a copper material above the barrier layer, forming a metal layer in the trench/opening on the first region of copper material, forming a second region of copper material on the metal layer, performing at least one CMP process to remove any materials positioned above a planarized upper surface of the layer of insulating material outside of the trench/opening so as to thereby define a structure comprised of the metal layer positioned between the first and second regions of copper material, forming a dielectric cap layer above the layer of insulating material and above the structure, and performing a metal diffusion anneal process to form a metal cap layer adjacent at least the upper surface of a conductive copper structure. | 2015-09-10 |
20150255340 | METHOD TO ETCH CU/TA/TAN SELECTIVELY USING DILUTE AQUEOUS HF/HCL SOLUTION - Copper can be etched with selectivity to Ta/TaN barrier liner and SiC hardmask layers, for example, to reduce the potential copper contamination. The copper film can be recessed more than the liner to further enhance the protection. Wet etch solutions including a mixture of HF and HCl can be used for selective etching copper with respect to the liner material, for example, the copper film can be recessed between 2 and 3 nm, and the barrier liner film can be recessed between 1.5 and 2 nm. | 2015-09-10 |
20150255341 | METHOD FOR MANUFACTURING A TRANSISTOR WITH SELF-ALIGNED TERMINAL CONTACTS - A MOS transistor includes a semiconductor layer with a drain region and a body region. A first insulating layer is disposed over the semiconductor layer, a gate-precursor layer is disposed over the first insulating layer, a second insulating layer disposed over the first insulating layer and a third insulating layer disposed over the second insulating layer. A source opening extends through the third insulating layer, the second insulating layer, the gate-precursor layer, and the first insulating layer. An implant through the source opening forms a source-precursor region in the semiconductor layer. The source opening is then lined and an body contact opening is made through the liner, the source-precursor region and into the body region. An implant through the body contact opening forms the body contact region below the source-precursor. The body contact opening is then filled with a metal. | 2015-09-10 |
20150255342 | SELECTIVE LOCAL METAL CAP LAYER FORMATION FOR IMPROVED ELECTROMIGRATION BEHAVIOR - A method of forming a wiring structure for an integrated circuit device includes forming one or more copper lines within an interlevel dielectric layer (ILD); masking selected regions of the one or more copper lines; selectively plating metal cap regions over exposed regions of the one or more copper lines; and forming a conformal insulator layer over the metal cap regions and uncapped regions of the one or more copper lines. | 2015-09-10 |
20150255343 | SELECTIVE LOCAL METAL CAP LAYER FORMATION FOR IMPROVED ELECTROMIGRATION BEHAVIOR - A method of forming a wiring structure for an integrated circuit device includes forming one or more copper lines within an interlevel dielectric layer (ILD); masking selected regions of the one or more copper lines; selectively plating metal cap regions over exposed regions of the one or more copper lines; and forming a conformal insulator layer over the metal cap regions and uncapped regions of the one or more copper lines. | 2015-09-10 |
20150255344 | ELECTROLESS METAL THROUGH SILICON VIA - A method of making a substrate-through metal via having a high aspect ratio, in a semiconductor substrate, and a metal pattern on the substrate surface, includes providing a semiconductor substrate (wafer) and depositing poly-silicon on the substrate. The the poly-silicon on the substrate surface is patterned by etching away unwanted portions. Then, Ni is selectiveley deposited on the poly-silicon by an electroless process. A via hole is made through the substrate, wherein the walls in the hole is subjected to the same processing as above. Cu is deposited on the Ni by a plating process. Line widths and spacings<10 μm are provided on both sides of the wafer. | 2015-09-10 |
20150255345 | METHODS AND STRUCTURE FOR CARRIER-LESS THIN WAFER HANDLING - Methods of forming a microelectronic assembly and the resulting structures and devices are disclosed herein. In one embodiment, a method of forming a microelectronic assembly includes removing material exposed at portions of a surface of a substrate to form a processed substrate having a plurality of thinned portions separated by integral supporting portions of the processed substrate having a thickness greater than a thickness of the thinned portions, at least some of the thinned portions including a plurality of electrically conductive interconnects extending in a direction of the thicknesses of the thinned portions and exposed at the surface; and removing the supporting portions of the substrate to sever the substrate into a plurality of individual thinned portions, at least some individual thinned portions including the interconnects. | 2015-09-10 |
20150255346 | BAKING TOOL FOR IMPROVED WAFER COATING PROCESS - Baking methods and tools for improved wafer coating are described. In one embodiment, a method of dicing a semiconductor wafer including integrated circuits involves coating a surface of the semiconductor wafer to form a mask covering the integrated circuits. The method involves baking the mask with radiation from one or more light sources. The method involves patterning the mask with a laser scribing process to provide a patterned mask with gaps, exposing regions of the substrate between the ICs. The method may also involves singulating the ICs, such as with a plasma etching operation. | 2015-09-10 |
20150255347 | Method and Apparatus for Plasma Dicing a Semi-conductor Wafer - The present invention provides a method for plasma dicing a substrate. The method comprising providing a process chamber having a wall; providing a plasma source adjacent to the wall of the process chamber; providing a work piece support within the process chamber; placing the substrate onto a support film on a frame to form a work piece work piece; loading the work piece onto the work piece support; providing a clamping electrode for electrostatically clamping the work piece to the work piece support; providing a mechanical partition between the plasma source and the work piece; generating a plasma through the plasma source; and etching the work piece through the generated plasma. | 2015-09-10 |
20150255348 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - The present invention has an object to perform a peeling treatment in a short time. Peeling is performed while a peeling layer is exposed to an atmosphere of an etching gas. Alternatively, peeling is performed while an etching gas for a peeling layer is blown to the peeling layer in an atmosphere of an etching gas. Specifically, an etching gas is blown to a part to be peeled while a layer to be peeled is torn off from a substrate. Alternatively, peeling is performed in an etchant for a peeling layer while supplying an etchant to the peeling layer. | 2015-09-10 |
20150255349 | APPROACHES FOR CLEANING A WAFER DURING HYBRID LASER SCRIBING AND PLASMA ETCHING WAFER DICING PROCESSES - Approaches for cleaning a wafer during hybrid laser scribing and plasma etching wafer dicing processes are described. In an example, a method of dicing a semiconductor wafer having a front surface having a plurality of integrated circuits thereon involves forming an underfill material layer between and covering metal pillar/solder bump pairs of the integrated circuits. The method also involves forming a mask layer on the underfill material layer. The method also involves laser scribing mask layer and the underfill material layer to provide scribe lines exposing portions of the semiconductor wafer between the integrated circuits. The method also involves removing the mask layer. The method also involves, subsequent to removing the mask layer, plasma etching the semiconductor wafer through the scribe lines to singulate the integrated circuits, wherein the second insulating layer protects the integrated circuits during at least a portion of the plasma etching. The method also involves, subsequent to the plasma etching, thinning but not removing the underfill material layer to partially expose the metal pillar/solder bump pairs of the integrated circuits. | 2015-09-10 |
20150255350 | ELECTRONIC DEVICES AND SYSTEMS, AND METHODS FOR MAKING AND USING SAME - Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced sigma V | 2015-09-10 |
20150255351 | Guard Rings on Fin Structures - A method includes forming a gate stack over a semiconductor fin, wherein the semiconductor fin forms a ring, and etching a portion of the semiconductor fin not covered by the gate stack to form a recess. The method further includes performing an epitaxy to grow an epitaxy semiconductor region from the recess, forming a first contact plug overlying and electrically coupled to the epitaxy semiconductor region, and forming a second contact plug, wherein the second contact plug is overlying and electrically coupled to the gate stack. | 2015-09-10 |
20150255352 | Semiconductor Structures and Methods of Forming the Same - A method of forming a semiconductor structure may include: forming a first dielectric layer having a first thickness over a substrate; removing a first portion of the first dielectric layer to expose a second region of the substrate; forming a second dielectric layer having a second thickness over the second region of the substrate; removing a second portion of the first dielectric layer to expose a third region of the substrate; forming a third dielectric layer having a third thickness over the third region of the substrate; and forming a first plurality of gate stacks comprising the first dielectric layer in a first region of the substrate, a second plurality of gate stacks comprising the second dielectric layer in the second region of the substrate, and a third plurality of gate stacks comprising the third dielectric layer in the third region of the substrate. | 2015-09-10 |
20150255353 | FORMING SOURCE/DRAIN REGIONS WITH SINGLE RETICLE AND RESULTING DEVICE - Methods for forming FinFET source/drain regions with a single reticle and the resulting devices are disclosed. Embodiments may include forming a first fin and a second fin above a substrate, forming a gate crossing over the first fin and the second fin, removing portions of the first fin and the second fin on both sides the gate, forming silicon phosphorous tops on the first fin and the second fin in place of the portions, removing the silicon phosphorous tops on the first fin, and forming silicon germanium tops on the first fin in place of the silicon phosphorous tops. | 2015-09-10 |
20150255354 | COMPOSITE SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - Provided is a composite substrate which has a high-performance semiconductor layer. A composite substrate of the present invention comprises: a supporting substrate which is formed of an insulating material; a semiconductor layer which is formed of a single crystal semiconductor that is superposed on and joined to the supporting substrate; and interfacial inclusions which are present in the interface between the supporting substrate and the semiconductor layer at a density of 10 | 2015-09-10 |
20150255355 | SUBSTRATE PROCESSING APPARATUS, SUBSTRATE PROCESSING METHOD AND MEMORY MEDIUM - A substrate processing system includes a film-forming device to form photosensitive film on substrate, an exposure device to expose the film on the substrate, a relay device to transfer the substrate between the film-forming and exposure devices, a warping data acquisition device to acquire measured warping data of the substrate, a communication device to perform data communication with the exposure device, and a control device including film-forming, relay, measuring, and communication control sub-devices. The film-forming sub-device controls the film-forming device to form the film on the substrate, the relay sub-device controls the relay device to transfer the substrate to the exposure device, the measuring sub-device controls the warping data acquisition device to acquire the data after the controlling by the film-forming sub-device prior to the controlling by the relay sub-device, and the communication sub-device controls the communication device to transmit the data to the exposure device. | 2015-09-10 |
20150255356 | SUBSTRATE BAKING DEVICE AND TEMPERATURE ADJUSTING METHOD THEREOF - The present disclosure discloses a substrate baking device and a method for adjusting temperatures thereof. The substrate baking device comprises a baking device body having a hot plate composed of a plurality of subplates for baking a substrate, and a temperature adjusting mechanism for adjusting heating temperatures in the plurality of subplates of the baking device body. A heat conducting layer is arranged on the hot plate to cover the plurality of subplates. The substrate baking device is capable of improving film thickness uniformity. | 2015-09-10 |
20150255357 | POLISHING APPARATUS AND POLISHING METHOD - A polishing apparatus capable of achieving a good control operation for a distribution of remaining film thickness is disclosed. The polishing apparatus includes: a top ring configured to apply pressures separately to zones on a back surface of a substrate to press a front surface of the substrate against a polishing pad; a film-thickness sensor configured to obtain a film-thickness signal that varies in accordance with a film thickness of the substrate; and a polishing controller configured to manipulate the pressures. The polishing controller calculates indexes of a remaining film thickness in zones on the front surface of the substrate, manipulate the pressures based on the indexes for controlling a distribution of the remaining film thickness, and update at least one of control parameters using polishing data obtained during polishing of the substrate. | 2015-09-10 |
20150255358 | CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package includes a semiconductor chip, a first and a second depression, a first and second redistribution layer and a packaging layer. The semiconductor chip has an electronic component and a conductive pad that are electrically connected and disposed on an upper surface of the semiconductor chip. The first depression and first redistribution layer extend from the upper surface toward the lower surface of the semiconductor chip. The first redistribution layer and the conductive pad are electrically connected. The second depression and the second redistribution layer extends from the lower surface toward the upper surface and is in connection with the first depression through a connection portion. The second redistribution layer is electrically connected to the first redistribution layer through the connection portion. The packaging layer is disposed on the lower surface. | 2015-09-10 |
20150255359 | ELECTRONIC COMPONENT HAVING ENCAPSULATED WIRING BOARD AND METHOD FOR MANUFACTURING THE SAME - An electronic component including a wiring board having interlayer insulation layers and conductive patterns, the wiring board having a first surface and a second surface on the opposite side of the first surface, multiple first bumps formed on a first conductive pattern positioned on the first surface of the wiring board among the conductive patterns of the wiring board, a semiconductor element mounted on the first surface of the wiring board through the first bumps, an encapsulating resin encapsulating the semiconductor element and at least a portion of a side surface of the wiring board, the side surface of the wiring board extending between the first surface and second surface of the wiring board, and multiple of second bumps formed on the second surface of the wiring board and connected to a second conductive pattern of the conductive patterns in the wiring board. | 2015-09-10 |
20150255360 | PACKAGE ON PACKAGE STRUCTURE AND FABRICATION METHOD THEREOF - A package on package (PoP) structure is provided, which includes: a packaging substrate having a plurality of conductive bumps, wherein each of the conductive bumps has a metal ball and a solder material covering the metal ball; and an electronic element having a plurality of conductive posts, wherein the electronic element is stacked on the packaging substrate by correspondingly bonding the conductive posts to the conductive bumps, and each of the conductive posts and the corresponding conductive bump form a conductive element. The present invention facilitates the stacking process through butt joint of the conductive posts and the metal balls of the conductive bumps. | 2015-09-10 |
20150255361 | SEMICONDUCTOR DEVICE WITH THIN REDISTRIBUTION LAYERS - A semiconductor device with thin redistribution layers is disclosed and may include forming a first redistribution layer on a dummy substrate, electrically coupling a semiconductor die to the first redistribution layer, and forming a first encapsulant layer on the redistribution layer and around the semiconductor die. The dummy substrate may be removed thereby exposing a second surface of the first redistribution layer. A dummy film may be temporarily affixed to the exposed second surface of the redistribution layer and a second encapsulant layer may be formed on the exposed top surface of the semiconductor die, a top surface and side edges of the first encapsulant layer, and side edges of the first redistribution layer. The dummy film may be removed to again expose the second surface of the first redistribution layer, and a second redistribution layer may be formed on the first redistribution layer and on the second encapsulant layer. | 2015-09-10 |
20150255362 | Semiconductor Device with a Passivation Layer and Method for Producing Thereof - A semiconductor device includes a semiconductor body having a first surface, a contact electrode on the first surface, and a passivation layer on the first surface adjacent the contact electrode and partially overlapping the contact electrode. The passivation layer comprises a layer stack with a first layer comprising an oxide on the first surface, and a second layer comprising a nitride on the first layer. | 2015-09-10 |
20150255363 | SILICON-ON-INSULATOR HEAT SINK - An approach for sinking heat from a transistor is provided. A method includes forming a substrate contact extending from a first portion of a silicon-on-insulator (SOI) island to a substrate. The method also includes forming a transistor in a second portion of the SOI island. The method further includes electrically isolating the substrate contact from the transistor by doping the first portion of the SOI island. | 2015-09-10 |
20150255364 | Thermal Vias Disposed in a Substrate Without a Liner Layer - An apparatus relating generally to a substrate is disclosed. In such an apparatus, the substrate has formed therein a plurality of vias. A liner layer is located on the substrate, including being located in a subset of the plurality of vias. At least one of the plurality of vias does not have the liner layer located therein. A thermally conductive material is disposed in the at least one of the plurality of vias to provide a thermal via structure. | 2015-09-10 |
20150255365 | MICROELECTRONIC PACKAGE PLATE WITH EDGE RECESSES FOR IMPROVED ALIGNMENT - A microelectronic package includes a package substrate with at least one semiconductor die mounted thereon and a plate coupled to the package substrate. The plate is configured with a first recess formed in a first edge of the plate and a second recess formed in a second edge of the plate wherein the first edge and the second edge are formed on opposing sides of the plate. One advantage of the above-described embodiments is that a stiffener plate or heat spreader that is sized to cover most or all of the periphery of a package substrate can be coupled to the package substrate without causing alignment issues in subsequent fabrication processes. | 2015-09-10 |
20150255366 | EMBEDDED SYSTEM IN PACKAGE - In some embodiments, a system and/or method may include forming a semiconductor device package assembly. The method may include forming a substrate including a first surface and a second surface substantially opposite the first surface. The substrate may include an opening in the second surface. The first surface may include a first set of electrical conductors. The method may include positioning a first die in the opening. The first die may include a second set of electrical conductors. The method may include forming a third set of electrical conductors on a second die. The third set of conductors may include a first width and a first height. The method may include forming a fourth set of electrical conductors on the second die. The fourth set of conductors may include a second width and a second height. The second width may be less than the first width. The second height may be greater than the first height. | 2015-09-10 |
20150255367 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A base plate has a mounting surface on which a semiconductor element is mounted and a heat-radiation surface for radiating heat to a cooler. The cover has a portion that seals the semiconductor element on the mounting surface of the base plate. The cover has a projecting portion arranged outside the heat-radiation surface and projecting from a level of the heat-radiation surface in a thickness direction. The intermediate layer is arranged on the heat-radiation surface of the base plate, projects from the level of the projecting portion of the cover in a thickness direction, and is made of a thermoplastic material in a solid-phase state. | 2015-09-10 |
20150255368 | SILICON-ON-PLASTIC SEMICONDUCTOR DEVICE WITH INTERFACIAL ADHESION LAYER - A semiconductor device and methods for manufacturing the same are disclosed. The semiconductor device includes a polymer substrate and an interfacial layer over the polymer substrate. A buried oxide layer resides over the interfacial layer, and a device layer with at least a portion of a field effect device resides over the buried oxide layer. The polymer substrate is molded over the interfacial adhesion layer and has a thermal conductivity greater than 2 watts per meter Kelvin (W/mK) and an electrical resistivity greater than 10 | 2015-09-10 |
20150255369 | SEMICONDUCTOR DEVICE - [Object]A semiconductor device is configured to release heat from semiconductor chips more efficiently. [Means for Solution]A semiconductor device includes: a die pad | 2015-09-10 |
20150255370 | SEMICONDUCTOR DEVICE - A semiconductor device with improved heat radiation and improved insulation performance. The semiconductor device includes a semiconductor element, a lead frame bonded on one surface to the semiconductor element, a first insulating layer disposed on the other surface of the lead frame, and a metal base plate connected to the lead frame with the first insulating layer interposed between them, wherein an outer peripheral portion of the first insulating layer is inside an outer peripheral portion of the metal base plate, and the outer peripheral portion of the first insulating layer is covered with a second insulating layer having higher moisture resistance and higher insulation performance than the first insulating layer, the outer peripheral portion including an electric field concentrated point in an outer peripheral portion of the lead frame. | 2015-09-10 |
20150255371 | SEMICONDUCTOR PACKAGE WITH THERMAL VIA AND METHOD FOR FABRICATION THEREOF - A semiconductor package includes a semiconductor die having an active face and dielectric layers disposed on the active face of the semiconductor die. At least one opening is formed through the dielectric layers and extends from a non-bond pad area of the active face to an exterior surface of the dielectric layers. An electrically conductive layer is formed in the opening and is in physical contact with the active face of the semiconductor die. A thermally conductive material fills the opening to form a thermal via for dissipating heat away from the semiconductor die. | 2015-09-10 |
20150255372 | THROUGH-SILICON VIA (TSV)-BASED DEVICES AND ASSOCIATED TECHNIQUES AND CONFIGURATIONS - Embodiments of the present disclosure are directed toward through-silicon via (TSV)-based devices and associated techniques and configurations. In one embodiment, an apparatus includes a die having active circuitry disposed on a first side of the die and a second side disposed opposite to the first side, a bulk semiconductor material disposed between the first side and the second side of the die and a device including one or more of a capacitor, resistor or resonator disposed in the bulk semiconductor material, the capacitor, resistor or resonator including one or more TSV structures that extend through the bulk semiconductor material, an electrically insulative material disposed in the one or more TSV structures and an electrode material or resistor material in contact with the electrically insulative material within the one or more TSV structures. | 2015-09-10 |
20150255373 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR INTEGRATED CIRCUIT WAFER - According to one embodiment, a method of manufacturing a semiconductor device comprises forming through holes extending through a semiconductor substrate in a thickness direction to integrated circuits in chip areas, and forming a first mark opening and second mark openings in a dicing line. The method detects the first mark opening based on positions of the second mark openings. Then, the method performs alignment of exposure positions based on the position of the first mark opening to perform photolithography, thereby forming a resist pattern on the back side of the semiconductor substrate. | 2015-09-10 |
20150255374 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - In a semiconductor device in which a plurality of semiconductor chips are stacked, performance is enhanced without deteriorating productivity. The semiconductor device has a first semiconductor substrate having a first surface and a second surface opposite the first surface, a first insulating film formed on the first surface, a first hole formed in the first insulating film and partially extending into the first semiconductor substrate, a second hole formed in the second surface, a first electrode entirely filling the first hole, and a conductive film conformally formed in the second hole. The conductive film is electrically connected to a bottom surface of the first electrode and leaves a third hole in the first semiconductor substrate open. The third hole is configured to receive a second electrode of a second semiconductor substrate. | 2015-09-10 |
20150255375 | STACKED INTERCONNECT STRUCTURE AND METHOD OF MAKING THE SAME - A method is provided of forming an interconnect structure. The method comprises forming a first dielectric layer overlying a first conductive layer, etching a trench opening in the first dielectric layer, depositing a sacrificial material layer in the trench opening, and forming a second conductive layer overlying the sacrificial layer. The method also comprises forming a via to the sacrificial layer, and performing an etch to remove the sacrificial material layer through the via and leave a resultant air gap between the first conductive layer and the second conductive layer increasing the effective dielectric constant between the first and second conductive layers. | 2015-09-10 |
20150255376 | Power Semiconductor Package - A semiconductor package that includes a conductive can, a power semiconductor device electrically and mechanically attached to the inside surface of the can, and an IC semiconductor device copackaged with the power semiconductor device inside the can. | 2015-09-10 |
20150255377 | ULTRA-THIN SEMICONDUCTOR DEVICE AND PREPARATION METHOD THEREOF - A small and ultra-thin power semiconductor device and a preparation method are disclosed. The device includes a chip mounting unit with a plurality of pads with a plate arranged on top surface of each pad; a semiconductor chip flipped and attached on the chip mounting unit, where the electrodes at the front of the chip are electrically connected to the pads; a plastic packaging body covering the chip mounting units and the chip, where the top surface of the plate and the back surface of the chip are exposed out from top surface of the plastic packaging body and the bottom surfaces of the pads are exposed out of the bottom surface of the plastic packaging body; a plurality of top metal segments arranged on the top surface of the plastic packaging body and electrically connected to the top surface of each plate and the back surface of the chip. | 2015-09-10 |
20150255378 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a semiconductor device using a lead frame, in which an outer lead ( | 2015-09-10 |
20150255379 | SEMICONDUCTOR DEVICE WITH LEAD TERMINALS HAVING PORTIONS THEREOF EXTENDING OBLIQUELY - A semiconductor device in which a semiconductor chip, a lead frame and metal wires for electrically connecting the lead frame are sealed with sealing resin. The lead frame has a plurality of lead terminal portions, a supporting portion for supporting the semiconductor chip, and hanging lead portions supporting the supporting portion. Each of the lead terminal portions adjacent to the hanging lead portion is a chamfered lead terminal portion having, at its head, a chamfered portion formed substantially in parallel with the hanging lead portion so as to avoid interference with the hanging lead portion. | 2015-09-10 |
20150255380 | PACKAGE STRUCTURE - A package structure includes an insulation layer, a first conductive layer, a second conductive layer, at least one electronic component, and at least one thermal conduction structure. At least one first conductive via and at least one second conductive via are formed in the insulation layer. The first conductive layer is disposed on a top surface of the insulation layer and contacted with said at least one first conductive via. The second conductive layer is disposed on a bottom surface of the insulation layer and contacted with the second conductive via. The electronic component is embedded within the insulation layer, and includes plural conducting terminals. The plural conducting terminal is electrically connected with the first conductive layer and the second conductive layer through said at least one first conductive via and said at least one second conductive via. Said at least one thermal conduction structure is embedded within the insulation layer. | 2015-09-10 |
20150255381 | SEMICONDUCTOR PACKAGE - A semiconductor package having a structure in which a decoupling capacitor is disposed to be adjacent with a semiconductor chip using a vertical chip interconnection (VCI) to improve power integrity. The semiconductor package includes a semiconductor substrate including a first finger pad and a second finger pad, a semiconductor chip mounted on the semiconductor substrate and including a first chip pad and a second chip pad, a bonding tape electrically connecting the first finger pad and the first chip pad, and a bonding wire electrically connecting the second finger pad and the second chip pad. Here, the bonding tape is formed to make contact with a sidewall of the semiconductor chip in a vertical direction of the semiconductor chip. | 2015-09-10 |
20150255382 | Semiconductor Package with Conductive Clip - A semiconductor package that includes a conductive can, a power semiconductor device electrically and mechanically attached to the inside surface of the can, and an IC semiconductor device copackaged with the power semiconductor device inside the can. | 2015-09-10 |
20150255383 | MOUNTING MEMBER, ELECTRONIC COMPONENT, AND METHOD FOR MANUFACTURING MODULE - A mounting member includes a plurality of internal connecting portions, each of which is electrically connected to an electronic device, and a plurality of external connecting portions, each of which is soldered, wherein the plurality of external connecting portions include a first connecting portion in communication with at least any of the plurality of internal connecting portions, and a second connecting portion different from the first connecting portion, and surfaces of the first connecting portion and the second connecting portion include gold layers, and a thickness of the gold layer of the second connecting portion is smaller than a thickness of the gold layer of the first connecting portion. | 2015-09-10 |
20150255384 | ELECTRICAL CONNECTIVITY OF DIE TO A HOST SUBSTRATE - According to example configurations herein, an apparatus comprises a die and a host substrate. The die can include a first transistor and a second transistor. A surface of the die includes multiple conductive elements disposed thereon. The multiple conductive elements on the surface are electrically coupled to respective nodes of the first transistor and the second transistor. Prior to assembly, the first transistor and second transistor are electrically isolated from each other. During assembly, the surface of the die including the respective conductive elements is mounted on a facing of the host substrate. Accordingly, a die including multiple independent transistors can be flipped and mounted to a respective host substrate such as printed circuit board, lead frame, etc. | 2015-09-10 |
20150255385 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes insulating layers stacked in the shape of stairs, and conductive layers alternately stacked with the insulating layers, wherein the conductive layers each include a first region interposed between upper and lower insulating layers thereof, among the insulating layers, and a second region which extends from the first region and protrudes between the upper and lower insulating layers, and wherein a protruding part formed on a sidewall or an upper surface of the second region. | 2015-09-10 |
20150255386 | THREE-DIMENSIONAL (3D) SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING 3D SEMICONDUCTOR DEVICES - A three-dimensional (3D) semiconductor device includes a stack of conductive layers spaced from each other in a vertical direction, the stack having a staircase-shaped section in a connection region, and ends of the conductive layers constituting treads of the staircase-shaped section, respectively. The 3D semiconductor device further includes buffer patterns disposed on and protruding above the respective ends of the conductive layers, an interconnection structure disposed above the stack and including conductive lines, and contact plugs extending vertically between the conductive lines and the buffer patterns and electrically connected to the conductive layers of the stack via the buffer patterns. | 2015-09-10 |
20150255387 | SELECTIVE LOCAL METAL CAP LAYER FORMATION FOR IMPROVED ELECTROMIGRATION BEHAVIOR - A method of forming a wiring structure for an integrated circuit device includes forming a first metal line within an interlevel dielectric (ILD) layer, and forming a second metal line in the ILD layer adjacent the first metal line; masking selected regions of the first and second metal lines; selectively plating metal cap regions over exposed regions of the first and second metal lines at periodic intervals such that a spacing between adjacent metal cap regions of an individual metal line corresponds to a critical length, L, at which a back stress gradient balances an electromigration force in the individual metal line, so as to suppress mass transport of electrons; and wherein the metal cap regions of the first metal line are formed at staggered locations with respect to the metal cap regions of the second metal line, along a common longitudinal axis. | 2015-09-10 |
20150255388 | ENHANCEMENT OF ISO-VIA RELIABILITY - A semiconductor structure and a process for forming a semiconductor structure. There is a back end of the line wiring layer which includes a wiring line and an ILD layer. A metal-filled via extends through the ILD layer to make contact with the wiring line. There is a reliability enhancement material that surrounds at least part of the via so as to render the via compressive where the via contacts the wiring line. The reliability enhancement material may be compressive as deposited or may be made compressive after deposition. | 2015-09-10 |
20150255389 | Integrated Circuit Interconnects and Methods of Making Same - A copper alloy layer is blanket deposited over a low k dielectric layer and in via openings within the low k dielectric layer. The blanket deposited layer is then anisotropically etch to form horizontal interconnects. The interconnects are annealed to form a metal oxide barrier lining. A second low k dielectric layer is then depositing over the horizontal interconnects. Air gaps can be formed between adjacent interconnects to lower parasitic capacitance therebetween. | 2015-09-10 |
20150255390 | Semiconductor Devices and Methods of Manufacture Thereof - Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes forming an insulating material layer over a workpiece, patterning an upper portion of the insulating material layer with a conductive line pattern, and forming a stop layer comprising a metal oxide or a metal nitride over the patterned insulating material layer. A masking material is formed over the stop layer, and the masking material is patterned with a via pattern. The via pattern of the masking material is transferred to a lower portion of the insulating material layer. | 2015-09-10 |
20150255391 | Inductor With Magnetic Material - In accordance with an embodiment, a semiconductor device comprises a semiconductor die, an interposer, and conductive bumps bonding the semiconductor die to the interposer. The semiconductor die comprises a first metallization layer, and the first metallization layer comprises a first conductive pattern. The interposer comprises a second metallization layer, and the second metallization layer comprises a second conductive pattern. Some of the conductive bumps electrically couple the first conductive pattern to the second conductive pattern to form a coil. A magnetic layer is positioned within the coil. In another embodiment, a coil is formed on a single substrate, wherein a magnetic layer is positioned within the coil. Other embodiments contemplate other configurations of coils, inductors, and/or transformers, and contemplate methods of manufacture. | 2015-09-10 |
20150255392 | RESISTANCE STRUCTURE, INTEGRATED CIRCUIT, AND METHOD OF FABRICATING RESISTANCE STRUCTURE - A resistance structure including: a conductive layer provided at a surface layer portion of a semiconductor substrate; a first resistance element having long sides and short sides provided over the conductive layer with an insulating film interposed; a second resistance element having long sides and short sides provided over the conductive layer with the insulating film interposed and disposed such that one long side thereof opposes one long side of the first resistance element; first wiring that is connected to one end of the first resistance element; second wiring that is connected to one end of the second resistance element; third wiring that connects the other end of the first resistance element with the other end of the second resistance element; and a connection portion that connects any of the first wiring, the second wiring and the third wiring with the conductive layer. | 2015-09-10 |
20150255393 | ELECTRICAL FUSE WITH BOTTOM CONTACTS - A method including forming a fuse link after a first fuse contact and a second fuse contact. The fuse link is in direct contact with both the first fuse contact and the second fuse contact. Embodiments of the invention provide an e-fuse that is capable of being connected to a device either through back end of line or by a long contact allowing for sufficient separation between the e-fuse and the device. | 2015-09-10 |
20150255394 | SEMICONDUCTOR DEVICE WITH SELF-PROTECTING FUSE AND METHOD OF FABRICATING THE SAME - A semiconductor device with the metal fuse and a fabricating method thereof are provided. The metal fuse connects an electronic component (e.g., a transistor) and a existing dummy feature which is grounded. The protection of the metal fuse can be designed to start at the beginning of the metallization formation processes. The grounded dummy feature provides a path for the plasma charging to the ground during the entire back end of the line process. The metal fuse is a process level protection as opposed to the diode, which is a circuit level protection. As a process level protection, the metal fuse protects subsequently-formed circuitry. In addition, no additional active area is required for the metal fuse in the chip other than internal dummy patterns that are already implemented. | 2015-09-10 |
20150255395 | CONTROLLED METAL EXTRUSION OPENING IN SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING - Aspects of the present invention relate to a controlled metal extrusion opening in a semiconductor structure. Various embodiments include a semiconductor structure. The structure includes an aluminum layer. The aluminum layer includes an aluminum island within the aluminum layer, and a lateral extrusion receiving opening extending through the aluminum layer adjacent the aluminum island. The opening includes a lateral extrusion of the aluminum layer of the semiconductor structure. Additional embodiments include a method of forming a semiconductor structure. The method can include forming an aluminum layer over a titanium layer. The aluminum layer includes an aluminum island within the aluminum layer. The method can also include forming an opening extending through the aluminum layer adjacent the aluminum island within the aluminum layer. The opening includes a lateral extrusion of the aluminum layer of the semiconductor layer. | 2015-09-10 |