37th week of 2015 patent applcation highlights part 51 |
Patent application number | Title | Published |
20150255096 | NEAR-FIELD LIGHT GENERATOR INCLUDING A WAVEGUIDE AND A PLASMON GENERATOR - A plasmon generator includes a first portion and a second portion. A core of a waveguide includes a main body portion and a protruding portion. The main body portion has a first surface and a second surface parallel to each other. The protruding portion lies on the first surface. A cladding of the waveguide includes a receiving-portion-forming layer lying on the first surface. At least part of the first portion of the plasmon generator is received in a receiving portion defined by the protruding portion and the receiving-portion-forming layer. | 2015-09-10 |
20150255097 | NEAR FIELD TRANSDUCER AND HEAT SINK DESIGN FOR HEAT ASSISTED MAGNETIC RECORDING - Apparatuses, systems, and methods are disclosed related to heat assisted magnetic recording. According to one embodiment, an apparatus that includes a heat sink region and a near field transducer region is disclosed. The near field transducer region is thermally coupled to the heat sink region. At least one of the heat sink region and the near field transducer region includes both an inner core and an outer shell. The inner core can be comprised of a non-plasmonic material and the outer shell can be comprised of a plasmonic material. In further embodiments, the inner core is comprised of a material having a relatively higher electron-phonon coupling constant and the outer shell is comprised of a material having a relatively lower electron-phonon coupling constant. | 2015-09-10 |
20150255098 | MULTI-PURPOSE NEAR-FIELD TRANSDUCER HAVING A TEMPERATURE COEFFICIENT OF RESISTANCE - An apparatus includes a writer, an arrangement comprising a plasmonic near-field transducer (NFT) adjacent the writer and comprising a material having a temperature coefficient of resistance (TCR), and a lead arrangement connected to the NFT arrangement. In some configurations, the NFT arrangement includes a heat sink, and the lead arrangement is connected to the heat sink. In other configurations, the lead arrangement is connected directly to the NFT. | 2015-09-10 |
20150255099 | DISK DRIVE EMPLOYING MULTIPLE READ ELEMENTS TO INCREASE RADIAL BAND FOR TWO-DIMENSIONAL MAGNETIC RECORDING - A disk drive is disclosed comprising a disk comprising a plurality of tracks, and a head comprising at least three read elements including a first read element, a second read element, and a third read element. When the head is within a first radial band of the disk, data recorded on the disk is detected using the first read element and the second read element. When the head is within a second radial band of the disk different from the first radial band, data recorded on the disk is detected using the first read element and the third read element. The first read element is substantially aligned down-track with the third read element when the head is over a first radial location of the disk. | 2015-09-10 |
20150255100 | APPARATUS, SYSTEMS AND PROCESSES FOR REDUCING A HARD DISK DRIVE'S ACCES TIME AND CONCOMITANT POWER OPTIMIZATION - Rotational latency is reduced in a standard conventional form factor HDD system by replacing, for example—the prior art rotary arm actuator of a conventional HDD, with one or more belts and pulleys and one or more read/write heads mounted on, or otherwise associated with the belts. Multiple scaled iterations facilitate energy savings and power optimized systems, without compromise to data access performance. | 2015-09-10 |
20150255101 | TRACK MISREGISTRATION SENSITIVE INITIALIZATION OF JOINT EQUALIZER - A method of mitigating an effect of track misregistration on read performance in a system comprising an array-reader includes determining an estimated off-track condition, selecting translation coefficients based on the estimated off-track condition, determining updated equalizer coefficients by applying the translation coefficients to native equalizer coefficients, and applying the updated equalizer coefficients to signals received from the array-reader to output a read signal. | 2015-09-10 |
20150255102 | HEAD TRANSDUCER WITH MULTIPLE RESISTANCE TEMPERATURE SENSORS FOR HEAD-MEDIUM SPACING AND CONTACT DETECTION - A head transducer, configured to interact with a magnetic recording medium, includes a first sensor having a temperature coefficient of resistance (TCR) and configured to produce a first sensor signal, and a second sensor having a TCR and configured to produce a second sensor signal. One of the first and second sensors is situated at or near a close point of the head transducer in relation to the magnetic recording medium, and the other of the first and second sensors spaced away from the close point. Circuitry is configured to combine the first and second sensor signals and produce a combined sensor signal indicative of one or both of a change in head-medium spacing and head-medium contact. Each of the sensors may have a TCR with the same sign (positive or negative) or each sensor may have a TCR with a different sign. | 2015-09-10 |
20150255103 | MAGNETIC-DISK GLASS SUBSTRATE, MAGNETIC DISK AND METHOD FOR MANUFACTURING MAGNETIC-DISK GLASS SUBSTRATE - A magnetic-disk glass substrate of the present invention includes a pair of main surfaces, a side wall surface, and a chamfered surface between the main surfaces and the side wall surface. Regarding surface properties of at least one of the side wall surface and the chamfered surface of the glass substrate, an arithmetic average roughness (Ra) is 0.015 μm or less, and a bearing factor of a roughness cross-sectional area when a roughness percentage is 60% is 95% or more in a bearing curve of a roughness cross-sectional area. | 2015-09-10 |
20150255104 | TAPE RECORDING MEDIUM, INFORMATION RECORDING/REPRODUCING DEVICE, AND METHOD OF MANUFACTURING TAPE RECORDING MEDIUM - Provided is a tape recording medium including: a base layer having a first surface and a second surface; a first recording layer disposed over the first surface of the base layer and capable of optically recording first data; an imprinted layer disposed between the base layer and the first recording layer; and a second recording layer. The second recording layer is disposed over the second surface of the base layer, contains a magnetic material, and has recorded second data different from the first data. | 2015-09-10 |
20150255105 | METHOD FOR CONTROLLING POWER OF LASER EMITTING UNIT AND ASSOCIATED APPARATUS - A method for controlling a power of a laser emitting unit includes: receiving a reflected light from an object, where the object reflects light emitted from the laser emitting unit; determining a power of the reflected light; and determining a control signal by referring to a level of the power of the reflected light to control the power of the laser emitting unit. | 2015-09-10 |
20150255106 | OPTICAL RECORDING DEVICE, OPTICAL RECORDING METHOD, AND OPTICAL RECORDING MEDIUM - When recording is performed by focusing a short pulse laser on an inside of a transparent medium such as quartz glass, and forming a minute deformed region in which the refractive index is different from that of surroundings thereof, it is difficult to ensure a recording quality. | 2015-09-10 |
20150255107 | TAPE RECORDING MEDIUM, INFORMATION RECORDING/REPRODUCING DEVICE, AND METHOD OF MANUFACTURING TAPE RECORDING MEDIUM - Provided is an optically recordable or reproducible tape recording medium including tracking pattern groups and non-tracking pattern areas. The tracking pattern groups are repeatedly provided along a longitudinal direction of the tape, and each of the groups includes a plurality of tracking patterns. The non-tracking pattern areas are respectively provided between the tracking patterns. In addition, the non-tracking pattern areas have different lengths along the longitudinal direction of the tape. | 2015-09-10 |
20150255108 | RECORDING AND REPRODUCING APPARATUS - A recording and reproducing apparatus of this disclosure includes, reader writer | 2015-09-10 |
20150255109 | Non-Decision Directed Magnetoresistive Asymetry Estimation - Systems and methods for magnetoresistive asymmetry estimation may include, but are not limited to, operations for: receiving a magnetic read head transducer output; computing a mean value of the magnetic read head transducer output; computing a median value of the magnetic read head transducer output; and applying a correction coefficient to a magnetic read head detector input according to at least the mean value of the magnetic read head transducer output and the median value of the magnetic read head transducer output. | 2015-09-10 |
20150255110 | TAPE MEDIA KISS-CONTACT READ VERIFICATION - A supplemental module that includes one or more read elements periodically engages a magnetic recording medium, and the read elements generate an electrical signal corresponding to transitions written to the magnetic recording medium by a write element. A computer receives information representative of the electrical signal and determines if a quality metric of the magnetic recording medium derived from the electrical signal is within a defined range. If the quality metric is not within the defined range, a defined action is performed by the computer. | 2015-09-10 |
20150255111 | PERSONALIZED AUDIO CONTENT DEVICE FOR GIFTING AUDIO CONTENT - This invention is directed to a computerized audio content gifting device. The ability to send audio content to a recipient as a gift allows the personalization of gifts such as flowers and candy to be made. The invention includes a housing with a circuit board, operational buttons, a communication port, a speaker, an attachment member and, a set of computer readable instructions stored on the computer readable medium that, when executed by the processor, provides for: receiving audio content from a server in electronic communications with the circuit board using the communications port, playing the audio content when an operational button is placed in the “on” position. The invention can also determine if there are copyright restrictions on the audio content and manage the number of authorized copies. | 2015-09-10 |
20150255112 | HIGH PERFORMANCE CARTRIDGE FORMAT - In one embodiment, a computer program product includes a computer readable storage medium having program instructions embodied therewith, the program instructions readable/executable by a controller to cause the controller to: determine and/or receive, by the controller, a selection of which of at least two track width formats to use during writing of data on a magnetic recording tape, wherein the track width format is selected based on an environmental condition; and cause, by the controller, simultaneous writing of a plurality of data tracks to the magnetic recording tape using only one of the track width formats at a same time such that each of the data tracks written at the same time has a track width that is substantially the same. | 2015-09-10 |
20150255113 | Online Iteration Resource Allocation for Large Sector Format Drive - Systems and methods for resource allocation for a large sector format processing may include, but are not limited to, operations for: determining non-convergence of a magnetic disc sub-sector of a first magnetic disc sector within a processing time frame allocated to the magnetic disc sub-sector; determining a convergence of a second magnetic disc sector occurring in less time than a processing time frame allocated to the second magnetic disc sector; and processing the magnetic disc sub-sector during a portion of the processing time frame allocated to the second magnetic disc sector remaining after processing of the second magnetic disc sector. | 2015-09-10 |
20150255114 | METHOD FOR REDUCING WRITE AMPLIFICATION ON A DATA CARRIER WITH OVERLAPPING DATA TRACKS AND DEVICE THEREOF - A novel symmetrical band is disclosed, which may be used in connection with shingled magnetic recording (SMR) in order to reduce write amplification (read-modify-write). Depending on the embodiment, overlapping data tracks diverge from, or converge to the center of each symmetrical band. Associated guard regions may be located at the center, or at the band boundaries, and are shared such that the excess width of a write element is caught by the guard regions from both sides. A symmetrical band may reduce the maximum write amplification by more than half. A hard disk controller may maintain the number of taken or empty tracks on both sides of each symmetrical band substantially equal at every fill level. | 2015-09-10 |
20150255115 | Method for efficient write operations on a data carrier with overlapping data tracks and device thereof - A method and a device for efficient write operations are disclosed, which may be used in connection with shingled magnetic recording (SMR) in order to reduce write amplification (read-modify-write). The tracks on at least one data carrier surface are grouped into bands, and the address space of logical block addresses is divided into address subsets. Each of these address subsets is permanently assigned to a dedicated selection of tracks derived from all bands. Depending on the embodiment, the dedicated selection of tracks may be chosen in such a way that no write amplification occurs in a first phase and/or that recent data or newly added data can be altered without necessitating read-modify-write. | 2015-09-10 |
20150255116 | COMPUTER NODE TESTING - A computer node comprises dual hard drives. A method of testing the computer node comprises performing a test of the first hard drive, waiting a specific time period, and performing a test of the second hard drive. Each test comprises isolating the drive being tested, writing data to the drive being tested, removing power from the drive being tested, repowering the drive being tested, and reading data from the drive being tested. | 2015-09-10 |
20150255117 | Friction Adjustment Mechanisms for Optimizing Friction Between a Pad and a Disc in an Optical Disc Restoration Device, and Systems and Methods Thereof - The invention pertains in general to a latching mechanism for maintaining desired friction levels on an optical disc in an optical disc restoration device. In particular the invention pertains to devices, systems and methods for easily maintaining friction levels between pads and an optical disc in an optical disc restoration device for ease of adjusting friction settings during quality control, repair operation or when optimization settings are being set in an optical disc restoration device by a user. | 2015-09-10 |
20150255118 | Vapor and Heat Removal Systems in an Optical Disc Restoration Device, and Devices, Systems and Methods Thereof - The invention pertains in general to devices, systems and methods for removing vapor and heat generated during a restoration cycle in an optical disc restoration device. | 2015-09-10 |
20150255119 | DISPLAY APPARATUS AND METHOD FOR EDITING AND DISPLAYING RECORDED VIDEO CONTENT - A display apparatus and a method for editing and displaying recorded video content are provided. The method for editing recorded video content in a display apparatus includes receiving an input of an edit command for a specific frame section of the video content, generating an indexing packet to indicate the edit command for the specific frame section through extraction of information of the specific frame section for which the edit command is input, and storing a transport stream for the video content, the index packet being inserted to the transport stream. Accordingly, the display apparatus can accurately edit the video frame section that corresponds to the image selected by the user, and can reduce a blocking phenomenon that occurs during the editing. | 2015-09-10 |
20150255120 | METHOD AND APPARATUS FOR COMPOSITION OF SUBTITLES - Embodiments of the invention include a subtitling format encompassing elements of enhanced syntax and semantic to provide improved animation capabilities. The disclosed elements improve subtitle performance without stressing the available subtitle bitrate. This will become essential for authoring content of high-end HDTV subtitles in pre-recorded format, which can be broadcast or stored on high capacity optical media, e.g. the Blue-ray Disc. Embodiments of the invention include abilities for improved authoring possibilities for the content production to animate subtitles. For subtitles that are separate from AV material, a method includes using one or more superimposed subtitle layers, and displaying only a selected part of the transferred subtitles at a time. Further, colors of a selected part of the displayed subtitles may be modified, e.g. highlighted. | 2015-09-10 |
20150255121 | METHOD AND APPARATUS FOR COMPOSITION OF SUBTITLES - Embodiments of the invention include a subtitling format encompassing elements of enhanced syntax and semantic to provide improved animation capabilities. The disclosed elements improve subtitle performance without stressing the available subtitle bitrate. This will become essential for authoring content of high-end HDTV subtitles in pre-recorded format, which can be broadcast or stored on high capacity optical media, e.g. the Blue-ray Disc. Embodiments of the invention include abilities for improved authoring possibilities for the content production to animate subtitles. For subtitles that are separate from AV material, a method includes using one or more superimposed subtitle layers, and displaying only a selected part of the transferred subtitles at a time. Further, colors of a selected part of the displayed subtitles may be modified, e.g. highlighted. | 2015-09-10 |
20150255122 | NON-VOLATILE SLEMICONDUCTOR STORAGE DEVICE - A non-volatile semiconductor storage device according to each of the embodiments includes a cell array that includes a plurality of first wires extending in a first direction, a plurality of second wires extending in a second direction crossing the first direction, and a plurality of memory cells each provided at an intersection between each of the first wires and each of the second wires. Each memory cell includes a variable resistance film of which resistance varies depending on a state of a filament in a medium. Each cell array has a first portion at which a distance between the first wire and the second wire is minimized and a second portion at which a distance between the first wire and the second wire is larger than the first portion at the intersection between each of the first wires and each of the second wires. | 2015-09-10 |
20150255123 | SEMICONDUCTOR DEVICE - A semiconductor device may include a semiconductor substrate; a test circuit array region; a pad region on the semiconductor substrate and at at least a first side of the test circuit array region and outside of the test circuit array region, transistors arranged in the test circuit array region in a first direction and a second direction perpendicular to the first direction, source lines spaced apart from each other in the second direction, each of the source lines extending in the first direction and electrically connected to corresponding source electrodes of the transistors, and drain lines spaced apart from each other in the second direction, each of the drain lines extending in the first direction and electrically connected to drain electrodes of the transistors. | 2015-09-10 |
20150255124 | ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY AND STORAGE ARRAY OF THE SAME - An Electrically Erasable Programmable Read-Only Memory (EEPROM) and an EEPROM storage array are provided. The EEPROM storage array includes: at least one storage area, wherein the storage area comprises M word lines in a row direction, 8 bit lines in a column direction, 8 source lines in the column direction, and a plurality of storage units arranged in M rows and 8 columns, where M is a positive integer; and wherein gate electrodes of storage units in a same row are connected with a same word line, drain electrodes of storage units in a same column are connected with a same bit line, and source electrodes of storage units in a same column are connected with a same source line. The EEPROM's volume is reduced by connecting source electrodes of storage units in a same column to a same source line, and arranging the source lines in a column direction. | 2015-09-10 |
20150255125 | ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY AND STORAGE ARRAY OF THE SAME - An Electrically Erasable Programmable Read-Only Memory (EEPROM) and an EEPROM storage array are provided. The EEPROM storage array includes: at least one storage area, wherein the storage area includes M word lines in a row direction, 8 bit lines in a column direction, N source lines in the row direction, and a plurality of storage units arranged in M rows and 8 columns; wherein M and N are positive integers; and wherein gate electrodes of storage units in a same row are connected with a same word line, source electrodes of storage units in every two adjacent rows are connected with a same source line, and drain electrodes of storage units in a same column are connected with a same bit line. There is no need to perform a decoding operation on source lines of the EEPROM and the EEPROM storage array, and a volume of the EEPROM is reduced. | 2015-09-10 |
20150255126 | MEMORY DEVICE AND ASSOCIATED CONTROLLING METHOD - A memory device and associated controlling method are provided. The memory device includes a memory cell array, a sensing unit and a controller. The memory cell has a plurality of memory cells. The sensing unit is electrically connected to the memory cell array and the controller. The sensing unit senses characteristic of a memory cell of the plurality of memory cells. The controller determines whether the characteristic of the one of the memory cells deviates and accordingly controls the memory cell array. | 2015-09-10 |
20150255127 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device according to the present embodiment includes a memory cell array including a plurality of memory cells. First bit lines transmit read signal voltages from the memory cells. A gate of a first transistor is connected to the first bit lines. A second bit line is connected to one of a drain and a source of the first transistor. A step voltage line is connected to the other one of the drain and the source of the first transistor to apply a step voltage changing in a stepwise manner to the first transistor at a time of reading. A reference-voltage generator generates a reference voltage. A sense part is connected to the second bit line to receive the read signal voltages and the reference voltage. | 2015-09-10 |
20150255128 | AMPLIFYING CIRCIT AND SEMICONDUCTOR MEMORY DEVICE INCLDING THE SAME - An amplifying circuit includes a first sense amplifying unit suitable for sensing and amplifying data on input/output lines, a second sense amplifying unit suitable for sensing and amplifying the data on the input/output lines or an output signal of the first sense amplifying unit, and a control unit suitable for activating the first sense amplifying unit during an initial operation period of an active operation and inactivating the first sense amplifying unit after the initial operation period, wherein the second sense amplifying unit performs a sensing and amplifying operation, based on the output signal of the first sense amplifying unit during the initial operation period, and based on the data on the input/output lines after the initial operation period. | 2015-09-10 |
20150255129 | METHOD FOR PERFORMING MEMORY INTERFACE CONTROL OF AN ELECTRONIC DEVICE, AND ASSOCIATED APPARATUS - A method for performing memory interface control of an electronic device and an associated apparatus are provided, where the method includes the steps of: when it is detected that a phase difference between a data signal and a clock signal reaches a predetermined value, controlling the clock signal to switch from a first frequency to a second frequency, wherein both of the clock signal and the data signal are signals of a memory interface circuit of the electronic device, and the memory interface circuit is arranged for controlling a random access memory (RAM) of the electronic device; applying at least one phase shift to the data signal until a condition is satisfied; and controlling the clock signal to switch from the second frequency to the first frequency; wherein the memory interface circuit is calibrated with aid of the at least one phase shift. | 2015-09-10 |
20150255130 | DDR4-SSD DUAL-PORT DIMM DEVICE - As a solution to the type of problems noted above, this disclosure provides novel methods and systems that include dual-port solid-state drive (SSD) DIMM devices to provide primary storage capabilities with very low latency and better availability of DDR4 devices. The dual-port DDR4-SSD flash memory devices guarantee primary storage devices still accessible with one CPU or network failure. The novel DDR4 memory bus devices may be used not only for memory media and storage device buffers, but also to allow two CPUs to share data stored in flash SSD chips and to greatly improve DDR4 bus efficiency and bus utilizations by block accesses and eliminate PCIE-DMA data transfers. Through the features of the claimed subject matter described herein, dual-port DDR4-DIMM memory devices can be achieved that provide an All-Flash-Array storage system with substantially higher reliability, availability, and performance over conventional SATA/SAS-SSD, PCIE-SSD, and NVME-SSD solutions. | 2015-09-10 |
20150255131 | STACKED SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR SYSTEM CAPABLE OF INPUTTING SIGNALS THROUGH VARIOUS PATHS - A semiconductor apparatus includes a control signal reception portion. The control signal reception portion may set information related to operation of a memory chip by receiving a command signal and an address signal from one among a stack chip test portion, a control signal interface portion and a test setting portion. | 2015-09-10 |
20150255132 | SEMICONDUCTOR SYSTEM AND METHOD OF OPERATING THE SAME - A semiconductor system includes multiple semiconductor devices operating commonly in response to a command signal, wherein each of the multiple semiconductor devices is independently activated according to each of multiple data strobe signals respectively corresponding to the multiple semiconductor devices; and a controller suitable for providing the command signal and the multiple data strobe signals. | 2015-09-10 |
20150255133 | ASSISTED LOCAL SOURCE LINE - In some examples, a memory device has a memory array configured to include sets of bit cells grouped based in part on an arrangement of local source lines. Each of the groups of cells may include an assist bit having a lower impedance than the other bit cells of the group to cause current distributed by the local source lines to be largely provided to the assist bit. In some examples, the assist bit include a shorted tunnel junction and in other examples, multiple assist bits may be connected by one or more bridge assisted bit lines. | 2015-09-10 |
20150255134 | STORAGE CELL, STORAGE DEVICE, AND MAGNETIC HEAD - Provided is a storage cell that makes it possible to enhance magnetic characteristics of magnetization pinned layer, a storage device and a magnetic head that include the storage cell. The storage cell includes a layer structure including a base layer, a storage layer in which a direction of magnetization is varied in correspondence with information, a magnetization pinned layer that is formed above the base layer and has magnetization that is perpendicular to a film surface and serves as a reference of information stored in the storage layer, and an intermediate layer that is provided between the storage layer and the magnetization pinned layer and is made of a nonmagnetic body. The base layer has a laminated structure of ruthenium and a nonmagnetic body having a face-centered cubic lattice, and the ruthenium is formed at a location adjacent to the magnetization pinned layer. | 2015-09-10 |
20150255135 | MAGNETOELECTRIC DEVICE, METHOD FOR FORMING A MAGNETOELECTRIC DEVICE, AND WRITING METHOD FOR A MAGNETOELECTRIC DEVICE - A magnetoelectric device is provided. The magnetoelectric device includes a reference magnetic layer structure having a fixed magnetization orientation, and a synthetic antiferromagnetic layer structure including a free magnetic layer structure and a coupling magnetic layer structure antiferromagnetically coupled to each other, each of the free magnetic layer structure and the coupling magnetic layer structure having a magnetization orientation that is variable, wherein the reference magnetic layer structure and the synthetic antiferromagnetic layer structure are arranged one over the other. According to further embodiments of the present invention, a method for forming a magnetoelectric device and a writing method for a magnetoelectric device are also provided. | 2015-09-10 |
20150255136 | Symmetrical Differential Sensing Method and System for STT MRAM - The invention relates to methods and systems for reading a memory cell and in particular, an STT MRAM. In one example, a system for reading a memory cell includes a sense path and an inverse path. A reference current is provided through the sense path and is sampled via a first sampling element in the sense path, and a cell current from the memory cell is provided through the inverse sense path and is sampled via a second sampling element in the inverse sense path. Subsequently, the memory cell is disconnected from the inverse sense path, the cell current is provided through the sense path, the reference source is disconnected from the sense path, and the reference current is provided through the inverse sense path. The output levels are then determined by the cell and reference currents working against the sampled reference and sampled cell currents. | 2015-09-10 |
20150255137 | WORD LINE AUTO-BOOTING IN A SPIN-TORQUE MAGNETIC MEMORY HAVING LOCAL SOURCE LINES - In a spin-torque magnetic random access memory (MRAM) that includes local source lines, auto-booting of the word line is used to conserve power consumption by reusing charge already present from driving a plurality of bit lines during writing operations. Auto-booting is accomplished by first driving the word line to a first word line voltage. After such driving, the word line isolated. Subsequent driving of the plurality of bit lines that are capacitively coupled to the word line causes the word line voltage to be increased to a level desired to allow sufficient current to flow through a selected memory cell to write information into the selected memory cell. Additional embodiments include the use of a supplemental voltage provider that is able to further boost or hold the isolated word line at the needed voltage level. | 2015-09-10 |
20150255138 | CIRCUIT AND METHOD FOR IMPRINT REDUCTION IN FRAM MEMORIES - A method of operating a memory circuit (FIGS. | 2015-09-10 |
20150255139 | SEMICONDUCTOR DEVICE - [Problem] To provide a semiconductor device suitable for miniaturization. To provide a highly reliable semiconductor device. To provide a semiconductor device with improved operating speed. | 2015-09-10 |
20150255140 | SEMICONDUCTOR MEMORY DEVICE AND REFRESH CONTROL SYSTEM - A semiconductor memory device includes an address latch unit suitable for consecutively latching first refresh addresses, which correspond to successively-activated word lines, from consecutively received addresses for word lines to be activated in response to word line hit signals identifying the successively-activated word lines; an address comparison unit suitable for generating a comparison result signal by comparing the previously latched first address with the currently latched first address; a refresh control unit suitable for selecting a first refresh operation corresponding to the currently latched first address, and a second refresh operation corresponding to a second address in response to the comparison result signal, and a refresh command signal; and a refresh operation unit suitable for performing the first and second refresh operations on memory cells therein according to the selection of the refresh control unit. | 2015-09-10 |
20150255141 | MEMORY DEVICE - In a memory device, memory capacity per unit area is increased while a period in which data is held is ensured. The memory device includes a driver circuit provided over a substrate, and a plurality of memory cell arrays which are provided over the driver circuit and driven by the driver circuit. Each of the plurality of memory cell arrays includes a plurality of memory cells. Each of the plurality of memory cells includes a first transistor including a first gate electrode overlapping with an oxide semiconductor layer, and a capacitor including a source electrode or a drain electrode, a first gate insulating layer, and a conductive layer. The plurality of memory cell arrays is stacked to overlap. Thus, in the memory device, memory capacity per unit area is increased while a period in which data is held is ensured. | 2015-09-10 |
20150255142 | Compact System with Memory and PMU Integration - One or more integrated circuits including at least one integrated circuit that is fabricated in a DRAM fabrication process. Capacitors in the DRAM-fabricated integrated circuit can be used for decoupling for logic components of the integrated circuits, and may be used for fine-grain on-chip PMUs. Embedded DRAM memories can be used instead of SRAM memories, with increased density and reduced leakage. More compact systems can be implemented using the integrated circuits. | 2015-09-10 |
20150255143 | SEMICONDUCTOR DEVICE - According to an embodiment, a semiconductor device includes a first pull-up driver, a first pull-down driver, a second pull-up driver and a second pull-down driver. The first pull-up driver is configured to pull up a voltage of a signal output terminal, whose ON resistance is capable of being adjusted to a predetermined reference resistance value. The first pull-down driver is configured to pull down the voltage of the signal output terminal, whose ON resistance is capable of being adjusted to the reference resistance value. The second pull-up driver is configured to pull up the voltage of the signal output terminal, whose ON resistance is capable of being adjusted to n times the reference resistance value. The second pull-down driver is configured to pull down the voltage of the signal output terminal, whose ON resistance is capable of being adjusted to the n times the reference resistance value. | 2015-09-10 |
20150255144 | METHOD AND APPARATUS FOR CALIBRATING WRITE TIMING IN A MEMORY SYSTEM - A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period. | 2015-09-10 |
20150255145 | DEVICE AND APPARATUS HAVING ADDRESS AND COMMAND INPUT PATHS - A device includes a plurality of input terminals, a control circuit, and a plurality of signal buses. Each of the signal buses is coupled between the control circuit and an associated one of the plurality of input terminals and includes one or more first buffers, one or more second buffers and at least one latch circuit coupled between the one or more first buffers and the one or more second buffers. The one or more first buffers of one of the signal buses are different in number from the one or more first buffers of a different one of the signal buses. | 2015-09-10 |
20150255146 | SEMICONDUCTOR DEVICE INCLUDING SUBWORD DRIVER CIRCUIT - The present invention is provided with: subword drivers SWD for driving subword lines SWL, a selection circuit for supplying either negative potential VKK | 2015-09-10 |
20150255147 | WRITING METHOD FOR SOLID STATE DISK - A writing method for a solid state disk is disclosed. The method comprises following steps: A writing unit is arranged in a buffer memory, wherein plane addresses of the writing unit are in one-to-one correspondence with non-volatile memories of the solid state disk. A writing data is received. A reordered plane address of the writing unit is obtained by using the residue of the logical allocation address of the writing data dividing the plane address number. Whether the reordered plane address is empty is checked. If the reordered plane address is not empty, the next plane address is shifted and the plane address is reordered. If the reordered plane address is empty, the writing data is buffered to the reordered plane address and the logical allocation address of the writing data is arranged in order. | 2015-09-10 |
20150255148 | BIT LINE WRITE ASSIST FOR STATIC RANDOM ACCESS MEMORY ARCHITECTURES - SRAM devices are disclosed that utilize write assist circuits to improve the logical transitions of bit lines. In one embodiment, an SRAM device includes a pair of complimentary bit lines traversing a memory cell array for writing data to memory cells. The bit lines have a first end and a second end. A pair of complimentary write drivers is proximate to the first end of the bit lines that writes to the bit lines. A write assist circuit is proximate to the second end of the bit lines that receives a pre-charge signal to assist the write drivers in transitioning the bit lines from a logical zero state to a logical one state. The write assist circuit also receives a boost signal to assist the write drivers in transitioning the bit lines from a logical one state to a logical zero state. | 2015-09-10 |
20150255149 | MEMORY SYSTEM AND CONTROL METHOD - According to one embodiment, there is provided a memory system including a volatile memory and a controller. The volatile memory has 1 | 2015-09-10 |
20150255150 | MEMORY DEVICE WITH MEMORY BUFFER FOR PREMATURE READ PROTECTION - Devices and methods for accurate reading of data in memory technology prone to drifting memory characteristics. An example device includes a memory array for storing data, and a memory buffer for storing a subset of the data in the memory array. A memory controller is configured to read data from the memory buffer if the data was written to the memory array before a predetermined duration of time, and to read the data from the memory array if the data is at least one of not valid or not available at the memory buffer. | 2015-09-10 |
20150255151 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device according to the present embodiment includes a constant current source. A reference current path is connected to the constant current source to flow a reference current and to generate a reference voltage. A supply current path or a plurality of supply current paths are connected to bit lines to selectively flow supply a current or currents different from each other and generate a detection voltage. A sense amplifier is connected to the reference current path and the supply current paths to amplify a voltage difference between the reference voltage and the detection voltage. | 2015-09-10 |
20150255152 | RESISTANCE VARIABLE MEMORY SENSING - The present disclosure includes apparatuses and methods for sensing a resistance variable memory cell. A number of embodiments include programming a memory cell to an initial data state and determining a data state of the memory cell by applying a programming signal to the memory cell, the programming signal associated with programming memory cells to a particular data state, and determining whether the data state of the memory cell changes from the initial data state to the particular data state during application of the programming signal. | 2015-09-10 |
20150255153 | RESISTIVE MEMORY SENSING - The present disclosure includes apparatuses and methods for sensing a resistive memory cell. A number of embodiments include performing a sensing operation on a memory cell to determine a current value associated with the memory cell, applying a programming signal to the memory cell, and determining a data state of the memory cell based on the current value associated with the memory cell before applying the programming signal and a current value associated with the memory cell after applying the programming signal. | 2015-09-10 |
20150255154 | NON-VOLATILE MEMORY INCLUDING REFERENCE SIGNAL PATH - Some embodiments include apparatuses and methods having a first memory element and a first select component coupled to the first memory element, a second memory element and a second select component coupled to the second memory element, and an access line shared by the first and second select components. At least one of the embodiments can include a circuit to generate a signal indicating a state of the second memory element based on a first signal developed from a first signal path through the first memory element and a second signal developed from a second signal path through the second memory element. | 2015-09-10 |
20150255155 | STORAGE DEVICE WITH 2D CONFIGURATION OF PHASE CHANGE MEMORY INTEGRATED CIRCUITS - A storage device, apparatus, and method to write and/or read data from such storage device. The storage device, comprises a channel controller and phase change memory integrated circuits (PCM ICs) arranged in sub-channels, wherein each of the sub-channels comprises several PCM ICs connected by at least one data bus line, which at least one data bus line connects to the channel controller. The channel controller is configured to write data to and/or read data from the PCM ICs according to a matrix configuration of PCM ICs, wherein: a number of columns of the matrix configuration respectively corresponds to a number of the sub-channels, the sub-channels forming a channel, and a number of rows of the matrix configuration respectively corresponds to a number of sub-banks, the sub-banks forming a bank, wherein each of the sub-banks comprises PCM ICs that belong, each, to distinct sub-channels of the sub-channels. | 2015-09-10 |
20150255156 | Isolation Switching For Backup Memory - Certain embodiments described herein include a memory system having a volatile memory subsystem, a non-volatile memory subsystem, a controller coupled to the non-volatile memory subsystem, and a circuit coupled to the volatile memory subsystem, to the controller, and to a host system. In a first mode of operation, the circuit is operable to selectively isolate the controller from the volatile memory subsystem, and to selectively couple the volatile memory subsystem to the host system to allow data to be communicated between the volatile memory subsystem and the host system. In a second mode of operation, the circuit is operable to selectively couple the controller to the volatile memory subsystem to allow data to be communicated between the volatile memory subsystem and the nonvolatile memory subsystem using the controller, and the circuit is operable to selectively isolate the volatile memory subsystem from the host system. | 2015-09-10 |
20150255157 | SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE - A semiconductor device capable of generating a signal (e.g., a potential signal or a current signal) suitable for usage environment or a purpose. The semiconductor device includes a first memory circuit, a first circuit, and a second memory circuit. The first circuit converts a digital signal input from the first memory circuit into an analog signal. The first memory circuit includes an input node, an output node, a transistor, and a capacitor. The capacitor is electrically connected to the output node. The transistor can control a conduction state between the input node and the output node. An analog signal is input to the input node from the first circuit. The transistor includes an oxide semiconductor layer where a channel formation region is formed. | 2015-09-10 |
20150255158 | NONVOLATILE MEMORY AND MEMORY SYSTEM - According to one embodiment, in a nonvolatile memory, the determination unit determines whether a change process is executable or not. The change process is a process based on characteristics of the memory cell array when a first write process is performed. The change process changes at least one of a value of a write start voltage and an increase amount in a write voltage in a second write process. The second write process is a process where a write operation of writing data to upper pages of at least part of the plurality of nonvolatile memory cells and a verification operation are alternately repeated. The setting unit sets a maximum value for determining whether the second write process succeeds or fails to a first value when the change process is executable, and sets the maximum value to a second value when the change process is not executable. | 2015-09-10 |
20150255159 | METHOD FOR CONTROLLING A NON-VOLATILE SEMICONDUCTOR MEMORY, AND SEMICONDUCTOR STORAGE SYSTEM - A semiconductor storage system includes a first memory region including at least one block constituted from a plurality of memory cells, the memory cell is capable of storing n bits data, the block is a minimum unit which is capable of being independently erased, a second memory region including at least one block constituted from a plurality of memory cells, the memory cell is capable of storing m (m>n: m is integer) bits data, the block is a minimum unit which is capable of being independently erased, and a controller which controls a number of rewrites for the block in the first memory region not to be more than first predetermined number of times, and controls a number of rewrites for the block in the second memory region not to be more than a second predetermined number of times. | 2015-09-10 |
20150255160 | MEMORY HAVING MULTIPLE SELECTABLE SPECIFICATION GRADES AND METHOD FOR OPERATING THE SAME - A memory having multiple selectable specification grades, including: a plurality of storage bit units, control units corresponding to the storage bit units, a WL control unit for the storage bit units, and a selecting unit for controlling a memory of different specification grades. The storage bit units are regularly arrayed into row storage groups and column storage groups. Control electrodes of each row storage group are connected with one another and connected to a corresponding WL terminal. Source electrodes of the flash storage bit units of the row storage groups and the column storage groups are connected with one another and then connected to SL terminals. Drain electrodes of each column storage bit groups are connected with one another and connected to a corresponding BL terminal. The BL terminals in the column storage groups are connected to an amplifier detector via multiple paths of selectors. | 2015-09-10 |
20150255161 | NONVOLATILE MEMORY SYSTEM AND METHOD OF OPERATING THE SAME - According to example embodiments, a nonvolatile memory system includes a nonvolatile memory device and a memory controller. The nonvolatile memory device includes a plurality of planes and each plane includes a plurality of memory blocks. The memory controller is configured to classify the memory blocks of each of the planes into a plurality of groups. The memory controller is configured to select at least two memory blocks in a corresponding one of the groups, and to control the nonvolatile memory device so that the selected at least two memory blocks are multi-block erased. | 2015-09-10 |
20150255162 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR DETECTING LEAK CURRENT - According to one embodiment, a semiconductor memory device includes a leak current detection circuit that includes: a detection input end connected to a word line; a first detection end; a coupling circuit connected between the detection input end and the first detection end; a first switching circuit that supplies a voltage to be a reference to the first detection end according to a control signal; and an output circuit that outputs a detection signal corresponding to a change in a voltage of the first detection end caused by the detection input end and the first detection end being coupled by the coupling circuit. | 2015-09-10 |
20150255163 | DETERMINING AND USING SOFT DATA IN MEMORY DEVICES AND SYSTEMS - The present disclosure includes methods, devices, and systems for determining and using soft data in memory devices and systems. One or more embodiments include an array of memory cells and control circuitry coupled to the array. The control circuitry is configured to perform a number of sense operations on the memory cells using a number of sensing voltages to determine soft data associated with a target state of the memory cells, and adjust a sensing voltage used to determine the target state based, at least partially, on the determined soft data. | 2015-09-10 |
20150255164 | READ MARGIN MEASUREMENT IN A READ-ONLY MEMORY - Read margin measurement circuitry for measuring the read margin of floating-gate programmable non-volatile memory cells. In some embodiments, the read margin of a cell with a floating-gate transistor in a non-conductive state is measured by periodically clocking a counter following initiation of a read cycle; a latch stores the counter contents upon the cell under test making a transition due to leakage of the floating-gate transistor. Logic for testing a group of cells in parallel is disclosed. In some embodiments, the read margin of a cell in which the floating-gate transistor is set to a conductive state is measured by repeatedly reading the cell, with the output developing a voltage corresponding to the duty cycle of the output of the read circuit. | 2015-09-10 |
20150255165 | Sensing Circuits for Use In Low Power Nanometer Flash Memory Devices - Improved sensing circuits for use in low power nanometer flash memory devices are disclosed. | 2015-09-10 |
20150255166 | Compensating Source Side Resistance Versus Word Line - A method and non-volatile storage system are provided in which the voltage applied to the source end of a NAND string depends on the location of the non-volatile storage element that is selected for sensing. This may be done without body-biasing the NAND string. Having the magnitude of the voltage applied to the source end of a NAND string depend on the location of the selected memory cell (without any body biasing) helps to mitigate failures that are dependent on which word line is selected during a sensing operation of one embodiment. Additionally, the magnitude of a read pass voltage may depend on either the source line voltage or the location of the selected memory cell. | 2015-09-10 |
20150255167 | CLOCK MODE DETERMINATION IN A MEMORY SYSTEM - A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device. | 2015-09-10 |
20150255168 | SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME - A semiconductor memory device includes a command buffering unit suitable for receiving and buffering a command signal based on an enable control signal, a fuse array suitable for programming data based on the command signal, and an enable control unit suitable for generating the enable control signal, wherein an activation operation on the command buffering unit by the enable control signal is controlled during a programming operation period of the fuse array. | 2015-09-10 |
20150255169 | SEMICONDUCTOR DEVICE INCLUDING FUSE CIRCUIT - Disclosed herein is an apparatus that includes a fuse circuit including a fuse element, the fuse circuit configured to provide a first output signal having a first voltage or a second voltage responsive to a state of the fuse element, and a sense circuit configured to provide a second output signal having the first voltage or a third voltage responsive to the first output signal, the third voltage different from the second voltage. | 2015-09-10 |
20150255170 | Threshold Voltage Compensation Circuit Of Thin Film Transistor And Method For The Same, Shift Register, And Display Device - Provided are a threshold voltage compensation circuit of TFT and a method for the same, a shift register and a display device. The threshold voltage compensation circuit includes an input terminal, an output terminal connected to the source of the thin film transistor, a first resistor to a K | 2015-09-10 |
20150255171 | DISPLAY DEVICE - An objective of the present invention is to provide a display device capable of suppressing consumption of the current flowing through gate clock signal bus lines by reducing the loads on the gate clock signal bus lines. | 2015-09-10 |
20150255172 | GATE DRIVING CIRCUIT - An Nth stage shift register of a gate driving circuit includes a pull-up unit for pulling up an Nth stage gate signal of a gate line to a high level voltage according to a driving voltage and a first clock signal; an energy-store unit for providing the driving voltage to the pull-up unit; a driving unit for charging the energy-store unit according to a previous stage gate signal; a pull-down unit for pulling down the driving voltage and the Nth stage gate signal to a low level voltage according to a control signal; and a control unit for generating the control signal according to a second clock signal and the driving voltage ; wherein the first and the second clock signals have a same pulse width, and a rising edge of the first clock signal leads a rising edge of the second clock signal by 1/4 to 1/2 pulse width. | 2015-09-10 |
20150255173 | SWITCHED CAPACITOR CIRCUIT AND DRIVE METHOD THEREFOR - A switched capacitor circuit according to the present invention includes: a capacitor including a first terminal to which the input voltage is applied and a second terminal; a capacitor including a third terminal and a fourth terminal; an inverting amplifier including a second output terminal and a second input terminal which is connected to the fourth terminal; a capacitor including a fifth terminal and a sixth terminal; a capacitor including a seventh terminal and an eighth terminal and included in an electrical path between the second output terminal and the fifth terminal; and a capacitor including a ninth terminal and a tenth terminal connected to the second terminal and the sixth terminal, respectively. The third terminal is connected to the second terminal. The sixth terminal is connected to the output terminal. | 2015-09-10 |
20150255174 | MEMORY TESTING METHOD AND APPARATUS - A method and an apparatus for testing a memory are provided, where the memory includes a plurality of sectors each of which includes a plurality of bytes, and the testing is performed to the memory byte by byte. The method includes: during the testing, once a first byte in a first sector fails the testing, stopping testing the rest bytes in the first sector which haven't been tested, and skipping the testing to a second byte in a second sector. Accordingly, if one byte of the first sector fails the testing, the testing will be skipped to a second sector, and the remained bytes of the first sector will not be tested any more, and other testing items will not be implemented to the first sector within the whole testing flow. Therefore, redundant testing steps can be avoided and testing efficiency can be improved. | 2015-09-10 |
20150255175 | MEMORY TESTING AND FAILURE DATA FILTERING - A method for evaluating test results for a memory module. Contents of a data stream are reviewed for one or more sections of the memory module. A plurality of counters is incremented when a defective portion is encountered in the data stream for a first section of the memory module. Values of the plurality of counters are compared to corresponding threshold values. Provided two or more counter values are at or above their threshold values, the first section is marked as bad, all defective portions of the first section are removed from the test data stream, and a failure header indicating that the first section is bad is stored and because of which counters in an error cache, otherwise each defective portion of the first section is marked as good in the data stream provided an error correction counter value of the plurality of counter values is equal to or below a first threshold value. Data from the data stream identifying defective portions of the first section are stored in an error cache for each remaining defective portion of the first section identified after the error correction counter value passes the first threshold value. | 2015-09-10 |
20150255176 | MEMORY TEST ECC AUTO-CORRECTION OF FAILING DATA - A method according to one embodiment of the present invention for evaluating test results for a memory module. The method comprises reviewing contents of a test data stream for one or more sections of the memory module. A first counter is incremented when a defective portion is encountered in the test data stream for a first section of the one or more sections of the memory module. Each defective portion of the first section is marked as good in the test data stream so long as a first counter value is equal to or below a first threshold value. Data from the test data stream identifying defective portions of the first section are stored in an error cache for each remaining defective portion of the first section identified after the first counter passes a first threshold value. | 2015-09-10 |
20150255177 | SEMICONDUCTOR DEVICE AND MEMORY SYSTEM - According to one embodiment, there is provided a semiconductor device including a temperature detection circuit, a first register, a second register, and a selector. The temperature detection circuit is configured to output a first level when the temperature exceeds the detection temperature from under the detection temperature, and output a second level when the temperature decreases under the open temperature from above the open temperature. The first register is configured to hold a value to set a first detection temperature into the temperature detection circuit. The second register is configured to hold a value to set a second detection temperature into the temperature detection circuit. The selector is configured to output either the value of the first register or the value of the second register based on an output level of the temperature detection circuit in order to set the detection temperature of the temperature detection circuit. | 2015-09-10 |
20150255178 | Control Rod Drive Mechanism - A control rod drive mechanism includes an outer tube and a guide tube which is arranged in the outer tube and is held by the outer tube. Furthermore, the control rod drive mechanism includes a spool piece with an inner magnet coupling and a rotary shaft connected to the inner magnet coupling arranged internally. The lower end portion of the outer tube is supported by the spool piece in the spool piece. The outside diameter of the outer tube, through the length of the outer tube, is smaller than the inside diameter of the spool piece and the outer tube, in the radial direction of the outer tube, is not projected outside the inner surface of the spool piece. Therefore, the installation places of the O-rings which are a seal member are reduced and the time required for maintenance of the control rod drive mechanism can be shortened. | 2015-09-10 |
20150255179 | Surface Sediment Core Catcher - A core catcher comprising: a cap configured to be secured to a first end of a core liner such that when the first end of the core liner is inserted into sediment a sample sediment core enters the core liner through the cap; a cross-beam coupled to the cap and mounted across the first end of the core liner such that a cross-section of the first end of the core liner is divided into two openings; a flexible member secured to the cross-beam such that the flexible member, the cross-beam, and the cap form a dual-flap valve designed to allow the sediment core to enter the core liner through the two openings and to prevent the sediment core from escaping the core liner through the cap. | 2015-09-10 |
20150255180 | Safe Geometry Vacuum Design - A vacuum assembled along a centerline axis used to collect fissile material. The vacuum includes a housing having internal chamber, a top end having a top opening, a bottom end having a bottom opening, and a radial intake port opening. The vacuum includes a suction apparatus having an intake disposed at the intake opening and having a hose connection means for mating with a vacuum hose assembly. The suction apparatus also includes a flow-through fan disposed in the top opening. The fan intakes and exhausts the airflow in a direction parallel with the centerline axis. The suction apparatus also includes a container connection means disposed at the bottom opening for connecting an external container to bottom end of the housing. There is also provided a first cylindrical free space having a center point disposed along the centerline axis and a diameter passing through the center point. The diameter of the first cylindrical free space is less than or equal to the safe diameter for the fissile material of interest. The vacuum cleaner apparatus is sized to fit entirely within the diameter of the first free space. Therefore, the vacuum apparatus constitutes a single fissile unit that is safe by passive geometry control to prevent the potential for a nuclear criticality in the vacuum. | 2015-09-10 |
20150255181 | NUCLEAR POWER GENERATION SYSTEM - A nuclear power generation system and related power cycle are disclosed, in one embodiment, the system includes primary coolant circulation through a hydraulically interconnected reactor containing nuclear fuel and a steam generating vessel collectively defining a steam supply system. Liquid secondary coolant for the power cycle flows through the steam generating vessel and is converted to steam by the primary coolant to drive a low pressure turbine of a turbine-generator set. Steam exiting the turbine is condensed and heated prior to return to the steam supply system, thereby completing a secondary coolant flow loop. In one embodiment, a majority of the secondary coolant heating occurs within the steam generating vessel via heat exchange with the primary coolant rather than externally in the secondary coolant flow loop. This creates a temperature differential between the primary and secondary coolant sufficient to create natural thermally induced convective circulation of the primary coolant | 2015-09-10 |
20150255182 | CLOSURE DEVICE FOR CONTAINERS FOR TRANSPORTING RADIOACTIVE SUBSTANCES - The invention relates to a closure device for containers for transporting radioactive substances, having a first and a second component each with a comb-like portion, wherein the comb-like portions, with the closure device locked, has a bolt element passing through them. The bolt, element, has a head with an accommodating recess running or to the longitudinal axis of the bolt element, that one of the components has a through-opening which, with the bolt passing through the comb-like portions, is aligned with an accommodating recess. | 2015-09-10 |
20150255183 | TRANSPARENT CONDUCTOR AND OPTICAL DISPLAY INCLUDING THE SAME - A transparent conductor and an optical display including the same are disclosed. The transparent conductor includes a base layer, and a transparent conductive layer formed on the base layer and including metal nanowires. The transparent conductor has a total diffuse reflection (DR) of greater than or equal to about 80% and less than 330% at a wavelength of about 380 nm to about 780 nm and a reflective b* value from about −2 to about 1 at a wavelength of about 380 nm to about 780 nm. | 2015-09-10 |
20150255184 | GRAPHENE COATED ELECTRONIC COMPONENTS - In one aspect, coated electrical components are described herein. In some implementations, a coated electrical component comprises an electrical component and a graphene coating layer disposed on a surface of the electrical component. The graphene coating layer, in some implementations, has a thickness of about 300 nm or less. In another aspect, methods of increasing the service life of an electronic apparatus are disclosed herein. In some implementations, such a method comprises disposing a graphene coating layer on an environment-facing surface of an electronic component of the apparatus, wherein the electronic apparatus exhibits at least a 10 percent improvement in environmental testing performance compared to an otherwise equivalent electronic apparatus not comprising a graphene coating layer, the environmental testing performance comprising performance in a waterproofness test, acetic acid test, sugar solution test, or methyl alcohol test described herein. | 2015-09-10 |
20150255185 | CONDUCTIVE PASTE USED FOR SOLAR CELL ELECTRODES - The present invention is directed to a conductive paste used for solar cell electrodes comprising, (i) 60 wt % to 95 wt % of a conductive powder, based on the total weight of the conductive paste, (ii) 0.1 wt % to 10 wt % of a lead-tellurium-oxide powder, based on the total weight of the conductive paste, comprising 20 wt % to 60 wt % of PbO and 20 wt % to 60 wt % of TeO | 2015-09-10 |
20150255186 | BASE MATERIAL WITH A TRANSPARENT CONDUCTIVE FILM, METHOD FOR MANUFACTURING THE SAME, TOUCH PANEL, AND SOLAR CELL - A aspect of the present disclosure provides a base material with a transparent conductive film on or above the base material. The transparent conductive film includes a conductive layer containing metal wires, and a protective layer being located on a side of the conductive layer and containing a resin and a particle, the side not opposing to the base material. The particle is soluble in an acidic etching solution, and the resin is resistant to the acidic etching solution. | 2015-09-10 |
20150255187 | Separation of Single-Walled Carbon Nanotubes By Electronic Type Using Block Copolymers - The separation of single-walled carbon nanotubes (SWNTs), by electronic type using centrifugation of compositions of SWNTs and surface active block copolymers in density gradient media. | 2015-09-10 |
20150255188 | CONDUCTIVE SHAFT AND CONDUCTIVE ROLL FOR OA EQUIPMENT USING THE SHAFT, AND METHOD OF PRODUCING CONDUCTIVE SHAFT - Provided is a shaft made of a fiber-reinforced resin, in which a continuous glass fiber bundle is embedded in parallel with a lengthwise direction of the shaft, the shaft including a matrix resin formed of a resin composition comprising (A) a thermosetting resin as a main component, (B) carbon black, (C) a dispersant having a basic functional group, and (D) a curing agent for the component (A), in which the component (B) is particulate and is distributed along continuous glass fibers constituting the continuous glass fiber bundle. Thus, there can be provided a conductive shaft that is lightweight, has high strength, is excellent in conductivity, and is inexpensive, and a conductive roll for OA equipment using the shaft, and a method of producing the conductive shaft. | 2015-09-10 |
20150255189 | CABLE COMPRISING A PTFE COATING - A cable having one or more cores coated in a coating comprising at least one layer (a) of a material based on polytetrafluoroethylene (PTFE) with 5% to 80% by weight filler, and at least one layer (b) of a material based on PTFE with less than 8% by weight filler, the layer (b) being positioned outside the layer (a), and also a method of preparing the cable and a kit for constructing the cable. | 2015-09-10 |
20150255190 | WIRE STRUCTURE AND METHOD FOR DESIGNING THE SAME - A wire structure defined between a first plane and a second plane is provided. The first plane and the second plane are parallel to each other. The wire structure includes a main body and at least three convex portions. The main body has a center defined by its centroid and a periphery defined by the perimeter of the main body. The convex portions protrude from and are adjacently arranged around the periphery. At least one convex portion is tangent to the first plane, and at least two convex portions are tangent to the second plane. The number of the at least one convex portion tangent to the first plane is not equal to the number of the at least two convex portions tangent to the second plane. | 2015-09-10 |
20150255191 | SHIELDED ELECTRICAL RIBBON CABLE WITH DIELECTRIC SPACING - An electrical ribbon cable includes at least one conductor set having at least two elongated conductors extending from end-to-end of the cable. Each of the conductors are encompassed along a length of the cable by respective first dielectrics. A first and second film extend from end-to-end of the cable and are disposed on opposite sides of the cable The conductors are fixably coupled to the first and second films such that a consistent spacing is maintained between the first dielectrics of the conductors of each conductor set along the length of the cable. A second dielectric disposed within the spacing between the first dielectrics of the wires of each conductor set. | 2015-09-10 |
20150255192 | BUS BAR, BUS BAR MODULE, AND METHOD OF MANUFACTURING BUS BAR - A bus bar ( | 2015-09-10 |
20150255193 | SHELF BRACKETS TO CONDUCT ELECTRICITY TO REFRIGERATOR SHELVES - Shelf brackets to conduct electricity to refrigerator shelves are disclosed. An example shelf bracket includes an end configured to engage a support rail, the end having a first area to conduct electricity from the support rail to the shelf bracket, an arm extending from the end to support the shelf, the arm comprising a second area to conduct electricity from the shelf bracket to the shelf, a non-electrically conductive coating applied to substantially all of the shelf bracket except in the first and second areas, a first electrically conductive material applied to at least a portion of the first area, and a second electrically conductive material applied to at least a portion of the second area, wherein the shelf bracket is formed from a third electrically conductive material, the third electrically conductive material to conduct electricity between the first and second areas. | 2015-09-10 |
20150255194 | SELECTION METHOD FOR STRONG WIND REGION COMPOSITE INSULATOR BASED ON INTRINSIC FREQUENCY, AND COMPOSITE INSULATOR - A selection method for a strong wind region composite insulator based on a intrinsic frequency, and a composite insulator are provided. When a selection is made among a plurality of composite insulators according to the selection method, a intrinsic frequency of a composite insulator to be selected is measured first; if the composite insulator is an unequal-diameter umbrella, the intrinsic frequency of a large umbrella skirt in the composite insulator is measured; if the composite insulator is an equal-diameter umbrella, the intrinsic frequency of any umbrella skirt in the composite insulator is measured; and then a composite insulator is selected according to the intrinsic frequency, wherein the composite insulator whose intrinsic frequency is greater than or equal to 45 Hz is selected. The composite insulator is a composite insulator having corresponding structure parameters. Study is carried out on wind-resistant performance of an insulator when applied to a strong wind region to obtain the selection method, and the method is easy to operate and implement. When the composite insulator is applied to a strong wind region where the highest wind speed reaches 50 m/s, the problem of violent oscillation of umbrella skirts or tear of the umbrella skirts does not occur, and the composite insulator may still operate reliably. | 2015-09-10 |
20150255195 | VOLTAGE NONLINEAR RESISTIVE ELEMENT - A voltage nonlinear resistive element | 2015-09-10 |