36th week of 2010 patent applcation highlights part 53 |
Patent application number | Title | Published |
20100228921 | CACHE HIT MANAGEMENT - A system and method for cache hit management. | 2010-09-09 |
20100228922 | METHOD AND SYSTEM TO PERFORM BACKGROUND EVICTIONS OF CACHE MEMORY LINES - A method and system to provide a method and system to perform background evictions of cache memory lines. In one embodiment of the invention, when a processor of a system determines that the occupancy rate of its bus interface is between a low and a high threshold, the processor performs evictions of cache memory lines that are dirty. In another embodiment of the invention, the processor performs evictions of the dirty cache memory lines when a timer between each periodic clock interrupt of an operating system has expired. By performing background evictions of dirty cache memory lines, the number of dirty cache memory lines required to be evicted before the processor changes its state from a high power state to a low power state is reduced. | 2010-09-09 |
20100228923 | Memory system having multiple processors - A memory system includes multiple processors. The memory system includes first and second processors, a storage device and a controller. The storage device includes one or more banks which are respectively allocated to the first processor or the second processor. The controller controls the storage device to access a plurality of banks through an interleaving method when the plurality of banks are allocated to one processor. The memory system can improve performance and power efficiency. | 2010-09-09 |
20100228924 | RESOURCE SHARING IN A TELECOMMUNICATIONS ENVIRONMENT - A transceiver is designed to share memory and processing power amongst a plurality of transmitter and/or receiver latency paths, in a communications transceiver that carries or supports multiple applications. For example, the transmitter and/or receiver latency paths of the transceiver can share an interleaver/deinterleaver memory. This allocation can be done based on the data rate, latency, BER, impulse noise protection requirements of the application, data or information being transported over each latency path, or in general any parameter associated with the communications system. | 2010-09-09 |
20100228925 | PROCESSING SYSTEM WITH INTERSPERSED PROCESSORS USING SHARED MEMORY OF COMMUNICATION ELEMENTS - A processing system comprising processors and the dynamically configurable communication elements coupled together in an interspersed arrangement. The processors each comprise at least one arithmetic logic unit, an instruction processing unit, and a plurality of processor ports. The dynamically configurable communication elements each comprise a plurality of communication ports, a first memory, and a routing engine. For each of the processors, the plurality of processor ports is configured for coupling to a first subset of the plurality of dynamically configurable communication elements. For each of the dynamically configurable communication elements, the plurality of communication ports comprises a first subset of communication ports configured for coupling to a subset of the plurality of processors and a second subset of communication ports configured for coupling to a second subset of the plurality of dynamically configurable communication elements. | 2010-09-09 |
20100228926 | MULTI-PORT MEMORY DEVICES AND METHODS - An integrated circuit device may include a first integrated circuit (IC) portion having a single memory port to access at least one memory array, the single port including a first set of address, control and data paths; and a second IC portion comprising at least a first memory port and a second memory port for providing access to the memory locations of the first IC portion through the single port of the first IC portion. | 2010-09-09 |
20100228927 | STM WITH MULTIPLE GLOBAL VERSION COUNTERS - A software transactional memory system is provided with multiple global version counters. The system assigns an affinity to one of the global version counters for each thread that executes transactions. Each thread maintains a local copy of the global version counters for use in validating read accesses of transactions. Each thread uses a corresponding affinitized global version counter to store version numbers of write accesses of executed transactions. The system adaptively changes the affinities of threads when data conflict or global version counter conflict is detected between threads. | 2010-09-09 |
20100228928 | MEMORY BLOCK SELECTION - The present disclosure includes methods and devices for memory block selection. In one or more embodiments, a memory controller includes control circuitry coupled to one or more memory devices having multiple Groups of planes associated therewith, each Group including at least two planes of physical blocks organized into Super Blocks, with each Super Block including a physical block from each of the at least two planes. The control circuitry is configured to receive a first unassigned logical block address (LBA) associated with a write operation and determine a particular free Super Block within a selected one of the multiple Groups to receive data associated with the write operation. | 2010-09-09 |
20100228929 | EXPEDITED COMPLETION OF A TRANSACTION IN STM - A software transactional memory system is provided that provides privatization safety. The system identifies situations where the completion of a transaction may be expedited because a privatization artifact will not occur. The system determines whether a privatization artifact may occur using a read and write set intersection test, transactional variables, pessimistic locks, or declared privatizing transactions. If a privatization artifact will not occur for a transaction, then the system may allow the transaction to complete prior to one or more earlier transactions. | 2010-09-09 |
20100228930 | ACCESS CONTROL DEVICE, INFORMATION PROCESSING DEVICE, ACCESS CONTROL PROGRAM AND ACCESS CONTROL METHOD - An access control device which writes data to each of predetermined storage block sets in a storage device of which a storage area has been divided into a plurality of storage blocks. The control device includes a management information storage section and an access processing section. The management information storage section stores, for each of said storage blocks, record enable/disable information indicating whether said storage block is a non-defective block in which the data can be recorded or a defective block in which the data cannot be recorded. If the data is written to each of said storage block sets, the access processing section writes the data only to non-defective blocks in said storage block set based on the record enable/disable information stored in said management information storage section. | 2010-09-09 |
20100228931 | MANAGEMENT APPARATUS, SYSTEM, CONTROL METHOD, AND RECORDING MEDIUM - The present invention provides a management apparatus that can control a connection of each image forming apparatus to a network so as to maintain a function (capacity) of a big box formed by a plurality of image forming apparatuses. | 2010-09-09 |
20100228932 | METHOD OF TRANSFERRING AND ALIGNING OF INPUT DATA AND MEMORY DEVICE USING THE SAME - A method of transferring input data is disclosed. In one embodiment, during a burst having a burst length of N, the method comprises transferring to a memory device data for each of a plurality of unit intervals (UIs) of the burst through a plurality of terminals, wherein each of the transfers includes D bits of input data and at least some of the input data is to be written to the memory device. The method further comprises transferring to the memory device mask data during the burst as part of the input data, the mask data occupying at least two UIs, and transferring to the memory device content data during the burst as part of the input data, wherein the mask data transferred during each of the at least two UIs has the same value. | 2010-09-09 |
20100228933 | AUTOMATIC SELECTION OF STORAGE VOLUMES IN A DATA STORAGE SYSTEM - Automatic Selection of Storage Volumes in a Data Storage System A method of selecting a target volume in a storage system is provided. The method comprises defining one or more parameters for a plurality of storage volumes in the storage system according to user preference; dynamically collecting information related to the parameters while the storage volumes are used; receiving a request to backup a first source volume in the storage system; and selecting or creating the target volume based on the collected information. | 2010-09-09 |
20100228934 | Zero Copy Transport for iSCSI Target Based Storage Virtual Appliances - A method of transferring data from a virtual machine (VM) to a storage virtual appliance (SVA) is disclosed. In this method, the data is transferred to an iSCSI (Internet Small Computer System Interface) device that is coupled to the VM and has a zero copy data mover implementation of a TCP socket interface. The method further includes sending a memory address of the data to the SVA. The SVA includes an iSCSI device having a zero copy data mover implementation of a TCP socket interface to receive the memory address of the data. The VM and the SVA are running in a same hypervisor host. | 2010-09-09 |
20100228935 | CONDITIONAL STORAGE OF MULTIPLE INFORMATION ITEMS - A method for consistent version of multiple information items is provided. The method includes receiving a conditional request to copy a version of multiple information items at a condition fulfillment point of time that is associated with a fulfillment of a condition of the conditional request. Then determining that the condition is fulfilled, and participating in generating a condition fulfillment point in time version of the multiple information items. | 2010-09-09 |
20100228936 | ACCESSING MEMORY LOCATIONS FOR PAGED MEMORY OBJECTS IN AN OBJECT-ADDRESSED MEMORY SYSTEM - One embodiment of the present invention provides a system that accesses memory locations in an object-addressed memory system. During a memory access in the object-addressed memory system, the system receives an object identifier and an address. The system then uses the object identifier to identify a paged memory object associated with the memory access. Next, the system uses the address and a page table associated with the paged memory object to identify a memory page associated with the memory access. After determining the memory page, the system uses the address to access a memory location in the memory page. | 2010-09-09 |
20100228937 | SYSTEM AND METHOD FOR CONTROLLING EXIT OF SAVED DATA FROM SECURITY ZONE - A system for controlling exit of saved data from a security zone, comprising an access control device, the access control device comprising an access detection module for detecting access of an application to a security zone and access of an application to a general zone, a target checking module for comparing the application, detected by the access detection module, with a list and then controlling access of the application to the security zone and access of the application to the general zone, and a processing control module for controlling writing of data of the application to the general zone. | 2010-09-09 |
20100228938 | METHOD AND INSTRUCTION SET INCLUDING REGISTER SHIFTS AND ROTATES FOR DATA PROCESSING - A method includes identifying a first register with M bits and a second register with N bits. The process also includes shifting K bits, where K<=N, from the second register into the first register. The shifting operation executes a left shift operation including reading bits K . . . N−1 from the first register, writing bits K . . . N−1 into bit positions O . . . N−K−1 of the first register, reading K bits from the second register, and writing K bits from second register into bit positions N−K . . . N−1 of first register, or a right shift operation including reading bits O . . . N−K−1 from the first register, writing bits O . . . N−K−1 into bit position K . . . N−1 of the first register, reading the K bits from the second register, and writing K bits from second register into bit positions O . . . K−1 of first register. | 2010-09-09 |
20100228939 | Parallel Read Functional Unit for Microprocessors - A functional unit for a microprocessor is provided, which allows for fast, parallel data read, write, and manipulation operations in the microprocessor that are useful for a number of software applications, such as cryptography. The functional unit includes first and second source registers for receiving first and second data items to be processed by the functional unit, first and second banks of memory tables, a combinational logic circuit, and a decoder. The first and second banks of memory tables are in communication with the first source register, and each of the tables is indexed by an index comprising a portion of the first data item received by the first source register. Each index points to a lookup result in a respective one of the memory tables. The combinational logic circuit is in communication with the first and second banks of memory tables and the second source register, receives the lookup results, and processes the lookup results and the second data item in the second source register to produce a result data item. The decoder circuit is in communication with the combinational logic circuit, and extracts an operational code from an instruction supplied to the functional unit, decodes the operational code, and controls the combinational logic circuit in accordance with the operational code. | 2010-09-09 |
20100228940 | MEMORY BLOCK MANAGEMENT - Various embodiments include one or more memory devices having at least two planes of physical blocks organized into super blocks, with each super block including a physical block from each of the at least two planes. Embodiments include determining defective blocks within the planes. If none of the blocks at a particular block position are determined to be defective, embodiments include assigning the blocks at the particular block position to a super block, and if one or more of the blocks at a particular block position are determined to be defective, embodiments include: assigning the blocks at the particular block position determined to be defective to a super block; and assigning a respective replacement block to the super block for each of the one or more blocks at the particular block position determined to be defective. The respective replacement block is selected from a number of blocks within a respective one of the planes that includes the respective block determined to be defective. | 2010-09-09 |
20100228941 | Configurable Cache and Method to Configure Same - In a particular embodiment, a cache is disclosed that includes a tag state array that includes a tag area addressable by a set index. The tag state array also includes a state area addressable by a state address, where the set index and the state address include at least one common bit. | 2010-09-09 |
20100228942 | HOST COMPUTER, MULTIPATH SYSTEM, PATH ALLOCATION METHOD, AND PROGRAM - Provided is a host computer which is connected to a system resource through n (n≧2) number of paths. The host computer includes: a plurality of logical partitions accessible to the system resource; an allocation unit that allocates the paths to the plurality of logical partitions; and an allocation table. The allocation table is user configurable and stores, in a correlated manner, information indicating the logical partitions and information capable of indicating the number of paths to be allocated to the logical partitions indicated by the information. The allocation unit allocates the paths to the logical partitions in accordance with the allocation table. This makes it possible to secure the I/O response also for logical partitions having a small amount of I/O. | 2010-09-09 |
20100228943 | ACCESS MANAGEMENT TECHNIQUE FOR STORAGE-EFFICIENT MAPPING BETWEEN IDENTIFIER DOMAINS - Access management techniques have been developed to specify and facilitate mappings between I/O and host domains in ways that are storage-efficient and which can provide flexibility in the form, granularity and/or extent of mappings, attributes and access controls coded relative to a particular I/O domain. Indeed, different identifier and/or operation translation models may be employed on a per logical device (or even a per sub-window) basis. In general, the flexibility and efficiency afforded using some embodiments of the present invention can be desirable, particularly as numbers of I/O domains increase, such as in the case of virtualization system implementations in which a multiplicity of logical I/O devices may be represented using underlying physical resources. | 2010-09-09 |
20100228944 | Apparatus and Method to Translate Virtual Addresses to Physical Addresses in a Base Plus Offset Addressing Mode - An apparatus and method to translate virtual addresses to physical addresses in a base plus offset addressing mode are disclosed. In an embodiment, a method includes performing a first translation lookaside buffer (TLB) lookup based on a base address value to retrieve a speculative physical address. While performing the TLB lookup based on the base address value, the base address value is added to an offset value to generate an effective address value. The method also includes performing a comparison of the base address value and the effective address value based on a variable page size to determine whether the speculative physical address corresponds to the effective address. | 2010-09-09 |
20100228945 | ACCESS MANAGEMENT TECHNIQUE WITH OPERATION TRANSLATION CAPABILITY - Access management techniques have been developed to specify and facilitate mappings between I/O and host domains in ways that provide flexibility in the form, granularity and/or extent of mappings, attributes and access controls coded relative to a particular I/O domain. In some embodiments of the present invention, operation translations coded relative to a particular logical I/O device, domain or sub-window seek to optimize functionality, isolation or some other figure of merit without regard to needs or limitations of another. In this way, operation translations need not be uniform and need not reduce supported operation semantics to correspond to that of a lowest common denominator I/O device. In some embodiments, the form of mappings (e.g., of operation translations) may be specialized on a per-logical-device basis (or even a per-sub-window basis), thereby offering individual logical I/O devices (or sub-windows thereof) immediate, indexed, and/or untranslated operation mapping frameworks appropriate to their individual requirements or needs. In general, flexibilities and efficiencies afforded in some embodiments of the present invention can be desirable, particularly as the diversity of I/O device types and richness of transaction semantics supported in interconnect fabrics increase. Some embodiments may be leveraged in support of sophisticated system partitions or I/O virtualizations. | 2010-09-09 |
20100228946 | METHOD FOR ASSOCIATING PHYSICAL ADDRESS WITH LOGICAL COMMUNICATION ADDRESS IN A MEDIA LIBRARY ASSEMBLY - A method for associating a physical address with a logical communication address for an Ethernet-connected media drive ( | 2010-09-09 |
20100228947 | ADDRESS GENERATOR - The address generator has a hash network for producing hashed Y | 2010-09-09 |
20100228948 | Electronic Device, Time Difference Data Acquisition Method, and Data Structure for Time Difference Data - An electronic device has a reception unit that can receive satellite signals transmitted from positioning information satellites and acquire positioning information and time information, a time difference data storage means in which a data table and a memory address table are stored, and a time difference data acquisition means that acquires time difference data corresponding to positioning information acquired by the reception unit from the time difference data storage means. The data table is compiled by dividing geographical information to which time difference data is assigned into segments of a constant size, setting only one time difference in each segment, grouping the segments into blocks each containing a specific number of segments, and storing the time difference data of each segment as block data by block unit while storing the block data only once for blocks containing the same time difference data array and storing the block data for mutually different time difference data arrays once each. The memory address table stores the memory address where the block data for each block is stored in the data table. The time difference data acquisition means identifies the block corresponding to the positioning information acquired by the reception unit, reads the memory address corresponding to said block from the memory address table, acquires the block data indicated by the memory address in the data table, and acquires the time difference data for the segment corresponding to the positioning information from said block data. | 2010-09-09 |
20100228949 | PROCESSORS - A processing apparatus comprises a plurality of processors ( | 2010-09-09 |
20100228950 | MICROPROCESSOR WITH FAST EXECUTION OF CALL AND RETURN INSTRUCTIONS - A microprocessor includes an instruction set architecture, comprising a call instruction type, a return instruction type, and other instruction types. Execution units correctly execute program instructions of the other instruction types. A call/return stack has a plurality of entries arranged in a last-in-first-out manner. The call/return stack is architectural state of the microprocessor not modifiable by program instructions of the other instruction types. The call/return stack is architectural state of the microprocessor indirectly modifiable by program instructions of the call and return instruction types. The microprocessor also includes a fetch unit that fetches program instructions and sends the program instructions of the other instruction types to the execution units to be correctly executed. The fetch unit correctly executes program instructions of the call and return instruction types without sending the program instructions of the call and return instruction types to the execution units to be correctly executed. | 2010-09-09 |
20100228951 | PARALLEL PROCESSING MANAGEMENT FRAMEWORK - The present disclosure includes a management framework system for processing a parallel task. The framework includes a job package, a job submitter, task trackers, communicators, a plurality of processors, and a node service. The job package has a bundle of implementations defined by a user and an input data domain. The job submitter module has a splitter interface and a reducer interface. The job submitter is configured to split the input data domain into a plurality of sub-data domains. In addition, the job submitter module is configured to send and receive the plurality of sub-data domains to a plurality of processors. The one or more processors are configured to execute parallel tasks on sub-data domains. The management framework separates user-defined applications from parallel execution such that user-implementations are separated from management framework implementations. | 2010-09-09 |
20100228952 | APPARATUS AND METHOD FOR FAST CORRECT RESOLUTION OF CALL AND RETURN INSTRUCTIONS USING MULTIPLE CALL/RETURN STACKS IN THE PRESENCE OF SPECULATIVE CONDITIONAL INSTRUCTION EXECUTION IN A PIPELINED MICROPROCESSOR - A microprocessor having a plurality of call/return stacks (CRS) correctly resolves a call or return instruction rather than issuing the instruction to execution units of the microprocessor to be resolved. The microprocessor fetches a call or return instruction and determines whether the instruction is the first call or return instruction fetched after fetching a conditional branch instruction that has yet to be resolved. The microprocessor copies the contents of a current CRS to another CRS and designates the other CRS as the current CRS, if the state exists. The microprocessor pushes the address of the next sequential instruction following the call instruction onto the current CRS and fetches an instruction at the call instruction target address if the instruction is a call instruction. The microprocessor pops a second return address from the current CRS and fetches an instruction at the second return address, if the instruction is a return instruction. | 2010-09-09 |
20100228953 | REDUCING DATA HAZARDS IN PIPELINED PROCESSORS TO PROVIDE HIGH PROCESSOR UTILIZATION - A pipelined computer processor is presented that reduces data hazards such that high processor utilization is attained. The processor restructures a set of instructions to operate concurrently on multiple pieces of data in multiple passes. One subset of instructions operates on one piece of data while different subsets of instructions operate concurrently on different pieces of data. A validity pipeline tracks the priming and draining of the pipeline processor to ensure that only valid data is written to registers or memory. Pass-dependent addressing is provided to correctly address registers and memory for different pieces of data. | 2010-09-09 |
20100228954 | GENERAL PURPOSE EMBEDDED PROCESSOR - The invention provides an embedded processor architecture comprising a plurality of virtual processing units that each execute processes or threads (collectively, “threads”). One or more execution units, which are shared by the processing units, execute instructions from the threads. An event delivery mechanism delivers events—such as, by way of non-limiting example, hardware interrupts, software-initiated signaling events (“software events”) and memory events—to respective threads without execution of instructions. Each event can, per aspects of the invention, be processed by the respective thread without execution of instructions outside that thread. The threads need not be constrained to execute on the same respective processing units during the lives of those threads—though, in some embodiments, they can be so constrained. The execution units execute instructions from the threads without needing to know what threads those instructions are from. A pipeline control unit which launches instructions from plural threads for concurrent execution on plural execution units. | 2010-09-09 |
20100228955 | METHOD AND APPARATUS FOR IMPROVED POWER MANAGEMENT OF MICROPROCESSORS BY INSTRUCTION GROUPING - A method of power gating a microprocessor having an instruction scheduling unit for receiving issued instructions from an instruction decode unit; an execution unit coupled to receive and send signals from and to the instruction scheduling unit; and a state machine located within the execution unit, the method comprises: obtaining a number of instructions per cycle being issued to the instruction scheduling unit; determining, subsequent to obtaining the number of instructions per cycle, if the number of instruction per cycle being issued to the instruction scheduling unit is less than a threshold level, and then determining if at least two of the instructions being issued to the instruction scheduling unit are independent of each other only when the instructions per cycle is less than the threshold level; determining when at least two of the instructions being issued to the instruction scheduling unit are independent of each other; and power gating the microprocessor to gate off power to idle macros with a signal from the state machine when the instructions are independent of each other without incurring significant loss of performance until an issue queue in the instruction scheduling unit is filled with instruction data. | 2010-09-09 |
20100228956 | CONTROL CIRCUIT, INFORMATION PROCESSING DEVICE, AND METHOD OF CONTROLLING INFORMATION PROCESSING DEVICE - A control circuit for receiving data transmitted by a data transmitting circuit and transmitting the received data to a data receiving circuit includes: a data receiving unit for receiving the data transmitted by the data transmitting circuit; a packet analyzing unit for judging whether the data received from the data transmitting circuit is a packet including history acquisition information and reading the history acquisition information from the received data; a history acquisition executing unit for starting or stopping acquiring the history information of the transmission and reception of the data according to the history acquisition information read by the packet analyzing unit to store the history information acquired; and a data transmitting unit for transmitting the packet including the history acquisition information or a packet other than the packet including the history acquisition information to the data receiving circuit. | 2010-09-09 |
20100228957 | Systems and Methods for Branch Prediction Override During Process Execution - Various embodiments of the present invention provide systems and methods for branch prediction. As an example, some embodiments of the present invention provides processor circuits that include a program address circuit, a branch target buffer, a branch prediction replacement circuit, and an execution pipeline. The branch target buffer includes a plurality of entries each associated with a respective change of flow instruction. Each entry includes an indication of an entry source and a next program address corresponding to the respective change of flow instruction. The branch prediction replacement circuit is operable to determine replacement priorities of the plurality of entries based at least in part on the entry source for each of the plurality of entries. The execution pipeline receives an executable instruction corresponding to one of the next program addresses. | 2010-09-09 |
20100228958 | INFORMATION PROCESSING APPARATUS, METHOD FOR CONTROLLING INFORMATION PROCESSING APPARATUS AND COMPUTER READABLE MEDIUM - An information processing apparatus includes a first circuit configuration section, a second circuit configuration section and a circuit configuration controller. The first circuit configuration section includes a first circuit configuration configured by a plurality of first calculation units. Each of the first calculation units has a circuit being configured to be dynamically reconfigured. The second circuit configuration section includes a second circuit configuration configured by a plurality of second calculation units. Each of the second calculation units has a fixed circuit. The circuit configuration controller controls the first circuit configuration and the second circuit configuration in accordance with processing time to be taken for performing information processing. | 2010-09-09 |
20100228959 | COMMUNICATION DEVICE AND METHOD FOR STARTING UP THE COMMUNICATION DEVICE - A method for starting up the communication device includes searching a non-volatile storage unit of the communication device for start up data of the communication device according to a predetermined identifier of the start up data, loading the start up data into a volatile storage unit of the communication device, starting the communication device according to the start up data in the volatile storage unit. The method also includes searching the non-volatile storage unit for data except for the start up data, load the data except for the start up data into the volatile storage unit. | 2010-09-09 |
20100228960 | VIRTUAL MEMORY OVER BASEBOARD MANAGEMENT CONTROLLER - Embodiments of the present invention generally relate to techniques for updating a BIOS image stored in a computer system. The BIOS image is stored in a flash memory and updated over an embedded system, such as a baseboard management controller (BMC). In one embodiment, a method for updating a BIOS image on a computer system includes receiving, by a service processor, an updated BIOS image over a communications channel, moving a current BIOS image from a first storage location to a second storage location, moving the updated BIOS image to the first storage location, receiving, from a chipset coupled to the service processor, a request to access the BIOS image on the server system, and directing, by the service processor, the request to access the BIOS image to the BIOS image in the second storage location. | 2010-09-09 |
20100228961 | HIERARCHICAL SECURE NETWORKS - Systems and methods for creating hierarchical network communications between trusted domains are described herein. An illustrative system includes a first, second, and third network. The first and second networks each include a plurality of routers, each router capable of establishing a secure data path with another router in the respective network. The third network includes a first router and a second router, each router capable of establishing a secure data path with the other router. The definition of each secure data path is provided by an external storage device that detachably couples to a router. The storage devices defining the secure data paths are unique to each router. The first and second networks communicate through the third network. | 2010-09-09 |
20100228962 | OFFLOADING CRYPTOGRAPHIC PROTECTION PROCESSING - Some embodiments are directed to processing packet data sent according to a security protocol between a first computer and a second computer via a forwarding device. The forwarding device performs a portion of the processing, and forwards the packet data to a third computer, connected to the forwarding device, for other processing. The third computer may support non-standard extensions to the security protocol, such as extensions used in authorizing and establishing a connection over the secure protocol. The packet data may be subject to policies, such as firewall policies or security policies, that may be detected by the third computer. The third computer sends the results of its processing, such as a cryptographic key, or a detected access control policy, to the forwarding device. | 2010-09-09 |
20100228963 | METHODS OF PLACING ADVERTISMENTS, INTERSTITIALS AND TOOLBARS IN A WEB BROWSER - The present invention provides methods and systems that can render INE content to a web browser. Various methods and approaches are disclosed that when implemented would enable an INE to place some of INE's contents in a web browser of a user. The INE content can be in the form of a tool bar or interstitial content. The invention can provide one or more of the following advantages: a) provide an opportunity for INE to conduct e-commerce, b) enable an INE to develop alternate revenue generation model, and c) enable an INE or it's related entities to participate in e-commerce and advertising. | 2010-09-09 |
20100228964 | Ethernet PHY Level Security - A system and method are provided for securing links at the physical (PHY) layer in an IEEE 802.3 Ethernet communication system. A local device (LD) receives an electrical waveform representing link partner security information from a network-connected link partner (LP) via unformatted message pages. The LD accesses predetermined LP reference information stored in a tangible memory medium. The LD compares the received LP security information to the LP reference information. In response to the LD matching the received LP security information to the LP reference information, a secure link to the LP is verified. Likewise, the LD may send electrical waveforms representing security information to the LP via the unformatted message pages. In response to the LP matching the LD security information to the LD reference information, a secure link to the LD is verified. | 2010-09-09 |
20100228965 | SYSTEM AND METHOD FOR USING A STREAMING PROTOCOL - An initialization vector (IV) is employed to decrypt a block of a stream that has been encrypted with Cypher Block Chaining (CBC) encryption, without requiring decryption of previous blocks within the stream. For example, a listener who accesses a distribution point to retrieve encrypted content authenticates himself to an application server that regulates access to encrypted content on the distribution point, and responsively receives a key. The listener then requests access to a reference point within the encrypted content stream somewhere after its beginning (e.g., using preview clips). The distribution point relates the reference point to a corresponding block of the encrypted stream, and identifies an IV previously used for encryption of that block. The distribution point provides the associated encrypted block of content and the IV to the listener to enable mid-stream rendering of the encrypted content, without requiring the listener to decrypt previous blocks within the encrypted stream. | 2010-09-09 |
20100228966 | CONTROL DEVICE, COMMUNICATION APPARATUS, CONTROL SYSTEM, CONTROL METHOD AND STORAGE MEDIUM - A control system which can control a function of a device depending on the result of authentication of an external device that exists outside the device and prevent others from using the device without permission is provided. The control system includes a control device ( | 2010-09-09 |
20100228967 | METHOD OF ESTABLISHING SECURITY ASSOCIATION IN INTER-RAT HANDOVER - A method of establishing security association during handover between heterogeneous networks in a radio access system is disclosed. A method of establishing security association before handover with a target base station included in a heterogeneous radio access network is performed comprises transmitting a request message to a service base station, the request message requesting the service base station to transfer authentication related information of a mobile station to a target network authentication server; and receiving a response message from the service base station before the handover with the target base station is performed, the response message including security related information used in a target network. | 2010-09-09 |
20100228968 | SPLIT TERMINATION OF SECURE COMMUNICATION SESSIONS WITH MUTUAL CERTIFICATE-BASED AUTHENTICATION - A method and apparatus are provided for split-terminating a secure client-server communication connection when the client and server perform mutual authentication by exchanging certificates, such as within a Lotus Notes environment. When the client submits a certificate to the server, an intermediary device intercepts the certificate and submits to the server a substitute client certificate generated by that intermediary. A certificate authority's private key is previously installed on the intermediary to enable it to generate public keys, private keys and digital certificates. With the private key corresponding to the substitute certificate, the intermediary extracts a temporary key from a subsequent server message. The intermediary uses the temporary key to read a session key issued later by the server. Thereafter, the intermediary shares the session key with another intermediary, and together they use the session keys to access and optimize (e.g., accelerate) messages sent by the client and the server. | 2010-09-09 |
20100228969 | CUSTOMIZABLE PUBLIC KEY INFRASTRUCTURE AND DEVELOPMENT TOOL FOR SAME - A public key infrastructure comprises a client side to request and utilize certificates in communication across a network and a server side to administer issuance and maintenance of said certificates. The server side has a portal to receive requests for a certificate from a client. A first policy engine to processes such requests in accordance with a set of predefined protocols. A certification authority is also provided to generate certificates upon receipt of a request from the portal. The CA has a second policy engine to implement a set of predefined policies in the generation of a certificate. Each of the policy engines includes at least one policy configured as a software component e.g. a Java bean, to perform the discreet functions associated with the policy and generate notification in response to a change in state upon completion of the policy. | 2010-09-09 |
20100228970 | Public key certificate issuing system, public key certificate issuing method, digital certification apparatus, and program storage medium - A public key certificate issuing system is disclosed which comprises a certificate authority for issuing a public key certificate used by an entity, and a registration authority which, on receiving a public key certificate issuance request from anyone of entities under jurisdiction thereof, transmits the received request to the certificate authority. The certificate authority, having a plurality of signature modules each executing a different signature algorithm, selects at least one of the plurality of signature modules in accordance with the public key certificate issuance request from the registration authority, and causes the selected signature module to attach a digital signature to message data constituting a public key certificate. | 2010-09-09 |
20100228971 | METHODS FOR BROADCASTING AND RECEIVING A SCRAMBLED MULTIMEDIA PROGRAMME, NETWORK HEAD, TERMINAL, RECEIVER AND SECURITY PROCESSOR FOR THESE METHODS - A method of broadcasting a scrambled multimedia programme, by way of a broadband network, in which before transmitting a license key: —a network head carries out a step of authenticating a terminal, and—if the terminal has been successfully authenticated, the network head sends the terminal a license transmission message containing the license key or cryptogram of the license key, by way of a point-to-point link, and—if the terminal is not successfully authenticated, the network head acts (at | 2010-09-09 |
20100228972 | System and Method for Content Distribution with Broadcast Encryption - The claimed invention relates to system and method for providing encrypted content via a distribution network | 2010-09-09 |
20100228973 | ELECTRONIC DATA COMMUNICATION SYSTEM - There is described a key server which is connected to a local area network, and an encryption authority transfers private keys for clients of the local area network to the key server. In an embodiment, the key server encrypts outgoing emails using public keys for the recipients and decrypts internal emails using private keys for the recipients. In another embodiment, the clients of the local area network download their respective private keys from the key server so that encryption operations may be performed by client software. | 2010-09-09 |
20100228974 | VLAN TAGGING OVER IPSec TUNNELS - In accordance with a nonlimiting example, a network device transfers communications data along a communications channel within an Internet Protocol (IP) network. A communications module includes a signal input connected to the communications channel of the IP network and receives an Ethernet packet having an Ethernet header and IP data. A processor is coupled to the communications module and processes the Ethernet packet. It removes the Ethernet header and adds Virtual Local Area Network (VLAN) tagging information to a padding section in the packet. In one aspect, the processor includes an encryption module that encrypts the VLAN tagging information along with the IP data. The network device includes a signal output through which the packet is transferred to a destination within the IP network over the communications channel as an IPSec tunnel. | 2010-09-09 |
20100228975 | METHOD, SYSTEM AND SOFTWARE PRODUCT FOR TRANSFERRING CONTENT TO A REMOTE DEVICE - The present invention relates to a method for transferring content to a device, the method including the steps of: receiving a request for content from the device; delivering a uniquely identifiable, ephemeral player to the device; and transferring content to the device, for presentation on the device by the player. The invention has particular application to digital rights management in respect of the distribution of audiovisual content such as film and television programs, advertisements and live event broadcasts over communication networks such as the Internet. | 2010-09-09 |
20100228976 | METHOD AND APPARATUS FOR PROVIDING SECURED NETWORK ROBOT SERVICES - At least one client robot in a domain are connected to a domain security management unit and a root security management unit is connected to at least one external server outside the domain and the domain security management unit via a network. A method for providing secured network robot services includes generating, at the domain security management unit, a shared key between the client robot and the external server when the client robot requests key distribution; generating, at the domain security management unit, a key distribution request message containing the shared key; and transmitting, at the domain security management unit, the key distribution request message to the external server. | 2010-09-09 |
20100228977 | Communications Hub for Use in Life Critical Network - Secured communications between patient portable communicators (PPC) and a central authority (CA) via an unsecured network are implemented using software implemented by a communications device. The communications device provides for detecting, using a multiplicity of disparate communication protocols, presence of entities requesting a network connection and determining whether or not each of the entities is a PPC, establishing, only for the entities determined to be PPCs, a connection to the CA via the unsecured network using the disparate communication protocols, authenticating only the PPCs to the CA, and facilitating communication of PPC data between the PPCs and the CA via the communications device and the unsecured network upon successful PPC authentication. The PPC data comprises at least some patient implantable medical device data acquired by the PPCs. | 2010-09-09 |
20100228978 | Terminal Device, System, Connection Management Server, and Computer Readable Medium - A second terminal device is used in a system including a connection management server, a first terminal device, and the second terminal device. The second terminal device includes: a local address obtaining unit configured to obtain a first local IP address and first authentication information of the first terminal device from the connection management server, if a first global IP address matches a second global IP address; a determination unit configured to determine, by using of the obtained first authentication information, whether a first particular terminal device with which the second terminal device can communicate by use of the first local IP address is the first terminal device; and a target data communication unit configured to communicate first data with the first terminal device by using the first local IP address, if the first particular terminal device is determined to be the first terminal device. | 2010-09-09 |
20100228979 | Terminal Device, System and Computer Readable Medium - A second terminal device is used in a system including a server, a first terminal device, and the second terminal device. The second terminal device includes: a first command transmission unit configured to transmit a first command to the first terminal device via the server; a storage control unit configured to hold a first address and first authentication information of the first terminal device; a second command transmission unit configured to transmit a second command to the first address; a determination unit configured to determine whether a terminal device as a destination of the second command is the first terminal device, by using first response data from the terminal device and the first authentication information; and a third command transmission unit configured to transmit a third command to the first address if the terminal device is determined to be the first terminal device. | 2010-09-09 |
20100228980 | Method and Arrangement for Providing a Wireless Mesh Network - A method and an arrangement are provided wherein a newly added mesh node does not require a link to the AAA server for the purpose of authentication. Authentication is carried out using a node which is already present in the mesh network and which has a link to the AAA server | 2010-09-09 |
20100228981 | Communication method, mesh netwrok system and communication terminal - A communication method in which an operation, such as authentication, required when a new communication terminal participates in a mesh network is carried out in a more efficient manner. A second communication terminal that has already established an adjacent communication link with at least two first communication terminals, out of a plurality of communication terminals, distributes an adjacent terminal list including terminal identifiers of the first communication terminals along with a temporal key generated by the second communication terminal. One of the first communication terminals that received the adjacent terminal list and the temporal key distributes adjacent registration information, which is generated using a second temporal key. The other one of the first communication terminals that received both the adjacent terminal list and the adjacent registration information determines whether the terminal identifier of one of the first communication terminals is included in the adjacent terminal list, and whether the first temporal key distributed along with the adjacent terminal list matches with the second temporal key used for generating the adjacent registration information. If both determination results are affirmative, one of the first communication terminals is authenticated. | 2010-09-09 |
20100228982 | FAST-RECONNECTION OF NEGOTIABLE AUTHENTICATION NETWORK CLIENTS - Modern network communications often require a client application requesting data to authenticate itself to an application providing the data. Such authentication requests can be redundant, especially in the case of stateless network protocols. When a full authentication is performed, a conversation identifier and one or more encryption keys can be agreed upon. Subsequent authentication requests can be answered with a fast reconnect token comprising the conversation identifier and a cryptographically signed version of it using the one or more encryption keys. Should additional security be desirable, a sequence number can be established and incremented in a pre-determined or a random manner to enable detection of replayed fast reconnect tokens. If the recipient can verify the fast reconnect token, the provider can be considered to have been authenticated based on the prior authentication. If an aspect of the fast re-authentication should fail, recourse can be had to the original full authentication process. | 2010-09-09 |
20100228983 | Third-party watermarking - A “third-party watermark” is inserted into a file or files uploaded by a client to a “storing party” such as a file backup server. The third-party watermark may contain information about the upload itself, such as time and date of the upload and the identity of the client. The third-party watermark may also contain authentication information received from the client or elsewhere that establishes that the client is in proper possession of the file, e.g., it is not a “bootlegged” copy. | 2010-09-09 |
20100228984 | FULL-RIGHTS LOCAL PLAYBACK OF DIGITAL CONTENT - A method of playing a digital content item includes downloading the digital content item from a removable data-holding medium to a local data-holding medium of a media playing system, and sending a licensing request to a network-accessible, digital-content service. The method further includes receiving a full-rights license for the digital content item from the digital-content service, where the full-rights license grants a right to play the digital content item from the local data-holding medium of the media playing system without the removable data-holding medium being present. The method further includes receiving a request to play the digital content item, and verifying the full-rights license for the digital content item. The method further includes playing the digital content item from the local data-holding medium if the full-rights license verifies, without the removable data-holding medium being present. | 2010-09-09 |
20100228985 | CONTENT MANAGEMENT METHOD AND APPARATUS IN INTELLIGENT ROBOT SERVICE SYSTEM - A content management method in an intelligent robot service system includes: generating a key to distribute the key to a content generation node and a content execution node; generating a signature for a content using the distributed key in the content generation node; providing the content and the signature to the content execution node; and verifying a validity of the content in the content execution node to execute the verified content. | 2010-09-09 |
20100228986 | AUTHENTICATION SYSTEM AND METHOD USING ELECTRONIC TAGS - An authentication method of a prover device by a verifier device by means of cryptographic coupons is provided for, wherein a coupon comprises, on one hand, a pseudo-random number r | 2010-09-09 |
20100228987 | System and method for securing information using remote access control and data encryption - The invention relates to a system and method for enhancing the security of information by decoupling the user authentication from the data storage and access. User information, stored by a service provider, is encrypted using a hashed password and access to the encrypted user information is protected by a separate access control server. The access control server and service provider may be provided a uniquely hashed first and second password, respectively. The access control server uses the first hashed password to allow the user access to the service provider, and the service provider then decrypts the user information using the second hashed password. The system ensures that even if the malicious user manages to compromise either the service provider or the access control server the malicious user would remain unable to decrypt and access any stored user information. | 2010-09-09 |
20100228988 | METHOD AND DEVICE FOR VISUAL CODE TRANSACTION VERIFICATION - A method and device for visual code transaction verification enables more secure electronic transactions. The method includes generating a window having a first pattern of elongated segments. A second pattern of elongated segments is then generated, wherein a dynamic visual code is produced when the window and the first pattern of elongated segments are superimposed with the second pattern of elongated segments. A transaction with a user is then verified by matching the dynamic visual code with a code string entered by the user. | 2010-09-09 |
20100228989 | ACCESS CONTROL USING IDENTIFIERS IN LINKS - Methods, systems, and computer-readable media are disclosed for access control. A particular method receives a resource access identifier associated with a shared computing resource and embeds the resource access identifier into a link to the shared resource. The link to the shared resource is inserted into an information element. An access control scheme is associated with the information element to generate a protected information element, and the protected information element is sent to a destination computing device. | 2010-09-09 |
20100228990 | Using Hidden Secrets and Token Devices to Create Secure Volumes - A system for encrypting Secure Volumes using an encryption key which is saved in the open after being encoded inside a hardware token device utilizing a secure secret which is stored inside the device, and which never leaves the device. The encrypted volume can be accessed again only after a hardware token has decoded this encryption key. The system also provides means whereby the holder of a Master token and the holder of a Grand Master token may also have access to the volume as long as the user token was previously registered to the Master token, and the Master Token was previously registered to the Grand master token before the secured volume was encrypted. Also, the system allows members of user groups so designated at the time the volume is encrypted, to be able to have access to the volume as long as their token was previously registered with the same Master Token as the user that encrypted the volume and as long as the token encrypting the volume was also a member of the authorized user group. | 2010-09-09 |
20100228991 | Using Hidden Secrets and Token Devices to Control Access to Secure Systems - A system for using an encrypted version of a password or access code which is stored in the open on a computer or other device, which utilizes a hardware token to decrypt the password or access code utilizing a secure secret which is stored inside the device, and which never leaves the device, to allow the owner of the device to have access to the Secure System. The system also provides means whereby the holder of a Master token and the holder of a Grand Master token may also have access to the Secure System as long as the user token was previously registered to the Master token and the Master Token was previously registered to the Grand master token before the secured resource was locked by the user token. Also the system allows members of user groups so designated at the time the resource is locked, to be able to have access as long as their token was previously registered with the same Master Token as the user that locked the resource and as long as the token locking the resource was also a member of the authorized user group. | 2010-09-09 |
20100228992 | CRYPTOGRAPHIC METHOD AND APPARATUS FOR ENHANCING COMPUTATION PERFORMANCE OF A CENTRAL PROCESSING UNIT - A cryptographic method for enhancing computation performance of a central processing unit involves the execution of a conversion function of the cryptographic method by the central processing unit. The conversion function computation requires the use of a plurality of substitution boxes. The method comprises the steps of: (A) detecting a processing bit length of the central processing unit; (B) generating at least one new substitution box from original substitution boxes according to the processing bit length and a bit permutation sequence, each of the at least one new substitution box containing a plurality of new substitution values whose bit length is equal to the processing bit length; and (C) using a bit expansion operation, a bitwise exclusive OR operation, the selection operations that use the at least one new substitution box generated in step (B), a plurality of bitwise AND operations, and at least one bitwise OR operation to conduct the conversion function computation. The at least one new substitution box is designed according to different bit processing capabilities (e.g., 8 bits, 16 bits, 32 bits), such that the processing capability of a central processing unit can be fully utilized. | 2010-09-09 |
20100228993 | USB interface apparatus and USB packet transmitting/receiving method - A USB interface apparatus is provided in electronic equipment on a USB packet transmission side, and includes a conversion unit for converting CRC object data which is data contained in a field subjected to CRC calculation in a USB packet, based on a predetermined rule corresponding to reverse conversion of conversion to be performed on the CRC object data by destination electronic equipment; a CRC calculation unit for calculating a CRC of CRC object data obtained before conversion by the conversion unit; and a packet generation unit for generating a USB packet containing data converted by the conversion unit and the CRC calculated by the CRC calculation unit. | 2010-09-09 |
20100228994 | SECURITY METHOD OF KEYBOARD INPUT DIRECTLY CONTROLLING THE KEYBOARD CONTROLLER - Disclosed herein is a method of securing keyboard input information by directly controlling a keyboard controller of a keyboard. The keyboard includes the keyboard controller, an interrupt controller, an input information processing module and a keyboard security module. The method includes a status information checking step of enabling the input information processing module to check status information of the keyboard controller; an interrupt inactivation step of inactivating an interrupt request function of the keyboard controller; an input information encryption step of encrypting the keyboard input information written to the keyboard input/output ports; a transfer step of transferring the encrypted input information to the keyboard security module; and an input information deletion step of deleting the keyboard input information remaining in the keyboard controller. | 2010-09-09 |
20100228995 | Universal Serial Bus Data Encryption Device with the Encryption Key Delivered by any Infrared Remote Handheld Controller where the Encryption Key is Unreadable by the Attached Computer System - The user may deliver an encryption key via any infrared remote controller to a computer data encryption controller external to the computing system but connected to the aforementioned computer system via the Universal Serial Bus (USB) port. The infrared delivered key may be combined with the computer system supplied key but this key can not be read directly by the computer system. All encryption functions are done external to the computers processing system, memory system, and disk drive as to erase the possibility of rouge unwanted programs such as spyware, viruses, malware, keystroke loggers, and root-kit programs from gathering encryption-key information. | 2010-09-09 |
20100228996 | Systems and Methods for Secure Transaction Management and Electronic Rights Protection - The present invention provides systems and methods for secure transaction management and electronic rights protection. Electronic appliances such as computers equipped in accordance with the present invention help to ensure that information is accessed and used only in authorized ways, and maintain the integrity, availability, and/or confidentiality of the information. Such electronic appliances provide a distributed virtual distribution environment (VDE) that may enforce a secure chain of handling and control, for example, to control and/or meter or otherwise monitor use of electronically stored or disseminated information. Such a virtual distribution environment may be used to protect rights of various participants in electronic commerce and other electronic or electronic-facilitated transactions. Distributed and other operating systems, environments and architectures, such as, for example, those using tamper-resistant hardware-based processors, may establish security at each node. These techniques may be used to support an all-electronic information distribution, for example, utilizing the “electronic highway.” | 2010-09-09 |
20100228997 | METHOD AND APPARATUS FOR VERIFYING AUTHENTICITY OF INITIAL BOOT CODE - A programmable processor initializes its state, then computes and verifies a hash of a boot code region of memory before executing any user instructions in the memory. Systems using similar processors, and software to control such a processor's operation, are also described and claimed. | 2010-09-09 |
20100228998 | METHOD AND APPARATUS FOR SECURE DATA MIRRORING A STORAGE SYSTEM - A secure data mirroring capability in a storage system includes encrypting data blocks in a primary volume in preparation for a data mirroring operation. The encrypted data blocks are mirrored to a secure secondary volume. Host systems provide keys from which encryption keys are produced for encrypting the data blocks. Access to data on the secure secondary volume requires decryption using the key that was used to produce the encrypted data blocks. | 2010-09-09 |
20100228999 | Trusted Storage Systems and Methods - Systems and methods are disclosed for providing a trusted database system that leverages a small amount of trusted storage to secure a larger amount of untrusted storage. Data are encrypted and validated to prevent unauthorized modification or access. Encryption and hashing are integrated with a low-level data model in which data and meta-data are secured uniformly. Synergies between data validation and log-structured storage are exploited. | 2010-09-09 |
20100229000 | SOFTWARE COPYRIGHT PROTECTION AND LICENSING SYSTEM USING RFID - The present invention provides a software copyright protection and licensing system ( | 2010-09-09 |
20100229001 | NONVOLATILE MEMORY DEVICE AND OPERATING METHOD - Disclosed is an operating method of a non-volatile memory device which comprises randomizing data to store the randomized data; erasing the randomized data; and outputting erase data according to information of a flag cell of the non-volatile memory device at a read operation. | 2010-09-09 |
20100229002 | SYSTEMS AND METHODS FOR WATERMARKING SOFTWARE AND OTHER MEDIA - Systems and methods are disclosed for embedding information in software and/or other electronic content such that the information is difficult for an unauthorized party to detect, remove, insert, forge, and/or corrupt. The embedded information can be used to protect electronic content by identifying the content's source, thus enabling unauthorized copies or derivatives to be reliably traced, and thus facilitating effective legal recourse by the content owner. Systems and methods are also disclosed for protecting, detecting, removing, and decoding information embedded in electronic content, and for using the embedded information to protect software or other media from unauthorized analysis, attack, and/or modification. | 2010-09-09 |
20100229003 | METHOD, SYSTEM AND COMPUTER PROGRAM FOR SECURELY STORING DATA - A method of securely storing data comprising the steps of:
| 2010-09-09 |
20100229004 | PROTECTION OF SECURITY PARAMETERS IN STORAGE DEVICES - Security parameters used to encrypt data stored on a storage device may be protected using embodiments of systems and methods described herein. During a resize operation, data stored on a memory unit in the storage device may be altered prior to communicating an updated partition size to a host computer. In some examples, data is altered prior to storing the updated partition sizes in the storage device. In this manner, a host system may not receive the updated partition sizes until after the data is altered. Altering data may avoid exposure encrypted data, information about one or more security parameters used to encrypt data on the memory unit or decrypt data retrieved from the memory unit, or combinations thereof. | 2010-09-09 |
20100229005 | DATA WHITENING FOR WRITING AND READING DATA TO AND FROM A NON-VOLATILE MEMORY - Systems, apparatuses, and methods are provided for whitening and managing data for storage in non-volatile memories, such as Flash memory. In some embodiments, an electronic device such as media player is provided, which may include a system-on-a-chip (SoC) and a non-volatile memory. The SoC may include SoC control circuitry and a memory interface that acts as an interface between the SoC control circuitry and the non-volatile memory. The SoC can also include an encryption module, such as a block cipher based on the Advanced Encryption Standard (AES). The memory interface can direct the encryption module to whiten all types of data prior to storage in the non-volatile memory, including sensitive data, non-sensitive data, and memory management data. This can, for example, prevent or reduce program-disturb problems or other read/write/erase reliability issues. | 2010-09-09 |
20100229006 | Memory for Protecting Data, Memory System Including the Memory, and Method of Driving the Memory - A memory for protecting data includes a first storage area storing N-number of encryption keys, where N is a natural number, a second storage area receiving the N-number of encryption keys from the first storage area and storing again the received N-number of encryption keys, and a selection unit selecting one of the N-number of encryption keys stored in the second storage area according to a control signal, and encoding data input from outside the memory using a selected encryption key or decoding the data stored in the first storage area using the selected encryption key. | 2010-09-09 |
20100229007 | Nonvolatile Memory Device and Operating Method Thereof - An operating method of a non-volatile memory device includes randomizing source data to form randomized source data, storing the randomized source data, generating a seed based on an address, generating a random data sequence based on the seed, and de-randomizing the randomized data using the random data sequence. Related nonvolatile memory devices and methods of reading data stored in non-volatile memory devices are also disclosed. | 2010-09-09 |
20100229008 | Sound Effect Power Supply Configuration - A sound effect power supply configuration includes a USB power supply source, an external audio source, a sound effect unit and an external speaker, wherein the USB power input terminal provides sound effect unit USB power source, for the sound effect unit after obtaining USB power source may receive the audio signals output by the external audio source, and after appropriately processing the audio, may drive the external speaker to generate sounds having high quality sound effect. | 2010-09-09 |
20100229009 | Applying power to a network interface - A host device capable of communicating with an external network. The host device may comprise a power-application unit and a network interface. The power-application unit may receive from a power-supply unit a first power-supply output having a first voltage level and a second power-supply output having a second voltage level. The power-application unit may be controllable for producing selectively a first power-application output having a third voltage level from the first power-supply output and a second power-application output having a fourth voltage level from the second power-supply output. The network interface may transmit data to and receive data from an external network, and may be powered at least in part by the first and second power-application outputs. | 2010-09-09 |
20100229010 | COMPUTER SYSTEM, METHOD FOR CONTROLLING THE SAME, AND PROGRAM - A computer system | 2010-09-09 |
20100229011 | Power Reduction in Microcontrollers - The disclosed implementations provide for power reduction in microcontrollers by reactivating a clock in the microcontroller for one or more peripheral modules in response to an internal or external trigger event, thus allowing the one or more peripheral modules to respond to events while operating in a low-power sleep mode. In some implementations, one or more peripheral modules in a microcontroller provide a clock request signal to a clock generator in the microcontroller. In response to the clock request signal, the clock generator reactivates one or more oscillator sources. The clock generator resumes clock generation only for the one or more requesting peripheral modules, keeping power consumption in the microcontroller to a minimum and not disturbing other modules in the microcontroller. | 2010-09-09 |
20100229012 | MICROPROCESSOR THAT PERFORMS ADAPTIVE POWER THROTTLING - A microprocessor that performs adaptive power throttling includes a calculation unit that calculates an average power consumed by the microprocessor over a most recent predetermined sample time and determines whether the average power is less than a predetermined maximum power value. A power management unit controls the microprocessor to conditionally operate at a predetermined frequency if the average power is less than the predetermined maximum power value. The predetermined frequency is a frequency at which the microprocessor may consume more than the predetermined maximum power value. The predetermined maximum power value and sample time are specified to achieve power and/or thermal design goals of a system in which the microprocessor operates. The predetermined maximum power and/or sample time values are programmable by system software. To maintain a running average power value, a counter is incremented, both in sleeping and running states, by different increments depending upon the current performance point. | 2010-09-09 |
20100229013 | METHOD AND SYSTEM FOR IMPLEMENTING ENERGY EFFICIENT ETHERNET TECHNIQUES IN A MACSEC ENABLED PHY - Aspects of a method and system for implementing energy efficient Ethernet techniques in a MACSec enabled PHY are provided. In this regard, an Ethernet PHY comprising memory may be operable to perform packet processing functions comprising MACSec protocol processing and energy efficient Ethernet (EEE) processing. In this regard, the memory may be utilized for implementing the MACSec protocol processing and energy efficient Ethernet (EEE) processing. The Ethernet packet processing functions may comprise packet inspection, packet generation, and packet modification. The energy efficient Ethernet (EEE) processing may comprise generating and/or inspecting messages for controlling when to transition into and out-of an energy-saving mode. The Ethernet PHY may be operable to monitor signals and/or conditions within the Ethernet PHY and control transitions into and out-of an energy-saving mode based on the monitored signals and/or conditions. The energy saving mode may comprise a low power idle mode and/or a subset PHY mode. | 2010-09-09 |
20100229014 | MONITORING A COMPUTER - A computer implemented method of monitoring the operational state of a computer, comprises running on the monitored computer a monitoring program configured to monitor a set of parameters. The set of monitored parameters comprises for example the name(s) of any process(es) running on the computer, together with i) the values of a plurality of metrics indicating the level of activity of the computer, and/or ii) time. The monitored parameters are provided by the monitoring program to another, monitoring, computer; which runs a comparison program which compares the set of monitored parameters with a predetermined model which determines whether or not the monitored computer is in a predetermined operational state defined by the model, and produces an indication of whether or not the monitored computer complies with the model. | 2010-09-09 |
20100229015 | Method and Apparatus of Power Management - A power management system for home entertainment networks having three power states. The network controller is empowered to move nodes within the home entertainment network between the power states. | 2010-09-09 |
20100229016 | ASSESSING CONDITIONS OF POWER CONSUMPTION IN COMPUTER NETWORK - A network system forms a computer network, and includes: a collecting unit; a calculating unit; and a display unit. The collecting unit collects power consumption information from a connecting device. The power consumption information shows power consumption of the connecting device. The calculating unit calculates power consumption of the computer network based on the collected power consumption information. The calculated power consumption is itemized into constituent units based on a configuration of the computer network. The display unit displays the calculated power consumption. | 2010-09-09 |
20100229017 | IN-VEHICLE POWER SUPPLY APPARATUS - Provided is an in-vehicle power supply apparatus which supplies power to both a high-power load such as an actuator, and the CPU for controlling the high-lower load, and which is capable of preventing reduction in voltage of the CPU even when voltage of the in-vehicle power supply is momentarily reduced due to power consumption of the high-power load, and which include an auxiliary power supply having its capacity reduced so as to enable reduction of the size of the power supply apparatus. The in-vehicle power supply apparatus for supplying a power to both a power load, and a CPU for controlling the power load comprises: a first distribution line for distributing, to the power load, the power supplied from an in-vehicle power supply through a bus; a second distribution line for distributing, to the CPU, the power supplied from the in-vehicle power supply through the bus; an auxiliary power supply, connected to the second distribution line, for supplying the power to the CPU when a voltage is reduced in the bus; and a backward flow prevention section for preventing a charge stored in the auxiliary power supply from flowing into the bus. | 2010-09-09 |
20100229018 | THREE STAGE POWER UP IN COMPUTER STORAGE SYSTEM - Embodiments for operation of a storage system following a power loss are provided. The system switches to the local power supply, prevents the receipt of input/output commands and copies the content of cache memory to a local storage device. On detecting resumption of external power, the system charges a local power supply, copies the content of the local storage device to the cache memory and processes the content of the cache memory with respect to at least one storage volume. When the charge stored on the local power supply exceeds the charge required to copy the content of the cache memory to the local storage device by a predetermined amount, the system allows the receipt of input/output commands using a reduced portion of the cache memory. Once the charge stored on the local power supply has reached a predetermined level, the system allows the receipt of input/output commands using all cache memory. | 2010-09-09 |
20100229019 | Method of Controlling Spread-Spectrum Clock Generation - A method of controlling spread-spectrum clock generation is disclosed. A first-in first-out (FIFO) buffer is first monitored. When the FIFO buffer is determined to be abnormal, an associated spread-spectrum clock generator (SSCG) is turned off or its spread range is decreased. | 2010-09-09 |
20100229020 | PROCESSING SYSTEM WITH INTERSPERSED PROCESSORS USING SELECTIVE DATA TRANSFER THROUGH COMMUNICATON ELEMENTS - A processing system comprising processors and the dynamically configurable communication elements coupled together in an interspersed arrangement. The processors each comprise at least one arithmetic logic unit, an instruction processing unit, and a plurality of processor ports. The dynamically configurable communication elements each comprise a plurality of communication ports, a first memory, and a routing engine. For each of the processors, the plurality of processor ports is configured for coupling to a first subset of the plurality of dynamically configurable communication elements. For each of the dynamically configurable communication elements, the plurality of communication ports comprises a first subset of communication ports configured for coupling to a subset of the plurality of processors and a second subset of communication ports configured for coupling to a second subset of the plurality of dynamically configurable communication elements. | 2010-09-09 |