36th week of 2010 patent applcation highlights part 17 |
Patent application number | Title | Published |
20100225308 | Signal processing circuit of rotation detector and rotation angle detector - A signal processing circuit for a rotation detector includes a rotational direction determining portion, an effective edge determining portion, a normal-rotation pulse request holding portion, a reverse-rotation pulse request holding portion, an output request signal outputting portion, a pulse outputting portion, a first resetting portion, and a second resetting portion. When one of the holding portions holds an output request signal, the pulse outputting portion outputs a pulse based on the output request signal. When the other one of the holding portions holds an output request signal and then a condition for holding the output request signal that is already held by the one of the holding portions is satisfied in a state where the one of the holding portions holds the output request signal, the second resetting portion resets the output request signal held by the other one of the holding portion. | 2010-09-09 |
20100225309 | ROTATION DETECTING DEVICE AND BEARING ASSEMBLY EQUIPPED WITH SUCH ROTATION DETECTING DEVICE - A rotation detecting device includes a plurality of magnetic encoders disposed coaxially and having respective numbers of magnetic poles different from each other and a plurality of magnetic sensors for detecting respective magnetic fields emanating from those magnetic encoders. Each of the magnetic sensors is in a ring form and obtains the position information within the magnetic poles of the associated magnetic encoder. A phase difference detector determines the difference in phase between magnetic field signals detected respectively by the magnetic sensors. An angle calculator is provided, which is operable on the basis of the difference in phase so detected to calculate an absolute angle of each of the magnetic encoders. A corrector corrects the initial phase difference occurring in the magnetic field signals, detected respectively by the magnetic sensors, as a result of the fitting position of the magnetic encoders. | 2010-09-09 |
20100225310 | TOUCH-DOWN DETERMINING DEVICE, TOUCH-DOWN DETERMINING METHOD, AND MAGNETIC DISK DEVICE - According to one embodiment, a touch-down determining device, includes: an alternating current perturbation module configured to periodically perturb power of a heater by an alternating current, the heater adjusting protrusion amounts of a write magnetic pole and a read element of a magnetic head in a direction towards a recording medium; a change detector configured to detect a change in a spectrum level of a portion of a spectrum of a read signal read from the recording medium by the magnetic head receiving the power perturbed by the alternating current, the portion of the spectrum corresponding to the alternating current; and a touch-down determining module configured to determine whether touch-down is made, based on the change in the spectrum level detected by the change detector. | 2010-09-09 |
20100225311 | METHOD OF CHARACTERIZING A POLYCRYSTALLINE DIAMOND ELEMENT BY AT LEAST ONE MAGNETIC MEASUREMENT - In an embodiment, a method of characterizing a polycrystalline diamond element is disclosed. The method includes providing the polycrystalline diamond element, and measuring at least one magnetic characteristic of the polycrystalline diamond element. | 2010-09-09 |
20100225312 | Signal processing device using magnetic film and signal processing method - A signal processing device includes a continuous film, a plurality of spin wave generators, and at least one signal detector. The continuous film includes at least one magnetic layer. The plurality of spin wave generators are provided on the continuous film in such a manner as to be in direct contact with the continuous film or be in contact with the continuous film while having an insulation layer interposed therebetween, and each has a contact surface with the continuous film in a dot shape and generates a spin wave in a region of the magnetic layer of the continuous film by receiving an input signal, the region being immediately under the contact surface. The signal detector is provided on the continuous film and detects, as an electrical signal, the spin waves generated by the spin wave generators and propagating through the continuous film. | 2010-09-09 |
20100225313 | ATOMIC MAGNETOMETERS FOR USE IN THE OIL SERVICE INDUSTRY - An apparatus for obtaining information from a subterranean environment, the apparatus includes: an atomic magnetometer configured to measure a magnetic field related to the information. An associated method for obtaining the information is also disclosed. | 2010-09-09 |
20100225314 | NUCLEAR MAGNETIC RESONANCE MEASURING METHOD - The present invention provides a method for measuring nuclear magnetic resonance that employs a compound in which a plurality of nuclei is labeled with isotopes as a probe agent, highly selectively and highly sensitively obtains a nuclear magnetic resonance signal of the above described probe agent, and can attach a spatial positional information to the above described nuclear magnetic resonance signal, and an apparatus therefore. | 2010-09-09 |
20100225315 | Tuning Low-Inductance Coils at Low Frequencies - A method and apparatus for tuning and matching extremely small sample coils with very low inductance for use in magnetic resonance experiments conducted at low frequencies. A circuit is disclosed that is appropriate for performing measurements in fields where magnetic resonance is beneficially utilized. The circuit has a microcoil, an adjustable tuning capacitance, and added inductance in the form of a tuning inductor. The microcoil is an electrical coil having an inductance of about 25 nanohenries (nH) or less. Because additional inductance is purposefully added, the capacitance required for resonance and apparatus function is proportionally and helpfully reduced. The apparatus and method permit the resonant circuit and the magnet to be made extremely small, which is crucial for new applications in portable magnetic resonance imaging, for example. | 2010-09-09 |
20100225316 | METHOD AND APPARATUS FOR ENHANCED IN VIVO MRI IMAGING - A method and apparatus for detecting the presence of abnormal tissues of the present invention utilizing a magnetic resonance imaging system in communication with a computer. The apparatus is configured to define a confidence region using a probability based confidence interval calculation such as multivariate or bivariate analysis for at least two parameters in a normal tissue sample by making a magnetic resonance image, and then to evaluate a second sample by making a magnetic resonance image. Parameters detectable by magnetic resonance imaging | 2010-09-09 |
20100225317 | MULTI-CHANNEL METHOD AND DEVICE TO EVALUATE MAGNETIC RESONANCE SIGNALS, WITH REDUCED NUMBER OF CHANNELS - An optimized processing of data of multiple local coils is enabled by a device and a method to evaluate signals received with coils of a magnetic resonance tomography apparatus, wherein first signals are generated by means of coils via magnetic fields coming from a body, wherein a region in the body is defined, wherein weighting factors are calculated with the use of the first signals, wherein second signals are generated with the coils from magnetic fields coming from a body, wherein signals weighted with the use of the weighting factors are calculated from the second signals, wherein the weighted signals are processed further. | 2010-09-09 |
20100225318 | MAGNETIC RESONANCE SYSTEM AND METHOD FOR SPATIALLY RESOLVED DETECTION OF MOVEMENT PROCESSES - A method for spatially resolved detection and display of movement processes in an examination subject by means of magnetic resonance tomography includes the steps of imposing a magnetization pattern on at least a portion of a fluid medium located in the intestine of the examination subject, acquiring at least one image data set or a portion of an image data set that images the region of the examination subject on which the magnetization pattern was imposed, determining at least one item of movement information from the at least one image data set or portion of an image data set, by an analysis of the magnetization pattern in a processor, and presenting the at least one item of movement information through presentation device in communication with the processor. | 2010-09-09 |
20100225319 | DETERMINING PHASE-ENCODING DIRECTION FOR PARALLEL MRI - Example systems, methods, and apparatus associated with determining a phase-encoding direction for parallel MRI are described. One example, method includes selecting a set of projection directions along which an MRI apparatus is to apply RF energy to an object to be imaged. The method includes controlling the MRI apparatus to selecting a set of projection directions and to acquire MR signal from the object through a set of detectors. The method includes analyzing the MR signal to identify individual sensitivities for members of the set of detectors and selecting a phase-encoding direction for a pMRI session based on the individual sensitivities for the members. The method produces a concrete, tangible, and useful result by controlling the MRI apparatus to perform the pMRI session based on the selected phase-encoding direction. | 2010-09-09 |
20100225320 | RF STRIPLINE ANTENNA WITH IMPEDANCE ADAPTATION FOR MR IMAGING - The efficiency and the field structure of an antenna arrangement for a magnetic resonance tomography apparatus are improved by at least one impedance transformation circuit connected with the antenna. | 2010-09-09 |
20100225321 | MAGNETIC RESONANCE DEVICE - A magnetic resonance device has a cryostat and a gradient coil assembly situated within an inner bore of the cryostat. A seal is positioned between the gradient coil assembly and the inner bore. The seal includes a first fluid filled toroid or helix mounted concentrically with the gradient coils; and a second fluid filled toroid or helix situated within the first toroid, or first helix. | 2010-09-09 |
20100225322 | SYSTEM AND METHOD FOR ELEVATED SOURCE TO BOREHOLE ELECTROMAGNETIC SURVEY - Methods and systems are provided to determine a property of an earth formation, comprising a mobile transmitter disposed at a predetermined elevated height above a surface of the earth formation, and one or more receivers moveably disposed in a wellbore penetrating the earth formation. Electromagnetic energy is transmitted from the mobile transmitter into the formation from a plurality of locations; and at the one or more receivers a signal is measured. Using the signal received by the one or more receivers, a property of the formation, such as resistivity, can be determined and mapped. | 2010-09-09 |
20100225323 | Collocated Tri-Axial Induction Sensors With Segmented Horizontal Coils - A logging tool for use in a borehole to obtain multicomponent resistivity induction measurements using collocated coils wherein each of the transverse antennas comprises a pair of mirror-image coils symmetrically disposed about an axis of the logging tool. | 2010-09-09 |
20100225324 | MULTI-COMPONENT MARINE ELECTROMAGNETIC SIGNAL AQUISITION METHOD - A method for determining a component of electric field response to a time varying electromagnetic field induced in the Earth's subsurface involves measuring magnetic field gradient in at least two orthogonal directions in response to the induced electromagnetic field and determining an electric field response in a direction normal to the magnetic field gradient measurements. A method for determining a component of electric field response of the Earth's subsurface to a time varying electromagnetic field induced in the Earth's subsurface involves measuring electric field response along a substantially closed pattern on at least one of the Earth's surface and the bottom of a body of water and determining an electric field response in a direction normal to the measured electric field response using electric field response measurements made at opposed positions along the closed pattern. | 2010-09-09 |
20100225325 | Battery System and Method for System State of Charge Determination - A battery system and method of providing a state of charge of for the system in one embodiment includes at least one first cell, the at least one first cell having a first battery chemistry exhibiting a first open circuit potential, and at least one second cell in series connection with the at least one first cell, the at least one second cell having a second battery chemistry exhibiting a second open circuit potential, wherein the at least one first cell exhibits an open circuit potential with a center slope that is greater than the center slope of the open circuit potential exhibited by the at least one second cell. | 2010-09-09 |
20100225326 | DEVICE FOR MEASURING BATTERY VOLTAGE - A device is used for measuring an output voltage of a battery. The device includes a detecting circuit, an encoding circuit, a control circuit, and a processing circuit. The detecting circuit is configured for detecting the output voltage of the battery and generating a first signal, a second signal, and a third signal accordingly. The encoding circuit is configured for generating a first code and a second code according to the first signal and the second signal. The control unit is configured for modifying the second code when the third signal indicates that the output voltage is lower than a predetermined value. The processing unit is configured for generating and outputting display control signals according to the first and second codes. The display control signals are used to control a display panel to display information of the output voltage of the battery. | 2010-09-09 |
20100225327 | VOLTAGE MEASURING APPARATUS OF ASSEMBLED BATTERY - A voltage measuring apparatus for measuring an output voltage of an assembled battery in which a plurality of unit cells are connected in series and are divided into a plurality of blocks is provided. The voltage measuring apparatus includes: a block voltage detection unit which detects a voltage of at least one of the plurality of blocks; a sampling voltage generation unit which is provided in the block voltage detection unit and generates an analog sampling voltage applied in the sampling voltage generation unit; an A/D conversion unit which is provided in the block voltage detection unit and digitizes the analog sampling voltage to output a digital sampling voltage; and a voltage variation detection unit which obtains an error ratio of the voltage detected by the block voltage detection unit based on the digital sampling voltage. | 2010-09-09 |
20100225328 | BATTERY SYSTEM FOR MONITORING A BATTERY - A locomotive, a battery system and a method for monitoring a battery are provided. The battery has a first plurality of cells electrically coupled in series to one another. The first plurality of cells includes a second plurality of cells and a third plurality of cells electrically coupled together at a node. The method includes calculating a first number of failed cells in the first plurality cells. The method further includes calculating a second number of failed cells in the second plurality cells and a third number of failed cells in the third plurality cells. | 2010-09-09 |
20100225329 | LOAD COMPENSATION IN DISTANCE PROTECTION OF A THREE-PHASE POWER TRANSMISSION LINE - A load compensation method for phase-to-ground loops in distance protection. A first reactive reach is estimated assuming zero fault resistance or with a positive sequence current. A second reactive reach is estimated with a zero sequence current. A third reactive reach is estimated with a negative sequence current. An import or export condition is estimated. A fourth reactive reach for import or export condition is estimated based on the first, second and third reactive reach. A fault impedance is estimated based on the estimated fourth reactive reach. | 2010-09-09 |
20100225330 | Method of testing electric fuse, and electric fuse circuit - An object of the present invention is to provide a method of testing an electric fuse which enables to reduce a time for testing. The method of testing an electric fuse according to the present invention comprises: selecting a plurality of disconnection-targeted fuses among a plurality of electric fuses; disconnecting a plurality of disconnection-targeted fuse blocks in tern, each of which includes at least one disconnection-targeted fuse; electrically connecting one terminal of each of the plurality of disconnection-targeted fuses to a first node and connecting another terminal of the each disconnection-targeted fuse to a second node, after disconnecting; and judging whether or not all of said plurality of disconnection-targeted fuses are disconnected after electrically connecting, by applying a voltage to the first node to judge whether or not a current flows between the first node and the second node. | 2010-09-09 |
20100225331 | Continuity testing apparatus and continuity testing method including open/short detection circuit - A continuity testing apparatus includes open/short detection circuits provided for to-be-tested terminals, respectively and configured to determine the presence or absence of at least any one of an open-circuit failure and a short-circuit failure in to-be-tested terminals. Then, the continuity testing apparatus generates detected results of the open/short detection circuits based on the condition of continuity of the to-be-tested terminals having connections to the open/short detection circuits and the detected results from the open/short detection circuits in the preceding stages, and outputs the generated detected results to the open/short detection circuits in the succeeding stages. Further, the continuity testing apparatus determines the condition of continuity based on the output from the open/short detection circuit in the last stage. | 2010-09-09 |
20100225332 | PROXIMITY SENSOR - A proximity sensor has an oscillation circuit, an amplitude measurement circuit, a control circuit and a signal processing circuit. The oscillation circuit has an LC resonant circuit and an oscillation control circuit that is configured to supply an electric current to the LC resonant circuit to generate oscillating voltage across the LC resonant circuit. The amplitude measurement circuit is configured to produce an amplitude signal corresponding to the amplitude of the oscillating voltage. The control circuit is configured to set the negative conductance of the oscillation control circuit to a critical value by which the LC resonant circuit can oscillate based on the amplitude signal. The signal processing circuit is configured to produce a distance signal corresponding to the distance between an object and the sensing coil based on a parameter associated with the negative conductance. | 2010-09-09 |
20100225333 | EXCITATION PHASE DETECTING CAPACITANCE-TYPE POSITION TRANSDUCER - An excitation phase detecting capacitance-type position transducer comprises a stationary part having a plurality of excitation electrode groups and a movable part having a plurality of coupling electrodes. The capacitance-type position transducer detects a signal of which phase varies according to the relative positions of the movable part with respect to the stationary par and calculates an intra-period phase angle φ from two excitation signals having a phase difference of 90° captured at a zero-cross point of the detection signal. | 2010-09-09 |
20100225334 | LIQUID CONCENTRATION SENSOR - A liquid concentration sensor includes an electrode capacitance conversion circuit, a stray capacitance conversion circuit and a difference calculation circuit. The electrode capacitance conversion circuit includes a detection electrode and a switching device. The detection electrode has a pair of opposing terminals and is partially located in a liquid fuel. The switching device is turned ON and OFF to switch between charging and discharging of the detection electrode. The electrode capacitance conversion circuit outputs a first measurement value determined by the charging and discharging of the detection electrode. The stray capacitance conversion circuit has the almost same configuration as the electrode capacitance conversion circuit so as to output a second measurement value corresponding to a stray capacitance of the electrode capacitance conversion circuit. The difference calculation circuit outputs a difference between the first and second measurement values. | 2010-09-09 |
20100225335 | METHOD FOR DETERMINING THE MOISTURE CONTENT OF WOOD - A method for determining the moisture content of wood ( | 2010-09-09 |
20100225336 | Object proximity detector and object position detector - The present invention offers an object proximity detector and object position detector. The variation of frequency of an oscillator is used to detect the proximity of an object to a sensor plate. The dependence of the sensitivity of the detector on the area of the sensor plate is reduced by conducting the sensor plate to two capacitors in series. The conducting wire of the sensor plate can be flexible without causing error detection. In the sensor element of the sensor oscillator, a resistor is connected at one terminal of the sensor plate to form a high pass filter. A resistor and a capacitor are added to the sensor oscillator to form a low pass filter. The high pass filter is used to reduce the low frequency electromagnetic interference. The low pass filter is used to reduce the high frequency electromagnetic interference. | 2010-09-09 |
20100225337 | CHEMICAL SENSORS FOR DETECTING VOLATILE ORGANIC COMPOUNDS AND METHODS OF USE - The presently-disclosed subject matter provides sensors and methods for detecting volatile organic compounds (VOCs) by determining the conductivity of a chemiresistant film upon exposure to VOCs, including for example chemiresistant films comprised of surfactant-coated metal alloy nanoparticles. | 2010-09-09 |
20100225338 | Probe and arrangement for determining the moisture content or conductivity of a material - In a probe and an arrangement comprising a probe for determining a moisture content or a conductivity of a material, comprising a base body including two electrical conductors of which at least one has the form of a tape, the base body includes an electrically insulated area in which at least one of the conductors is disposed. | 2010-09-09 |
20100225339 | DETECTION METHOD FOR DEFECT OF SENSOR - A defect detection method for a sensor in which a fixing member provides a seal between a sensor element and tubular metallic members, the method being capable of detecting breakage of a conductor caused by breakage of the element. | 2010-09-09 |
20100225340 | Digital Foam - A displacement sensor element and a haptic sensor arrangement using two or more displacement sensor elements are provided. The arrangements can be used for real-time capture of the shape of haptic deformation of the sensor arrangement. Although examples described in detail herein are primarily directed to tactile applications, the sensor can be used in the machine, robotic and medical fields where a sensor of this type can usefully be applied where only machine or computer controlled robotic elements are interacting, particularly if the machines or robotic elements are being used in human like applications but other force measurement applications are possible. | 2010-09-09 |
20100225341 | APPARATUS, SYSTEM AND METHOD FOR DETECTING DEFECTS IN BUILDING STRUCTURES - An apparatus, system and method for detecting defects in building structures is provided. The apparatus includes a detector operable to determine an indication of the defect; and a transmitter operable to wirelessly transmit the indication from the apparatus to a central controller. The system includes the detection unit; a locator operable to determine the location of the detection unit; and a memory for storing the indication and the location in association with each other. The memory may be part of a central controller in wireless communication with the detection unit. The apparatus or central controller may include a processor operable to determine from a plurality of measurements performed by the detection unit a resultant measurement vector indicating a direction from the detection unit toward the defect. The detection unit may be operable to autonomously change its location. A display showing resultant measurement vectors at various locations can be produced. | 2010-09-09 |
20100225342 | PROBE CARD AND MICROSTRUCTURE INSPECTING APPARATUS - A probe card | 2010-09-09 |
20100225343 | Probe card, semiconductor testing device including the same, and fuse checking method for probe card - A probe card according to an exemplary aspect of the present invention includes: a force terminal supplied with a first power supply voltage; a probe needle that supplies a voltage corresponding to the first power supply voltage to a semiconductor integrated circuit to be tested; a fuse connected in series on a first signal line which connects the force terminal and the probe needle; and a fuse check circuit that supplies a voltage different from the first power supply voltage supplied from the force terminal, to a first node located on a signal line between the probe needle and one end of the fuse. The circuit configuration enables checking of a connection state of a fuse prior to product inspection. This makes it possible to perform semiconductor testing with high reliability. | 2010-09-09 |
20100225344 | PROBING APPARATUS WITH GUARDED SIGNAL TRACES - A probing apparatus can comprise a substrate, conductive signal traces, probes, and electromagnetic shielding. The substrate can have a first surface and a second surface opposite the first surface, and the electrically conductive first signal traces can be disposed on the first surface of the first substrate. The probes can be attached to the first signal traces, and the electromagnetic shielding structures can be disposed about the signal traces. | 2010-09-09 |
20100225345 | APPARATUS AND METHOD FOR TESTING A SEMICONDUCTOR DEVICE - Provided are an apparatus and a method of testing a semiconductor device. A horizontal maintaining unit provided inside a test head applies load to a probe card in a direction perpendicular to the probe card to hold the probe card in a horizontal state. Probe needles of the probe card are uniformly placed on a central region of pads of the semiconductor device, thereby providing an apparatus and a method of testing a semiconductor device capable of improving productivity and reducing a yield loss of a test process. | 2010-09-09 |
20100225346 | DEVICE AND METHOD FOR EVALUATING ELECTROSTATIC DISCHARGE PROTECTION CAPABILITIES - A device and a method for evaluating ESD protection capabilities of an integrated circuit, the method includes: connecting multiple test probe to multiple integrated circuit testing points. The method is characterized by repeating the stages of: (i) charging a discharge capacitor to an ESD protection circuit triggering voltage level; (ii) connecting the discharge capacitor to the integrated circuit during a testing period such as to cause the discharge capacitor to interact with the integrated circuit; (iii) measuring at least one signal of the integrated circuit, during at least a portion of the testing period; and (iv) determining at least one ESD protection characteristic of the integrated circuit in response to the at least one signal. | 2010-09-09 |
20100225347 | Circuit for Measuring Magnitude of Electrostatic Discharge (ESD) Events for Semiconductor Chip Bonding - A circuit for recording a magnitude of an ESD event during semiconductor assembly includes a voltage divider connected between an input and a ground. The circuit also includes a measurement block having a recorder device. Each measurement block receives current from a segment of the voltage divider. The magnitude of the ESD event is determined based upon a read-out of the measurement devices after the ESD event. The recorder device may be a capacitor that would be damaged during the ESD event. During the ESD event the capacitor may be damaged. Reading out the recorder device determines if the magnitude of the ESD event exceeded a threshold magnitude that damages the capacitor. | 2010-09-09 |
20100225348 | METHOD AND APPARATUS FOR STATISTICAL CMOS DEVICE CHARACTERIZATION - A unified test structure having a large number of electronic devices under test is used to characterize both capacitance-voltage parameters (C-V) and current-voltage parameters (I-V) of the devices. The devices are arranged in an array of columns and rows, and selected by control logic which gates input/output pins that act variously as current sources, sinks, clamps, measurement ports and sense lines. The capacitance-voltage parameter is measured by taking baseline and excited current measurements for different excitation voltage frequencies, calculating current differences between the baseline and excited current measurements, and generating a linear relationship between the current differences and the different frequencies. The capacitance is then derived by dividing a slope of a line representing the linear relationship by the excitation voltage. Different electronic devices may be so tested, including transistors and interconnect structures. | 2010-09-09 |
20100225349 | Techniques for Providing Calibrated On-Chip Termination Impedance - Techniques are provided for calibrating on-chip termination impedances on integrated circuits. An on-chip termination (OCT) calibration circuit generates calibration codes that selectively control the conductive states of a set of transistors coupled in parallel. The OCT calibration circuit selects a calibration code that causes the impedance of the transistors to be near a matching impedance. The selected calibration code controls an on-chip termination impedance at a pin. According to some embodiments, the OCT calibration circuit compares a signal from the transistors to two or more reference signals to improve the tolerance range of the calibrated on-chip termination impedance. According to other embodiments, the OCT calibration circuit selects a calibration code based on a signal from the transistors after an extra transistor is turned on by a control signal. The control signal is not used to control the on-chip termination impedance. | 2010-09-09 |
20100225350 | RECONFIGURABLE MAGNETIC LOGIC-CIRCUIT ARRAY AND METHODS FOR PRODUCING AND OPERATING SUCH LOGIC DEVICES - The invention relates to a reconfigurable magnetic logic-circuit array having at least two magnetoresistive elements, each composed of at least two magnetic layers, which are separated from one another by an intermediate layer, in each instance, whereby one of the magnetic layers, as a reference layer, does not substantially change its magnetization under the influence of external magnetic fields, and the other magnetic layer, as a free layer, changes its magnetization perceptibly under the influence of external magnetic fields, and having at least one conductor for signal ports, with which conductor, when current is flowing, a first magnetic field can be generated that flips the magnetization of the free layers, and having a device for on-demand generation of a second variable magnetic field, which also influences the magnetoresistive elements. For this purpose, two such magnetoresistive elements are disposed adjacent to one another, whereby the magnetization of the two reference layers is oriented in opposite directions by means of preadjusted unidirectional anisotropy, and the magnetoresistive elements are interconnected with one another in such a manner that, as a result of the action of the first and second magnetic fields on the magnetoresistive elements, the switching behavior of all basic logic functions, especially the AND, OR, NAND, NOR, XOR or XNOR functions, can be induced on the basis of the resulting changes in the orientation of the magnetization of the free layers, and thus of the resistance of the magnetoresistive elements in the logic-circuit array. | 2010-09-09 |
20100225351 | Resolving Mestastability - A logic circuit latch including an input stage for receiving a logical input signal and a pair of differential amplifiers, each having an input operatively coupled to the input stage, and at least one of them having an output arranged to supply the logical output of the latch. Each of the differential amplifiers includes a transistor connected as a load, and an output of each of the differential amplifiers is coupled to bias the load transistor of the other differential amplifier. If the latch switches from the transparent state to the closed state while the logical input signal is transitioning between logical levels, the differential amplifiers drive up the logical output of the latch if the logical input signal transitions from a first to a second logical level, and drive down the logical output of the latch if the input signal transitions from the second to the first logical level. | 2010-09-09 |
20100225352 | Integrated circuit with pin-selectable mode of operation and level-shift functionality and related apparatus, system, and method - An apparatus includes a digital interface circuit configured to provide a digital interface. The digital interface is configurable based on a mode of operation of the digital interface circuit. The apparatus also includes input and output level-shift circuits. The input level-shift circuit is configured to shift a voltage level of an input signal for the digital interface circuit. The output level-shift circuit is configured to shift a voltage level of an output signal from the digital interface circuit. The input level-shifting and the output level-shifting are based on first and second level-shift input voltages. The apparatus further includes a mode detector configured to identify at least two modes of operation for the digital interface circuit based on the first and second level-shift input voltages. For example, the digital interface circuit could be configured to function as a serial or parallel interface depending on which level-shift input voltage is greater. | 2010-09-09 |
20100225353 | METHODS AND SYSTEMS FOR REDUCING CLOCK SKEW IN A GATED CLOCK TREE - Systems and methods for synthesizing a gated clock tree with reduced clock skew are provided. A gated clock tree circuit with reduced clock skew may include a clock source and edge-triggered state elements. A gated clock tree disposed between the clock source and state elements may include a level in which each logic gate has a common logic type. Logic gates in the gated clock tree may also be configured as logic-gate buffers. The logic gates may also be configured as NAND-gated equivalents. The clock signal distributed through the gated clock tree may drive both positive-edge-triggered and negative-edge-triggered state elements. | 2010-09-09 |
20100225354 | LOOKUP TABLE, SEMICONDUCTOR INTEGRATED CIRCUIT, METHOD FOR MAKING LOOKUP TABLE AND METHOD FOR MAKING SEMICONDUCTOR INTEGRATED CIRCUIT - A lookup table includes a single via layer having 2 | 2010-09-09 |
20100225355 | Current-controlled CMOS logic family - Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C | 2010-09-09 |
20100225356 | LATCH CIRCUIT - A latch circuit includes an input part receiving an external input signal; a plurality of CMOS inverter circuits divided into a first group that includes a first CMOS inverter circuit and a second CMOS inverter circuit outputting inverted data with respect to the input signal, and a second group that includes a third CMOS inverter circuit and a fourth CMOS inverter circuit outputting the same data as the input signal; and a feedback path through which the input signal is fed back to the input part via the plurality of CMOS inverter circuits, wherein a second-polarity drain belonging to one of the first CMOS inverter circuit and the second CMOS inverter circuit is arranged between a first-polarity drain belonging to the first CMOS inverter circuit and a first-polarity drain belonging to the second CMOS inverter circuit. | 2010-09-09 |
20100225357 | REAL TIME CLOCK MONITORING METHOD AND SYSTEM - Method for monitoring a real time clock and a device having real time clock monitoring capabilities, the device includes: (i) a real time clock tree, (ii) a clock frequency monitor that is adapted to determine a frequency of a real time clock signal, during a short monitoring period; (iii) a monitoring enable module, adapted to activate the clock frequency monitor during short motoring periods and to deactivate the clock frequency monitor during other periods, wherein the monitoring enable module is adapted to determine a timing of the short monitoring periods in a non-deterministic manner; and (iv) a real time clock violation indication generator adapted to indicate that a real time clock violation occurred, in response to an error signal provided from the clock frequency monitor. | 2010-09-09 |
20100225358 | METHOD AND DEVICE FOR COMPARATOR OFFSET CANCELLATION - A method and a device for canceling an offset voltage in an output of a comparator circuit include sampling a set of offset voltages; applying a set of correction voltages equal in magnitude and opposite in polarity to the set of offset voltages, the set of correction voltages being applied to an output generating arrangement of the comparator circuit; and enabling output of the output generating arrangement after the set of correction voltages is applied. | 2010-09-09 |
20100225359 | OUTPUT SIGNAL GENERATING DEVICE - An output signal generating device according to the present invention includes a control circuit for generating a control signal, a reference signal generating unit for generating a reference signal, an output signal generating unit for generating an output signal according to a comparison result between the control signal and the reference signal, an output signal detecting unit for detecting the output signal based on a sampling signal, and an output signal storage unit for storing the output signal detected by the output signal detecting unit. The control circuit includes a readout unit for reading out the output signal stored in the output signal storage unit. According to the present invention, the output signal can be stored in real time and the results thereof can be processed by software. | 2010-09-09 |
20100225360 | Apparatus and Method for Frequency Conversion and Filter Thereof - The present invention relates to an apparatus for frequency conversion, comprising: an analog-to-digital (A/D) converter, receiving and sampling an input signal according to a sampling frequency for producing a first digital signal, and the sampling frequency and the frequency of the input signal having a correspondence; a sign conversion circuit, used for receiving the first digital signal, and performing a sign conversion on the first digital signal and producing a second digital signal; a first switching module, used for selecting one of the first digital signal and the second digital signal as an output signal according to the sampling frequency; a filter, coupled to the first switching module, used for filtering the output signal from the first switching module, and producing a filter signal; and a second switching module, coupled to the filter, used for outputting the filter signal to a first output path or a second output path alternately according to the sampling frequency. Thereby, according to the present invention, by means of the correspondence between the sampling frequency and the frequency of the input signal, the use of a filter and an A/D converter can be saved, and thus reducing circuit area and cost. | 2010-09-09 |
20100225361 | FREQUENCY DIVIDER, FREQUENCY SYNTHESIZER AND APPLICATION CIRCUIT - A frequency divider includes a prescaler and multiple modulus dividers commonly coupled to the prescaler. The prescaler generates intermediate frequency signals having a same phase difference with respect to one another in response to an oscillation frequency signal. The prescaler operates at a first frequency. The modulus dividers respectively divide the intermediate frequency signals with respective ratio to provide a plurality of division frequency signals in response to a control signal. The modulus dividers operate at a second frequency less than the first frequency. | 2010-09-09 |
20100225362 | Reduced line driver output dependency on process, voltage, and temperature variations - According to one exemplary embodiment, a transmitter module includes a line drive including a current digital-to-analog converter, where the line driver provides an analog output waveform. The current digital-to-analog converter receives a digitally filtered input waveform including at least two voltage steps. The at least two voltage steps of the digitally filtered input waveform cause a rise time of the analog output waveform to have a reduced dependency on process, voltage, and temperature variations in the line driver, while meeting stringent rise time requirements. The digitally filtered input waveform has an initial voltage level and a final voltage level, where the final voltage level is substantially equal to a sum of the at least two voltage steps of the digitally filtered input waveform. | 2010-09-09 |
20100225363 | Integrated Circuit for Driving Semiconductor Device and Power Converter - An integrated circuit for driving a semiconductor device, which is adaptable for demands, such as a higher output (larger current), a higher voltage, and a smaller loss, and has a small size, is produced at a low cost, and has high reliability. A power converter including such an integrated circuit is also provided. Circuit elements constituting a drive section of an upper arm drive circuit | 2010-09-09 |
20100225364 | Stacked semiconductor devices and signal distribution methods thereof - A stacked semiconductor device includes a plurality of stacked chips, each having a plurality of elements to receive a signal. At least one first ladder main signal line for receiving the signal is arranged to pass through the chips. At least one second ladder main signal line is arranged to pass through the chips. A plurality of ladder buffers buffer the signal applied from the first ladder main signal line to the second ladder main signal line. The signal is uniformly distributed to the stacked chips using a ladder type circuit network technique. | 2010-09-09 |
20100225365 | CLOCK DIVIDING CIRCUIT - A clock dividing circuit includes a control logic unit and a flip-flop. The control logic unit outputs an enable signal and a data signal according to a clock signal and a division ratio. The flip-flop outputs a divided clock signal based on the clock signal, the enable signal and the data signal. The clock signal can be directly outputted as the divided clock signal through the flip-flop. | 2010-09-09 |
20100225366 | SIGNAL GENERATOR WITH OUTPUT FREQUENCY GREATER THAN THE OSCILLATOR FREQUENCY - Systems and methods for design and operation of signal generator circuitry with output frequencies greater than the oscillator frequency. Accordingly, in a first method embodiment, a method of producing an output periodic electronic signal comprises accessing four signals having a quadrature phase relationship. First and second pairs of these signals having a one half cycle phase relationship are averaged to produce two signals having an improved duty cycle and a one-quarter cycle phase relationship. The first and second averaged periodic electronic signals are combined in an exclusive OR circuit to produce the output periodic electronic signal at twice the oscillator frequency. Advantageously, the periodic signal may comprise a desirable duty cycle of 50 percent. | 2010-09-09 |
20100225367 | FREQUENCY SYNTHESIZER WITH IMMUNITY FROM OSCILLATOR PULLING - Frequency synthesizer with immunity from oscillator pulling. The frequency synthesizer for generating an output frequency includes an oscillator that is capable of generating a first frequency. The frequency synthesizer also includes an output divider coupled to the oscillator. The output divider is configurable to allow the oscillator to generate a second frequency to prevent degradation in phase noise due to an interference to the first frequency of the oscillator, and to generate the output frequency from the second frequency. | 2010-09-09 |
20100225368 | PHASE-LOCKED LOOP CIRCUIT AND AN ASSOCIATED METHOD - The present invention relates to a PLL circuit and an associated method that allows the PLL circuit to operate at a higher operating frequency with a wider bandwidth and a better out-band noise suppression. The PLL circuit comprises a delay locked loop (DLL), a phase-frequency detector (PFD), a loop filter, a voltage controlled oscillator (VCO) and a frequency divider. | 2010-09-09 |
20100225369 | Devices Comprising Delay Line for Applying Variable Delay to Clock Signal - The disclosure relates to a device comprising at least one delay line for applying a variable delay to a clock signal and a controller for controlling the variable delay of the delay line. Each delay line comprises a plurality of concatenated delay banks which provide different delay values with respect to each other, a bypass parallel over each of said the delay banks, and switching elements associated with each of the delay banks for selecting either the respective delay bank or the respective bypass. Each of the delay banks is provided with a delay bank status indicator for indicating propagation of the clock signal through the delay bank towards the controller. The controller is provided for taking the indicated propagation of the clock signal into account upon setting said switching elements. Devices according to this disclosure are, amongst other uses, suited for use in Ultra Wide Band (UWB) receiving or transmitting devices, in particular those devices, designed for low power consumption, by enabling power on and off switching of parts of such devices as analog to digital converters and integrators, during timing windows. | 2010-09-09 |
20100225370 | Frequency-Doubling Delay Locked Loop - A frequency multiplier circuit comprising a delay line receiving at one end thereof a reference clock for generating clock tap outputs from respective ones of a plurality of period matched delay elements; a clock combining circuit responsive to pairs of tap outputs for generating a rising and falling edge of an output clock pulse from respective ones of the pairs whereby the output clock period is less than the input clock period. | 2010-09-09 |
20100225371 | Methods of Operating Timers to Inhibit Timing Error Accumulation - Methods of operating timers include generating a periodic timing signal having a first frequency that differs from a desired timer frequency (1 KHz) by a first amount. This periodic timing signal having the first frequency can be generated by dividing a frequency of an input clock signal (e.g., 32.768 KHz) by N, where N is a positive integer greater than one. A typical value of N may be 32. The methods also include techniques to inhibit timing error accumulation by switching a frequency of the periodic timing signal from the first frequency to a second frequency that differs from the desired timer frequency by a second amount. This periodic timing signal having the second frequency can be generated by dividing the frequency of the input clock signal by M, where M is a positive integer unequal to N (e.g., M−N equals±1). | 2010-09-09 |
20100225372 | DUTY CYCLE CORRECTION SYSTEMS AND METHODS - Duty cycle correction systems and methods of adjusting duty cycles are provided. One such duty cycle correction system includes a duty cycle adjustor and a variable delay line coupled to the output of the duty cycle adjustor. First and second phase detectors have first inputs coupled to the output of the duty cycle adjustor through an inverter and second inputs coupled to the output of the variable delay line. The phase detectors cause the delay line to align rising or falling edges of signals at the output of the delay line with rising or falling edges, respectively, of signals at the output of the inverter. The controller simultaneously causes the duty cycle adjustor to adjust the duty cycle of the output clock signal until the rising and falling edges of signals at the output of the delay line are aligned with rising and falling edges, respectively, of signals at the output of the inverter. | 2010-09-09 |
20100225373 | Delay Circuit - A delay circuit includes current sources, switches, a transistor switch, a charging unit and a comparator. Each of the switches is provided for receiving an enable signal to activate and convey one of the current sources. The transistor switch is activated for pulling down voltage of an operating node coupled to the switches. The charging unit provides an operating voltage for the operating node based on one of the current sources when the transistor switch is deactivated and one of the switches is activated to convey one of the current sources to the charging unit. The comparator is provided for comparing the operating voltage with a reference voltage. | 2010-09-09 |
20100225374 | LOW NOISE MIXER - One embodiment relates to a mixer for providing a mixed output signal. The mixer includes a radio-frequency (RF) stage, first and second power dividers, and first and second frequency-conversion stages. The RF stage includes a first differential pair. The first power divider is coupled to a first transistor of the first differential pair, and the second power divider is coupled to a second transistor of the first differential pair. The first frequency-conversion stage, which is adapted to provide a first converted-frequency signal, includes a second differential pair coupled to the second power divider and a third differential pair coupled to the first power divider. The second frequency-conversion stage, which is adapted to provide a second converted-frequency signal, includes a fourth differential pair coupled to the second power divider and a fifth differential pair coupled to the first power divider. Other techniques are also provided. | 2010-09-09 |
20100225375 | REFERENCE SIGNAL GENERATOR CIRCUIT PROVIDED WITH TWO 90-DEGREE PHASE SHIFTERS AND TWO MIXER CIRCUITS - A first mixer circuit mixes a first center frequency signal with a first local oscillation signal to generate a second mixed signal, and mixes the first center frequency signal with a second local oscillation signal to generate a first mixed signal, and a second mixer circuit mixes a second center frequency signal with the first local oscillation signal to generate a fourth mixed signal, and mixes the second center frequency signal with the second local oscillation signal to generate a third mixed signal. An adder and subtracter circuit subtracts the third mixed signal from the second mixed signal to output a signal of subtraction result as a first upper side band signal, and adds the first mixed signal to the fourth mixed signal to output a signal of addition result as a second upper side band signal different in phase from the first upper side band signal by 90 degrees. | 2010-09-09 |
20100225376 | SEMICONDUCTOR SWITCH, SEMICONDUCTOR SWITCH MMIC, CHANGEOVER SWITCH RF MODULE, POWER RESISTANCE SWITCH RF MODULE, AND TRANSMITTER AND RECEIVER MODULE - A semiconductor switch for switching a signal according to input power and maintaining performance of a receiver system with a simple configuration. The semiconductor switch comprises: a first FET connected between a first input/output terminal and a second input/output terminal; a first transmission line connected between the first input/output terminal and a third input/output terminal; a second transmission line parallel to the first transmission line; and a detector circuit connected to one end of the second transmission line, for outputting a DC voltage corresponding to power level of the high frequency signal, branched by the second transmission line. The first FET is controlled and switched according to an output from the detector circuit to switch between a route from the first input/output terminal to the second input/output terminal and a route from the first input/output terminal to the third input/output terminal. | 2010-09-09 |
20100225377 | SWITCH CIRCUIT - A switch circuit includes an input section; an output section; a first series section having an output and comprising at least a first 4-terminal FET connected between the input section and the output section through the output of the first series section; a first shunt section comprising at least a second 4-terminal FET connected between an output of the first series section and a ground; a first control terminal section connected with a gate of the first 4-terminal FET; a second control terminal section connected with a gate of the second 4-terminal FET; and a back gate control terminal section connected with a back gate of each of the first and second 4-terminal FETs. A bias power supply section is configured to apply a reverse bias voltage between the back gate control terminal section and the ground. | 2010-09-09 |
20100225378 | RADIO FREQUENCY SWITCHING CIRCUIT AND SEMICONDUCTOR DEVICE - A radio frequency switching circuit includes: a first switching element; a second switching element; a first biasing resistive element connected to a control terminal of the first switching element; a second biasing resistive element connected to a control terminal of the second switching element; and a control circuit which controls the first switching element and the second switching element according to a control signal being output from a control signal output terminal. C | 2010-09-09 |
20100225379 | ANALOG SWITCH - An analog switch including at least one first MOS transistor capable of transferring a signal from a first terminal to a second terminal; a connection circuit for bringing a substrate terminal of the first transistor to a voltage which is a function of the voltages of the first and second terminals; and a circuit for controlling a control voltage of the first transistor with the signal. | 2010-09-09 |
20100225380 | Implementing Tamper Resistant Integrated Circuit Chips - A method and tamper resistant circuit for resisting tampering including reverse engineering in a semiconductor chip, and a design structure on which the subject circuit resides are provided. A sensing device for detecting a chip tampering state is formed with the semiconductor chip including the circuitry to be protected. A tamper resistant control signal generator is coupled to the sensing unit for generating a tamper resistant control signal responsive to a detected chip tampering state. A functional operation inhibit circuit is coupled to the tamper resistant control signal generator for inhibiting functional operation of the circuitry to be protected responsive to the tamper resistant control signal. | 2010-09-09 |
20100225381 | FUSE FOR USE IN HIGH-INTEGRATED SEMICONDUCTOR DEVICE - The invention relates to a semiconductor device comprising a fuse that is implemented as a bar type pattern that forms a straight line instead of a pattern that is difficult to secure a manufacturing margin. A fuse block including a plurality of fuses comprises a plurality of first connection parts, each including a blowing area, a plurality of second connection parts, wherein the plurality of the second connection parts and the plurality of the corresponding first connection parts respectively form part of the fuse, and a common connection unit configured to electrically connect the plurality of the first connection parts and the plurality of the second connection parts. | 2010-09-09 |
20100225382 | APPARATUS FOR CONTROLLING SUBSTRATE VOLTAGE OF SEMICONDUCTOR DEVICE - A semiconductor integrated circuit apparatus includes an internal circuit having a MIS transistors on a semiconductor substrate and a substrate voltage control block that supplies a substrate voltage to the internal circuit and controls threshold voltages for the MIS transistors of the internal circuit. The apparatus also includes a leakage current detection MIS transistor and a leakage current detection circuit. The substrate voltage control block generates a substrate voltage based on comparison results of the comparator and applies the generated substrate voltage to the substrate of the leakage current detection MIS transistor and the substrate of the MIS transistors of the internal circuit. The substrate voltage control block includes a switch arranged between first and second input terminals of a comparator and a drain of the leakage current detection MIS transistor and a reference potential terminal, as well as an input data corrector that carries out substrate voltage adjustment. | 2010-09-09 |
20100225383 | CHARGE PUMP CONVERTER AND METHOD THEREFOR - In one embodiment, a charge pump converter is formed to use various values of an output voltage to selectively control a value of a charging current during a charging cycle of the charge pump converter. | 2010-09-09 |
20100225384 | REFERENCE CURRENT SOURCE CIRCUIT PROVIDED WITH PLURAL POWER SOURCE CIRCUITS HAVING TEMPERATURE CHARACTERISTICS - A reference current source circuit is provided which is capable of outputting a constant reference current even if surrounding environments such as temperature and power source voltage change in a power source circuit that operates in a minute current region in an order of nanoamperes. The reference current source circuit includes an nMOS-configured power source circuit, a pMOS-configured power source circuit, and a current subtracter circuit. The nMOS-configured power source circuit includes a current generating nMOSFET, and generates a first current having temperature characteristics of an output current dependent on an electron mobility. The pMOS-configured power source circuit includes a current generating pMOSFET, and generates a second current having temperature characteristics of an output current dependent on a hole mobility. The current subtracter circuit generates a constant reference current by subtracting the second current from the first current. | 2010-09-09 |
20100225385 | ACTIVE POWER FILTER METHOD AND APPARATUS - This disclosure provides active power filter methods and apparatus to control the PF, harmonics and/or ripple current associated with powering electrical devices. According to one exemplary aspect, an active power filter is configured to measure the momentary ac line output current, measure the momentary ac line input current and switch an energy buffer to provide additional current to the ac line output or draw current from the ac line input to control the PF associated with the device. | 2010-09-09 |
20100225386 | QUADRATURE SIGNAL DEMODULATOR CIRCUITRY SUITABLE FOR DOPPLER ULTRASOUND - Quadrature signal demodulator circuitry for demodulating multiple related input signals into respective pairs of quadrature signals for selective combining to provide a composite pair of quadrature signals with a maximized signal-to-noise ratio (SNR). | 2010-09-09 |
20100225387 | FM demodulator apparatus and method includes an amplitude locked loop and a delay-line quadrature detector without the use of a limited amplifier - The present invention relates to an FM demodulator incorporating a delay-line quadrature detector without the use of a limiter amplifier. An Amplitude Locked Loop circuit provides a carrier signal with no amplitude variation prior to performing a conversion from frequency modulation to phase modulation. A delay-line performs this conversion using a standard IF ceramic filter with a precise delay of 90 degrees to the un-modulated carrier frequency. The original non-delayed carrier is multiplied with the delayed carrier using a four quadrant linear multiplier to generate a demodulated audio output. | 2010-09-09 |
20100225388 | POWER AMPLIFIER - A Doherty amplifier is provided with a clipping circuit for making signal power flow to ground if the signal power becomes equal to or higher than a predetermine value in order to prevent a carrier amplifier, which is a small amplifier, from being destroyed if the signal power is increased to a sevenfold to tenfold multiple of a ratio of the size of the carrier amplifier to that of a peak amplifier. | 2010-09-09 |
20100225389 | HIGH EFFICIENCY RF SYSTEM LINEARIZER USING CONTROLLED COMPLEX NONLINEAR DISTORTION GENERATORS - A linearizer reduces nonlinear intermodulation distortion in radio frequency and microwave systems by first directly generating in-phase and quadrature nonlinear intermodulation products of the system input. Controllable amounts of each phase are then added back into the system such that the vector sum of nonlinear intermodulation products at the output is reduced or eliminated by destructive interference, while the fundamentals are substantially unaffected. The quadrature distorted signals are generated with two lightly-biased and thus overdriven differential pairs having gain-determining degeneration impedances that are in quadrature with each other. The amount of each quadrature phase summed to the output is controlled with electronically tunable four-quadrant variable attenuators. The quadrature phasing enables rapidly convergent tuning to minimize distortion using conventional scalar spectral analysis. The advantages of a linearizer using rectangular vector coordinate system are significant. | 2010-09-09 |
20100225390 | Resource Efficient Adaptive Digital Pre-Distortion System - A digital pre-distortion system which can provide the flexibility to model the highly non-linear distortion associated with High Efficiency RF Power Amplifiers while through a novel implementation of a least squares estimation process allows an implementation well suited for an FPGA application where limited resources and in particular memory resources are available. | 2010-09-09 |
20100225391 | Three-level half-bridge pulse-width modulation amplifier and method of driving the same - A three-level half-bridge PWM amplifier includes a PWM generator and an output stage. The PWM generator changes a width of a pulse at a first level or a second level according to amplitude of an input signal and outputs a three-level PWM output signal having the first level, the second level, and a reference level. The output stage drives an output node connected to a terminal of a load to a first power supply voltage, a second power supply voltage, or a third power supply voltage based on the three-level PWM output signal. Accordingly, unnecessary static current consumption is reduced, thereby increasing efficiency. | 2010-09-09 |
20100225392 | HIGH BANDWIDTH, RAIL-TO-RAIL DIFFERENTIAL AMPLIFIER WITH OUTPUT STAGE AMPLIFIER - An error amplifier expected to exhibit rail-to-rail operation, high bandwidth, and high slew rate, is described, the error amplifier comprising a first stage to receive an input differential voltage and to provide transconductance gain, an intermediate stage to provide current gain, and an output stage to drive a load. | 2010-09-09 |
20100225393 | HIGH BANDWIDTH, RAIL-TO-RAIL DIFFERENTIAL AMPLIFIER WITH INTERMEDIATE STAGE CURRENT AMPLIFIER - An error amplifier expected to exhibit rail-to-rail operation, high bandwidth, and high slew rate, is described, the error amplifier comprising a first stage to receive an input differential voltage and to provide transconductance gain, an intermediate stage to provide current gain, and an output stage to drive a load. | 2010-09-09 |
20100225394 | HIGH BANDWIDTH, RAIL-TO-RAIL DIFFERENTIAL AMPLIFIER WITH INPUT STAGE TRANSCONDUCTANCE AMPLIFIER - An error amplifier expected to exhibit rail-to-rail operation, high bandwidth, and high slew rate, is described, the error amplifier comprising a first stage to receive an input differential voltage and to provide transconductance gain, an intermediate stage to provide current gain, and an output stage to drive a load. | 2010-09-09 |
20100225395 | Input Buffer With Impedance Cancellation - An exemplary negative impedance converting circuit for functioning as a voltage buffer and/or negating the impedance of a connected load. The negative impedance converting circuit includes inputs, outputs, a first transconductance stage and a second transconductance stage. The transconductance gain value of the first transconductance stage is greater than a transconductance gain value of the second transconductance stage. Exemplary embodiments of a reference voltage buffer using the negative impedance converting circuit are also described. | 2010-09-09 |
20100225396 | SEMICONDUCTOR INTEGRATED CIRCUIT AND ELECTRONIC DEVICE - An electronic device has a manipulation part which outputs a control signal including a first analog signal and a second analog signal obtained by inverting a phase of the first analog signal; and a display part which includes a semiconductor integrated circuit supplied at an input terminal thereof with the control signal to output a signal depending upon the control signal from an output terminal thereof, and which displays a predetermined image based on the signal output from the semiconductor integrated circuit. | 2010-09-09 |
20100225397 | AMPLIFIER AND RADIO - An amplifier includes: a substrate; first to fourth amplifying units arranged on the substrate and each having first and second terminals, and each amplifying first and second signals to generate first and second amplified signals; a first inductive line arranged on the substrate, connecting the first terminal of the first amplifying unit and the first terminal of the second amplifying unit, and having a linear portion and a bending portion; a second inductive line arranged on the substrate, connecting the second terminal of the second amplifying unit and the first terminal of the third amplifying unit, and having a linear portion and a bending portion; a third inductive line arranged on the substrate, connecting the second terminal of the third amplifying unit and the first terminal of the fourth amplifying unit, and having a linear portion and a bending portion; a fourth inductive line arranged on the substrate, connecting the second terminal of the fourth amplifying unit and the second terminal of the first amplifying unit, and having a linear portion and a bending portion; and a fifth inductive line which establishes magnetic field coupling with the first to fourth inductive lines, and has third and fourth terminals, combines the plurality of the first amplified signals amplified to output the first combined signal from the third terminal, and combines the plurality of the second amplified signals to output the second combined signal from the fourth terminal. | 2010-09-09 |
20100225398 | MULTI-PATH, MULTI-OXIDE-THICKNESS AMPLIFIER CIRCUIT - An embodiment of a multi-path, multi-oxide-thickness amplifier circuit includes a first amplifier having at least one thin-oxide output transistor, and a second amplifier having at least one thick-oxide output transistor. The first and second amplifiers are connected in parallel with each other between an input terminal and an output terminal of the amplifier circuit. The thin-oxide output transistor has a gate-oxide layer thickness that is less than a gate-oxide layer thickness of the thick-oxide output transistor. | 2010-09-09 |
20100225399 | POWER AMPLIFIER, AND METHOD OF CONTROLLING POWER AMPLIFIER - A power amplifier of the present invention comprises MOS transistor ( | 2010-09-09 |
20100225400 | METHOD AND SYSTEM FOR ON-CHIP IMPEDANCE CONTROL TO IMPEDANCE MATCH A CONFIGURABLE FRONT END - Methods and systems for on-chip impedance control to impedance match a configurable front end are disclosed and may include selectively enabling one or more amplifiers coupled to taps on a multi-tap transformer in a chip including the amplifiers. The impedances of the amplifiers may be matched to impedances of the taps on the transformer. The amplifiers may include low noise amplifiers wherein the input impedance of each of the low noise amplifiers may be different. The amplifiers may include power amplifiers wherein an output impedance of each of the power amplifiers may be different. The transformer may be coupled to an on-chip antenna, or to an antenna integrated on a package coupled to the chip. The multi-tap transformer may be integrated on the package. RF signals may be communicated via the selectively enabled amplifiers and the multi-tap transformer. The multi-tap transformer may include ferromagnetic materials integrated in the chip. | 2010-09-09 |
20100225401 | SEMICONDUCTOR DEVICE - The present invention provides a technology capable of achieving an improvement in the characteristic of a power amplifier when a power amplifier mounted onto mobile communication equipment such as a cellular phone is comprised of the balance amplifier. One feature of an embodiment resides in that each of passive parts disposed in a low-band signal negative path and each of passive parts disposed in a low-band signal positive path are placed in positions where they are symmetric with respect to a center line of a semiconductor chip. Thus, the symmetry between the low-band signal negative path and the low-band signal positive path is enhanced. As a result, a loss in matching due to the difference between the low-band signal negative path and the low-band signal positive path can be enough reduced, and the characteristic of a low-band signal balance amplifier can be enhanced. | 2010-09-09 |
20100225402 | VCO TUNING WITH TEMPERATURE COMPENSATION - Techniques for setting a fine tuning input signal Vtune for a voltage-controlled oscillator (VCO) in a coarse tuning mode of the VCO. In an exemplary embodiment, the fine tuning input signal during coarse tuning mode is made temperature-dependent to account for possible variation of Vtune over temperature during fine tuning mode. Methods and apparatuses employing the techniques are further described. | 2010-09-09 |
20100225403 | CRYSTAL- BASED OSCILLATOR FOR USE IN SYNCHRONIZED SYSTEM - A crystal oscillator-based module, which includes a crystal resonator receiving a conditioned signal from a first bus and passing a resonator signal to a sustaining stage amplifier. A synchronization range expansion circuit is connected between a gain control network and the resonator. A tri-state buffer has a main input connected to receive the resonator signal through a buffer. The output of the tri-state buffer is connected to a second bus, through a matching network if necessary. A synchronous clock system can be formed by connecting these modules alternately to the two busses. The tri-state buffer also has a control input, which may be connected to a delay circuit between Vcc and ground, so as to allow hot swapping and for other benefits. | 2010-09-09 |
20100225404 | ELECTRONIC PULSE GENERATOR AND OSCILLATOR - Improvements in and relating to electronic pulse generation or oscillation circuitry based on a signal path exhibiting endless electromagnetic continuity and affording signal phase inversion in setting pulse duration or half-cycles of oscillation within time of signal traverse of said signal path, and having active switching means associated with said signal path to set rise and fall times of each said pulse or said half-cycle of oscillation, including for frequency adjustment by selective inductance and power saving without stopping pulse generation or oscillation. | 2010-09-09 |
20100225405 | OSCILLATOR DEVICE COMPRISING A THERMALLY-CONTROLLED PIEZOELECTRIC RESONATOR - The crystal oscillator device includes an air-tight case ( | 2010-09-09 |
20100225406 | SELF-CALIBRATING OSCILLATOR - A self-calibrating oscillator that increases the output frequency accuracy without using a charge pump includes an oscillation circuit, a pulse counter, a charging circuit, a reset circuit, a calibration circuit, and a timing control unit. The pulse counter counts a pulse signal having frequency f | 2010-09-09 |
20100225407 | Interference resistant local oscillator - With some embodiments, a VCO (voltage controlled oscillator) operates at an integer multiple (N) above a desired transmission frequency. | 2010-09-09 |