36th week of 2022 patent applcation highlights part 59 |
Patent application number | Title | Published |
20220285501 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - At any timing after formation of gate electrodes, particle beam irradiation is performed to a semiconductor wafer having an n | 2022-09-08 |
20220285502 | METHOD FOR MANUFACTURING SiC SUBSTRATE - An object to be solved by the present invention is to provide a new technology for producing a SiC substrate in which strain is removed and capable of achieving a flat surface as flat as a surface that has been subjected to CMP. The present invention, which solves the above object, is a method for producing a SiC substrate, the method including an etching step of etching a SiC substrate having arithmetic average roughness (Ra) of a surface of equal to or less than 100 nm in an atmosphere containing Si element and C element. | 2022-09-08 |
20220285503 | METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR DEVICE AND NITRIDE SEMICONDUCTOR DEVICE - A method for manufacturing a nitride semiconductor device including: forming N-type regions in a nitride semiconductor layer; implanting ions of an acceptor element into a region sandwiched by the N-type regions in the nitride semiconductor layer; and forming a P-type region sandwiched by the N-type regions by subjecting the nitride semiconductor layer to heat treatment and activating the acceptor element. The forming the N-type regions includes implanting ions of a donor element to the nitride semiconductor layer such that concentration of the donor element in the N-type regions is equal to or greater than concentration of the acceptor element in the P-type region. The implanting ions of the acceptor element includes implanting ions of the acceptor element such that concentration of the acceptor element in the P-type region is 1×10 | 2022-09-08 |
20220285504 | METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR DEVICE AND NITRIDE SEMICONDUCTOR DEVICE - A method for manufacturing a nitride semiconductor device including: forming an N-type region in a nitride semiconductor layer; implanting ions of an acceptor element into a region under the N-type region in the nitride semiconductor layer; and forming a first P-type region under the N-type region by subjecting the nitride semiconductor layer to heat treatment and activating the acceptor element. The forming the N-type region includes implanting ions of a donor element into the nitride semiconductor layer such that concentration of the donor element in the N-type region is equal to or greater than concentration of the acceptor element in the first P-type region. The implanting ions of the acceptor element into a region under the N-type region includes implanting ions of the acceptor element such that concentration of the acceptor element in the first P-type region is 1×10 | 2022-09-08 |
20220285505 | INDIUM-GALLIUM-NITRIDE STRUCTURES AND DEVICES - InGaN layers characterized by an in-plane lattice parameter within a range from 3.19 Å to 3.50 Å are disclosed. The InGaN layers are grown by coalescing InGaN grown on a plurality of GaN seed regions. The InGaN layers can be used to fabricate optical and electronic devices for use in light sources for illumination and display applications. | 2022-09-08 |
20220285506 | NOR-TYPE STORAGE DEVICE, METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC APPARATUS INCLUDING STORAGE DEVICE - A NOR-type storage device, a method of manufacturing the same, and an electronic apparatus including the same are provided. The NOR-type storage device includes: a gate stack extending vertically on a substrate; an active region surrounding a periphery of the gate stack, the active region including first and second source/drain regions, a first channel region between the first and second source/drain regions, third and fourth source/drain regions, and a second channel region between the third and fourth source/drain regions; first, second, third and fourth interconnection layers extending laterally from the first to fourth source/drain regions, respectively; and a source line contact part extending vertically with respect to the substrate to pass through the first to fourth interconnection layers and electrically connected to one of the first interconnection layer and the second interconnection layer, and to one of the third interconnection layer and the fourth interconnection layer. | 2022-09-08 |
20220285507 | TRANSISTOR, TERNARY INVERTER INCLUDING SAME, AND TRANSISTOR MANUFACTURING METHOD - A transistor includes a substrate; a pair of constant current forming regions provided in the substrate; a pair of source/drain regions respectively provided on the pair of constant current forming regions in the substrate; and a gate structure provided between the pair of source/drain regions, wherein any one of the constant current forming regions immediately adjacent to any one of the pair of source/drain regions serving as a drain forms a constant current between the any one of the pair of source/drain region serving as the drain and the any one of the constant current forming regions. | 2022-09-08 |
20220285508 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a substrate, a first source finger provided on the substrate, a first gate finger provided adjacent to the first source finger in a width direction of the first source finger, a second source finger having a width smaller than a width of the first source finger, a second gate finger provided adjacent to the second source finger in the width direction of the second source finger, a first source wiring connecting the first source finger to the second source finger, a first gate wiring sandwiching the second source finger between the first gate wiring and the second gate finger, a second gate wiring intersecting the first source wiring in a non-contact manner, and connecting the first gate wiring to the first gate finger, and a first drain finger sandwiching the first gate finger and the second gate finger between the first drain finger. | 2022-09-08 |
20220285509 | SEMICONDUCTOR DEVICE - A semiconductor device includes a base body, a stacked body on the base body and a first columnar part. The base body includes a substrate, a first insulating film on the substrate, a first conductive film on the first insulating film, and a first semiconductor part on the first conductive film. The stacked body includes conductive layers and insulating layers stacked alternately in a stacking direction. The first columnar part is provided inside the stacked body and the first semiconductor part. The first columnar part includes a semiconductor body and a memory film between the semiconductor body and conductive layers. The semiconductor body extends in the stacking direction. The first columnar part has a first diameter and a second diameter in a first direction crossing the stacking direction. The first diameter inside the first semiconductor part is larger than the second diameter inside the stacked body. | 2022-09-08 |
20220285510 | Semiconductor Device with Backside Contact and Methods of Forming Such - In an exemplary aspect, the present disclosure is directed to a device. The device includes a fin-shaped structure extending lengthwise along a first direction. The fin-shaped structure includes a stack of semiconductor layers arranged one over another along a second direction perpendicular to the first direction. The device also includes a first source/drain feature of a first dopant type on the fin-shaped structure and spaced away from the stack of semiconductor layers. The device further includes a second source/drain feature of a second dopant type on the fin-shaped structure over the first source/drain feature along the second direction and connected to the stack of semiconductor layers. The second dopant type is different from the first dopant type. Furthermore, the device additionally includes an isolation feature interposing between the first source/drain feature and the second source/drain features. | 2022-09-08 |
20220285511 | SEMICONDUCTOR DEVICE - A semiconductor device includes active regions extending on a substrate in a first direction, gate structures intersecting the active regions and extending on the substrate in a second direction, source/drain regions in recess regions in which the active regions are recessed, on both sides of each of the gate structures, and contact plugs connected to the source/drain regions, wherein each of the source/drain regions include first and second epitaxial layers sequentially stacked on the active regions in the recess regions in a third direction perpendicular to an upper surface of the substrate, respectively, and wherein ratios of the first epitaxial layer thickness in the third direction to the second epitaxial layer thickness in the third direction are different in different ones of the source/drain regions. | 2022-09-08 |
20220285512 | Semiconductor Device With Gate Isolation Features And Fabrication Method Of The Same - Semiconductor structures and the manufacturing method thereof are disclosed. An exemplary manufacturing method includes providing a workpiece that includes a substrate, first channel members and second channel members over the substrate, a first gate structure engaging the first channel members, a second gate structure engaging the second channel members, a dielectric fin disposed between the first and second gate structures, an isolation feature disposed under the dielectric fin. The method also includes forming a metal cap layer at the frontside of the workpiece and depositing a dielectric feature on the dielectric fin. The dielectric feature dividing the metal cap layer into a first segment and a second segment. The method also includes etching the isolation feature to form a trench at the backside of the substrate, depositing a spacer on sidewalls of the trench, etching the dielectric fin from the trench, and depositing a seal layer in the trench. | 2022-09-08 |
20220285513 | SOURCE/DRAIN CONTACT WITH LOW-K CONTACT ETCH STOP LAYER AND METHOD OF FABRICATING THEREOF - Gate spacer that improves performance and methods for fabricating such are disclosed herein. An exemplary device includes a gate stack disposed over a semiconductor layer and a gate spacer disposed on a sidewall of the gate stack. A source/drain feature is disposed in the semiconductor layer and adjacent the gate spacer. A low-k contact etch stop layer is disposed on a top surface and a sidewall of the gate spacer and a portion of the gate spacer is disposed between the low-k contact etch stop layer and the semiconductor layer. A source/drain contact is disposed on the source/drain feature and adjacent the low-k contact etch stop layer. | 2022-09-08 |
20220285514 | Forming Low-Resistance Capping Layer Over Metal Gate Electrode - A semiconductor device includes a plurality of active region structures that each protrude upwards in a vertical direction. The active region structures each extend in a first horizontal direction. The active region structures are separated from one another in a second horizontal direction different from the first horizontal direction. A gate structure is disposed over the active region structures. The gate structure extends in the second horizontal direction. The gate structure partially wraps around each of the active region structures. A conductive capping layer is disposed over the gate structure. A gate via is disposed over the conductive capping layer. A dimension of the conductive capping layer measured in the second horizontal direction is substantially greater than a maximum dimension of the gate via measured in the second horizontal direction. | 2022-09-08 |
20220285515 | GRAPHENE WRAP-AROUND CONTACT - The present disclosure provides source/drain epitaxial structures and source/drain contacts wrapped with graphene layers in fin structures of FETs, and fabricating methods thereof. In some embodiments, a disclosed semiconductor device includes a fin structure on a substrate. The fin structure includes an epitaxial region. The semiconductor device further includes a metal contact above the epitaxial region, and a graphene film covering a top surface and sidewalls of the epitaxial region and covering a bottom surface and sidewalls of the metal contact. | 2022-09-08 |
20220285516 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes plurality of fin structures extending in first direction on semiconductor substrate. Fin structure's lower portion is embedded in first insulating layer. First gate electrode and second gate electrode structures extend in second direction substantially perpendicular to first direction over of fin structures and first insulating layer. The first and second gate electrode structures are spaced apart and extend along line in same direction. First and second insulating sidewall spacers are arranged on opposing sides of first and second gate electrode structures. Each of first and second insulating sidewall spacers contiguously extend along second direction. A second insulating layer is in region between first and second gate electrode structures. The second insulating layer separates first and second gate electrode structures. A third insulating layer is in region between first and second gate electrode structures. The third insulating layer is formed of different material than second insulating layer. | 2022-09-08 |
20220285517 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICES - A semiconductor device includes a gate structure disposed over a channel region and a source/drain region. The gate structure includes a gate dielectric layer over the channel region, one or more work function adjustment material layers over the gate dielectric layer, and a metal gate electrode layer over the one or more work function adjustment material layers. The one or more work function adjustment layers includes an aluminum containing layer, and a diffusion barrier layer is disposed at at least one of a bottom portion and a top portion of the aluminum containing layer. The diffusion barrier layer is one or more of a Ti-rich layer, a Ti-doped layer, a Ta-rich layer, a Ta-doped layer and a Si-doped layer. | 2022-09-08 |
20220285518 | SEMICONDUCTOR DEVICE - A semiconductor device and a method of fabricating a semiconductor device, the device including a fin-type pattern extending in a first direction; a gate electrode extending in a second direction over the fin-type pattern, the second direction being different from the first direction; spacers on sidewalls of the gate electrode; a capping structure on the gate electrode and the spacers, the capping structure including a first capping pattern and a second capping pattern, the second capping pattern being on the first capping pattern; and an interlayer insulating film surrounding sidewalls of each of the spacers and sidewalls of the capping structure, the interlayer insulating film being in contact with the first capping pattern. | 2022-09-08 |
20220285519 | CARRIER BARRIER LAYER FOR TUNING A THRESHOLD VOLTAGE OF A FERROELECTRIC MEMORY DEVICE - The present disclosure relates to an integrated circuit (IC) chip including a memory cell with a carrier barrier layer for threshold voltage tunning. The memory cell may, for example, include a gate electrode, a ferroelectric structure, and a semiconductor structure. The semiconductor structure is vertically stacked with the gate electrode and the ferroelectric structure, and the ferroelectric structure is between the gate electrode and the semiconductor structure. A pair of source/drain electrodes is laterally separated and respectively on opposite sides of the gate electrode, and a carrier barrier layer separates the source/drain electrodes from the semiconductor structure. | 2022-09-08 |
20220285520 | PROCESS FOR PREPARING A THIN LAYER OF FERROELECTRIC MATERIAL - A process for preparing a thin layer made of ferroelectric material based on alkali metal, exhibiting a determined Curie temperature, transferred from a donor substrate to a carrier substrate by using a transfer technique including implanting light species into the donor substrate in order to produce an embrittlement plane, the thin layer having a first, free face and a second face that is arranged on the carrier substrate. The process comprises a first heat treatment of the transferred thin layer at a temperature higher than the Curie temperature, the thin layer exhibiting a multi-domain character upon completion of the first heat treatment, and introducing, after the first heat treatment, protons into the thin layer, followed by applying a second heat treatment of the thin layer at a temperature lower than the Curie temperature to generate an internal electric field that results in the thin layer being made single domain. | 2022-09-08 |
20220285521 | Negative Capacitance Transistor Having A Multilayer Ferroelectric Structure Or A Ferroelectric Layer With A Gradient Doping Profile - A negative capacitance semiconductor device includes a substrate. A dielectric layer is disposed over a portion of the substrate. A ferroelectric structure disposed over the dielectric layer. Within the ferroelectric structure: a material composition of the ferroelectric structure varies as a function of a height within the ferroelectric structure. A gate electrode is disposed over the ferroelectric structure. | 2022-09-08 |
20220285522 | METHOD FOR FORMING A HIGH-VOLTAGE METAL-OXIDE-SEMICONDUCTOR TRANSISTOR DEVICE - A semiconductor substrate is provided. A trench isolation region is formed in the semiconductor substrate. A resist pattern having an opening exposing the trench isolation region and partially exposing the semiconductor substrate is disposed adjacent to the trench isolation region. A first ion implantation process is performed to implant first dopants into the semiconductor substrate through the opening, thereby forming a well region in the semiconductor substrate. The trench isolation region is within the well region. A second ion implantation process is performed to implant second dopants into the semiconductor substrate through the opening, thereby forming an extended doped region contiguous with the well region. The resist pattern is then removed. After removing the resist pattern, a gate dielectric layer is formed on the semiconductor substrate. A gate is then formed on the gate dielectric layer. The gate overlaps with the extended doped region. | 2022-09-08 |
20220285523 | ELECTRICAL ISOLATION STRUCTURE USING REVERSE DOPANT IMPLANTATION FROM SOURCE/DRAIN REGION IN SEMICONDUCTOR FIN - A structure includes a semiconductor fin on a substrate. A first fin transistor (finFET) is on the substrate, and a second finFET is on the substrate adjacent the first finFET. The first finFET and the second finFET include respective pairs of source/drain regions with each including a first dopant of a first polarity. An electrical isolation structure is in the semiconductor fin between one of the source/drain regions of the first finFET and one of the source/drain regions for the second FinFET, the electrical isolation structure including a second dopant of an opposing, second polarity. The electrical isolation structure extends to an upper surface of the semiconductor fin. A related method is also disclosed. | 2022-09-08 |
20220285524 | SCHOTTKY BARRIER DIODE WITH REDUCED LEAKAGE CURRENT AND METHOD OF FORMING THE SAME - A semiconductor device includes a first well region in a substrate; a first dielectric layer over the first well region, wherein the first dielectric layer includes a stepped shape over the first well region; and a conductive layer over the first well region. The conductive layer forms a Schottky barrier interface with the first well region. | 2022-09-08 |
20220285525 | METHOD FOR MANUFACTURING STRUCTURE, AND STRUCTURE - There is provided a method for manufacturing a structure, including: forming a recess portion by performing a first etching to a surface of a member composed of Group III nitride; and flattening a bottom of the recess portion by performing a second etching to the bottom, wherein in forming the recess portion, a flat portion and a protruding portion are formed on the bottom of the recess portion, the protruding portion being raised with respect to the flat portion because it is less likely to be etched by the first etching than the flat portion, and in flattening the bottom, by etching the protruding portion by the second etching, the protruding portion is lowered. | 2022-09-08 |
20220285526 | METHOD OF MAKING HETEROEPITAXIAL STRUCTURES AND DEVICE FORMED BY THE METHOD - A method for making a heteroepitaxial layer. The method comprises providing a semiconductor substrate. A seed area delineated with a selective growth mask is formed on the semiconductor substrate. The seed area comprises a first material and has a linear surface dimension of less than 100 nm. A heteroepitaxial layer is grown on the seed area, the heteroepitaxial layer comprising a second material that is different from the first material. Devices made by the method are also disclosed. | 2022-09-08 |
20220285527 | TRANSISTOR ARRANGEMENTS WITH STACKED TRENCH CONTACTS AND GATE CONTACTS WITHOUT GATE CAPS - Described herein are fabrication processes and resulting transistor arrangements with trench contacts that have two parts—a first trench contact (TCN1) and a second trench contact (TCN2)—stacked over one another, and with gate contacts (VCGs). In such transistor arrangements, the TCN1 may be self-aligned to adjacent gates and may be used to make cell-level connections, the TCN2 may also make cell-level connections and may be provided after the self-aligned TCN1 formation and may have an inverse taper shape, the spacer around the TCN2 may be a higher dielectric constant dielectric material than conventional spacer materials, and the VCGs may be formed without the presence of any gate caps or after using only thin temporary gate caps. Fabrication processes and transistor arrangement described herein may provide several improvements in terms of increased edge placement error margin, cost-efficiency, and device performance. | 2022-09-08 |
20220285528 | FORMATION OF TRANSISTOR GATES - A method comprises forming first and second fins each comprising alternately stacking first and second semiconductor layers; forming dummy gate structures over the first and second fins, and gate spacers on either side of the dummy gate structures; removing the dummy gate structures to form first and second gate trenches; removing the first semiconductor layers such that the second semiconductor layers are suspended in the first and second gate trenches; depositing a first dielectric layer around the second semiconductor layers and a second dielectric layer around the first dielectric layer; performing an ALD process to form a hard mask layer around the second dielectric layer, the ALD process comprising pulsing a first precursor for a first pulse time longer than about one second; patterning the hard mask layer; and etching a portion of the second gate dielectric layer in the second gate trench. | 2022-09-08 |
20220285529 | Dielectric Spacer to Prevent Contacting Shorting - A method includes forming a first and a second dummy gate stack crossing over a semiconductor region, forming an ILD to embed the first and the second dummy gate stacks therein, replacing the first and the second dummy gate stacks with a first and a second replacement gate stack, respectively, performing a first etching process to form a first opening. A portion of the first replacement gate stack and a portion of the second replacement gate stack are removed. The method further includes filling the first opening to form a dielectric isolation region, performing a second etching process to form a second opening, with the ILD being etched, and the dielectric isolation region being exposed to the second opening, forming a contact spacer in the second opening, and filling a contact plug in the second opening. The contact plug is between opposite portions of the contact spacer. | 2022-09-08 |
20220285530 | Air Spacer and Method of Forming Same - In an embodiment, a method of forming a semiconductor device includes forming a dummy gate stack over a substrate; forming a first spacer layer over the dummy gate stack; oxidizing a surface of the first spacer layer to form a sacrificial liner; forming one or more second spacer layers over the sacrificial liner; forming a third spacer layer over the one or more second spacer layers; forming an inter-layer dielectric (ILD) layer over the third spacer layer; etching at least a portion of the one or more second spacer layers to form an air gap, the air gap being interposed between the third spacer layer and the first spacer layer; and forming a refill layer to fill an upper portion of the air gap. | 2022-09-08 |
20220285531 | ISOLATED FIN STRUCTURES IN SEMICONDUCTOR DEVICES - A semiconductor device and a method of forming the same are disclosed. The method includes forming a fin with a sacrificial layer on a semiconductor substrate, forming isolation regions on the semiconductor substrate and adjacent to the fin, forming a superlattice structure with first and second nanostructured layers on the sacrificial layer, forming a sacrificial structure that surrounds the superlattice structure, forming a first spacer on the superlattice structure, forming an air gap between the superlattice structure and the fin, and forming a second spacer on the fin and below the superlattice structure. | 2022-09-08 |
20220285532 | SEMICONDUCTOR DIE WITH A POWER DEVICE AND METHOD OF MANUFACTURING THE SAME - The disclosure relates to a semiconductor die with a transistor device, which has a channel region formed in a semiconductor body, a gate region aside the channel region, for controlling a channel formation, a drift region formed in the semiconductor body, and a field electrode in a field electrode trench, which extends from a frontside of the semiconductor body vertically into the drift region, wherein an insulating layer is formed on the frontside of the semiconductor body and a frontside metallization is formed on the insulating layer, and wherein a capacitor electrode is formed in the insulating layer, which is conductively connected to at least a portion of the field electrode. | 2022-09-08 |
20220285533 | MULTI-GATE DEVICE AND RELATED METHODS - A method of fabricating a device includes providing a fin extending from a substrate, where the fin includes an epitaxial layer stack having a plurality of semiconductor channel layers interposed by a plurality of dummy layers. In some embodiments, the method further includes removing a portion of the epitaxial layer stack within a source/drain region of the semiconductor device to form a trench in the source/drain region that exposes lateral surfaces of the plurality of semiconductor channel layers and the plurality of dummy layers. After forming the trench, in some examples, the method further includes performing a dummy layer recess process to laterally etch ends of the plurality of dummy layers to form first recesses along a sidewall of the trench. In some embodiments, the method further includes conformally forming a cap layer along the exposed lateral surfaces of the plurality of semiconductor channel layers and within the first recesses. | 2022-09-08 |
20220285534 | IGBT Device - Provided is an IGBT device. The IGBT device includes an MOSFET cell array, where each MOSFET cell includes a p-type body region located at the top of an n-type drift region, an n-type emitter region located in the p-type body region, and a gate dielectric layer, a gate electrode and an n-type floating gate which are located above the p-type body region. The gate electrode is located above the gate dielectric layer, the n-type floating gate is located above the gate dielectric layer, and the gate electrode acts on the n-type floating gate through capacitive coupling. The n-type floating gate of at least one MOSFET cell is isolated from the p-type body region through the gate dielectric layer, and the n-type floating gate of at least one MOSFET cell contacts the p-type body region through an opening in the gate dielectric layer to form a p-n junction diode. | 2022-09-08 |
20220285535 | IGBT POWER DEVICE - Provided is an insulated gate bipolar transistor power device. The IGBT power device includes a gate dielectric layer located above the two p-type body regions and the n-type drift region between the two p-type body regions, an n-type floating gate located above the gate dielectric layer; a gate located above the gate dielectric layer and the n-type floating gate; an insulating dielectric layer between the gate and the n-type floating gate; a first opening located in the gate dielectric layer, where the n-type floating gate is in contact with one of the two p-type body regions through the first opening to form a p-n junction diode; and a second opening located in the gate dielectric layer, where the n-type floating gate is in contact with the other of the two p-type body regions through the second opening to form the p-n junction diode. | 2022-09-08 |
20220285536 | IGBT DEVICE - Provided is an insulated gate bipolar transistor (IGBT) device. The IGBT device includes p-type body regions located on a top of an n-type drift region, a first n-type emitter region located within the p-type body region; a first gate structure located over the p-type body region, where the first gate structure includes a first gate dielectric layer, a first gate and an n-type floating gate which are located above the first gate dielectric layer, where the n-type floating gate is located on a side close to the n-type drift region in a lateral direction; an insulating dielectric layer located between the n-type floating gate and the first gate; and one opening in the first gate dielectric layer. The n-type floating gate is in contact with the p-type body region to form a p-n junction diode through the one opening. | 2022-09-08 |
20220285537 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate, a drift layer of a first conductivity type, a buffer layer of the first conductivity type, a first semiconductor layer, and a second semiconductor layer. The first semiconductor layer and the second semiconductor layer are provided on the side of the second main surface of the semiconductor substrate with respect to the buffer layer. The first semiconductor layer and the second semiconductor layer are arranged in this order in a direction from the second main surface toward the first main surface of the semiconductor substrate. The first semiconductor layer and the second semiconductor layer have conductivity types identical to each other. The second semiconductor layer has a larger number of atoms of impurities per unit volume than the first semiconductor layer. | 2022-09-08 |
20220285538 | NORMALLY-CLOSED DEVICE AND FABRICATION METHOD THEREOF - A normally-closed device and a fabrication method thereof, relating to the technical field of semiconductors, is disclosed. The normally-closed device comprises a substrate, an epitaxial layer connected to the substrate comprising a first P-type nitride layer and a modified layer located on two sides of the first P-type nitride layer and formed by modifying a second P-type nitride layer in a preset region, where the first P-type nitride layer and the second P-type nitride layer are formed by epitaxially growing synchronously, a barrier layer connected to the first P-type nitride layer and the modified layer, a gate electrode connected to the barrier layer, and a source electrode and a drain electrode connected to the modified layer. | 2022-09-08 |
20220285539 | Type III-V Semiconductor Device with Improved Leakage - A semiconductor device includes a semiconductor substrate including a barrier region, a channel layer disposed below the barrier region and forming a heterojunction with the barrier region such that a two-dimensional charge carrier gas channel is disposed in the channel layer near the heterojunction, and a sub-channel region disposed below the channel layer, and a first interface in the semiconductor substrate between a first region of type III-V material and a second region of type III-V material that is disposed below the first region of type III-V material, wherein the first and second regions of type III-V material form polarization charges on either side of the first interface, wherein the first interface is within or formed by the sub-channel region, and wherein semiconductor substrate has a vertically varying dopant concentration of deep energy acceptor dopant atoms that is locally increased at the first interface. | 2022-09-08 |
20220285540 | INTEGRATION OF P-CHANNEL AND N-CHANNEL E-FET III-V DEVICES WITHOUT PARASITIC CHANNELS - In some embodiments, the present disclosure relates to an integrated transistor device, including a first barrier layer arranged over a substrate. Further, an undoped layer may be arranged over the first barrier layer and have a n-channel device region laterally next to a p-channel device region. The n-channel device region of the undoped layer has a topmost surface that is above a topmost surface of the p-channel device region of the undoped layer. The integrated transistor device may further comprise a second barrier layer over the n-channel device region of the undoped layer. A first gate electrode is arranged over the second barrier layer, and a second gate electrode is arranged over the p-channel device region of the undoped layer. | 2022-09-08 |
20220285541 | NITRIDE SEMICONDUCTOR DEVICE - A nitride semiconductor device | 2022-09-08 |
20220285542 | VERTICAL FIELD-EFFECT TRANSISTOR AND METHOD FOR FORMING SAME - A vertical field effect transistor, including a drift region having a first conductivity type, a trench structure on or above the drift region, a shielding structure, and a source/drain electrode. The trench structure includes at least one side wall at which a field effect transistor (FET) channel region is formed. The FET channel region includes a III-V heterostructure for forming a two-dimensional electron gas at a boundary surface of the III-V heterostructure. The shielding structure is situated laterally adjacent to the at least one side wall of the trench structure and extends vertically into the drift region or vertically further in the direction of the drift region than the trench structure. The shielding structure has a second conductivity type that differs from the first conductivity type. The source/drain electrode is electroconductively connected to the III-V heterostructure of the trench structure and to the shielding structure. | 2022-09-08 |
20220285543 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEM - There is provided a semiconductor device comprising at least, a crystalline oxide semiconductor layer which has a band gap of 4.5 eV or more; and a field-effect mobility of 10 cm | 2022-09-08 |
20220285544 | SEMICONDUCTOR POWER DEVICE - Provided is a semiconductor power device. The device includes: at least one p-type body region located on the top of an n-type drift region, a first n-type source region and a second n-type source region located within the p-type body region, a first gate structure configured to control a first current channel between the first n-type source region and the n-type drift region to be turned on or off; and a second gate structure configured to control a second current channel between the second n-type source region and the n-type drift region to be turned on or off. The second gate structure is recessed in the n-type drift region. | 2022-09-08 |
20220285545 | Integrated Circuit Structure with Source/Drain Spacers - The device includes a semiconductor substrate and a stack of channel layers on the semiconductor substrate. A top surface of a topmost channel layer extends along a first height relative to the substrate surface. A bottom surface of a bottommost channel layer extends along a second height relative to the substrate surface. The device further includes a gate structure that engages with the stack of channel layers and extending along a first direction. Additionally, the device includes a source/drain feature on first sidewall surfaces of the stack of channel layers and on the substrate, where the first sidewall surfaces extends in parallel to the first direction. Moreover, the source/drain feature has a first width along the first direction at the first height and a second width along the first direction at the second height, and wherein the first width is greater than the second width. | 2022-09-08 |
20220285546 | FLOATING GATE BASED 3-TERMINAL ANALOG SYNAPSE DEVICE AND A MANUFACTURING METHOD THEREOF - Provided is a floating gate based 3-terminal analog synapse device including a silicon channel layer; a gate oxide deposited on the silicon channel layer; a charge trap layer deposited on the gate oxide, wherein charges are injected into the charge trap layer; a barrier layer deposited on the charge trap layer, and having lower electron affinity than electron affinity of a material of the charge trap layer; and a gate metal layer deposited on an upper surface of the barrier layer, wherein a gate voltage is applied to the gate metal layer. | 2022-09-08 |
20220285547 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device including: forming a conductor film for floating gates through a gate insulating film on a semiconductor substrate; etching the conductor film, the gate insulating film, and the semiconductor substrate so as to form an element isolation trench extending in one direction of the semiconductor substrate and having a width and depth that periodically change along an extension direction; and forming an element isolation insulating film by burying the element isolation trench with an insulator. | 2022-09-08 |
20220285548 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device includes a semiconductor part, first to third electrodes, and a control electrode. The first electrode is provided on a back surface of the semiconductor part. The second electrode is provided at a front surface side of the semiconductor part. The third electrode and the control electrode are provided inside a trench of the semiconductor part. The control electrode includes first and second control portions. The semiconductor device further includes first to third insulating films. The first insulating film is between the control electrode and the semiconductor part. The second insulating film covers the first and second control portions. The third insulating film is between the second electrode and the second insulating film. The third insulating film includes a portion extending between the first and second control portions. The third electrode is between the first electrode and the extension portion of the third insulating film. | 2022-09-08 |
20220285549 | SEMICONDUCTOR DEVICE COMPRISING MUTUALLY SEPARATED TRENCH STRUCTURES - A semiconductor device and method of manufacturing thereof is provided, including one or more mutually separated trench structures and semiconductor devices in which a first polysilicon body and a second polysilicon body are provided in the trenches, and the first and second polysilicon bodies can be individually biased. The method according to the present disclosure includes the step of performing a wet oxidation for oxidizing the first polysilicon body and the exposed upper surface of the sidewall for forming, within the active area, a first part of a second dielectric layer and subsequently performing a dry oxidation for forming a remaining part of the second dielectric layer. A second polysilicon body is arranged next within the active area on the second dielectric layer in the trench so that the second polysilicon body is separated from the sidewall of the trench and from the first polysilicon body by the second dielectric layer. | 2022-09-08 |
20220285550 | Semiconductor Device Having Contact Trenches Extending from Opposite Sides of a Semiconductor Body - A method of manufacturing a semiconductor body includes forming a pattern at a first side of a substrate, forming a semiconductor layer on the first side of the substrate, attaching the substrate and the semiconductor layer to a carrier via a surface of the semiconductor layer, and removing the substrate from a second side opposite to the first side. | 2022-09-08 |
20220285551 | GATE ELECTRODE EXTENDING INTO A SHALLOW TRENCH ISOLATION STRUCTURE IN HIGH VOLTAGE DEVICES - In some embodiments, the present disclosure relates to an integrated chip that includes a source region and a drain region arranged over and/or within a substrate. Further, a shallow trench isolation (STI) structure is arranged within the substrate and between the source and drain regions. A gate electrode is arranged over the substrate, over the STI structure, and between the source and drain regions. A portion of the gate electrode extends into the STI structure such that a bottommost surface of the portion of the gate electrode is arranged between a topmost surface of the STI structure and a bottommost surface of the STI structure. | 2022-09-08 |
20220285552 | Semiconductor Device and Method - In accordance with some embodiments, a method is provided. The method includes: forming a semiconductor fin protruding from a substrate; depositing a spacer layer over the semiconductor fin; after the depositing the spacer layer over the semiconductor fin, implanting a first dopant in the spacer layer and depositing a dopant layer of the first dopant on the spacer layer in alternating repeating steps; removing the dopant layer; and performing a thermal anneal process to drive the first dopant into the semiconductor fin from the spacer layer. | 2022-09-08 |
20220285553 | SEMICONDUCTOR DEVICE - A semiconductor device according to an embodiment includes first and second electrodes, a gate electrode, first to third semiconductor regions, and first and second insulating parts. The first semiconductor region is located on the first electrode. The second semiconductor region is located on the first semiconductor region. The third semiconductor region is located on the second semiconductor region. The first insulating part is arranged with the third semiconductor region, the second semiconductor region, and a portion of the first semiconductor region. The gate electrode is located in the first insulating part. The gate electrode faces the second semiconductor region. The second insulating part is located on the third semiconductor region. The second insulating part is not overlapping the gate electrode. The second insulating part has tensile stress. The second electrode is located on the second insulating part and electrically connected with the third semiconductor region. | 2022-09-08 |
20220285554 | MINIMIZATION OF SILICON GERMANIUM FACETS IN PLANAR METAL OXIDE SEMICONDUCTOR STRUCTURES - A method and apparatus for minimizing silicon germanium facets in planar metal oxide semiconductor structures is disclosed. For example, a device fabricated according to the method may include a semiconductor substrate, a plurality of gate stacks formed on the substrate, a plurality of source/drain regions formed from silicon germanium, and a shallow trench isolation region positioned between two source/drain regions of the plurality of source/drain regions. Each source/drain region of the plurality of source/drain regions is positioned adjacent to at least one gate stack of the plurality of gate stacks. Moreover, the shallow trench isolation region forms a trench in the substrate without intersecting the two source/drain regions. | 2022-09-08 |
20220285555 | SEMICONDUCTOR DEVICE AND DISPLAY DEVICE INCLUDING THE SAME - To improve field-effect mobility and reliability in a transistor including an oxide semiconductor film. A semiconductor device includes a transistor including an oxide semiconductor film. The transistor includes a region where the maximum value of field-effect mobility of the transistor at a gate voltage of higher than 0 V and lower than or equal to 10 V is larger than or equal to 40 and smaller than 150; a region where the threshold voltage is higher than or equal to minus 1 V and lower than or equal to 1 V; and a region where the S value is smaller than 0.3 V/decade. | 2022-09-08 |
20220285556 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - By using a conductive layer including Cu as a long lead wiring, increase in wiring resistance is suppressed. Further, the conductive layer including Cu is provided in such a manner that it does not overlap with the oxide semiconductor layer in which a channel region of a TFT is formed, and is surrounded by insulating layers including silicon nitride, whereby diffusion of Cu can be prevented; thus, a highly reliable semiconductor device can be manufactured. Specifically, a display device which is one embodiment of a semiconductor device can have high display quality and operate stably even when the size or definition thereof is increased. | 2022-09-08 |
20220285557 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEM - A semiconductor device including at least a crystalline oxide semiconductor layer, which has a band gap of 3 eV or more and a field-effect mobility of 30 cm | 2022-09-08 |
20220285558 | FLASH MEMORY DEVICE WITH THREE-DIMENSIONAL HALF FLASH STRUCTURE AND METHODS FOR FORMING THE SAME - A flash memory device and method of making the same are disclosed. The flash memory device is located on a substrate and includes a floating gate electrode, a tunnel dielectric layer located between the substrate and the floating gate electrode, a smaller length control gate electrode and a control gate dielectric layer located between the floating gate electrode and the smaller length control gate electrode. The length of a major axis of the smaller length control gate electrode is less than a length of a major axis of the floating gate electrode. | 2022-09-08 |
20220285559 | VERTICAL STORAGE DEVICE, METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC APPARATUS INCLUDING STORAGE DEVICE - A vertical storage device, a method of manufacturing the same, and an electronic apparatus including the storage device are provided. The storage device includes: a first source/drain layer located at a first height with respect to a substrate and a second source/drain layer located at a second height different from the first height; a channel layer connecting the first source/drain layer and the second source/drain layer; and a gate stack including a storage function layer, the storage function layer extending on a sidewall of the channel layer and extending in-plane from the sidewall of the channel layer onto a sidewall of the first source/drain layer and a sidewall of the second source/drain layer. | 2022-09-08 |
20220285560 | TRANSISTOR AND DISPLAY DEVICE - A transistor whose characteristic degradation due to stray light is small is provided. The transistor includes a first insulator, a second insulator over the first insulator, a metal oxide over the second insulator, a first and a second conductor over the metal oxide, a third insulator over the first insulator, the second insulator, the metal oxide, the first conductor, and the second conductor, a fourth insulator over the metal oxide, a fifth insulator over the fourth insulator, and a third conductor over the fifth insulator. The third insulator has an opening to overlap with a region between the first conductor and the second conductor. The fourth insulator, the fifth insulator, and the third conductor are positioned in the opening. The metal oxide has a bandgap greater than or equal to 3.3 eV. The transistor has V | 2022-09-08 |
20220285561 | Semiconductor Devices With Modified Source/Drain Feature And Methods Thereof - A method includes providing a semiconductor structure including a fin protruding from a substrate, where the fin includes first semiconductor layers and second semiconductor layers, recessing the fin to form a source/drain (S/D) recess, forming an S/D feature in the S/D recess, trimming the S/D feature, depositing a dielectric layer to cover the S/D feature, forming a contact hole in the dielectric layer to expose the S/D feature, and forming a metal contact in the contact hole. | 2022-09-08 |
20220285562 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - In a semiconductor device including a transistor including a gate electrode formed over a substrate, a gate insulating film covering the gate electrode, a multilayer film overlapping with the gate electrode with the gate insulating film provided therebetween, and a pair of electrodes in contact with the multilayer film, a first oxide insulating film covering the transistor, and a second oxide insulating film formed over the first oxide insulating film, the multilayer film includes an oxide semiconductor film and an oxide film containing In or Ga, the oxide semiconductor film has an amorphous structure or a microcrystalline structure, the first oxide insulating film is an oxide insulating film through which oxygen is permeated, and the second oxide insulating film is an oxide insulating film containing more oxygen than that in the stoichiometric composition. | 2022-09-08 |
20220285563 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes: a semiconductor layer of a first conductivity-type; a well region of a second conductivity-type provided at an upper part of the semiconductor layer; a base region of the second conductivity-type provided at an upper part of the well region; a carrier supply region of the first conductivity-type provided at an upper part of the base region; a drift region of the first conductivity-type provided separately from the base region; a carrier reception region of the first conductivity-type provided at an upper part of the drift region; a gate electrode provided on a top surface of the well region interposed between the base region and the drift region via a gate insulating film; and a punch-through prevention region of the second conductivity-type provided at the upper part of the well region and having an impurity concentration different from the impurity concentration of the base region. | 2022-09-08 |
20220285564 | Buried Zener Design - A method for manufacturing a Zener diode includes implanting an N-type Buried Layer (NBL) with an N-type dopant in a first epitaxial layer, wherein the NBL comprises an NBL opening excluding the N-type dopant. A P-type Buried Layer (PBL) having a peak PBL doping concentration below the NBL is implanted. A second epitaxial layer is grown over the NBL. A P-type region (Plink) is implanted to couple to the PBL above the NBL opening, and to couple the Plink to an Anode electrode. An N-type region (Nlink) is implanted to couple the NBL to a Cathode electrode. | 2022-09-08 |
20220285565 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The present disclosure discloses a semiconductor device and a method for preparing the same. The semiconductor device includes a substrate, a doped epitaxial layer located on one side of the substrate, a channel layer located on one side of the doped epitaxial layer away from the substrate, a potential barrier layer located on one side of the channel layer away from the doped epitaxial layer, and a first electrode and a second electrode located on one side of the potential barrier layer away from the channel layer, wherein the first electrode penetrates the potential barrier layer, the channel layer and part of the doped epitaxial layer, the first electrode forms a Schottky contact with the channel layer, and a resistance of the part of the doped epitaxial layer in contact with the first electrode is greater than a resistance of the channel layer. | 2022-09-08 |
20220285566 | SEMICONDUCTOR PACKAGE AND FORMING METHOD THEREOF - A semiconductor package is provided. The semiconductor package includes a heat dissipation substrate including a first conductive through-via embedded therein; a sensor die disposed on the heat dissipation substrate; an insulating encapsulant laterally encapsulating the sensor die; a second conductive through-via penetrating through the insulating encapsulant; and a first redistribution structure and a second redistribution structure disposed on opposite sides of the heat dissipation substrate. The second conductive through-via is in contact with the first conductive through-via. The sensor die is located between the second redistribution structure and the heat dissipation substrate. The second redistribution structure has a window allowing a sensing region of the sensor die receiving light. The first redistribution structure is electrically connected to the sensor die through the first conductive through-via, the second conductive through-via and the second redistribution structure. A method of forming the semiconductor package is also provided. | 2022-09-08 |
20220285567 | METHOD FOR THROUGH-HOLE PLATING - A method for plating by means of a through-hole on a semiconductor wafer at least comprising the steps: providing a semiconductor wafer having a top side and a bottom side, wherein the semiconductor wafer has a plurality of solar cell stacks and comprises a substrate on the bottom side, and each solar cell stack has at least two III-V subcells, disposed on the substrate, and at least one through-hole, extending from the top side to the bottom side of the semiconductor wafer, with a continuous side wall, wherein the through-hole has a first edge region on the top side and a second edge region on the bottom side; applying an insulating layer to part of the first edge region, the side wall, and to the second edge region by means of a first printing process; and applying an electrically conductive layer. | 2022-09-08 |
20220285568 | OPTOELECTRONIC DEVICE COMPRISING PEROVSKITES - The invention provides an optoelectronic device comprising a porous material, which porous material comprises a semiconductor comprising a perovskite. The porous material may comprise a porous perovskite. Thus, the porous material may be a perovskite material which is itself porous. Additionally or alternatively, the porous material may comprise a porous dielectric scaffold material, such as alumina, and a coating disposed on a surface thereof, which coating comprises the semiconductor comprising the perovskite. Thus, in some embodiments the porosity arises from the dielectric scaffold rather than from the perovskite itself. The porous material is usually infiltrated by a charge transporting material such as a hole conductor, a liquid electrolyte, or an electron conductor. The invention further provides the use of the porous material as a semiconductor in an optoelectronic device. Further provided is the use of the porous material as a photosensitizing, semiconducting material in an optoelectronic device. The invention additionally provides the use of a layer comprising the porous material as a photoactive layer in an optoelectronic device. Further provided is a photoactive layer for an optoelectronic device, which photoactive layer comprises the porous material. | 2022-09-08 |
20220285569 | THIN FILM STACKS FOR GROUP V DOPING, PHOTOVOLTAIC DEVICES INCLUDING THE SAME, AND METHODS FOR FORMING PHOTOVOLTAIC DEVICES WITH THIN FILM STACKS - According to the embodiments provided herein, a method for forming a photovoltaic device can include depositing a plurality of semiconductor layers. The plurality of semiconductor layers can include a doped layer that is doped with a group V dopant. The doped layer can include cadmium selenide or cadmium telluride. The method can include annealing the plurality of semiconductor layers to form an absorber layer. | 2022-09-08 |
20220285570 | LASER BEAM SHAPING FOR FOIL-BASED METALLIZATION OF SOLAR CELLS - Approaches for foil-based metallization of solar cells and the resulting solar cells are described. For example, a method of fabricating a solar cell involves locating a metal foil above a plurality of alternating N-type and P-type semiconductor regions disposed in or above a substrate. The method also involves laser welding the metal foil to the alternating N-type and P-type semiconductor regions. The method also involves patterning the metal foil by laser ablating through at least a portion of the metal foil at regions in alignment with locations between the alternating N-type and P-type semiconductor regions. The laser welding and the patterning are performed at the same time. | 2022-09-08 |
20220285571 | NANO-ENGINEERED THIN-FILM THERMOELECTRIC CONVERTER FOR PHOTOVOLTAIC APPLICATIONS - Systems, apparatuses, and methods are provided for manufacturing nano-engineered thin-film thermoelectric (NETT) devices for photovoltaic applications, such as NETT converters that harness the coldness of space for satellite applications or for integration with terrestrial PV. An example method can include mounting a thin-film thermoelectric device to a photovoltaic device. The example method can further include mounting a heat sink device to the thin-film thermoelectric device. The example method can further include mounting a radiator device or heat exchanger device to the heat sink device. | 2022-09-08 |
20220285572 | SEMICONDUCTOR CHIP PACKAGE AND METHOD OF FORMING - A solar cell string and a photovoltaic module are provided. The solar cell string includes a first adhesive layer including N placement regions sequentially arranged along a first direction, N solar cells, first wires, and a second adhesive layer. Each of the N solar cells is disposed on a corresponding placement region of the N placement regions. The first wires stretch across adjacent placement regions to electrically connect adjacent solar cells. The second adhesive layer is disposed on the surface of the at least one of the N solar cells away from the first adhesive layer, the first wires are located between the second adhesive layer and the at least one of the N solar cells, and the first adhesive layer, the first wires, the N solar cells, and the second adhesive layer are bonded and fixed. | 2022-09-08 |
20220285573 | PHOTOVOLTAIC MODULE - Described herein is a photovoltaic module, which includes PV cells capable of converting light incoming from the front side and from the rear side, the module including a front side exposing an upper external surface designed for receiving direct sunlight and a rear side exposing a lower external surface designed for receiving diffuse light, where the lower external surface is formed, at least in part, by a microstructured layer, characterized in that the microstructured layer includes pyramidal microstructures whose triangular bases are fixed in the layer. The microstructured layer results in anisotropic transmission properties. The module shows improved efficiency compared to similar bifacial PV modules. | 2022-09-08 |
20220285574 | METHODS, SYSTEMS, AND APPARATUSES FOR PRODUCING, GENERATING AND UTILIZING POWER AND ENERGY - Methods, systems, and apparatuses for generating, producing, and utilizing energy. | 2022-09-08 |
20220285575 | SEMICONDUCTOR DEVICE - An optical detection portion includes a substrate of a first conductivity type, a semiconductor layer of the first conductivity type provided on the substrate, a first conductivity-type layer provided in the semiconductor layer, and a second conductivity-type layer provided on the first conductivity-type layer. The circuit portion includes a first well of a second conductivity type provided in the semiconductor layer, a second well of the first conductivity type provided in the first well, a first drain layer provided in the second well, a first source layer provided in the second well, a second drain layer provided in the first well, and a second source layer. | 2022-09-08 |
20220285576 | SEMICONDUCTOR DEVICE - A semiconductor device is provided, which includes an active structure and a first semiconductor layer. The active structure includes an active region having a topmost surface and a bottommost surface, and a first dopant distributing from the topmost surface to the bottommost surface. The first semiconductor layer is located under the active structure and includes a second dopant. The active region includes a semiconductor material including As. | 2022-09-08 |
20220285577 | Methods for Die-to-Wafer Device Layer Transfer with Precise Control of Device Layer Vertical Position - Methods and structures are described to facilitate the transfer of device layer coupons with controlled vertical position. In an embodiment, a plurality of device layer coupons is bonded to a receiving substrate with an adhesive layer, where distance between front surfaces of the plurality of device layer coupons and a bulk layer of the receiving substrate is controlled by a plurality of rigid mechanical spacers. | 2022-09-08 |
20220285578 | LIGHT-EMITTING DIODE AND DISPLAY DEVICE INCLUDING THE SAME - Provided is a light-emitting diode including a first-light emitting cell, a second light-emitting cell, and a third light-emitting cell that are sequentially provided in one direction and configured to emit light of different colors from each other, a first tunnel junction provided between the first light-emitting cell and the second light-emitting cell, the first tunnel junction being configured to electrically connect the first light-emitting cell and the second light-emitting cell and induce lateral current spreading, and a second tunnel junction provided between the second light-emitting cell and the third light-emitting cell, the second tunnel junction being configured to electrically connect the second light-emitting cell and the third light-emitting cell and induce lateral current spreading. | 2022-09-08 |
20220285579 | SINGLE CHIP MULTI BAND LIGHT EMITTING DIODE AND METHOD OF FABRICATING THE SAME - A light emitting diode according to an exemplary embodiment of the present disclosure includes an n-type nitride semiconductor layer, a V-pit generation layer, a sub-emission layer, an active layer, and a p-type nitride semiconductor layer. The sub-emission layer is disposed on the n-type nitride semiconductor layer and having V-pits. The active layer is disposed on the sub-emission layer and having a first well region formed along a flat surface of the V-pit generation layer and a second well region formed in the V-pit of the V-pit generation layer. The p-type nitride semiconductor layer is disposed on the active layer. An energy band gap of the sub-emission layer is wider than that of the first well region of the active layer. The light emitting diode emits light having at least three different peak wavelengths at a single chip level. | 2022-09-08 |
20220285580 | Semiconductor Light-Emitting Device - The semiconductor light-emitting device includes an n-type semiconductor layer, a plurality of columnar semiconductors on the n-type semiconductor layer, a buried layer filling in a space between the columnar semiconductors, and a current suppression region suppressing a current. The columnar semiconductors has a hexagonal column and an active layer covering the hexagonal column. The hexagonal column has a hexagonal first surface and a second surface opposite to the first surface. The first surface of the columnar semiconductors faces the base layer. The second surface of the columnar semiconductors faces the current suppression region. | 2022-09-08 |
20220285581 | DISPLAY DEVICE INCLUDING REFLECTIVE STRUCTURE - Provided is a display device including a driving substrate, a barrier layer disposed on an upper surface of the driving substrate and including a plurality of recesses, a micro-semiconductor light emitting device disposed in each of the plurality of recesses, and a side reflective structure disposed in the barrier layer and provided adjacent to a sidewall of each of the plurality of recesses. | 2022-09-08 |
20220285582 | LIGHT EMITTING ELEMENT, MANUFACTURING METHOD OF LIGHT EMITTING ELEMENT, AND DISPLAY DEVICE INCLUDING LIGHT EMITTING ELEMENT - A light emitting element includes: a first semiconductor layer including a semiconductor of a first type; a second semiconductor layer including a semiconductor of a second type different from the first type; and an active layer between the first and second semiconductor layers, the active layer including a first active area including a first well layer, and a second active area including a second well layer. The first well layer has a first band gap, and the second well layer has a second band gap smaller than the first band gap. At least a portion of the first active area is between the second active area and the second semiconductor layer. A distance between the second active area and the second semiconductor layer is equal to or greater than 0.1 times of a distance between the first and second semiconductor layers. | 2022-09-08 |
20220285583 | LIGHT-EMITTING DEVICE AND PRODUCTION METHOD THEREOF - A light-emitting device includes a light-emitting laminating structure having an ohmic contact layer, a transition layer, a current-spreading layer, a first type semiconductor layer, an active layer, and a second type semiconductor layer. The current-spreading layer has aluminum, and, in the current-spreading layer, a relative content of the aluminum with respect to a composition of the current-spreading layer is fixed. The transition layer has aluminum, and, in the transition layer, a relative content of the aluminum with respect to a composition of the transition layer is less than the relative content of the aluminum in the current-spreading layer. A method for producing the light-emitting device is also disclosed. | 2022-09-08 |
20220285584 | INDIUM-GALLIUM-NITRIDE LIGHT EMITTING DIODES WITH LIGHT REFLECTING MIRRORS - Exemplary processing methods of forming a semiconductor structure may include forming subpixels on a substrate. Each of the subpixels may include a gallium-and-nitrogen-containing layer formed on an exposed portion of a nucleation layer on the substrate. The subpixels may further include a porosified region formed on or in the gallium-and-nitrogen-containing region, and an active region formed on the porosified region. The active region may include an indium-gallium-and-nitrogen-containing material. The processing methods may further include forming a first reflection layer around one of the subpixels, wherein the first reflection layer includes a first metal layer. The methods may additionally include forming a second reflection layer around another of the subpixels, wherein the second reflection layer includes a second metal that is different than the first metal. | 2022-09-08 |
20220285585 | SEMICONDUCTOR STRUCTURES AND MANUFACTURING METHODS THEREOF - The present disclosure provides a semiconductor structure and a manufacturing method thereof. In the manufacturing method, a P-type semiconductor layer is provided, where the P-type semiconductor layer includes a GaN-based material and an upper surface of the P-type semiconductor layer is a Ga surface. A first N-type semiconductor layer is formed on the P-type semiconductor layer, where the first N-type semiconductor layer comprises a GaN-based material. An upper surface of the first N-type semiconductor layer is an N surface. A part of the first N-type semiconductor layer is removed by wet etching to expose a part of the P-type semiconductor layer. | 2022-09-08 |
20220285586 | DISPLAY DEVICE AND METHOD FOR MANUFACTURING SAME - A display device may include: a base layer including a plurality of islands, at least one first bridge configured to connect the islands in a first direction, and at least one second bridge configured to connect the islands in a second direction; and at least one pixel including a plurality of sub-pixels in the base layer. Each of the sub-pixels may include: a first electrode and a second electrode in one island of the islands and spaced from each other; a third electrode and a fourth electrode in one bridge of the at least one first bridge and the at least one second bridge and spaced from each other; at least one first light emitting element between the first electrode and the second electrode; and at least one second light emitting element between the third electrode and the fourth electrode. | 2022-09-08 |
20220285587 | LIGHT EMITTING DEVICE - A light emitting device including a cell area, a peripheral area surrounding the cell area, a light source disposed in the cell area and including at least one light emitting layer, a first light shielding layer disposed in the cell area and the peripheral area, a portion of the first light shielding layer overlapping with the light source, and a rough structure disposed in the cell area and overlapping with the light source. | 2022-09-08 |
20220285588 | MULTI-SPECTRAL STEALTH DEVICE - Disclosed is a multi-spectral stealth device that generates a camouflage color in a visible ray region, has low reflectivity in near-infrared ray and short-wavelength infrared-ray regions, and has low emissivity in mid-wavelength and long-wavelength infrared-ray regions. The multi-spectral stealth device includes a metal layer made of a first metal having electrical conductivity; a semiconductor layer disposed on a top surface of the metal layer and made of a semiconductor material having a bandgap in which the semiconductor material is capable of absorbing a visible ray and a near-infrared ray; and a plurality of metal patterns regularly arranged on a top surface of the semiconductor layer and made of a second metal having electrical conductivity. | 2022-09-08 |
20220285589 | METHOD FOR PRODUCING SEMICONDUCTOR NANOPARTICLES AND LIGHT-EMITTING DEVICE - Provided is a method for producing semiconductor nanoparticles. The method includes: providing first semiconductor nanoparticles containing a semiconductor containing an element M1, an element M2 and an element Z, wherein the element M1 is at least one element selected from the group consisting of Ag, Cu, Au and an alkali metal, and contains at least Ag, the element M2 is at least one element selected from the group consisting of Al, Ga, In and Tl, and contains at least one of In and Ga, and the element Z contains at least one element selected from the group consisting of S, Se and Te; and heat-treating a mixture containing the first semiconductor nanoparticles, a first compound having a Ga—S bond, a second compound containing Ga and not containing S, and an organic solvent to obtain second semiconductor nanoparticles. | 2022-09-08 |
20220285590 | COLOR CONVERTER LAYER AND MANUFACTURING METHOD THEREOF - A color converter layer is provided. The color converter layer includes a first light blocking member in which a plurality of pixel regions comprising a first pixel region and a second pixel region are disposed to be spaced apart from each other, a first color converter disposed in the first pixel region for converting and emitting incident light into a first color, a second color converter disposed in the second pixel region for converting and emitting the incident light into a second color different from the first color, and a second light blocking member that extends with a preset thickness and is formed on a surface of the first light blocking member, and blocks transmission of the incident light into an adjacent pixel region by partitioning the first pixel region and the second pixel region. The preset thickness may be greater than the thickness of the first light blocking member. | 2022-09-08 |
20220285591 | -LED, -LED DEVICE, DISPLAY AND METHOD FOR THE SAME - The invention relates to various aspects of a μ-LED or a μ-LED array for augmented reality or lighting applications, in particular in the automotive field. The μ-LED is characterized by particularly small dimensions in the range of a few μm. | 2022-09-08 |
20220285592 | -LED, -LED DEVICE, DISPLAY AND METHOD FOR THE SAME - The invention relates to various aspects of a μ-LED or a μ-LED array for augmented reality or lighting applications, in particular in the automotive field. The μ-LED is characterized by particularly small dimensions in the range of a few μm. | 2022-09-08 |
20220285593 | Micro LED Display Element - The present invention provides a flip-chip mounted monolithic micro LED having improved contrast. The light-emitting device includes a substrate, an n-type layer, a light-emitting layer, a p-type layer, a transparent electrode, a p-electrode, an n-electrode, a protective film, an absorbing structure, and a side wall insulating film. The absorbing structure is a layered body in which a dielectric film and a metal film are alternately deposited, and the top layer is a dielectric film. Reflected light of light emitted from the light-emitting layer or reflected light of light from the outside, or transmitted light from the backside of the substrate can be absorbed by the absorbing structure, thereby improving contrast. | 2022-09-08 |
20220285594 | LIGHT EMITTING DIODES WITH REFLECTIVE SIDEWALLS COMPRISING POROUS PARTICLES - Sidewall reflectors disposed on the sidewalls of an LED or pcLED comprise porous (for example, hollow) high refractive index light scattering particles dispersed in a transparent binder. The porous particles exhibit a high refractive index contrast and corresponding strong scattering at the interfaces between the porous particle material and one or more pores in each particle. These sidewall reflectors can provide light confinement with thin reflector structures, allowing close spacing between LEDs and pcLEDs, and may be advantageously employed in microLED arrays. | 2022-09-08 |
20220285595 | DISPLAY APPARATUS - A display apparatus includes a display area including pixels on a substrate, a pad portion on the substrate in a non-display area outside the display area, and including a conductive line, a first dummy line around the conductive line, and a first anti-fuse and a second anti-fuse adjacent to the conductive line and spaced apart from each other in a lengthwise direction of the conductive line, the first anti-fuse and the second anti-fuse each including a first electrode electrically connected to a portion of the conductive line, and a second electrode over the first electrode with a first insulating layer therebetween, and electrically connected to a portion of the first dummy line, and a circuit portion overlapping, and electrically connected to, the pad portion. | 2022-09-08 |
20220285596 | LIGHT-EMITTING DEVICE - A light-emitting device includes a carrier substrate, a flip-chip light-emitting diode (LED) mounted onto the carrier substrate, and an electrode unit disposed between the carrier substrate and the flip-chip LED. The electrode unit includes first and second connecting electrodes that have opposite conductivity. Each of the first and second connecting electrodes includes an intermediate metal layer and a binding layer that are sequentially disposed on the flip-chip LED in such order. The binding layer includes a first portion being adjacent to the carrier substrate and forming an eutectic system with tin, and a second portion located between the first portion and the intermediate metal layer. | 2022-09-08 |
20220285597 | Display Device - A display device is disclosed. The display device includes a substrate and a LED device. The substrate includes a translucent body and a conductive wire layer. The translucent body has a translucent body first surface. The conductive wire layer is disposed on the translucent body first surface. The LED device includes a base and a LED chip. The base is disposed on the other side of the conductive wire layer with respect to the translucent body and is coupled with the conductive wire layer. The base has a base first surface facing the translucent body first surface. The LED chip is disposed on the base first surface. | 2022-09-08 |
20220285598 | DISPLAY DEVICE, AND METHOD FOR FABRICATING DISPLAY DEVICE - A display device and a method for fabricating a display device are provided. The display device includes a display panel, a printed circuit film, and an adhesive member interposed between the display panel and the printed circuit film, wherein the display panel comprises an insulating layer and a plurality of grooves overlapping with the adhesive member in a thickness direction of the display device and disposed on a surface of the insulating layer, and wherein the plurality of grooves is filled with the adhesive member. | 2022-09-08 |
20220285599 | CIRCUIT BOARD HAVING MULTIPLE SOLDER RESISTS AND DISPLAYING APPARATUS HAVING THE SAME - A circuit board includes a base having a plurality of interconnections on an upper surface thereof, a first photosensitive solder resist (PSR) covering the interconnections and defining a pad open region exposing portions of the interconnections, a second PSR covering the first PSR and having an opening exposing the pad open region. The opening of the second PSR is larger than the pad open region of the first PSR. | 2022-09-08 |
20220285600 | MICRO LIGHT EMITTING DEVICE DISPLAY APPARATUS - A micro light emitting device display apparatus including a substrate, a plurality of micro light emitting devices, an isolation layer, and at least one first air gap is provided. The substrate has a plurality of connection pads. The micro light emitting devices are discretely disposed on the substrate. The isolation layer is disposed between the substrate and each of the micro light emitting devices. The at least one first air gap is disposed between the substrate and a surface of the isolation layer facing the substrate. | 2022-09-08 |