36th week of 2022 patent applcation highlights part 57 |
Patent application number | Title | Published |
20220285301 | SEMICONDUCTOR MODULE AND METHOD OF MANUFACTURING SEMICONDUCTOR MODULE - A semiconductor module includes: a semiconductor device; a bonding layer that is arranged on the semiconductor device, contains nickel or copper, and is electrically connected to the semiconductor device; a solder portion containing gold, disposed on the bonding layer; and a protective layer disposed directly on the bonding layer, covering an outer peripheral edge of the bonding layer. | 2022-09-08 |
20220285302 | SEMICONDUCTOR DEVICE AND DATA STORAGE SYSTEM INCLUDING THE SAME - A semiconductor device includes a first semiconductor structure including a first substrate, circuit devices on the first substrate, a lower interconnection structure on the circuit devices, and a lower bonding structure electrically connected to the lower interconnection structure, and a second semiconductor structure including a second substrate disposed on the first semiconductor structure, gate electrodes stacked and spaced apart from each other in a first direction perpendicular to a lower surface of the second substrate, channel structures that penetrate the gate electrodes and extend in the first direction, and an upper bonding structure electrically connected to the gate electrodes and the channel structures and bonded to the lower bonding structure. The second semiconductor structure further includes a first via connected to an upper portion of the second substrate, a second via spaced apart from the first via and the second substrate, and a contact plug. | 2022-09-08 |
20220285303 | CONTACT STRUCTURES FOR DIRECT BONDING - A bonded structure is disclosed. The bonded structure can include a first element that includes a first conductive feature and a first nonconductive region. The first conductive feature can include a fine grain metal that has an average grain size of 500 nm or less. The bonded structure can include a second element that includes a second conductive feature and a second nonconductive region. The first conductive feature is directly bonded to the second conductive feature without an intervening adhesive, and the second nonconductive region is directly bonded to the second nonconductive region without an intervening adhesive. | 2022-09-08 |
20220285304 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - Provided is a semiconductor package including: a pad substrate on which a semiconductor chip is installed; a solder formed on the pad substrate having a length same as or longer than a side of the semiconductor chip; and an intagliated groove formed on the pad substrate having a length longer than at least the side of the semiconductor chip and filled with at least a certain amount of melted solder, wherein the solder having a thickness of at least 1 μm or above is filled in the intagliated groove to have a length of at least 3 μm or above and an intermetallic compound layer is formed on a certain area included in an inner wall of the intagliated groove. Accordingly, movement of the semiconductor chip may be restricted so that the quality of following processes may be improved, and electrical and mechanical combination between the solder and the pad substrate may be stabled. | 2022-09-08 |
20220285305 | SEMICONDUCTOR DEVICE WITH A SEMICONDUCTOR CHIP CONNECTED IN A FLIP CHIP MANNER - A semiconductor device includes a wiring board, a semiconductor chip, and a connecting member provided between a surface of the wiring board and a functional surface of the semiconductor chip. The connecting member extends a distance between the wiring board surface and the functional surface. A sealing material seals a gap space between the wiring board and the semiconductor chip. An electrode is formed at the wiring board surface and arranged outside of an outer periphery of the sealing material. A lateral distance between an outer periphery of the semiconductor chip and the outer periphery of the sealing material is between 0.1 mm and a lateral distance from the outer periphery of the semiconductor chip to the electrode. | 2022-09-08 |
20220285306 | ROUNDED METAL TRACE CORNER FOR STRESS REDUCTION - An integrated circuit package is disclosed. The integrated circuit package comprises a first integrated circuit die and a second integrated circuit die. The integrated circuit package further includes a substrate, wherein both the first integrated circuit die and the second integrated circuit die are connected to the substrate. The substrate includes an interconnect bridge embedded within the substrate, wherein the interconnect bridge includes at least one metal trace component, wherein the metal trace component includes rounded corners on a bottom portion of the metal trace component. | 2022-09-08 |
20220285307 | Semiconductor Device, Semiconductor Arrangement and Method for Producing the Same - A semiconductor device includes a semiconductor wafer or a single semiconductor chip or die, and a layer stack. The layer stack comprises a first layer comprising NiSi, and a second layer comprising NiV, wherein the second layer is arranged between the first layer and the semiconductor wafer or single semiconductor chip or die. | 2022-09-08 |
20220285308 | RADAR DEVICE - A radar device includes: a substrate including multiple high-frequency conductor layers arranged on a front surface; a semiconductor component in contact with the high-frequency conductor layers via conductive members; and an adhesive that bonds the semiconductor component to the front surface of the substrate. The semiconductor component has a bottom surface and a first side surface facing in a first direction. All the multiple high-frequency conductor layers include at least high-frequency conductor layers bending in a plane of the front surface and thereby extend, on the front surface, from inside ends facing the bottom surface to outside ends positioned in the first direction from the first side surface. The adhesive is in contact with the front surface except for the sites of the multiple high-frequency conductor layers formed and in contact with the side surfaces of the semiconductor component. | 2022-09-08 |
20220285309 | VARIABLE STIFFNESS MODULES - A variable-stiffness module comprises a rigid structure ( | 2022-09-08 |
20220285310 | Bonding with Pre-Deoxide Process and Apparatus for Performing the Same - A method includes picking up a first package component, removing an oxide layer on an electrical connector of the first package component, placing the first package component on a second package component after the oxide layer is removed, and bonding the first package component to the second package component. | 2022-09-08 |
20220285311 | Installing an Electronic Assembly - Various embodiments include a method for installing an electronic assembly having a die and a substrate with a reference plane. The method may include: providing a product carrier having recesses with varying dimensions different from one another; and arranging planar molded parts, joining materials, and the die on the product carrier. The die is in electrical contact with at least one planar molded part and at least one joining material. The method further includes forming functional elements from the planar molded parts and/or the die and the joining materials, the functional elements supporting the substrate and electrically contacting the reference plane. | 2022-09-08 |
20220285312 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a base chip and at least one semiconductor chip disposed on the base chip. An adhesive film is disposed between the base chip and the at least one semiconductor chip and is configured to fix the at least one semiconductor chip on the base chip. The adhesive film includes an inner film portion that overlaps the at least one semiconductor chip in a thickness direction of the base chip, and an outer film portion that does not overlap the at least one semiconductor chip in the thickness direction of the base chip. A width of the outer film portion in a direction perpendicular to a lateral edge of the at least one semiconductor chip is substantially uniform within a deviation range of 20% of an average width of the outer film portion. | 2022-09-08 |
20220285313 | METHOD FOR MANUFACTURING A SEMICONDUCTOR PACKAGE - A method for manufacturing a semiconductor package includes: (a) providing a substrate structure, wherein the substrate structure includes a chip attach area, a bottom area opposite to the chip attach area, a lower side rail surrounding the bottom area, a first lower structure and a second lower structure, wherein the first lower structure is disposed in a first lower region of the lower side rail, and a second lower occupancy ratio is greater than a first lower occupancy ratio; (b) attaching at least one semiconductor chip to the chip attach area; and (c) forming an encapsulant to cover the at least one semiconductor chip. | 2022-09-08 |
20220285314 | SEMICONDUCTOR APPARATUS AND FABRICATION METHOD THEREOF - A semiconductor apparatus includes a channel layer, a barrier layer, a source contact and a drain contact, a first doped group III-V semiconductor, a group III-V semiconductor, and a second doped group III-V semiconductor. The barrier layer is disposed on the channel layer. The source contact and the drain contact are disposed on the channel layer. The first doped group III-V semiconductor is disposed on the barrier layer. The group III-V semiconductor is disposed on the first doped group III-V semiconductor and between the source contact and the drain contact. The second doped group III-V semiconductor is disposed on the group III-V semiconductor and between the source contact and the drain contact. The group III-V semiconductor has a central region covered by the second doped group III-V semiconductor and a peripheral region free from coverage by the second doped group III-V semiconductor. | 2022-09-08 |
20220285315 | STACKED SEMICONDUCTOR DIES FOR SEMICONDUCTOR DEVICE ASSEMBLIES - Stacked semiconductor dies for semiconductor device assemblies and associated methods and systems are disclosed. In some embodiments, the semiconductor die assembly includes a substrate with an opening extending therethrough. The assembly can include a stack of semiconductor dies attached to the substrate. The stack includes a first die attached to a front surface of the substrate, where the first die includes a first bond pad aligned with the opening. The stack also includes a second die attached to the first die such that an edge of the second die extends past a corresponding edge of the first die. The second die includes a second bond pad uncovered by the first die and aligned with the opening. A bond wire formed through the opening couples the first and second bond pads with a substrate bond pad on a back surface of the substrate. | 2022-09-08 |
20220285316 | PACKAGED MEMORY DEVICE WITH FLIP CHIP AND WIRE BOND DIES - A memory device includes a substrate, a controller die, a flip chip die, first and second silicon dies, and bond wires. The controller and flip chip dies are attached to the substrate using connection balls and in electrical communication with each other. The first and second silicon dies include respective first and second contact pad surfaces. The bond wires electrically connect the contact pad surfaces to the substrate so the first and second silicon dies communicate with the controller die. The flip chip die and first and second silicon dies are NAND dies, the flip chip die is configured as SLC memory, and the silicon dies are configured as one of MLC memory, TLC memory, or QLC memory. | 2022-09-08 |
20220285317 | PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME - A package structure and method of forming the same are provided. The package structure includes a semiconductor unit, a package component and an underfill layer. The semiconductor structure unit includes a first semiconductor structure and a second semiconductor structure disposed as side by side, and an isolation region laterally between the first semiconductor structure and the second semiconductor structure. The isolation region vertically extends from a top surface to a bottom surface of the semiconductor structure unit. The semiconductor structure unit is disposed on and electrically connected to the package component. The underfill layer is disposed to fill a space between the semiconductor structure unit and the package component. | 2022-09-08 |
20220285318 | SEMICONDUCTOR PACKAGES AND METHODS FOR FORMING THE SAME - Embodiments of the present disclosure provide an integrated circuit die having edge interconnect features. The edge interconnect features may be conductive lines extending through sealing rings and exposed on edge surfaces of the integrated circuit die. The edge interconnect features are configured to connect with other integrated circuit dies without going through an interposer. The semiconductor device may include two or more integrated circuit dies with edge interconnect features and connected through one or more inter-chip connectors formed between the two or more integrated circuit dies. In some embodiments, the inter-chip connectors may be formed by a selective bumping process during packaging. | 2022-09-08 |
20220285319 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first stacked body including first semiconductor chips stacked in a first direction and offset relative to each other in a second direction; a first columnar electrode coupled to the first semiconductor chip and extending in the first direction; a second stacked body arranged relative to the first stacked body in the second direction and including second semiconductor chips stacked in the first direction and offset relative to each other in the second direction; a second columnar electrode coupled to the second semiconductor chip and extending in the first direction; and a third semiconductor chip arranged substantially equally spaced to the first columnar electrode and the second columnar electrode. | 2022-09-08 |
20220285320 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a first stacked body including a plurality of first semiconductor chips stacked along a first direction, each of the first semiconductor chips being offset from the other first semiconductor chips along a second direction perpendicular to the first direction; a first columnar electrode connected to an electrode pad of the first stacked body, and extending in the first direction; a second stacked body including a plurality of second semiconductor chips stacked along the first direction, each of the second semiconductor chips being offset from the other second semiconductor chips along the second direction, the second stacked body having a height larger than the first stacked body and overlap at least a portion of the first stacked body when viewed from the top; and a second columnar electrode connected to an electrode pad of the second stacked body, and extending in the first direction. | 2022-09-08 |
20220285321 | SEMICONDUCTOR PACKAGE INCLUDING A FILLET LAYER - A semiconductor package includes a base substrate having a first semiconductor substrate, and a first protective layer covering a top side thereof. A first semiconductor chip is on the first protective layer. A first fillet layer fills a space between the first protective layer and the first semiconductor chip. A first side surface of the base substrate extends in a first direction, and second and third side surfaces extend in a second direction. The base substrate includes two corner regions and a side region between the corner regions. A first protective layer in the side region includes a first side trench which overlaps the first semiconductor chip. A part of the first fillet layer fills the first side trench. | 2022-09-08 |
20220285322 | A 3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH METAL LAYERS - A semiconductor device including: a silicon layer including a single crystal silicon and a plurality of first transistors; a first metal layer disposed over the silicon layer; a second metal layer disposed over the first metal layer; a third metal layer disposed over the second metal layer, a second level including a plurality of second transistors, the first level disposed over the third metal layer; a fourth metal layer disposed over the second level; a fifth metal layer disposed over the fourth metal layer, the fourth metal layer is aligned to the first metal layer with a less than 40 nm alignment error; and a via disposed through the second level, the second level thickness is less than two microns, the fifth metal layer includes a global power distribution grid, where a fifth metal layer typical thickness is greater than a second metal layer typical thickness by at least 50%. | 2022-09-08 |
20220285323 | Semiconductor Packages and Methods of Forming Same - In an embodiment, a package includes a first package structure including a first die having a first active side and a first back-side, the first active side including a first bond pad and a first insulating layer a second die bonded to the first die, the second die having a second active side and a second back-side, the second active side including a second bond pad and a second insulating layer, the second active side of the second die facing the first active side of the first die, the second insulating layer being bonded to the first insulating layer through dielectric-to-dielectric bonds, and a conductive bonding material bonded to the first bond pad and the second bond pad, the conductive bonding material having a reflow temperature lower than reflow temperatures of the first and second bond pads. | 2022-09-08 |
20220285324 | MANUFACTURING METHOD OF THREE-DIMENSIONAL STACKING STRUCTURE - A stacking structure including a first die, a second die stacked on the first die, and a filling material is provided. The first die has a first bonding structure, and the first bonding structure includes first bonding pads and a first heat dissipating element. The second die has a second bonding structure, and the second bonding structure includes second bonding pads and a second heat dissipating element. The first bonding pads are bonded with the second bonding pads. The first heat dissipating element is connected to one first bonding pad of the first bonding pads and the second heat dissipating element is connected to one second bonding pad of the second bonding pads. The filling material is disposed over the first die and laterally around the second die. The first and second dies are bonded through the first and second bonding structures. | 2022-09-08 |
20220285325 | PACKAGED INTEGRATED CIRCUIT DEVICES WITH THROUGH-BODY CONDUCTIVE VIAS, AND METHODS OF MAKING SAME - A device is disclosed which includes at least one integrated circuit die, at least a portion of which is positioned in a body of encapsulant material, and at least one conductive via extending through the body of encapsulant material. | 2022-09-08 |
20220285326 | MICRO LED PANEL AND METHOD FOR MANUFACTURING THE SAME - Provided is a method of manufacturing a micro LED panel, the method including preparing a backplane; forming a plurality of micro LED cells in a matrix shape on a bottom portion of a growth substrate; bonding the micro LED cells to the backplane; separating the growth substrate from the micro LED cells; and disposing a partitioning wall structure on top portions of the micro LED cells, wherein the partitioning wall structure includes a light-transmitting member having a first surface facing light-emitting surfaces of the micro LED cells and a second surface facing the first surface, the light-transmitting member includes a plurality of first grooves formed to correspond in between the plurality of micro LED cells on any one of the first surface and the second surface, and the plurality of first grooves are filled with a partitioning wall composition to form partitioning walls. | 2022-09-08 |
20220285327 | DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A light emitting apparatus including a substrate, a plurality of light emitting diode devices disposed on the substrate, a light non-transmitting layer disposed on the substrate and having at least one of open regions, and a first conductive bonding layer disposed between the plurality of lighting emitting diode devices and the substrate and electrically contacting the plurality of light emitting diode devices, in which an upper surface of the first conductive bonding layer is placed above the light non-transmitting layer. | 2022-09-08 |
20220285328 | SEMICONDUCTOR PACKAGE INCLUDING REDISTRIBUTION SUBSTRATE - A semiconductor package includes a lower semiconductor chip disposed on a lower redistribution substrate, lower solder patterns disposed between the lower redistribution substrate and the lower semiconductor chip, conductive structures disposed on the lower redistribution substrate, a lower molding layer disposed on the lower redistribution substrate and covering a top surface of the lower semiconductor chip, an upper redistribution substrate disposed on the lower molding layer and electrically connected to the conductive structures, an upper semiconductor chip disposed on the upper redistribution substrate, upper solder patterns disposed between the upper redistribution substrate and the upper semiconductor chip, and an upper molding layer disposed on the upper redistribution substrate and covering a sidewall of the upper semiconductor chip. The number of the conductive structures is greater than that of chip pads of the upper semiconductor chip. | 2022-09-08 |
20220285329 | LIGHT EMITTING DEVICE FOR DISPLAY AND DISPLAY APPARATUS HAVING THE SAME - A light emitting device for a display including a circuit board, a plurality of light emitting units arranged on the circuit board, each light emitting unit comprising a first LED stack including a first conductivity type semiconductor layer, a second conductivity type semiconductor layer, a first electrode disposed on the first conductivity type semiconductor layer, and a second electrode disposed on the second conductivity type semiconductor layer, a plurality of bump pads disposed between the plurality of light emitting units and the circuit board, and a bonding layer disposed between the second electrode and the circuit board, in which the second electrode has a side surface recessed inwardly with respect to a side surface of the light emitting unit to define a recessed portion, and the bonding layer is filled in the recessed portion. | 2022-09-08 |
20220285330 | SEMICONDUCTOR DEVICE PACKAGE HAVING GALVANIC ISOLATION AND METHOD THEREFOR - A semiconductor device package having galvanic isolation is provided. The semiconductor device includes a package substrate having a first inductive coil formed from a first conductive layer and a second inductive coil formed from a second conductive layer. The first conductive layer and the second conductive layer are separated by a non-conductive material. A first semiconductor die is attached to a first major side of the package substrate. The first semiconductor die is conductively interconnected to the first inductive coil. A second semiconductor die is attached to the first major side of the package substrate. A first wireless communication link between the first semiconductor die and the second semiconductor die is formed by way of the first and second inductive coils. | 2022-09-08 |
20220285331 | PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A package structure includes a semiconductor die, an antenna substrate structure, and a redistribution layer. The semiconductor die is laterally wrapped by a first encapsulant. The antenna substrate structure is disposed over the semiconductor die, wherein the antenna substrate structure includes a circuit substrate and at least one antenna element inlaid in the circuit substrate. The redistribution layer is disposed between the semiconductor die and the antenna substrate structure, wherein the at least one antenna element is electrically connected with the semiconductor die through the circuit substrate and the redistribution layer. The at least one antenna element includes patch antennas. | 2022-09-08 |
20220285332 | DISPLAY DEVICE - According to one embodiment, a display device includes pixels each including transistors, pixel electrodes, a contact electrode, and light emitting elements, and an insulating basement, a first organic insulating layer, a second organic insulating layer, a resin layer, a common electrode, and first wiring lines. The common electrode is electrically connected to cathodes of the light emitting elements, and electrically connected to the contact electrodes of the pixels. The first wiring lines, each provided between the first organic insulating layer and the second organic insulating layer or between the second organic insulating layer and the resin layer, are electrically connected to the contact electrodes of the pixels, and are formed of a metal. | 2022-09-08 |
20220285333 | PHOTORELAY - A photorelay of an embodiment includes a polyimide substrate having a first surface and a second surface on an opposite side of the polyimide substrate from the first surface, the polyimide substrate having a thickness equal to or more than 10 μm and equal to or less than 120 μm, an input terminal provided on the second surface, an output terminal provided on the second surface, a light receiving element provided on the first surface, a light emitting element provided on the light receiving element, and a MOSFET provided on the first surface. | 2022-09-08 |
20220285334 | Semiconductor Device and Method of Stacking Semiconductor Die for System-Level ESD Protection - A semiconductor device has a first semiconductor die including a first protection circuit. A second semiconductor die including a second protection circuit is disposed over the first semiconductor die. A portion of the first semiconductor die and second semiconductor die is removed to reduce die thickness. An interconnect structure is formed to commonly connect the first protection circuit and second protection circuit. A transient condition incident to the interconnect structure is collectively discharged through the first protection circuit and second protection circuit. Any number of semiconductor die with protection circuits can be stacked and interconnected via the interconnect structure to increase the ESD current discharge capability. The die stacking can be achieved by disposing a first semiconductor wafer over a second semiconductor wafer and then singulating the wafers. Alternatively, die-to-wafer or die-to-die assembly is used. | 2022-09-08 |
20220285335 | METHODS OF MANUFACTURING LIGHT-EMITTING DEVICES WITH METAL INLAYS AND BOTTOM CONTACTS - Methods of manufacturing light-emitting devices are described herein. A method includes obtaining a packaging substrate. The packaging substrate includes an embedded metal inlay, vias in the packaging substrate and contacts on a bottom surface of the packaging substrate, each electrically coupled to a respective one of the vias. The method also includes forming a hybridized device, attaching a bottom surface of the hybridized device to a top surface of the metal inlay, and wirebonding a top surface of the hybridized device to a stop surface of the packaging substrate using a plurality of conductive connectors. | 2022-09-08 |
20220285336 | ELECTROSTATIC DISCHARGE PROTECTION DEVICE - A semiconductor device includes a P-doped well having a first concentration of P-type dopants in the substrate; a P-doped region having a second concentration of P-type dopants in the substrate and extending around a perimeter of the P-doped well; a shallow trench isolation structure (STI) between the P-doped well and the P-doped region; an active area on the substrate, the active area including an emitter region and a collector region; a deep trench isolation structure (DTI) extending through the active area and between the emitter region and the collector region; and an electrical connection between the emitter region and the P-doped region. | 2022-09-08 |
20220285337 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR STORAGE DEVICE - In one embodiment, a semiconductor device includes substrate, a plurality of electrode layers provided above the substrate, and separated from each other in a first direction perpendicular to a surface of the substrate, and a first plug provided in the plurality of electrode layers. The device further includes first and second diffusion layers provided in the substrate, one of the first and second diffusion layers functioning as an anode layer of an ESD (electrostatic discharge) protection circuit, the other of the first and second diffusion layers functioning as a cathode layer of the ESD protection circuit, a second plug provided at a position that overlaps with the first diffusion layer in planar view, and electrically connected with the first diffusion layer, and a third plug provided at a position that does not overlap with the first diffusion layer in planar view, and electrically connected with the first diffusion layer. | 2022-09-08 |
20220285338 | HIGH ESD IMMUNITY FIELD-EFFECT DEVICE AND MANUFACTURING METHOD THEREOF - An apparatus for providing electrostatic discharge (ESD) immunity and a method for fabricating the same are disclosed herein. The apparatus comprises a field effect transistor (FET) formed on a semiconductor substrate in a front-end-of-line (FEOL) layer during an FEOL process, a metal interconnect layer formed on top of the FEOL layer during a back-end-of-line (BEOL) process, wherein the metal interconnect layer comprises a plurality interconnects configured to interconnect the FET to a plurality of components formed on the semiconductor substrate, a power delivery network (PDN) formed under the semiconductor substrate in a backside layer during a backside back-end-of-line (B-BEOL) process, and a through substrate resistive component formed between the FEOL and B-BEOL layers, wherein a first contact of the through substrate resistive component is connected to a drain terminal of the FET and second contact is connected, through the PDN, to a power supply rail. | 2022-09-08 |
20220285339 | ELECTROSTATIC DISCHARGE CIRCUITS AND METHODS FOR OPERATING THE SAME - The present disclosure provides electrostatic discharge circuits and structures and methods for operating the electrostatic discharge circuits and structures. A circuit includes a first transistor and a second transistor. The first transistor includes a drain, a source, a gate, and a bulk. The drain of the first transistor is connected to a first terminal. The source of the first transistor is connected to receive a first voltage. The gate and the bulk of the first transistor is connected to receive a second voltage. The second transistor includes a drain, a source, a gate, and a bulk. The source, the gate, and the bulk of the second transistor is connected to receive the second voltage. The drain of the second transistor is connected to the first terminal. In response to the terminal reaching a trigger voltage, the first transistor is configured to be turned on. | 2022-09-08 |
20220285340 | LARGE CAPACITOR PRE-CHARGE METHOD AND CIRCUIT - A method of operating a circuit having a capacitor and a load that are connectable to, and disconnetable from, a voltage source by an electronically controllable switch, the method includes charging the capacitor by raising a voltage across the capacitor from an initial voltage value and at a constant rate by controlling the switch to supply current to the capacitor at a constant current supply rate that is selected to avoid damage to the switch, and then operating the switch to supply current from the voltage source to the capacitor when the voltage across the capacitor reaches the voltage source's voltage. | 2022-09-08 |
20220285341 | COMPOSITE POWER ELEMENT - A composite power element includes a substrate structure, an insulation layer, a dielectric layer, a MOSFET, and a Zener diode. The MOSFET is formed in a transistor formation region of the substrate structure. The Zener diode is formed in a circuit element formation region of the substrate structure, and includes a Zener diode doping structure that is formed in the substrate structure and is covered by the insulation layer. The Zener diode doping structure includes a first P-type doped region and a first N-type doped region that is formed on an inner side of the first P-type doped region. The Zener diode further includes a Zener diode metal structure that is formed on the dielectric layer and sequentially passes through the dielectric layer and the insulation layer to be electrically connected to the first P-type doped region and the first N-type doped region. | 2022-09-08 |
20220285342 | DEEP TRENCH VIA FOR THREE-DIMENSIONAL INTEGRATED CIRCUIT - Described herein are apparatuses, methods, and systems associated with a deep trench via in a three-dimensional (3D) integrated circuit (IC). The 3D IC may include a logic layer having an array of logic transistors. The 3D IC may further include one or more front-side interconnects on a front side of the 3D IC and one or more back-side interconnects on a back side of the 3D IC. The deep trench may be in the logic layer to conductively couple a front-side interconnect to a back-side interconnect. The deep trench via may be formed in a diffusion region or gate region of a dummy transistor in the logic layer. Other embodiments may be described and claimed. | 2022-09-08 |
20220285343 | INTEGRATION OF MULTIPLE FIN STUCTURES ON A SINGLE SUBSTRATE - Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure. The method includes forming a stack of semiconductor layers comprising a plurality of first semiconductor layers and a plurality of second semiconductor layers over a semiconductor substrate. A first stack of masking layers is formed over the stack of semiconductor layers with a first width and a second stack of masking layers is formed laterally offset from the stack of semiconductor layers with a second width less than the first width. A patterning process is performed on the semiconductor substrate and the stack of semiconductor layers, thereby defining a first fin structure laterally adjacent to a second fin structure. The first fin structure has the first width and the second fin structure has the second width. The stack of semiconductor layers directly overlies the first fin structure and has the first width. | 2022-09-08 |
20220285344 | METHOD TO EMBED PLANAR FETS WITH FINFETS - Various embodiments of the present disclosure are directed towards a method to embed planar field-effect transistor (FETs) with fin field-effect transistors (finFETs). A semiconductor substrate is patterned to define a mesa and a fin. A trench isolation structure is formed overlying the semiconductor substrate and surrounding the mesa and the fin. A first gate dielectric layer is formed on the mesa, but not the fin. The trench isolation structure recessed around the fin, but not the mesa, after the forming the first gate dielectric layer. A second gate dielectric layer is deposited overlying the first gate dielectric layer at the mesa and further overlying the fin. A first gate electrode is formed overlying the first and second gate dielectric layers at the mesa and partially defining a planar FET. A second gate electrode is formed overlying the second gate dielectric layer at the fin and partially defining a finFET. | 2022-09-08 |
20220285345 | SEMICONDUCTOR DEVICE, INTEGRATED CIRCUIT AND METHODS OF MANUFACTURING THE SAME - A semiconductor device includes a gate layer, a channel material layer, a first dielectric layer and source/drain terminals. The gate layer is disposed over a substrate. The channel material layer is disposed over the gate layer, where a material of the channel material layer includes a first low dimensional material. The first dielectric layer is between the gate layer and the channel material layer. The source/drain terminals are in contact with the channel material layer, where the channel material layer is at least partially disposed between the source/drain terminals and over the gate layer, and the gate layer is disposed between the substrate and the source/drain terminals. | 2022-09-08 |
20220285346 | Semiconductor Devices and Methods of Fabricating the Same - A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary semiconductor structure includes a number of channel members over a substrate, a gate structure wrapping around each of the number of channel members, a dielectric fin structure disposed adjacent to the gate structure, the dielectric fin structure includes a first dielectric layer disposed over the substrate and in direct contact with the first gate structure, a second dielectric layer disposed over the first dielectric layer, and a third dielectric layer. The third dielectric is disposed over the second dielectric layer and spaced apart from the first dielectric layer and the gate structure by the second dielectric layer. The dielectric fin structure also includes an isolation feature disposed directly over the third dielectric layer. | 2022-09-08 |
20220285347 | SEMICONDUCTOR DEVICE AND METHOD - A method includes etching a substrate to form a semiconductor fin, forming a gate stack on a top surface and sidewalls of the semiconductor fin, and forming a first recess in the semiconductor fin on a side of the gate stack, wherein forming the first recess comprises, performing a first etching process to form a first portion of the first recess, depositing a first dielectric layer on sidewalls of the gate stack and the first portion of the first recess, performing a second etching process to form a second portion of the first recess using the first dielectric layer as a mask, wherein the second portion of the first recess extends under the gate stack, and performing a third etching process to remove the first dielectric layer. | 2022-09-08 |
20220285348 | SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A semiconductor structure includes a substrate and a fin protruding from the substrate along a first direction, wherein the fin includes a first semiconductive layer over the substrate, a second semiconductive layer over the first semiconductive layer along the first direction, and a dielectric layer disposed between the first semiconductive layer and the second semiconductive layer and electrically isolated from the first semiconductive layer and the second semiconductive layer. The semiconductor structure also includes a gate electrode including: a first conductive portion extending in a second direction different from the first direction and including an upper surface level with an upper surface of the first semiconductive layer; and a second conductive portion electrically isolated from the first conductive portion and including a bottom surface level with a bottom surface of the second semiconductive layer. | 2022-09-08 |
20220285349 | Memory Cell and Method - An improved memory cell architecture including a nanostructure field-effect transistor (nano-FET) and a horizontal capacitor extending at least partially under the nano-FET and methods of forming the same are disclosed. In an embodiment, semiconductor device includes a channel structure over a semiconductor substrate; a gate structure encircling the channel structure; a first source/drain region adjacent the gate structure; and a capacitor adjacent the first source/drain region, the capacitor extending under the first source/drain region and the gate structure in a cross-sectional view. | 2022-09-08 |
20220285350 | MEMORY DEVICE AND METHOD OF MANUFACTURING MEMORY DEVICE - According to one embodiment, a memory includes: a first transistor including: a first semiconductor between the substrate and the bit line; and a first gate facing a side of the first semiconductor; a first memory element between the first transistor and the substrate; a first word line including a first conductor coupled to the first gate; a second transistor including: a second semiconductor between the substrate and the bit line; and a second gate facing a side of the second semiconductor; a second memory element between the second transistor and the substrate; and a second word line being adjacent to the first word line in a first direction and including a second conductor coupled to the second gate. The second semiconductor is adjacent to the first semiconductor in a second direction intersecting the first direction. | 2022-09-08 |
20220285351 | MULTIPLEXOR FOR A SEMICONDUCTOR DEVICE - A memory device can comprise an array of memory cells comprising a plurality of vertically stacked tiers of memory cells, a respective plurality of horizontal access lines coupled to each of the plurality of tiers, and a plurality of vertical sense lines coupled to each of the plurality of tiers. The array of memory cells can further comprise a plurality of multiplexors each coupled to a respective vertical sense line and configured to electrically couple the respective vertical sense line to a horizontal sense line. The memory device can also comprise a semiconductor under the array (SuA) circuitry, comprising a plurality of sense amplifiers, each sense amplifier coupled to a respective subset of the plurality of multiplexors. | 2022-09-08 |
20220285352 | MEMORY AND METHOD FOR MANUFACTURING MEMORY - A memory includes a substrate. An isolation layer is disposed on the substrate. The plurality of active regions arranged in an array are disposed in the isolation layer. A plurality of word lines are formed in the plurality of active regions and the isolation layer. Each word line includes gates disposed in the active regions and word line structures disposed in the isolation layer. The each word line is constituted by successive connection of the plurality of gates and the plurality of word line structures arranged at intervals. The plurality of gates included in the each word line are disposed in two correspondingly adjacent columns of active regions, and any two adjacent gates in the each word line are disposed in two correspondingly adjacent rows of active regions. | 2022-09-08 |
20220285353 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes: an active layer spaced apart from a substrate wherein the active layer extends in a direction parallel to the substrate, and includes a channel; a bit line extending in a direction perpendicular to the substrate and coupled to a first end of the active layer; a capacitor coupled to a second end of the active layer; and a double word line including a pair of dual work function electrodes that extend in a direction crossing the active layer with the active layer interposed therebetween, wherein each of the dual work function electrodes includes: a high work function electrode which is adjacent to the bit line; and a low work function electrode which is adjacent to the capacitor and having a lower work function than the high work function electrode. | 2022-09-08 |
20220285354 | INTEGRATED CIRCUIT DEVICE - A DRAM including a silicon substrate, buried word lines, and active areas is provided. The silicon substrate has a carrier surface. The buried word lines are buried in the silicon substrate. The active areas are located on the carrier surface. The buried word lines intersect the active area. Each of the buried word lines has a first width in one of the active area, and has a second width outside the active areas, and the first width is larger than the second width. A manufacturing method of DRAM is also provided. | 2022-09-08 |
20220285355 | HIGH-DENSITY 3D-DRAM CELL WITH SCALED CAPACITORS - A semiconductor device comprises a semiconductor substrate, and a pair of metal gates extends upwards from the semiconductor substrate. First and second channel regions are disposed between inner sidewalls of the pair of metal gates. First and second drain regions are disposed between the inner sidewalls of the pair of metal gates and are disposed directly over the first and second channel regions, respectively. First and second source regions are disposed between the inner sidewalls of the pair of metal gates directly below the first and second channel regions, respectively. A capacitor dielectric structure is disposed below the first and second source regions. A bottom capacitor electrode is disposed below the capacitor dielectric. The capacitor dielectric structure separates the first and second drain regions from the bottom capacitor electrode. | 2022-09-08 |
20220285356 | SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FABRICATING THE SAME - Disclosed are semiconductor memory devices and methods of fabricating the same. The semiconductor memory devices may include a plurality of layers sequentially stacked on a substrate in a vertical direction, each of the plurality of layers including a bit line extending in a first direction and a semiconductor pattern extending from the bit line in a second direction traversing the first direction, a gate electrode extending through the plurality of layers and including a vertical portion extending through the semiconductor patterns and a first horizontal portion extending from the vertical portion and facing a first surface of one of the semiconductor patterns, and a data storing element electrically connected to the one of the semiconductor patterns. The data storing element includes a first electrode electrically connected to the one of the semiconductor patterns, a second electrode on the first electrode, and a dielectric layer between the first and second electrodes. | 2022-09-08 |
20220285357 | Integrated Memory with Redistribution of Capacitor Connections, and Methods of Forming Integrated Memory - Some embodiments include an integrated assembly having digit-line-contact-regions between pairs of capacitor-contact-regions. The capacitor-contact-regions are arranged with six adjacent capacitor-contact-regions in a substantially rectangular configuration. Conductive plugs are coupled with the capacitor-contact-regions. Conductive redistribution material is coupled with the conductive plugs. Upper surfaces of the conductive redistribution material are arranged in a substantially hexagonal-close-packed configuration. Digit lines are over the digit-line-contact-regions. Insulative regions are between the digit lines and the conductive plugs. The insulative regions contain voids and/or low-k dielectric material. Capacitors are coupled with the upper surfaces of the conductive redistribution material. | 2022-09-08 |
20220285358 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD OF THE SAME - A semiconductor device includes: a bit line structure formed over a substrate; a storage node contact plug spaced apart from the bit line structure; and a nitride spacer positioned between the bit line structure and the storage node contact plug, wherein the nitride spacer has a higher silicon content in a portion adjacent to the storage node contact plug than in a portion adjacent to the bit line structure, | 2022-09-08 |
20220285359 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate, an oxide layer and a word line. The substrate has a plurality of protruding portions. Adjacent two of the protruding portions define a dense zone, and another adjacent two of the protruding portions define a loose zone. The oxide layer is disposed on the substrate. The word line is disposed on the substrate. A bottom surface of a portion of the word line in the dense zone and a bottom surface of a portion of the word line in the loose zone are substantially at the same height. | 2022-09-08 |
20220285360 | SEMICONDUCTOR DEVICE HAVING GATE TRENCH - Disclosed herein is a method that includes forming a gate trench in a semiconductor substrate, forming a gate insulating film on an inner wall of the gate trench, forming a gate electrode in the gate trench via the gate insulating film, ashing a top surface of the gate electrode to form a first insulating film, and for a gate cap insulating film embedded in the gate trench to cover the first insulating film. | 2022-09-08 |
20220285361 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor structure and a manufacturing method thereof are provided. The method includes following operations. A substrate including active regions and isolation regions is provided. First trench structures are formed on the substrate, the first trench structure passing through the active region and the isolation region. Bit line contact structures are formed in the first trench structures. Bit line structures are formed on the bit line contact structures, at least part of the bit line structure being positioned in the first trench structure. Bit line protection structures are formed on the bit line structures, the bit line protection structure at least covering an upper surface of the bit line structure. Capacitor contact assemblies are formed, the capacitor contact assembly including a first capacitor contact structure and a second capacitor contact structure which covers an upper surface and part of a side wall of the first capacitor contact structure. | 2022-09-08 |
20220285362 | METHODS AND STRUCTURES FOR THREE-DIMENSIONAL DYNAMIC RANDOM-ACCESS MEMORY - Methods for forming three-dimensional dynamic random-access memory (3D DRAM) structures that leverage a grid pattern of high aspect ratio holes to form subsequent features of the 3D DRAM. The method may include depositing alternating layers of crystalline silicon (c-Si) and crystalline silicon germanium (c-SiGe) using an heteroepitaxy process onto a substrate and HAR etching of a pattern of holes into the substrate. The holes configured to provide chemistry access to laterally etch or deposit materials to form 3D DRAM features without requiring subsequent HAR etching of holes to form the 3D DRAM features. | 2022-09-08 |
20220285363 | Memory and Fabricating Method Thereof - The present application provides a memory and a memory fabricating method. The memory includes a substrate, on which is disposed a separation layer, in which are arranged plural bitlines spaced apart from one another, the plural bitlines are arranged along a first direction, and each bitline is S-shaped. The method of fabricating the memory comprises the following steps: providing a substrate; forming on the substrate plural bitline grooves; forming in each bitline groove a first separation layer; forming bitlines on the first separation layer; forming a second separation layer on the bitlines; removing the substrate between adjacent separation walls, the separation wall including the first separation layer, the bitlines, and the second separation layer; and forming a third separation layer in a space between the adjacent separation walls, the third separation layer, the second separation layer, and the first separation layer together forming a separation layer. | 2022-09-08 |
20220285364 | METHODS AND APPARATUS FOR HIERARCHICAL BITLINE FOR THREE-DIMENSIONAL DYNAMIC RANDOM-ACCESS MEMORY - Methods for forming 3D DRAM leverage L-pad formations to increase memory density. Methods may include etching a substrate to form two Si walls oriented parallel to each other and forming a space therebetween, depositing a plurality of alternating Si layers and SiGe layers using epitaxial growth processes to form horizontal deposition layers on the space between the two Si walls and vertical deposition layers on sidewalls of the two Si walls, depositing a CMP stop layer on the substrate, planarizing the substrate to the CMP stop layer, removing a portion of a top of the two Si walls and forming an L-pad formation, deep etching a pattern of holes into the space between the two Si walls in horizontal portions of the plurality of alternating Si layers and SiGe layers, and forming vertical wordline structures from the pattern of holes in the horizontal portions. | 2022-09-08 |
20220285365 | VERTICAL CONTACTS FOR SEMICONDUCTOR DEVICES - Embodiments herein relate to vertical contacts for semiconductor devices. For instance, a memory device having vertical contacts can comprise a substrate including circuitry components, a vertical stack of layers formed from repeating iterations of a group of layers disposed on the substrate, the group of layers comprising a first dielectric material layer, a semiconductor material layer, and a second dielectric material layer including horizontal conductive lines formed along a horizontal plane in the second dielectric material layer, and vertical contacts coupled to the horizontal conductive lines, the vertical contacts extending along a vertical plane within the vertical stack of layers to directly electrically couple the horizontal conductive lines to the circuitry components. | 2022-09-08 |
20220285366 | CONDUCTIVE LAYERS WITH DIFFERENT THICKNESSES - A semiconductor chip includes: a memory cell having a bit line, a word line, and a power supply node; first, second and third conductive lines formed in first, second and third conductive layers, respectively, the bit line including a portion of the first conductive line; the word line including a portion of the second conductive line; and the power supply node including a portion of the third conductive line; wherein the second conductive line has a thickness which is thicker than those of the first conductive line and the third conductive line, and the first, second and third conductive layers are stacked with one another. The first conductive line is longer than the second conductive line substantially along a first direction. The second conductive line is longer than the first conductive line substantially along a second direction orthogonal to the first direction. | 2022-09-08 |
20220285367 | THIN FILM TRANSISTOR RANDOM ACCESS MEMORY - Methods, systems, and devices for thin film transistor random access memory are described. A memory device may include memory cells each having one or more transistors formed above a substrate. For example, a memory cell may include a transistor having a channel portion formed by one or more pillars or other structures formed above a substrate, and a gate portion including a conductor formed above the substrate and configured to activate the channel portion based at least in part on a voltage of the gate portion. A memory cell may include a set of two or more such transistors to support latching circuitry of the memory cell, or other circuitry configured to store a logic state, which may or may not be used in combination with one or more transistors formed at least in part from one or more portions of a substrate. | 2022-09-08 |
20220285368 | THIN FILM TRANSISTOR RANDOM ACCESS MEMORY - Methods, systems, and devices for thin film transistor random access memory are described. A memory device may include memory cells each having one or more transistors formed above a substrate. For example, a memory cell may include a transistor having a channel portion formed by one or more pillars or other structures formed above a substrate, and a gate portion including a conductor formed above the substrate and configured to activate the channel portion based at least in part on a voltage of the gate portion. A memory cell may include a set of two or more such transistors to support latching circuitry of the memory cell, or other circuitry configured to store a logic state, which may or may not be used in combination with one or more transistors formed at least in part from one or more portions of a substrate. | 2022-09-08 |
20220285369 | Memory Device with Improved Margin and Performance and Methods of Formation Thereof - A substrate includes a first doped region having a first type dopant, and a second doped region having a second type dopant and adjacent to the first doped region. A stack is formed that includes first layers and second layers alternating with each other. The first and second layers each have a first and second semiconductor material, respectively. The second semiconductor material is different than the first semiconductor material. A mask element is formed that has an opening in a channel region over the second doped region. A top portion of the stack not covered by the mask element is recessed. The stack is then processed to form a first and a second transistors. The first transistor has a first number of first layers. The second transistor has a second number of first layers. The first number is greater than the second number. | 2022-09-08 |
20220285370 | LAYOUT OF STATIC RANDOM ACCESS MEMORY PERIPHERY CIRCUIT - A static random access memory (SRAM) periphery circuit includes a first n-type transistor and a second n-type transistor that are disposed in a first well region of first conductivity type, the first well region occupies a first distance in a row direction equal to a bitcell-pitch of an SRAM array. The SRAM periphery circuit includes a first p-type transistor and a second p-type transistor that are disposed in a second well region of second conductivity type. The second well region occupies a second distance in the row direction equal to the bitcell-pitch of the SRAM array. The second well region is disposed adjacent to the first well region in the row direction. | 2022-09-08 |
20220285371 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes: a first stack including a first polycrystalline semiconductor layer having a first average crystal grain size, a second polycrystalline semiconductor layer having a second average crystal grain size smaller than the first average crystal grain size, an intermediate layer between the first and second polycrystalline semiconductor layers, and a third polycrystalline semiconductor layer provided on the second polycrystalline semiconductor layer and having a third average crystal grain size smaller than the first average crystal grain size; a second stack provided above the first stack and having conductive layers and insulation layers, each conductive layer and each insulation layer being alternately stacked and extending in a first direction; a semiconductor layer through the second stack, and on the third polycrystalline semiconductor layer; and a memory layer through the second stack, and between the semiconductor layer and the conductive layer in the first direction. | 2022-09-08 |
20220285372 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR MEMORY DEVICE - Provided herein is a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device includes a stacked body including conductive patterns and interlayer insulating layers that are alternately stacked, a lower channel portion passing through the stacked body, a memory layer disposed between the stacked body and the lower channel portion, a upper channel portion disposed on the lower channel portion, a gate insulating layer enclosing a sidewall of the upper channel portion, a first gate pattern enclosing a sidewall of the gate insulating layer, a separation insulating pattern contacting a first portion of the first gate pattern, and a second gate pattern contacting a second portion of the first gate pattern. | 2022-09-08 |
20220285373 | INTEGRATED CIRCUIT STRUCTURE AND METHOD OF FORMING THE SAME - A structure includes a semiconductor substrate, a gate structure, a source/drain feature, a source/drain contact, a dielectric layer, and a ferroelectric random access memory (FERAM) structure. The gate structure is on the semiconductor substrate. The source/drain feature is adjacent to the gate structure. The source/drain contact lands on the source/drain feature. The dielectric layer spans the source/drain contact. The FeRAM structure is partially embedded in the dielectric layer and includes a bottom electrode layer on the source/drain contact and having an U-shaped cross section, a ferroelectric layer conformally formed on the bottom electrode layer, and a top electrode layer over the ferroelectric layer. | 2022-09-08 |
20220285374 | WAKEUP FREE APPROACH TO IMPROVE THE FERROELECTRICITY OF FERAM USING A STRESSOR LAYER - In some embodiments, the present disclosure relates to a memory device including a semiconductor substrate, a first electrode disposed over the semiconductor substrate, a ferroelectric layer disposed between the first electrode and the semiconductor substrate, and a first stressor layer separating the first electrode from the ferroelectric layer. The first stressor layer has a coefficient of thermal expansion greater than that of the ferroelectric layer. | 2022-09-08 |
20220285375 | INTEGRATED CIRCUIT READ ONLY MEMORY (ROM) STRUCTURE - An integrated circuit read only memory (ROM) structure includes a first ROM transistor with a first gate electrode, a first source, and a first drain, and a second ROM transistor with a second gate electrode, a second source, and a second drain. A drain conductive line is over the first drain and the second drain, and is between the first drain and the second drain. The first drain, the drain conductive line and the second drain are between the first gate electrode and the second gate electrode, and a first trench isolation structure electrically isolates the first drain from the first source is below the first gate electrode. | 2022-09-08 |
20220285376 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A method for fabricating a semiconductor device is provided. The method includes depositing a bottom electrode layer over a substrate; depositing a ferroelectric layer over the bottom electrode layer; depositing a first top electrode layer over the ferroelectric layer, wherein the first top electrode layer comprises a first metal; depositing a second top electrode layer over the first top electrode layer, wherein the second top electrode layer comprises a second metal, and a standard reduction potential of the first metal is greater than a standard reduction potential of the second metal; and removing portions of the second top electrode layer, the first top electrode layer, the ferroelectric layer, and the bottom electrode layer to form a memory stack, the memory stack comprising remaining portions of the second top electrode layer, the first top electrode layer, the ferroelectric layer, and the bottom electrode layer. | 2022-09-08 |
20220285377 | SEMICONDUCTOR DEVICE - Embodiments provide a semiconductor device capable of being highly integrated. | 2022-09-08 |
20220285378 | METHODS OF FORMING MICROELECTRONIC DEVICES, AND RELATED MICROELECTRONIC DEVICES, MEMORY DEVICES, AND ELECTRONIC SYSTEMS - A microelectronic device comprises a stack structure comprising blocks separated from one another by dielectric slot structures. At least one of the blocks comprises two crest regions, a stadium structure interposed between the two crest regions in a first horizontal direction, and two bridge regions neighboring opposing sides of the stadium structure in a second horizontal direction. A filled trench vertically overlies and is within horizontal boundaries of the stadium structure of the at least one of the blocks. The filled trench comprises a dielectric liner material on the opposing staircase structures of the stadium structure and on inner sidewalls of the two bridge regions, and dielectric structures on and having a different material composition than the dielectric liner material. The dielectric structures are substantially confined within horizontal areas of the steps of the stadium structure. Memory devices, electronic systems, and methods of forming microelectronic devices are also described. | 2022-09-08 |
20220285379 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a substrate that includes a first region and a second region. The first region includes: a plurality of first word line layers; a first semiconductor layer having an outer peripheral surface opposed to the plurality of first word line layers; and a first electric charge accumulating film disposed between the plurality of first word line layers and the first semiconductor layer. The second region includes: a part of the plurality of first word line layers; a plurality of first insulating layers, the plurality of first insulating layers; a first contact having an outer peripheral surface opposed to the plurality of first insulating layers; a second semiconductor layer disposed between the plurality of first word line layers and the plurality of first insulating layers; and a second electric charge accumulating film disposed between the plurality of first insulating layers and the second semiconductor layer. | 2022-09-08 |
20220285380 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes two first electrode films, a first column and a second insulating film. The two first electrode films extend in a first direction and are separated from each other in a second direction. The first column is provided between the two first electrode films and has a plurality of first members and a plurality of insulating members. Each of the first members and each of the insulating members are arranged alternately in the first direction. One of the plurality of first members has a semiconductor pillar, a second electrode film and a first insulating film provided between the semiconductor pillar and the second electrode film. The semiconductor pillar, the first insulating film and the second electrode film are arranged in the second direction. The second insulating film is provided between the first column and one of the two first electrode films. | 2022-09-08 |
20220285381 | SEMI-CONDUCTOR DEVICE HAVING DOUBLE-GATE AND METHOD FOR SETTING SYNAPSE WEIGHT OF TARGET SEMI-CONDUCTOR DEVICE WITHIN NEURAL NETWORK - Embodiments relate to a semiconductor device including a body made of a first conducting semiconductor material, a source and a drain made of a second conducting semiconductor material and formed on the body, a first gate formed on the body with a gate insulating layer interposed between the first gate and the body, a second gate formed opposite the first gate with respect to the body, and an insulating layer stack having a charge storage layer formed between the body and the second gate, and a method for controlling a synapse weight of a target semiconductor device within a neural network including semiconductor devices. | 2022-09-08 |
20220285382 | Memory Devices and Method of Fabricating Same - A device comprises a control gate structure and a memory gate structure over a substrate, a charge storage layer formed between the control gate structure and the memory gate structure, a first spacer along a sidewall of the memory gate structure, a second spacer along a sidewall of the control gate structure, an oxide layer over a top surface of the memory gate structure, a top spacer over the oxide layer, a first drain/source region formed in the substrate and adjacent to the memory gate structure and a second drain/source region formed in the substrate and adjacent to the control gate structure. | 2022-09-08 |
20220285383 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device according to an embodiment includes a substrate, a source line, a plurality of word lines, a pillar, and a first contact portion. The word lines are spaced apart from each other in a first direction. A bottom portion of the pillar reaches the source line. The first contact portion is provided on the substrate. The first contact portion is connected between the source line and the substrate. An inside of the first contact portion, or a portion in which a conductive layer included in the source line is in contact with the first contact portion, includes a portion functioning as a diode. The portion functioning as the diode is electrically connected in a reverse direction from the source line toward the substrate. | 2022-09-08 |
20220285384 | PROTECTIVE LINER LAYERS IN 3D MEMORY STRUCTURE - A memory device includes a stack of gate electrode layers and interconnect layers arranged over a substrate. A first memory cell that is arranged over the substrate includes a first source/drain conductive lines and a second source/drain conductive line extending vertically through the stack of gate electrode layers. A channel layer and a memory layer are arranged on outer sidewalls of the first and second source/drain conductive lines. A first barrier structure is arranged between the first and second source/drain conductive lines. A first protective liner layer separates the first barrier structure from each of the first and second source/drain conductive lines. A second barrier structure is arranged on an opposite side of the first source/drain conductive line and is spaced apart from the first source/drain conductive line by a second protective liner layer. | 2022-09-08 |
20220285385 | MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A memory device and a method for fabricating the memory device are provided. The memory device includes a substrate having an upper surface; a stack disposed on the substrate, wherein the stack includes a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, and a third insulating layer sequentially stacked on the upper surface of the substrate along a first direction; a channel layer penetrating the stack along the first direction, wherein the channel layer has a ring shape along a cross section view in a plane perpendicular to the first direction; and a memory layer disposed between the channel layer and the second conductive layer. | 2022-09-08 |
20220285386 | THREE-DIMENSIONAL MEMORY DEVICE INCLUDING DISCRETE CHARGE STORAGE ELEMENTS WITH LATERALLY-PROTRUDING PROFILES AND METHODS OF MAKING THEREOF - A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack and having lateral protrusions at levels of the electrically conductive layers, and memory opening fill structures located in the memory openings. Each of the memory opening fill structures includes a vertical semiconductor channel, a dielectric material liner laterally surrounding the vertical semiconductor channel, and a vertical stack of discrete memory elements laterally surrounding the dielectric material liner and located within volumes of the lateral protrusions. Each discrete memory element includes a vertical inner sidewall and a convex or stepped outer sidewall. | 2022-09-08 |
20220285387 | THREE-DIMENSIONAL MEMORY DEVICE INCLUDING LATERALLY-UNDULATING MEMORY MATERIAL LAYERS AND METHODS FOR FORMING THE SAME - A memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical semiconductor channel and a memory material layer. A vertical stack of insulating material portions can be provided at levels of the insulating layers to provide a laterally-undulating profile to the memory material layer. Alternatively, a combination of inner insulating spacers and outer insulating spacers can be employed to provide a laterally-undulating profile to the memory material layer. | 2022-09-08 |
20220285388 | THREE-DIMENSIONAL MEMORY DEVICE INCLUDING LATERALLY-UNDULATING MEMORY MATERIAL LAYERS AND METHODS FOR FORMING THE SAME - A memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical semiconductor channel and a memory material layer. A vertical stack of insulating material portions can be provided at levels of the insulating layers to provide a laterally-undulating profile to the memory material layer. Alternatively, a combination of inner insulating spacers and outer insulating spacers can be employed to provide a laterally-undulating profile to the memory material layer. | 2022-09-08 |
20220285389 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a substrate, conductive layers arranged in a first direction and extend in a second direction, a semiconductor layer extending in the first direction and opposed to the conductive layers, and n contact electrode regions arranged in a third direction. The n is a power of 2. The contact electrode region includes contact electrodes arranged in the second direction. The conductive layers include a first conductive layer and a second conductive layer that is an n-th conductive layer counted from the first conductive layer. The contact electrodes include a first contact electrode connected to the first conductive layer, a second contact electrode connected to the second conductive layer, and a third contact electrode disposed between them. The first contact electrode, the second contact electrode, and the third contact electrode are arranged in the second direction or the third direction. | 2022-09-08 |
20220285390 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a tunnel insulating layer, a data storage layer, and a blocking insulating layer that are sequentially disposed. The tunnel insulating layer includes Metal Organic Frameworks (MOF) having a lower dielectric constant than a dielectric constant of the blocking insulating layer. | 2022-09-08 |
20220285391 | SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR MANUFACTURING THE SAME - In a method for manufacturing a memory, a first stacked body is formed by stacking a first insulating film and a first sacrificial film. A first columnar body including a first semiconductor portion extending in the first stacked body in the first direction and a charge trapping film provided on an outer peripheral surface of the first semiconductor portion is formed. A second columnar body provided in a second direction of the first columnar body and including a second semiconductor portion stretching in the first stacked body in the first direction and a charge trapping film on an outer peripheral surface of the second semiconductor portion is formed. A second insulating film is formed above the first stacked body. A third columnar body including a third semiconductor portion provided on both the first columnar body and the second columnar body and stretching in the second insulating film in the first direction and a first gate insulating film provided on an outer peripheral surface of the third semiconductor portion is formed. A first division insulating film extending in the first direction and a third direction intersecting the first direction and the second direction and dividing the third semiconductor portion of the third columnar body in the second direction is formed. | 2022-09-08 |
20220285392 | Memory Devices and Methods of Forming Memory Devices - Some embodiments include an integrated assembly having pillars arranged in an array. The pillars have channel regions between upper and lower source/drain regions. Gating structures are proximate to the channel regions and extend along a row direction. Digit lines are beneath the pillars, extend along a column direction, and are coupled with the lower source/drain regions. Linear structures are above the pillars and extend along the column direction. Bottom electrodes are coupled with the upper source/drain regions. The bottom electrodes have horizontal segments adjacent the upper source/drain regions and have vertical segments extending upwardly from the horizontal segments. The vertical segments are adjacent to lateral sides of the linear structures. Ferroelectric-insulative-material and top-electrode-material are over the bottom electrodes. A slit passes through the top-electrode-material, is directly over one of the linear structures, and extends along the column direction. | 2022-09-08 |
20220285393 | THREE-DIMENSIONAL MEMORY DEVICE AND METHOD - A memory cell includes patterning a first trench extending through a first conductive line, depositing a memory film along sidewalls and a bottom surface of the first trench, depositing a channel layer over the memory film, the channel layer extending along the sidewalls and the bottom surface of the first trench, depositing a first dielectric layer over and contacting the channel layer to fill the first trench, patterning a first opening, wherein patterning the first opening comprises etching the first dielectric layer, depositing a gate dielectric layer in the first opening, and depositing a gate electrode over the gate dielectric layer and in the first opening, the gate electrode being surrounded by the gate dielectric layer. | 2022-09-08 |
20220285394 | THREE-DIMENSIONAL MEMORY DEVICE AND METHOD - 3D memory array devices and methods of manufacturing are described herein. A method includes etching a first trench and a second trench in a multilayer stack, the multilayer stack including alternating dielectric layers and sacrificial layers. The method further includes forming a word line by replacing a sacrificial layer with a conductive material. Once the word line has been formed, a first transistor is formed in the first trench, the first transistor including a first channel isolation structure. A cut channel plug is formed in the second trench, a centerline of the cut channel plug being aligned with a centerline of the channel isolation structure. The method further includes forming a second transistor in the second trench adjacent the cut channel plug, the word line being electrically coupled to the first transistor and the second transistor. | 2022-09-08 |
20220285395 | HIGH SELECTIVITY ISOLATION STRUCTURE FOR IMPROVING EFFECTIVENESS OF 3D MEMORY FABRICATION - In some embodiments, the present disclosure relates to a method for forming a memory device, including forming a plurality of word line stacks respectively including a plurality of word lines alternatingly stacked with a plurality of insulating layers over a semiconductor substrate, forming a data storage layer along opposing sidewalls of the word line stacks, forming a channel layer along opposing sidewalls of the data storage layer, forming an inner insulating layer between inner sidewalls of the channel layer and including a first dielectric material, performing an isolation cut process including a first etching process through the inner insulating layer and the channel layer to form an isolation opening, forming an isolation structure filling the isolation opening and including a second dielectric material, performing a second etching process through the inner insulating layer on opposing sides of the isolation structure to form source/drain openings, and forming source/drain contacts in the source/drain openings. | 2022-09-08 |
20220285396 | FERROELECTRIC MEMORY DEVICE, MANUFACTURING METHOD OF THE FERROELECTRIC MEMORY DEVICE AND SEMICONDUCTOR CHIP - A ferroelectric memory device, a manufacturing method of the ferroelectric memory device and a semiconductor chip are provided. The ferroelectric memory device includes a gate electrode, a ferroelectric layer, a channel layer, first and second blocking layers, and source/drain electrodes. The ferroelectric layer is disposed at a side of the gate electrode. The channel layer is capacitively coupled to the gate electrode through the ferroelectric layer. The first and second blocking layers are disposed between the ferroelectric layer and the channel layer. The second blocking layer is disposed between the first blocking layer and the channel layer. The first and second blocking layers comprise a same material, and the second blocking layer is further incorporated with nitrogen. The source/drain electrodes are disposed at opposite sides of the gate electrode, and electrically connected to the channel layer. | 2022-09-08 |
20220285397 | SEMICONDUCTOR MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF - A semiconductor device comprises a first conductive structure extending along a vertical direction and a second conductive structure extending along the vertical direction. The second conductive structure is spaced apart from the first conductive structure along a lateral direction. The semiconductor device further comprises a plurality of third conductive structures each extending along the lateral direction. The plurality of third conductive structures are disposed across the first and second conductive structures. The first and second conductive structures each have a varying width along the lateral direction. The plurality of third conductive structures have respective different thicknesses in accordance with the varying width of the first and second conductive structures. | 2022-09-08 |
20220285398 | THREE-DIMENSIONAL MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF - A semiconductor device includes a first conductor structure extending along a lateral direction. The semiconductor device includes a first memory film that extends along a vertical direction and is in contact with the first conductor structure. The semiconductor device includes a first semiconductor film that extends along the vertical direction and is in contact with the first memory film. Ends of the first semiconductor film align with ends of the first memory film, respectively. The semiconductor device includes a second conductor structure extending along the vertical direction. The semiconductor device includes a third conductor structure extending along the vertical direction. The semiconductor device includes a fourth conductor structure extending along the vertical direction. The second and fourth conductor structures are coupled to the ends of the first semiconductor film, and the third conductor structure is coupled to a portion of the first semiconductor film between its ends. | 2022-09-08 |
20220285399 | SEMICONDUCTOR MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF - A semiconductor device includes a first conductive structure extending along a vertical direction and a second conductive structure extending along the vertical direction. The second conductive structure is spaced apart from the first conductive structure along a first lateral direction. The semiconductor device includes third conductive structures each extending along the first lateral direction. The third conductive structures are disposed across the first and second conductive structures. The semiconductor device includes a first semiconductor channel extending along the vertical direction. The first semiconductor channel is disposed between the third conductive structures and the first conductive structure, and between the third conductive structures and the second conductive structure. The first and second conductive structures each have a first varying width along the first lateral direction, and the first semiconductor channel has a second varying width along a second lateral direction. | 2022-09-08 |
20220285400 | 3D MEMORY DEVICE WITH MODULATED DOPED CHANNEL - A semiconductor device comprises a first conductive structure extending along a vertical direction and a second conductive structuring extending along the vertical direction. The second conductive structure is spaced apart from the first conductive structure along a lateral direction. The semiconductor device further comprises a plurality of third conductive structures each extending along the lateral direction. The plurality of third conductive structures are disposed across the first and second conductive structures. The semiconductor device further comprises a first semiconductor channel extending along the vertical direction. The first semiconductor channel is disposed between the plurality of third conductive structures and the first conductive structure and between the plurality of third conductive structures and the second conductive structure. The first and second conductive structures each have a varying width along the lateral direction, and the first semiconductor channel has a doping concentration varying along the vertical direction. | 2022-09-08 |